clk: samsung: exynos4: fix g3d clocks

sclk_g3d clock doesn't have enable/disable bits, but the driver hijacked
g3d gate clock bits for this purpose and didn't provide real g3d clock
at all. This patch fixes this issue by adding proper definition for g3d
clock and removing incorrect access to GATE_IP_G3D register in sclk_g3d.
In addition CLK_SET_RATE_PARENT flag is dropped from sclk_g3d, because
it does not make any sense and most likely has been added by mistake.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
[tomasz.figa@gmail.com: Adjusted commit message.]
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 1b0dd73636c0b88f9a541aa774f9dc3d2ec30b58..b0c660b484eeaf30717d4f225e76503dd4e136d6 100644 (file)
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -733,8 +733,7 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
        DIV(0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
        DIV(0, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
        DIV(CLK_SCLK_MFC, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
-       DIV_F(0, "div_g3d", "mout_g3d", DIV_G3D, 0, 4,
-                       CLK_SET_RATE_PARENT, 0),
+       DIV(CLK_SCLK_G3D, "sclk_g3d", "mout_g3d", DIV_G3D, 0, 4),
        DIV(0, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
        DIV(0, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
        DIV(0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
@@ -857,8 +856,7 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
                0),
        GATE(CLK_TSI, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0),
        GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
-       GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0,
-                       CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_G3D, "g3d", "aclk200", GATE_IP_G3D, 0, 0, 0),
        GATE(CLK_PPMUG3D, "ppmug3d", "aclk200", GATE_IP_G3D, 1, 0, 0),
        GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
        GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),