drm/i915: state readout and cross checking for limited_color_range

At least on those platforms which have a simple bit and don't rely
on the fully programmable CSC unit to do this.

Note that with the current code this includes CHV, but I guess that
platform will match BYT.

Reviewed-by: Naresh Kumar Kachhi <naresh.kumar.kachhi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6240f1f543b92c67ff0f5ec4aeda08f42915f395..3a5b2ed53220d3a585bad81aee85878c9fd1259d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6062,6 +6062,9 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
                }
        }
 
+       if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
+               pipe_config->limited_color_range = true;
+
        if (INTEL_INFO(dev)->gen < 4)
                pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
 
@@ -7068,6 +7071,9 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
                break;
        }
 
+       if (tmp & PIPECONF_COLOR_RANGE_SELECT)
+               pipe_config->limited_color_range = true;
+
        if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
                struct intel_shared_dpll *pll;
 
@@ -9884,6 +9890,9 @@ intel_pipe_config_compare(struct drm_device *dev,
 
        PIPE_CONF_CHECK_I(pixel_multiplier);
        PIPE_CONF_CHECK_I(has_hdmi_sink);
+       if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
+           IS_VALLEYVIEW(dev))
+               PIPE_CONF_CHECK_I(limited_color_range);
 
        PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
                              DRM_MODE_FLAG_INTERLACE);

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index e43bf558f0cdba5d0d3d5e9fffe3d39583d96dae..650525a654a399dc61d62f8d4e9faa36aa8261f2 100644 (file)
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1348,6 +1348,8 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
        u8 val;
        bool ret;
 
+       sdvox = I915_READ(intel_sdvo->sdvo_reg);
+
        ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
        if (!ret) {
                /* Some sdvo encoders are not spec compliant and don't
@@ -1376,7 +1378,6 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
         * other platfroms.
         */
        if (IS_I915G(dev) || IS_I915GM(dev)) {
-               sdvox = I915_READ(intel_sdvo->sdvo_reg);
                pipe_config->pixel_multiplier =
                        ((sdvox & SDVO_PORT_MULTIPLY_MASK)
                         >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
@@ -1405,6 +1406,9 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
                }
        }
 
+       if (sdvox & HDMI_COLOR_RANGE_16_235)
+               pipe_config->limited_color_range = true;
+
        WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
             "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
             pipe_config->pixel_multiplier, encoder_pixel_multiplier);