void __iomem *gpc_base;
void __iomem *ccm_base;
+static int cpu_silicon_rev = -1;
+#define SI_REV_OFFSET 0x48
+
+static int get_mx6q_srev(void)
+{
+ void __iomem *romcp = ioremap(BOOT_ROM_BASE_ADDR, SZ_8K);
+ u32 rev;
+
+ if (!romcp) {
+ cpu_silicon_rev = -EINVAL;
+ return 0;
+ }
+
+ rev = __raw_readl(romcp + SI_REV_OFFSET);
+ rev &= 0xff;
+
+ iounmap(romcp);
+ if (rev == 0x10)
+ return IMX_CHIP_REVISION_1_0;
+ else if (rev == 0x11)
+ return IMX_CHIP_REVISION_1_1;
+ else if (rev == 0x20)
+ return IMX_CHIP_REVISION_2_0;
+ return 0;
+}
+
+/*
+ * Returns:
+ * the silicon revision of the cpu
+ * -EINVAL - not a mx50
+ */
+int mx6q_revision(void)
+{
+ if (!cpu_is_mx6q())
+ return -EINVAL;
+
+ if (cpu_silicon_rev == -1)
+ cpu_silicon_rev = get_mx6q_srev();
+
+ return cpu_silicon_rev;
+}
+EXPORT_SYMBOL(mx6q_revision);
+
static int __init post_cpu_init(void)
{
unsigned int reg;
* This structure defines the MX6 memory map.
*/
static struct map_desc mx6_io_desc[] __initdata = {
+ {
+ .virtual = BOOT_ROM_BASE_ADDR_VIRT,
+ .pfn = __phys_to_pfn(BOOT_ROM_BASE_ADDR),
+ .length = ROMCP_SIZE,
+ .type = MT_DEVICE},
{
.virtual = AIPS1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(AIPS1_ARB_BASE_ADDR),
/* define virtual address */
#define PERIPBASE_VIRT 0xF2000000
+#define BOOT_ROM_BASE_ADDR_VIRT (PERIPBASE_VIRT + BOOT_ROM_BASE_ADDR)
#define AIPS1_BASE_ADDR_VIRT (PERIPBASE_VIRT + AIPS1_ARB_BASE_ADDR)
#define AIPS2_BASE_ADDR_VIRT (PERIPBASE_VIRT + AIPS2_ARB_BASE_ADDR)
#define ARM_PERIPHBASE_VIRT (PERIPBASE_VIRT + ARM_PERIPHBASE)
+#define ROMCP_SIZE SZ_1M
#define AIPS1_SIZE SZ_1M
#define AIPS2_SIZE SZ_1M
#define ARM_PERIPHBASE_SIZE (SZ_8K + SZ_4K)