ENGR00230981-2 pfuze:standby voltage increase for PFM

There is 6% tolerance for PFM momde in standby so we need set 0.975V(>0.9V+%6)
for VDDSOC and VDDARM which maybe impact system resume ability.
Another two change is:
1.set  VDDARM and VDDSOC standby voltage by setting PFUZE register directly,it
is not very friendly.So use more common  "state_mem" in constrain of regulator
to set standby voltage.
2.align sabreauto code with sabresd
Signed-off-by: Robin Gong <b38343@freescale.com>

diff --git a/arch/arm/mach-mx6/mx6q_sabreauto_pmic_pfuze100.c b/arch/arm/mach-mx6/mx6q_sabreauto_pmic_pfuze100.c
index 8cb4ffcc78fa0ed7732c2427472a8b9cb9bffe4e..3987777d56ff568ee6abed28203157c0e4a06093 100644 (file)
--- a/arch/arm/mach-mx6/mx6q_sabreauto_pmic_pfuze100.c
+++ b/arch/arm/mach-mx6/mx6q_sabreauto_pmic_pfuze100.c
@@ -24,7 +24,11 @@
 #include <linux/gpio.h>
 #include <linux/regulator/machine.h>
 #include <linux/mfd/pfuze.h>
+#include <linux/io.h>
 #include <mach/irqs.h>
+#include "crm_regs.h"
+#include "regs-anadig.h"
+#include "cpu_op-mx6.h"
 
 /*
  * Convenience conversion.
@@ -38,32 +42,21 @@
 #define PFUZE100_I2C_DEVICE_NAME  "pfuze100"
 /* 7-bit I2C bus slave address */
 #define PFUZE100_I2C_ADDR         (0x08)
-
- /*SWBST*/
-#define PFUZE100_SW1ASTANDBY    33
-#define PFUZE100_SW1ASTANDBY_STBY_VAL   (0x19)
-#define PFUZE100_SW1ASTANDBY_STBY_M     (0x3f<<0)
-#define PFUZE100_SW1BSTANDBY   40
-#define PFUZE100_SW1BSTANDBY_STBY_VAL  (0x19)
-#define PFUZE100_SW1BSTANDBY_STBY_M    (0x3f<<0)
-#define PFUZE100_SW1CSTANDBY    47
-#define PFUZE100_SW1CSTANDBY_STBY_VAL   (0x19)
-#define PFUZE100_SW1CSTANDBY_STBY_M     (0x3f<<0)
-#define PFUZE100_SW2STANDBY     54
-#define PFUZE100_SW2STANDBY_STBY_VAL    0x0
-#define PFUZE100_SW2STANDBY_STBY_M      (0x3f<<0)
-#define PFUZE100_SW3ASTANDBY    61
-#define PFUZE100_SW3ASTANDBY_STBY_VAL   0x0
-#define PFUZE100_SW3ASTANDBY_STBY_M     (0x3f<<0)
-#define PFUZE100_SW3BSTANDBY    68
-#define PFUZE100_SW3BSTANDBY_STBY_VAL   0x0
-#define PFUZE100_SW3BSTANDBY_STBY_M     (0x3f<<0)
-#define PFUZE100_SW4STANDBY     75
-#define PFUZE100_SW4STANDBY_STBY_VAL    0
-#define PFUZE100_SW4STANDBY_STBY_M      (0x3f<<0)
-#define PFUZE100_SWBSTCON1      102
-#define PFUZE100_SWBSTCON1_SWBSTMOD_VAL (0x1<<2)
-#define PFUZE100_SWBSTCON1_SWBSTMOD_M   (0x3<<2)
+#define PFUZE100_DEVICEID              (0x0)
+#define PFUZE100_REVID                 (0x3)
+#define PFUZE100_SW1AMODE              (0x23)
+#define PFUZE100_SW1AVOL       32
+#define PFUZE100_SW1AVOL_VSEL_M        (0x3f<<0)
+#define PFUZE100_SW1CVOL       46
+#define PFUZE100_SW1CVOL_VSEL_M        (0x3f<<0)
+#define PFUZE100_SW1ACON               36
+#define PFUZE100_SW1ACON_SPEED_VAL     (0x1<<6)        /*default */
+#define PFUZE100_SW1ACON_SPEED_M       (0x3<<6)
+#define PFUZE100_SW1CCON               49
+#define PFUZE100_SW1CCON_SPEED_VAL     (0x1<<6)        /*default */
+#define PFUZE100_SW1CCON_SPEED_M       (0x3<<6)
+
+extern u32 arm_max_freq;
 
 static struct regulator_consumer_supply sw1a_consumers[] = {
        {
@@ -157,7 +150,13 @@ static struct regulator_init_data sw1a_init = {
                        .valid_modes_mask = 0,
                        .boot_on = 1,
                        .always_on = 1,
+                       .initial_state = PM_SUSPEND_MEM,
+                       .state_mem = {
+                               .uV = 975000,/*0.9V+6%*/
+                               .mode = REGULATOR_MODE_NORMAL,
+                               .enabled = 1,
                        },
+       },
        .num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
        .consumer_supplies = sw1a_consumers,
 };
@@ -183,7 +182,13 @@ static struct regulator_init_data sw1c_init = {
                        .valid_modes_mask = 0,
                        .always_on = 1,
                        .boot_on = 1,
+                       .initial_state = PM_SUSPEND_MEM,
+                       .state_mem = {
+                               .uV = 975000,/*0.9V+6%*/
+                               .mode = REGULATOR_MODE_NORMAL,
+                               .enabled = 1,
                        },
+       },
        .num_consumer_supplies = ARRAY_SIZE(sw1c_consumers),
        .consumer_supplies = sw1c_consumers,
 };
@@ -391,20 +396,82 @@ static struct regulator_init_data vgen6_init = {
 
 static int pfuze100_init(struct mc_pfuze *pfuze)
 {
-       int ret;
-       ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ASTANDBY,
-                           PFUZE100_SW1ASTANDBY_STBY_M,
-                           PFUZE100_SW1ASTANDBY_STBY_VAL);
+       int ret, i;
+       unsigned int reg;
+       unsigned char value;
+       /*read Device ID*/
+       ret = pfuze_reg_read(pfuze, PFUZE100_DEVICEID, &value);
+       if (ret)
+               goto err;
+       if (value != 0x10) {
+               printk(KERN_ERR "wrong device id:%x!\n", value);
+               goto err;
+       }
+
+       /*read Revision ID*/
+       ret = pfuze_reg_read(pfuze, PFUZE100_REVID, &value);
        if (ret)
                goto err;
-       ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1BSTANDBY,
-                           PFUZE100_SW1BSTANDBY_STBY_M,
-                           PFUZE100_SW1BSTANDBY_STBY_VAL);
+       if (value == 0x10) {
+               printk(KERN_WARNING "PF100 1.0 chip found!\n");
+       /* workaround ER1 of pfuze1.0: set all buck regulators in PWM mode
+       * except SW1C(APS) in normal and  PFM mode in standby.
+       */
+               for (i = 0; i < 7; i++) {
+                       if (i == 2)/*SW1C*/
+                               value = 0xc;/*normal:APS mode;standby:PFM mode*/
+                       else
+                               value = 0xd;/*normal:PWM mode;standby:PFM mode*/
+                       ret = pfuze_reg_write(pfuze,
+                                       PFUZE100_SW1AMODE + (i * 7),
+                                       value);
+                       if (ret)
+                               goto err;
+               }
+
+       } else {
+       /*set all switches APS in normal and PFM mode in standby*/
+               for (i = 0; i < 7; i++) {
+                       value = 0xc;
+                       ret = pfuze_reg_write(pfuze,
+                                       PFUZE100_SW1AMODE + (i * 7),
+                                       value);
+                       if (ret)
+                               goto err;
+               }
+
+       }
+       if (arm_max_freq == CPU_AT_1_2GHz) {
+               /*VDDARM_IN 1.475V*/
+               ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1AVOL,
+                                       PFUZE100_SW1AVOL_VSEL_M,
+                                       0x2f);
+               if (ret)
+                       goto err;
+               /*VDDSOC_IN 1.475V*/
+               ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CVOL,
+                                       PFUZE100_SW1CVOL_VSEL_M,
+                                       0x2f);
+               if (ret)
+                       goto err;
+               /*set VDDSOC&VDDPU to 1.25V*/
+               reg = __raw_readl(ANADIG_REG_CORE);
+               reg &= ~BM_ANADIG_REG_CORE_REG2_TRG;
+               reg |= BF_ANADIG_REG_CORE_REG2_TRG(0x16);
+               reg &= ~BM_ANADIG_REG_CORE_REG1_TRG;
+               reg |= BF_ANADIG_REG_CORE_REG1_TRG(0x16);
+               __raw_writel(reg, ANADIG_REG_CORE);
+
+       }
+       /*set SW1AB/1C DVSPEED as 25mV step each 4us,quick than 16us before.*/
+       ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON,
+                           PFUZE100_SW1ACON_SPEED_M,
+                           PFUZE100_SW1ACON_SPEED_VAL);
        if (ret)
                goto err;
-       ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CSTANDBY,
-                           PFUZE100_SW1CSTANDBY_STBY_M,
-                           PFUZE100_SW1CSTANDBY_STBY_VAL);
+       ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CCON,
+                           PFUZE100_SW1CCON_SPEED_M,
+                           PFUZE100_SW1CCON_SPEED_VAL);
        if (ret)
                goto err;
        return 0;

diff --git a/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c b/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c
index cbde44955f03c25ef5b06f8edaf289bf5c4a245f..6b38bd000bc0d1b5a723bb83eae99a8deba0abf1 100644 (file)
--- a/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c
+++ b/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c
@@ -41,36 +41,14 @@
 
 #define PFUZE100_I2C_DEVICE_NAME  "pfuze100"
 /* 7-bit I2C bus slave address */
-#define PFUZE100_I2C_ADDR         (0x08)
- /*SWBST*/
-#define PFUZE100_SW1AVOL       32
-#define PFUZE100_SW1AVOL_VSEL_M        (0x3f<<0)
-#define PFUZE100_SW1CVOL       46
-#define PFUZE100_SW1CVOL_VSEL_M        (0x3f<<0)
-#define PFUZE100_SW1ASTANDBY   33
-#define PFUZE100_SW1ASTANDBY_STBY_VAL  (0x19)
-#define PFUZE100_SW1ASTANDBY_STBY_M    (0x3f<<0)
-#define PFUZE100_SW1BSTANDBY   40
-#define PFUZE100_SW1BSTANDBY_STBY_VAL  (0x19)
-#define PFUZE100_SW1BSTANDBY_STBY_M    (0x3f<<0)
-#define PFUZE100_SW1CSTANDBY   47
-#define PFUZE100_SW1CSTANDBY_STBY_VAL  (0x19)
-#define PFUZE100_SW1CSTANDBY_STBY_M    (0x3f<<0)
-#define PFUZE100_SW2STANDBY     54
-#define PFUZE100_SW2STANDBY_STBY_VAL    0x0
-#define PFUZE100_SW2STANDBY_STBY_M      (0x3f<<0)
-#define PFUZE100_SW3ASTANDBY    61
-#define PFUZE100_SW3ASTANDBY_STBY_VAL   0x0
-#define PFUZE100_SW3ASTANDBY_STBY_M     (0x3f<<0)
-#define PFUZE100_SW3BSTANDBY    68
-#define PFUZE100_SW3BSTANDBY_STBY_VAL   0x0
-#define PFUZE100_SW3BSTANDBY_STBY_M     (0x3f<<0)
-#define PFUZE100_SW4STANDBY     75
-#define PFUZE100_SW4STANDBY_STBY_VAL    0
-#define PFUZE100_SW4STANDBY_STBY_M      (0x3f<<0)
-#define PFUZE100_SWBSTCON1     102
-#define PFUZE100_SWBSTCON1_SWBSTMOD_VAL        (0x1<<2)
-#define PFUZE100_SWBSTCON1_SWBSTMOD_M  (0x3<<2)
+#define PFUZE100_I2C_ADDR              (0x08)
+#define PFUZE100_DEVICEID              (0x0)
+#define PFUZE100_REVID                 (0x3)
+#define PFUZE100_SW1AMODE              (0x23)
+#define PFUZE100_SW1AVOL       32
+#define PFUZE100_SW1AVOL_VSEL_M        (0x3f<<0)
+#define PFUZE100_SW1CVOL       46
+#define PFUZE100_SW1CVOL_VSEL_M        (0x3f<<0)
 #define PFUZE100_SW1ACON               36
 #define PFUZE100_SW1ACON_SPEED_VAL     (0x1<<6)        /*default */
 #define PFUZE100_SW1ACON_SPEED_M       (0x3<<6)
@@ -166,7 +144,13 @@ static struct regulator_init_data sw1a_init = {
                        .valid_modes_mask = 0,
                        .boot_on = 1,
                        .always_on = 1,
+                       .initial_state = PM_SUSPEND_MEM,
+                       .state_mem = {
+                               .uV = 975000,/*0.9V+6%*/
+                               .mode = REGULATOR_MODE_NORMAL,
+                               .enabled = 1,
                        },
+       },
 
 #ifdef CONFIG_MX6_INTER_LDO_BYPASS
        .num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
@@ -195,7 +179,13 @@ static struct regulator_init_data sw1c_init = {
                        .valid_modes_mask = 0,
                        .always_on = 1,
                        .boot_on = 1,
+                       .initial_state = PM_SUSPEND_MEM,
+                       .state_mem = {
+                               .uV = 975000,/*0.9V+6%*/
+                               .mode = REGULATOR_MODE_NORMAL,
+                               .enabled = 1,
                        },
+       },
 #ifdef CONFIG_MX6_INTER_LDO_BYPASS
        .num_consumer_supplies = ARRAY_SIZE(sw1c_consumers),
        .consumer_supplies = sw1c_consumers,
@@ -399,8 +389,52 @@ static struct regulator_init_data vgen6_init = {
 
 static int pfuze100_init(struct mc_pfuze *pfuze)
 {
-       int ret;
+       int ret, i;
        unsigned int reg;
+       unsigned char value;
+       /*read Device ID*/
+       ret = pfuze_reg_read(pfuze, PFUZE100_DEVICEID, &value);
+       if (ret)
+               goto err;
+       if (value != 0x10) {
+               printk(KERN_ERR "wrong device id:%x!\n", value);
+               goto err;
+       }
+
+       /*read Revision ID*/
+       ret = pfuze_reg_read(pfuze, PFUZE100_REVID, &value);
+       if (ret)
+               goto err;
+       if (value == 0x10) {
+               printk(KERN_WARNING "PF100 1.0 chip found!\n");
+       /* workaround ER1 of pfuze1.0: set all buck regulators in PWM mode
+       * except SW1C(APS) in normal and  PFM mode in standby.
+       */
+               for (i = 0; i < 7; i++) {
+                       if (i == 2)/*SW1C*/
+                               value = 0xc;/*normal:APS mode;standby:PFM mode*/
+                       else
+                               value = 0xd;/*normal:PWM mode;standby:PFM mode*/
+                       ret = pfuze_reg_write(pfuze,
+                                       PFUZE100_SW1AMODE + (i * 7),
+                                       value);
+                       if (ret)
+                               goto err;
+               }
+
+       } else {
+       /*set all switches APS in normal and PFM mode in standby*/
+               for (i = 0; i < 7; i++) {
+                       value = 0xc;
+                       ret = pfuze_reg_write(pfuze,
+                                       PFUZE100_SW1AMODE + (i * 7),
+                                       value);
+                       if (ret)
+                               goto err;
+               }
+
+       }
+
        if (arm_max_freq == CPU_AT_1_2GHz) {
                /*VDDARM_IN 1.475V*/
                ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1AVOL,
@@ -423,16 +457,6 @@ static int pfuze100_init(struct mc_pfuze *pfuze)
                __raw_writel(reg, ANADIG_REG_CORE);
 
        }
-       ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ASTANDBY,
-                           PFUZE100_SW1ASTANDBY_STBY_M,
-                           PFUZE100_SW1ASTANDBY_STBY_VAL);
-       if (ret)
-               goto err;
-       ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CSTANDBY,
-                           PFUZE100_SW1CSTANDBY_STBY_M,
-                           PFUZE100_SW1CSTANDBY_STBY_VAL);
-       if (ret)
-               goto err;
        /*set SW1AB/1C DVSPEED as 25mV step each 4us,quick than 16us before.*/
        ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON,
                            PFUZE100_SW1ACON_SPEED_M,

diff --git a/arch/arm/mach-mx6/mx6sl_arm2_pmic_pfuze100.c b/arch/arm/mach-mx6/mx6sl_arm2_pmic_pfuze100.c
index 5cf34073bdc11115b6ad61ab75e46bebdc52d158..55a802b76b682485989925bb905325ed9ebdcee1 100644 (file)
--- a/arch/arm/mach-mx6/mx6sl_arm2_pmic_pfuze100.c
+++ b/arch/arm/mach-mx6/mx6sl_arm2_pmic_pfuze100.c
@@ -38,31 +38,9 @@
 #define PFUZE100_I2C_DEVICE_NAME  "pfuze100"
 /* 7-bit I2C bus slave address */
 #define PFUZE100_I2C_ADDR         (0x08)
- /*SWBST*/
-#define PFUZE100_SW1ASTANDBY   33
-#define PFUZE100_SW1ASTANDBY_STBY_VAL  (0x19)  /* 925mV */
-#define PFUZE100_SW1ASTANDBY_STBY_M    (0x3f<<0)
-#define PFUZE100_SW1BSTANDBY   40
-#define PFUZE100_SW1BSTANDBY_STBY_VAL  (0x19)  /* 925mV */
-#define PFUZE100_SW1BSTANDBY_STBY_M    (0x3f<<0)
-#define PFUZE100_SW1CSTANDBY   47
-#define PFUZE100_SW1CSTANDBY_STBY_VAL  (0x19)  /* 925mV */
-#define PFUZE100_SW1CSTANDBY_STBY_M    (0x3f<<0)
-#define PFUZE100_SW2STANDBY     54
-#define PFUZE100_SW2STANDBY_STBY_VAL    0x0
-#define PFUZE100_SW2STANDBY_STBY_M      (0x3f<<0)
-#define PFUZE100_SW3ASTANDBY    61
-#define PFUZE100_SW3ASTANDBY_STBY_VAL   0x0
-#define PFUZE100_SW3ASTANDBY_STBY_M     (0x3f<<0)
-#define PFUZE100_SW3BSTANDBY    68
-#define PFUZE100_SW3BSTANDBY_STBY_VAL   0x0
-#define PFUZE100_SW3BSTANDBY_STBY_M     (0x3f<<0)
-#define PFUZE100_SW4STANDBY     75
-#define PFUZE100_SW4STANDBY_STBY_VAL    0
-#define PFUZE100_SW4STANDBY_STBY_M      (0x3f<<0)
-#define PFUZE100_SWBSTCON1     102
-#define PFUZE100_SWBSTCON1_SWBSTMOD_VAL        (0x1<<2)
-#define PFUZE100_SWBSTCON1_SWBSTMOD_M  (0x3<<2)
+#define PFUZE100_DEVICEID              (0x0)
+#define PFUZE100_REVID                 (0x3)
+#define PFUZE100_SW1AMODE              (0x23)
 #define PFUZE100_SW1ACON               36
 #define PFUZE100_SW1ACON_SPEED_VAL     (0x1<<6)        /*default */
 #define PFUZE100_SW1ACON_SPEED_M       (0x3<<6)
@@ -158,7 +136,13 @@ static struct regulator_init_data sw1a_init = {
                        .valid_modes_mask = 0,
                        .boot_on = 1,
                        .always_on = 1,
+                       .initial_state = PM_SUSPEND_MEM,
+                       .state_mem = {
+                               .uV = 975000,/*0.9V+6%*/
+                               .mode = REGULATOR_MODE_NORMAL,
+                               .enabled = 1,
                        },
+       },
 #ifdef CONFIG_MX6_INTER_LDO_BYPASS
        .num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
        .consumer_supplies = sw1_consumers,
@@ -186,7 +170,13 @@ static struct regulator_init_data sw1c_init = {
                        .valid_modes_mask = 0,
                        .always_on = 1,
                        .boot_on = 1,
+                       .initial_state = PM_SUSPEND_MEM,
+                       .state_mem = {
+                               .uV = 975000,/*0.9V+6%*/
+                               .mode = REGULATOR_MODE_NORMAL,
+                               .enabled = 1,
                        },
+       },
        #ifdef CONFIG_MX6_INTER_LDO_BYPASS
        .num_consumer_supplies = ARRAY_SIZE(sw1c_consumers),
        .consumer_supplies = sw1c_consumers,
@@ -392,17 +382,51 @@ static struct regulator_init_data vgen6_init = {
 
 static int pfuze100_init(struct mc_pfuze *pfuze)
 {
-       int ret;
-       ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ASTANDBY,
-                           PFUZE100_SW1ASTANDBY_STBY_M,
-                           PFUZE100_SW1ASTANDBY_STBY_VAL);
+       int ret, i;
+       unsigned int reg;
+       unsigned char value;
+       /*read Device ID*/
+       ret = pfuze_reg_read(pfuze, PFUZE100_DEVICEID, &value);
        if (ret)
                goto err;
-       ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CSTANDBY,
-                           PFUZE100_SW1CSTANDBY_STBY_M,
-                           PFUZE100_SW1CSTANDBY_STBY_VAL);
+       if (value != 0x10) {
+               printk(KERN_ERR "wrong device id:%x!\n", value);
+               goto err;
+       }
+
+       /*read Revision ID*/
+       ret = pfuze_reg_read(pfuze, PFUZE100_REVID, &value);
        if (ret)
                goto err;
+       if (value == 0x10) {
+               printk(KERN_WARNING "PF100 1.0 chip found!\n");
+       /* workaround ER1 of pfuze1.0: set all buck regulators in PWM mode
+       * except SW1C(APS) in normal and  PFM mode in standby.
+       */
+               for (i = 0; i < 7; i++) {
+                       if (i == 2)/*SW1C*/
+                               value = 0xc;/*normal:APS mode;standby:PFM mode*/
+                       else
+                               value = 0xd;/*normal:PWM mode;standby:PFM mode*/
+                       ret = pfuze_reg_write(pfuze,
+                                       PFUZE100_SW1AMODE + (i * 7),
+                                       value);
+                       if (ret)
+                               goto err;
+               }
+
+       } else {
+       /*set all switches APS in normal and PFM mode in standby*/
+               for (i = 0; i < 7; i++) {
+                       value = 0xc;
+                       ret = pfuze_reg_write(pfuze,
+                                       PFUZE100_SW1AMODE + (i * 7),
+                                       value);
+                       if (ret)
+                               goto err;
+               }
+
+       }
        /*set SW1AB/SW1C DVSPEED as 25mV step each 4us,quick than 16us before.*/
        ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON,
                            PFUZE100_SW1ACON_SPEED_M,

diff --git a/arch/arm/mach-mx6/mx6sl_evk_pmic_pfuze100.c b/arch/arm/mach-mx6/mx6sl_evk_pmic_pfuze100.c
index 981d149d7aeeb790d610045b9f34abb9a6090338..bfd5fafc1d1b388d59d1efbd7284080ec3aedf0a 100644 (file)
--- a/arch/arm/mach-mx6/mx6sl_evk_pmic_pfuze100.c
+++ b/arch/arm/mach-mx6/mx6sl_evk_pmic_pfuze100.c
@@ -38,31 +38,9 @@
 #define PFUZE100_I2C_DEVICE_NAME  "pfuze100"
 /* 7-bit I2C bus slave address */
 #define PFUZE100_I2C_ADDR         (0x08)
- /*SWBST*/
-#define PFUZE100_SW1ASTANDBY   33
-#define PFUZE100_SW1ASTANDBY_STBY_VAL  (0x19)  /* 925mv */
-#define PFUZE100_SW1ASTANDBY_STBY_M    (0x3f<<0)
-#define PFUZE100_SW1BSTANDBY   40
-#define PFUZE100_SW1BSTANDBY_STBY_VAL  (0x19)  /* 925mv */
-#define PFUZE100_SW1BSTANDBY_STBY_M    (0x3f<<0)
-#define PFUZE100_SW1CSTANDBY   47
-#define PFUZE100_SW1CSTANDBY_STBY_VAL  (0x19)  /* 925mv */
-#define PFUZE100_SW1CSTANDBY_STBY_M    (0x3f<<0)
-#define PFUZE100_SW2STANDBY     54
-#define PFUZE100_SW2STANDBY_STBY_VAL    0x0
-#define PFUZE100_SW2STANDBY_STBY_M      (0x3f<<0)
-#define PFUZE100_SW3ASTANDBY    61
-#define PFUZE100_SW3ASTANDBY_STBY_VAL   0x0
-#define PFUZE100_SW3ASTANDBY_STBY_M     (0x3f<<0)
-#define PFUZE100_SW3BSTANDBY    68
-#define PFUZE100_SW3BSTANDBY_STBY_VAL   0x0
-#define PFUZE100_SW3BSTANDBY_STBY_M     (0x3f<<0)
-#define PFUZE100_SW4STANDBY     75
-#define PFUZE100_SW4STANDBY_STBY_VAL    0
-#define PFUZE100_SW4STANDBY_STBY_M      (0x3f<<0)
-#define PFUZE100_SWBSTCON1     102
-#define PFUZE100_SWBSTCON1_SWBSTMOD_VAL        (0x1<<2)
-#define PFUZE100_SWBSTCON1_SWBSTMOD_M  (0x3<<2)
+#define PFUZE100_DEVICEID              (0x0)
+#define PFUZE100_REVID                 (0x3)
+#define PFUZE100_SW1AMODE              (0x23)
 #define PFUZE100_SW1ACON               36
 #define PFUZE100_SW1ACON_SPEED_VAL     (0x1<<6)        /*default */
 #define PFUZE100_SW1ACON_SPEED_M       (0x3<<6)
@@ -161,7 +139,13 @@ static struct regulator_init_data sw1a_init = {
                        .valid_modes_mask = 0,
                        .boot_on = 1,
                        .always_on = 1,
+                       .initial_state = PM_SUSPEND_MEM,
+                       .state_mem = {
+                               .uV = 975000,/*0.9V+6%*/
+                               .mode = REGULATOR_MODE_NORMAL,
+                               .enabled = 1,
                        },
+       },
 #ifdef CONFIG_MX6_INTER_LDO_BYPASS
        .num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
        .consumer_supplies = sw1_consumers,
@@ -189,7 +173,13 @@ static struct regulator_init_data sw1c_init = {
                        .valid_modes_mask = 0,
                        .always_on = 1,
                        .boot_on = 1,
+                       .initial_state = PM_SUSPEND_MEM,
+                       .state_mem = {
+                               .uV = 975000,/*0.9V+6%*/
+                               .mode = REGULATOR_MODE_NORMAL,
+                               .enabled = 1,
                        },
+       },
 #ifdef CONFIG_MX6_INTER_LDO_BYPASS
        .num_consumer_supplies = ARRAY_SIZE(sw1c_consumers),
        .consumer_supplies = sw1c_consumers,
@@ -397,17 +387,52 @@ static struct regulator_init_data vgen6_init = {
 
 static int pfuze100_init(struct mc_pfuze *pfuze)
 {
-       int ret;
-       ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ASTANDBY,
-                           PFUZE100_SW1ASTANDBY_STBY_M,
-                           PFUZE100_SW1ASTANDBY_STBY_VAL);
+       int ret, i;
+       unsigned int reg;
+       unsigned char value;
+       /*read Device ID*/
+       ret = pfuze_reg_read(pfuze, PFUZE100_DEVICEID, &value);
        if (ret)
                goto err;
-       ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CSTANDBY,
-                           PFUZE100_SW1CSTANDBY_STBY_M,
-                           PFUZE100_SW1CSTANDBY_STBY_VAL);
+       if (value != 0x10) {
+               printk(KERN_ERR "wrong device id:%x!\n", value);
+               goto err;
+       }
+
+       /*read Revision ID*/
+       ret = pfuze_reg_read(pfuze, PFUZE100_REVID, &value);
        if (ret)
                goto err;
+       if (value == 0x10) {
+               printk(KERN_WARNING "PF100 1.0 chip found!\n");
+       /* workaround ER1 of pfuze1.0: set all buck regulators in PWM mode
+       * except SW1C(APS) in normal and  PFM mode in standby.
+       */
+               for (i = 0; i < 7; i++) {
+                       if (i == 2)/*SW1C*/
+                               value = 0xc;/*normal:APS mode;standby:PFM mode*/
+                       else
+                               value = 0xd;/*normal:PWM mode;standby:PFM mode*/
+                       ret = pfuze_reg_write(pfuze,
+                                       PFUZE100_SW1AMODE + (i * 7),
+                                       value);
+                       if (ret)
+                               goto err;
+               }
+
+       } else {
+       /*set all switches APS in normal and PFM mode in standby*/
+               for (i = 0; i < 7; i++) {
+                       value = 0xc;
+                       ret = pfuze_reg_write(pfuze,
+                                       PFUZE100_SW1AMODE + (i * 7),
+                                       value);
+                       if (ret)
+                               goto err;
+               }
+
+       }
+
        /*set SW1AB/SW1CDVSPEED as 25mV step each 4us,quick than 16us before.*/
        ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON,
                            PFUZE100_SW1ACON_SPEED_M,