imx/clock-imx27: use a macro to define registers

This way the base address isn't hard coded in each register definition

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Rabin Vincent <rabin@rab.in>
Cc: Javier Martin <javier.martin@vista-silicon.com>
Cc: Valentin Longchamp <valentin.longchamp@epfl.ch>

diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c
index b010bf9ceaaba1f4d18168fccdc31de2d7d26d2e..a53320860986bbfaaf071edbfc2c193fc7fd10ff 100644 (file)
--- a/arch/arm/mach-mx2/clock_imx27.c
+++ b/arch/arm/mach-mx2/clock_imx27.c
@@ -29,21 +29,23 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 
+#define IO_ADDR_CCM(off)       (IO_ADDRESS(CCM_BASE_ADDR) + (off))
+
 /* Register offsets */
-#define CCM_CSCR                (IO_ADDRESS(CCM_BASE_ADDR) + 0x0)
-#define CCM_MPCTL0              (IO_ADDRESS(CCM_BASE_ADDR) + 0x4)
-#define CCM_MPCTL1              (IO_ADDRESS(CCM_BASE_ADDR) + 0x8)
-#define CCM_SPCTL0              (IO_ADDRESS(CCM_BASE_ADDR) + 0xC)
-#define CCM_SPCTL1              (IO_ADDRESS(CCM_BASE_ADDR) + 0x10)
-#define CCM_OSC26MCTL           (IO_ADDRESS(CCM_BASE_ADDR) + 0x14)
-#define CCM_PCDR0               (IO_ADDRESS(CCM_BASE_ADDR) + 0x18)
-#define CCM_PCDR1               (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c)
-#define CCM_PCCR0               (IO_ADDRESS(CCM_BASE_ADDR) + 0x20)
-#define CCM_PCCR1               (IO_ADDRESS(CCM_BASE_ADDR) + 0x24)
-#define CCM_CCSR                (IO_ADDRESS(CCM_BASE_ADDR) + 0x28)
-#define CCM_PMCTL               (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c)
-#define CCM_PMCOUNT             (IO_ADDRESS(CCM_BASE_ADDR) + 0x30)
-#define CCM_WKGDCTL             (IO_ADDRESS(CCM_BASE_ADDR) + 0x34)
+#define CCM_CSCR               IO_ADDR_CCM(0x0)
+#define CCM_MPCTL0             IO_ADDR_CCM(0x4)
+#define CCM_MPCTL1             IO_ADDR_CCM(0x8)
+#define CCM_SPCTL0             IO_ADDR_CCM(0xc)
+#define CCM_SPCTL1             IO_ADDR_CCM(0x10)
+#define CCM_OSC26MCTL          IO_ADDR_CCM(0x14)
+#define CCM_PCDR0              IO_ADDR_CCM(0x18)
+#define CCM_PCDR1              IO_ADDR_CCM(0x1c)
+#define CCM_PCCR0              IO_ADDR_CCM(0x20)
+#define CCM_PCCR1              IO_ADDR_CCM(0x24)
+#define CCM_CCSR               IO_ADDR_CCM(0x28)
+#define CCM_PMCTL              IO_ADDR_CCM(0x2c)
+#define CCM_PMCOUNT            IO_ADDR_CCM(0x30)
+#define CCM_WKGDCTL            IO_ADDR_CCM(0x34)
 
 #define CCM_CSCR_UPDATE_DIS    (1 << 31)
 #define CCM_CSCR_SSI2          (1 << 23)