ENGR00182243 [MX6]Fix suspend/resume issue

When there is pending wake up source before SOC enter DSM,
we should restore DDR IO and enable cache then return. Previous
code break r2 register which keep the iram stack addr, will
lead to DDR IO restore fail, need to avoid it.

Signed-off-by: Anson Huang <b20788@freescale.com>

diff --git a/arch/arm/mach-mx6/mx6q_suspend.S b/arch/arm/mach-mx6/mx6q_suspend.S
index aca771eec24113bb04ff8720278e2fa4542b66bb..e52c66ad0151793f9f1ff05c3307be4bd5afddfe 100644 (file)
--- a/arch/arm/mach-mx6/mx6q_suspend.S
+++ b/arch/arm/mach-mx6/mx6q_suspend.S
@@ -579,17 +579,17 @@ ddr_iomux_save:
        stmfd   r0!, {r4}
 
 #ifdef CONFIG_CACHE_L2X0
-       ldr r2, =L2_BASE_ADDR
-       add r2, r2, #PERIPBASE_VIRT
+       ldr r1, =L2_BASE_ADDR
+       add r1, r1, #PERIPBASE_VIRT
 
-       ldr     r4, [r2, #L2X0_CTRL]
-       ldr     r5, [r2, #L2X0_AUX_CTRL]
-       ldr     r6, [r2, #L2X0_TAG_LATENCY_CTRL]
-       ldr     r7, [r2, #L2X0_DATA_LATENCY_CTRL]
+       ldr     r4, [r1, #L2X0_CTRL]
+       ldr     r5, [r1, #L2X0_AUX_CTRL]
+       ldr     r6, [r1, #L2X0_TAG_LATENCY_CTRL]
+       ldr     r7, [r1, #L2X0_DATA_LATENCY_CTRL]
        stmfd   r0!, {r4-r7}
 
-       ldr     r4, [r2, #L2X0_PREFETCH_CTRL]
-       ldr     r5, [r2, #L2X0_POWER_CTRL]
+       ldr     r4, [r1, #L2X0_PREFETCH_CTRL]
+       ldr     r5, [r1, #L2X0_POWER_CTRL]
        stmfd   r0!, {r4-r5}
 #endif