ARM: fix bad applied patch for arch/arm/Kconfig of stable 3.0.y tree.

No upstream commit as this is a merge error in the 3.0 tree.

ARM_ERRATA_764369 and PL310_ERRATA_769419 do not appear in config menu in
stable 3.0.y tree.
This is because backported patch for arm/arm/Kconfig applied wrong place.
This patch solves it.

Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index fad8e7205d83ab93369a4bf313f74c2d7757f51b..157781eba8103669202f753cf15e264262f6282d 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1234,6 +1234,32 @@ config ARM_ERRATA_754327
          This workaround defines cpu_relax() as smp_mb(), preventing correctly
          written polling loops from denying visibility of updates to memory.
 
+config ARM_ERRATA_764369
+       bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
+       depends on CPU_V7 && SMP
+       help
+         This option enables the workaround for erratum 764369
+         affecting Cortex-A9 MPCore with two or more processors (all
+         current revisions). Under certain timing circumstances, a data
+         cache line maintenance operation by MVA targeting an Inner
+         Shareable memory region may fail to proceed up to either the
+         Point of Coherency or to the Point of Unification of the
+         system. This workaround adds a DSB instruction before the
+         relevant cache maintenance functions and sets a specific bit
+         in the diagnostic control register of the SCU.
+
+config PL310_ERRATA_769419
+       bool "PL310 errata: no automatic Store Buffer drain"
+       depends on CACHE_L2X0
+       help
+         On revisions of the PL310 prior to r3p2, the Store Buffer does
+         not automatically drain. This can cause normal, non-cacheable
+         writes to be retained when the memory system is idle, leading
+         to suboptimal I/O performance for drivers using coherent DMA.
+         This option adds a write barrier to the cpu_idle loop so that,
+         on systems with an outer cache, the store buffer is drained
+         explicitly.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
@@ -1298,32 +1324,6 @@ source "drivers/pci/Kconfig"
 
 source "drivers/pcmcia/Kconfig"
 
-config ARM_ERRATA_764369
-       bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
-       depends on CPU_V7 && SMP
-       help
-         This option enables the workaround for erratum 764369
-         affecting Cortex-A9 MPCore with two or more processors (all
-         current revisions). Under certain timing circumstances, a data
-         cache line maintenance operation by MVA targeting an Inner
-         Shareable memory region may fail to proceed up to either the
-         Point of Coherency or to the Point of Unification of the
-         system. This workaround adds a DSB instruction before the
-         relevant cache maintenance functions and sets a specific bit
-         in the diagnostic control register of the SCU.
-
-config PL310_ERRATA_769419
-       bool "PL310 errata: no automatic Store Buffer drain"
-       depends on CACHE_L2X0
-       help
-         On revisions of the PL310 prior to r3p2, the Store Buffer does
-         not automatically drain. This can cause normal, non-cacheable
-         writes to be retained when the memory system is idle, leading
-         to suboptimal I/O performance for drivers using coherent DMA.
-         This option adds a write barrier to the cpu_idle loop so that,
-         on systems with an outer cache, the store buffer is drained
-         explicitly.
-
 endmenu
 
 menu "Kernel Features"