ENGR00176177-1 Add irq count mechanism to interactive governor

Add irq count to CPUFreq as a freq change condition.
Because some devices' working mode is unable to issue
CPUFreq change because of low CPU loading, but the cpu
freq will impact these devices' performace significantly.

Interactive govervor will sample the cpu loading as well
as the irq count which is registered. If the
loading or the irq count exceed the threshold we set,
governor will issue an CPUFreq change request.

These devices' irq threshold and enable/disable can be modified
via /sys/devices/system/cpu/cpufreq/interactive/irq_scaling

echo 0xAABBBC to change the default setting as below
AA : irq number
BBB: threshold
C  :enable or disable

Currently only enable USDHC3, USDHC4, GPU, SATA and
USB by default, we can add device to the init struct which is
located in arch/arm/mach-mx6/irq.c.

Signed-off-by: Anson Huang <b20788@freescale.com>

diff --git a/arch/arm/mach-mx6/irq.c b/arch/arm/mach-mx6/irq.c
index 3d8f81bb6e28d63fbeb658085860cfab19c2ef1c..753767bfd7c4fd8ac90eb7f68f5c440fefcc66d4 100644 (file)
--- a/arch/arm/mach-mx6/irq.c
+++ b/arch/arm/mach-mx6/irq.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -23,10 +23,16 @@
 #include <linux/irq.h>
 #include <asm/hardware/gic.h>
 #include <mach/hardware.h>
+#ifdef CONFIG_CPU_FREQ_GOV_INTERACTIVE
+#include <linux/cpufreq.h>
+#endif
 
 int mx6q_register_gpios(void);
 unsigned int gpc_wake_irq[4];
 extern bool enable_wait_mode;
+#ifdef CONFIG_CPU_FREQ_GOV_INTERACTIVE
+extern int cpufreq_gov_irq_tuner_register(struct irq_tuner dbs_irq_tuner);
+#endif
 
 static int mx6_gic_irq_set_wake(struct irq_data *d, unsigned int enable)
 {
@@ -44,6 +50,34 @@ static int mx6_gic_irq_set_wake(struct irq_data *d, unsigned int enable)
        }
        return 0;
 }
+#ifdef CONFIG_CPU_FREQ_GOV_INTERACTIVE
+static struct irq_tuner mxc_irq_tuner[] = {
+       {
+        .irq_number = 41, /* GPU 3D */
+        .up_threshold = 0,
+        .enable = 1,},
+       {
+        .irq_number = 56, /* uSDHC3 */
+        .up_threshold = 8,
+        .enable = 1,},
+       {
+        .irq_number = 57, /* uSDHC4 */
+        .up_threshold = 8,
+        .enable = 1,},
+       {
+        .irq_number = 71, /* SATA */
+        .up_threshold = 4,
+        .enable = 1,},
+       {
+        .irq_number = 75, /* OTG */
+        .up_threshold = 10,
+        .enable = 1,},
+       {
+        .irq_number = 0, /* END */
+        .up_threshold = 0,
+        .enable = 0,},
+};
+#endif
 void mx6_init_irq(void)
 {
        void __iomem *gpc_base = IO_ADDRESS(GPC_BASE_ADDR);
@@ -72,4 +106,8 @@ void mx6_init_irq(void)
                desc->irq_data.chip->irq_set_wake = mx6_gic_irq_set_wake;
        }
        mx6q_register_gpios();
+#ifdef CONFIG_CPU_FREQ_GOV_INTERACTIVE
+       for (i = 0; i < ARRAY_SIZE(mxc_irq_tuner); i++)
+               cpufreq_gov_irq_tuner_register(mxc_irq_tuner[i]);
+#endif
 }