/* parse the enumeration rom to identify all cores */
static void ai_scan(struct si_pub *sih, struct chipcregs *cc)
{
- struct si_info *sii = SI_INFO(sih);
+ struct si_info *sii = (struct si_info *)sih;
+
u32 erombase, *eromptr, *eromlim;
void *regs = cc;
*/
void *ai_setcoreidx(struct si_pub *sih, uint coreidx)
{
- struct si_info *sii = SI_INFO(sih);
+ struct si_info *sii = (struct si_info *)sih;
u32 addr = sii->coresba[coreidx];
u32 wrap = sii->wrapba[coreidx];
struct si_info *sii;
uint cidx;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
cidx = sii->curidx;
if (asidx == 0)
struct si_info *sii;
uint cidx;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
cidx = sii->curidx;
if (asidx == 0)
struct si_info *sii;
struct aidmp *ai;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
ai = sii->curwrap;
return R_REG(&ai->oobselouta30) & 0x1f;
struct si_info *sii;
u32 cia;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
cia = sii->cia[sii->curidx];
return (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
}
struct si_info *sii;
u32 cib;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
cib = sii->cib[sii->curidx];
return (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
}
struct si_info *sii;
struct aidmp *ai;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
ai = sii->curwrap;
return (((R_REG(&ai->ioctrl) & (SICF_FGC | SICF_CLOCK_EN)) ==
struct aidmp *ai;
u32 w;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
ai = sii->curwrap;
struct aidmp *ai;
u32 w;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
ai = sii->curwrap;
if (mask || val) {
struct aidmp *ai;
u32 w;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
ai = sii->curwrap;
if (mask || val) {
struct si_pub *si_local = NULL;
memcpy(&si_local, &sih, sizeof(struct si_pub **));
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
if (sii == NULL)
return;
{
struct si_info *sii;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
sii->intr_arg = intr_arg;
sii->intrsoff_fn = (u32 (*)(void *)) intrsoff_fn;
sii->intrsrestore_fn = (void (*) (void *, u32)) intrsrestore_fn;
{
struct si_info *sii;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
sii->intrsoff_fn = NULL;
}
{
struct si_info *sii;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
return sii->coreid[sii->curidx];
}
{
struct si_info *sii;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
return sii->curidx;
}
uint found;
uint i;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
found = 0;
void *cc;
struct si_info *sii;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
if (SI_FAST(sii)) {
/* Overloading the origidx variable to remember the coreid,
{
struct si_info *sii;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
if (SI_FAST(sii)
&& ((coreid == CC_CORE_ID) || (coreid == sih->buscoretype)))
return;
void ai_write_wrapperreg(struct si_pub *sih, u32 offset, u32 val)
{
- struct si_info *sii = SI_INFO(sih);
+ struct si_info *sii = (struct si_info *)sih;
u32 *w = (u32 *) sii->curwrap;
W_REG(w + (offset / 4), val);
return;
bool fast = false;
struct si_info *sii;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
if (coreidx >= SI_MAXCORES)
return 0;
u32 dummy;
struct aidmp *ai;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
ai = sii->curwrap;
struct aidmp *ai;
u32 dummy;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
ai = sii->curwrap;
/*
if (!CCCTL_ENAB(sih))
return;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
fast = SI_FAST(sii);
if (!fast) {
origidx = sii->curidx;
uint intr_val = 0;
bool fast;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
if (PMUCTL_ENAB(sih)) {
INTR_OFF(sii, intr_val);
fpdelay = si_pmu_fast_pwrup_delay(sih);
struct si_info *sii;
u32 in, out, outen;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
/* pcie core doesn't have any mapping to control the xtal pu */
if (PCIE(sii))
{
struct si_info *sii;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
/* chipcommon cores prior to rev6 don't support dynamic clock control */
if (sih->ccrev < 6)
return -1;
slen = snprintf(path, (size_t) size, "pci/%u/%u/",
- (((SI_INFO(sih))->pbus))->bus->number,
- PCI_SLOT(((struct pci_dev *)((SI_INFO(sih))->pbus))->devfn));
+ ((struct si_info *)sih)->pbus->bus->number,
+ PCI_SLOT(((struct pci_dev *)
+ (((struct si_info *)(sih))->pbus))->devfn));
if (slen < 0 || slen >= size) {
path[0] = '\0';
{
struct si_info *sii;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
return PCI(sii) && (sih->buscorerev <= 10);
}
{
struct si_info *sii;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
if (PCI_FORCEHT(sii))
_ai_clkctl_cc(sii, CLK_FAST);
{
struct si_info *sii;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
pcicore_sleep(sii->pch);
}
{
struct si_info *sii;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
/* release FORCEHT since chip is going to "down" state */
if (PCI_FORCEHT(sii))
u32 siflag = 0, w;
uint idx = 0;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
if (PCI(sii)) {
/* get current core index */
{
uint origidx;
void *regs = NULL;
- struct si_info *sii = SI_INFO(sih);
+ struct si_info *sii = (struct si_info *)sih;
/* Fixup PI in SROM shadow area to enable the correct PCI core access */
/* save the current index */
uint origidx;
u32 val;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
origidx = ai_coreidx(sih);
cc = (struct chipcregs *) ai_setcore(sih, CC_CORE_ID, 0);
struct chipcregs *cc;
uint origidx;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
origidx = ai_coreidx(sih);
cc = ai_setcore(sih, CC_CORE_ID, 0);
u32 w;
struct si_info *sii;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
pci_read_config_dword(sii->pbus, PCI_VENDOR_ID, &w);
if ((w & 0xFFFF) != PCI_VENDOR_ID_BROADCOM)
if ((sih->cccaps & CC_CAP_SROM) == 0)
return false;
- sii = SI_INFO(sih);
+ sii = (struct si_info *)sih;
origidx = sii->curidx;
cc = ai_setcoreidx(sih, SI_CC_IDX);
sromctrl = R_REG(&cc->sromcontrol);