if (timed) {
for (i = 0; i < s->n_chan; ++i) {
- devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
+ devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED;
ni_writeb(dev, devpriv->ao_conf[i],
NI_M_AO_CFG_BANK_REG(i));
ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i));
conf = 0;
switch (krange->max - krange->min) {
case 20000000:
- conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
+ conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
break;
case 10000000:
- conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
+ conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
break;
case 4000000:
- conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
+ conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
ni_writeb(dev, MSeries_Attenuate_x5_Bit,
NI_M_AO_REF_ATTENUATION_REG(chan));
break;
case 2000000:
- conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
+ conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
ni_writeb(dev, MSeries_Attenuate_x5_Bit,
NI_M_AO_REF_ATTENUATION_REG(chan));
break;
}
switch (krange->max + krange->min) {
case 0:
- conf |= MSeries_AO_DAC_Offset_0V_Bits;
+ conf |= NI_M_AO_CFG_BANK_OFFSET_0V;
break;
case 10000000:
- conf |= MSeries_AO_DAC_Offset_5V_Bits;
+ conf |= NI_M_AO_CFG_BANK_OFFSET_5V;
break;
default:
dev_err(dev->class_dev,
break;
}
if (timed)
- conf |= MSeries_AO_Update_Timed_Bit;
+ conf |= NI_M_AO_CFG_BANK_UPDATE_TIMED;
ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan));
devpriv->ao_conf[chan] = conf;
ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan));
#define NI_M_DAC_DIRECT_DATA_REG(x) (0x0c0 + ((x) * 4))
#define NI_M_AO_WAVEFORM_ORDER_REG(x) (0x0c2 + ((x) * 4))
#define NI_M_AO_CFG_BANK_REG(x) (0x0c3 + ((x) * 4))
+#define NI_M_AO_CFG_BANK_BIPOLAR BIT(7)
+#define NI_M_AO_CFG_BANK_UPDATE_TIMED BIT(6)
+#define NI_M_AO_CFG_BANK_REF(x) (((x) & 0x7) << 3)
+#define NI_M_AO_CFG_BANK_REF_MASK NI_M_AO_CFG_BANK_REF(7)
+#define NI_M_AO_CFG_BANK_REF_INT_10V NI_M_AO_CFG_BANK_REF(0)
+#define NI_M_AO_CFG_BANK_REF_INT_5V NI_M_AO_CFG_BANK_REF(1)
+#define NI_M_AO_CFG_BANK_OFFSET(x) (((x) & 0x7) << 0)
+#define NI_M_AO_CFG_BANK_OFFSET_MASK NI_M_AO_CFG_BANK_OFFSET(7)
+#define NI_M_AO_CFG_BANK_OFFSET_0V NI_M_AO_CFG_BANK_OFFSET(0)
+#define NI_M_AO_CFG_BANK_OFFSET_5V NI_M_AO_CFG_BANK_OFFSET(1)
#define NI_M_RTSI_SHARED_MUX_REG 0x1a2
#define NI_M_CLK_FOUT2_REG 0x1c4
#define NI_M_CLK_FOUT2_RTSI_10MHZ BIT(7)
#define NI_M_STATIC_AI_CTRL_REG(x) ((x) ? (0x260 + (x)) : 0x064)
#define NI_M_AO_REF_ATTENUATION_REG(x) (0x264 + (x))
-enum MSeries_AO_Config_Bank_Bits {
- MSeries_AO_DAC_Offset_Select_Mask = 0x7,
- MSeries_AO_DAC_Offset_0V_Bits = 0x0,
- MSeries_AO_DAC_Offset_5V_Bits = 0x1,
- MSeries_AO_DAC_Reference_Mask = 0x38,
- MSeries_AO_DAC_Reference_10V_Internal_Bits = 0x0,
- MSeries_AO_DAC_Reference_5V_Internal_Bits = 0x8,
- MSeries_AO_Update_Timed_Bit = 0x40,
- MSeries_AO_Bipolar_Bit = 0x80 /* turns on 2's complement encoding */
-};
-
enum MSeries_AO_Reference_Attenuation_Bits {
MSeries_Attenuate_x5_Bit = 0x1
};