ARM: davinci: da8xx: fix interrupt handling

CP_INTC code in entry-macro.S code reads SECR1n register to see if
an interrupt was indeed pending. This register is actually marked as
write-only in the OMAP-L138 TRM. Moreover, the code just checks to see
the entire register is non-zero and does not check a specific interrupt
number.

Fix this to use interrupt pending bit in GIPR register for this purpose.
GIPR register is already being read to know the highest priority interrupt
pending.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>

diff --git a/arch/arm/mach-davinci/include/mach/entry-macro.S b/arch/arm/mach-davinci/include/mach/entry-macro.S
index 768b3c0602140e789286b7182bb07e2b31336282..cf5f573eb5fd713c6d407bb752a870e7abbc0992 100644 (file)
--- a/arch/arm/mach-davinci/include/mach/entry-macro.S
+++ b/arch/arm/mach-davinci/include/mach/entry-macro.S
@@ -30,12 +30,10 @@
 #endif
 #if defined(CONFIG_CP_INTC)
 1001:          ldr \irqnr, [\base, #0x80] /* get irq number */
+               mov \tmp, \irqnr, lsr #31
                and \irqnr, \irqnr, #0xff  /* irq is in bits 0-9 */
-               mov \tmp, \irqnr, lsr #3
-               and \tmp, \tmp, #0xfc
-               add \tmp, \tmp, #0x280 /* get the register offset */
-               ldr \irqstat, [\base, \tmp] /* get the intc status */
-               cmp \irqstat, #0x0
+               and \tmp, \tmp, #0x1
+               cmp \tmp, #0x1
 #endif
 1002:
                .endm