PCI: Add offsets of PCIe capability registers

These offsets are not used, and in some cases are completely reserved
even in the spec, but I'm adding them for completeness just to match
the diagrams in the spec, e.g., PCIe spec r3.0, sec 7.8.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 28c83eceefe3cee9527e454e1b04badcce94b1a5..baa7852468ef6eced239446f81b7b88b765e083e 100644 (file)
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -565,15 +565,18 @@
 #define  PCI_EXP_DEVCTL2_OBFF_MSGA_EN  0x2000  /* Enable OBFF Message type A */
 #define  PCI_EXP_DEVCTL2_OBFF_MSGB_EN  0x4000  /* Enable OBFF Message type B */
 #define  PCI_EXP_DEVCTL2_OBFF_WAKE_EN  0x6000  /* OBFF using WAKE# signaling */
+#define PCI_EXP_DEVSTA2                42      /* Device Status 2 */
 #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44      /* v2 endpoints end here */
-#define PCI_EXP_LNKCAP2                44      /* Link Capability 2 */
+#define PCI_EXP_LNKCAP2                44      /* Link Capabilities 2 */
 #define  PCI_EXP_LNKCAP2_SLS_2_5GB     0x00000002 /* Supported Speed 2.5GT/s */
 #define  PCI_EXP_LNKCAP2_SLS_5_0GB     0x00000004 /* Supported Speed 5.0GT/s */
 #define  PCI_EXP_LNKCAP2_SLS_8_0GB     0x00000008 /* Supported Speed 8.0GT/s */
 #define  PCI_EXP_LNKCAP2_CROSSLINK     0x00000100 /* Crosslink supported */
 #define PCI_EXP_LNKCTL2                48      /* Link Control 2 */
 #define PCI_EXP_LNKSTA2                50      /* Link Status 2 */
+#define PCI_EXP_SLTCAP2                52      /* Slot Capabilities 2 */
 #define PCI_EXP_SLTCTL2                56      /* Slot Control 2 */
+#define PCI_EXP_SLTSTA2                58      /* Slot Status 2 */
 
 /* Extended Capabilities (PCI-X 2.0 and Express) */
 #define PCI_EXT_CAP_ID(header)         (header & 0x0000ffff)