After the change of frequency a SAMA5D4 can reach, we have to modify the
maximum clock specification for the master clock, up to 200MHz now.
It avoids the wrong message saying that "master clk is overclocked" for this
configuration.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
interrupt-parent = <&pmc>;
interrupts = <AT91_PMC_MCKRDY>;
clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
- atmel,clk-output-range = <125000000 177000000>;
+ atmel,clk-output-range = <125000000 200000000>;
atmel,clk-divisors = <1 2 4 3>;
};