ARM: dts: imx6: add anatop phandle for usbphy

Add anatop phandle for usbphy

Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 8a7ce97ccf940e5fe563458289ee296741e46bc1..e78497eebdef74396c4424d1038f262cddc3e3e8 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -576,6 +576,7 @@
                                reg = <0x020c9000 0x1000>;
                                interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 182>;
+                               fsl,anatop = <&anatop>;
                        };
 
                        usbphy2: usbphy@020ca000 {
@@ -583,6 +584,7 @@
                                reg = <0x020ca000 0x1000>;
                                interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 183>;
+                               fsl,anatop = <&anatop>;
                        };
 
                        snvs@020cc000 {

diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 983ca3871066f01954d84c5b873f4ae28076ad9e..ee08d1b31a56bae7133420e4d385fc6387704abe 100644 (file)
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -520,6 +520,7 @@
                                reg = <0x020c9000 0x1000>;
                                interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_USBPHY1>;
+                               fsl,anatop = <&anatop>;
                        };
 
                        usbphy2: usbphy@020ca000 {
@@ -527,6 +528,7 @@
                                reg = <0x020ca000 0x1000>;
                                interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_USBPHY2>;
+                               fsl,anatop = <&anatop>;
                        };
 
                        snvs@020cc000 {