viafb: add engine clock support

This patch adds support for enabling and configuring the engine on
VIAs IGPs. This is the main clock used for everything but pixel
output.

Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>

diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c
index df84251b8f933f8889b2ad428dfa9c6c449ce12c..e5311474219f367b39157986f1dcb757efd7022f 100644 (file)
--- a/drivers/video/via/hw.c
+++ b/drivers/video/via/hw.c
@@ -2289,6 +2289,7 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
                        get_sync(viafbinfo1));
        }
 
+       clock.set_engine_pll_state(VIA_STATE_ON);
        clock.set_primary_clock_source(VIA_CLKSRC_X1, true);
        clock.set_secondary_clock_source(VIA_CLKSRC_X1, true);
 

diff --git a/drivers/video/via/via_clock.c b/drivers/video/via/via_clock.c
index a829a246881c604af731b52c8a9488566e656a7a..af8f26b643c15cb8510022d53db9144969907697 100644 (file)
--- a/drivers/video/via/via_clock.c
+++ b/drivers/video/via/via_clock.c
@@ -87,6 +87,15 @@ static inline void k800_set_secondary_pll_encoded(u32 data)
        via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */
 }
 
+static inline void set_engine_pll_encoded(u32 data)
+{
+       via_write_reg_mask(VIASR, 0x40, 0x01, 0x01); /* enable reset */
+       via_write_reg(VIASR, 0x47, data & 0xFF);
+       via_write_reg(VIASR, 0x48, (data >> 8) & 0xFF);
+       via_write_reg(VIASR, 0x49, (data >> 16) & 0xFF);
+       via_write_reg_mask(VIASR, 0x40, 0x00, 0x01); /* disable reset */
+}
+
 static void cle266_set_primary_pll(struct via_pll_config config)
 {
        cle266_set_primary_pll_encoded(cle266_encode_pll(config));
@@ -117,6 +126,16 @@ static void vx855_set_secondary_pll(struct via_pll_config config)
        k800_set_secondary_pll_encoded(vx855_encode_pll(config));
 }
 
+static void k800_set_engine_pll(struct via_pll_config config)
+{
+       set_engine_pll_encoded(k800_encode_pll(config));
+}
+
+static void vx855_set_engine_pll(struct via_pll_config config)
+{
+       set_engine_pll_encoded(vx855_encode_pll(config));
+}
+
 static void set_primary_pll_state(u8 state)
 {
        u8 value;
@@ -153,6 +172,24 @@ static void set_secondary_pll_state(u8 state)
        via_write_reg_mask(VIASR, 0x2D, value, 0x0C);
 }
 
+static void set_engine_pll_state(u8 state)
+{
+       u8 value;
+
+       switch (state) {
+       case VIA_STATE_ON:
+               value = 0x02;
+               break;
+       case VIA_STATE_OFF:
+               value = 0x00;
+               break;
+       default:
+               return;
+       }
+
+       via_write_reg_mask(VIASR, 0x2D, value, 0x03);
+}
+
 static void set_primary_clock_state(u8 state)
 {
        u8 value;
@@ -247,6 +284,11 @@ static void dummy_set_pll_state(u8 state)
        printk(KERN_INFO "Using undocumented set PLL state.\n%s", via_slap);
 }
 
+static void dummy_set_pll(struct via_pll_config config)
+{
+       printk(KERN_INFO "Using undocumented set PLL.\n%s", via_slap);
+}
+
 void via_clock_init(struct via_clock *clock, int gfx_chip)
 {
        switch (gfx_chip) {
@@ -261,6 +303,9 @@ void via_clock_init(struct via_clock *clock, int gfx_chip)
                clock->set_secondary_clock_source = dummy_set_clock_source;
                clock->set_secondary_pll_state = dummy_set_pll_state;
                clock->set_secondary_pll = cle266_set_secondary_pll;
+
+               clock->set_engine_pll_state = dummy_set_pll_state;
+               clock->set_engine_pll = dummy_set_pll;
                break;
        case UNICHROME_K800:
        case UNICHROME_PM800:
@@ -280,6 +325,9 @@ void via_clock_init(struct via_clock *clock, int gfx_chip)
                clock->set_secondary_clock_source = set_secondary_clock_source;
                clock->set_secondary_pll_state = set_secondary_pll_state;
                clock->set_secondary_pll = k800_set_secondary_pll;
+
+               clock->set_engine_pll_state = set_engine_pll_state;
+               clock->set_engine_pll = k800_set_engine_pll;
                break;
        case UNICHROME_VX855:
        case UNICHROME_VX900:
@@ -292,6 +340,9 @@ void via_clock_init(struct via_clock *clock, int gfx_chip)
                clock->set_secondary_clock_source = set_secondary_clock_source;
                clock->set_secondary_pll_state = set_secondary_pll_state;
                clock->set_secondary_pll = vx855_set_secondary_pll;
+
+               clock->set_engine_pll_state = set_engine_pll_state;
+               clock->set_engine_pll = vx855_set_engine_pll;
                break;
 
        }

diff --git a/drivers/video/via/via_clock.h b/drivers/video/via/via_clock.h
index f213a7a8fc79eb3afe0f4c0aad47263967d22114..88714ae0d157d83eeb2dbb9151e21676dc5e3df9 100644 (file)
--- a/drivers/video/via/via_clock.h
+++ b/drivers/video/via/via_clock.h
@@ -53,6 +53,9 @@ struct via_clock {
        void (*set_secondary_clock_source)(enum via_clksrc src, bool use_pll);
        void (*set_secondary_pll_state)(u8 state);
        void (*set_secondary_pll)(struct via_pll_config config);
+
+       void (*set_engine_pll_state)(u8 state);
+       void (*set_engine_pll)(struct via_pll_config config);
 };