ENGR00154705 [MX6Q]suspend/resume sometimes hang

1. Better to write disable and reset together into
SRC_SCR register;
2. Should wait for reset done.

Signed-off-by: Anson Huang <b20788@freescale.com>

diff --git a/arch/arm/mach-mx6/plat_hotplug.c b/arch/arm/mach-mx6/plat_hotplug.c
index 3a124b084744499b505fbde60da2a3e798763de9..67e8196ac1201b465eeb5189e68dd0e9f2813b21 100644 (file)
--- a/arch/arm/mach-mx6/plat_hotplug.c
+++ b/arch/arm/mach-mx6/plat_hotplug.c
@@ -33,19 +33,31 @@ int platform_cpu_kill(unsigned int cpu)
        unsigned int val;
 
        val = jiffies;
-       /* wait secondary cpu to die, timeout is 500ms */
+       /* wait secondary cpu to die, timeout is 50ms */
        while (atomic_read(&cpu_die_done) == 0) {
-               if (time_after(jiffies, (unsigned long)(val + HZ / 2))) {
+               if (time_after(jiffies, (unsigned long)(val + HZ / 20))) {
                        printk(KERN_WARNING "cpu %d: cpu could not die\n", cpu);
                        break;
                }
        }
+
        /*
         * we're ready for shutdown now, so do it
         */
-       val = readl(src_base + SRC_SCR_OFFSET);
+       val = __raw_readl(src_base + SRC_SCR_OFFSET);
        val &= ~(1 << (BP_SRC_SCR_CORES_DBG_RST + cpu));
-       writel(val, src_base + SRC_SCR_OFFSET);
+       val |= (1 << (BP_SRC_SCR_CORE0_RST + cpu));
+       __raw_writel(val, src_base + SRC_SCR_OFFSET);
+
+       val = jiffies;
+       /* wait secondary cpu reset done, timeout is 10ms */
+       while ((__raw_readl(src_base + SRC_SCR_OFFSET) &
+               (1 << (BP_SRC_SCR_CORE0_RST + cpu))) != 0) {
+               if (time_after(jiffies, (unsigned long)(val + HZ / 100))) {
+                       printk(KERN_WARNING "cpu %d: cpu reset fail\n", cpu);
+                       break;
+               }
+       }
 
        atomic_set(&cpu_die_done, 0);
        return 1;