ixgbe: fix incorrect PHY register reads

Fix some register reads that had the opcode and register parameters swapped.
Also use define instead of a magic (0x3) number.

Signed-off-by: Emil Tantilov <emil.s.tantilov@intel.com>
Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
index bdf535aebb35691e92927b917293e2d31aef65ce..a3aa6333073f0727b67d5c4bb0ea4fe0ef31e6ee 100644 (file)
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
@@ -266,10 +266,10 @@ s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
        if (hw->mac.type == ixgbe_mac_X540) {
                if (hw->phy.id == 0)
                        hw->phy.ops.identify(hw);
-               hw->phy.ops.read_reg(hw, 0x3, IXGBE_PCRC8ECL, &i);
-               hw->phy.ops.read_reg(hw, 0x3, IXGBE_PCRC8ECH, &i);
-               hw->phy.ops.read_reg(hw, 0x3, IXGBE_LDPCECL, &i);
-               hw->phy.ops.read_reg(hw, 0x3, IXGBE_LDPCECH, &i);
+               hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i);
+               hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i);
+               hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i);
+               hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i);
        }
 
        return 0;