ENGR00171087 [MX6]Need to add L1 Icache invalidate

As there might be dirty data line on any core of MX6
SOC when power on or reset, we need to do L1 I-cache
invalidation in the resume process and start up
process for all cores.

This is very important for us, as not all of the hardware
will do cache invalidation during power on or reset, so
we need to do the invalidation for all cache(L1, L2,
I and D) before first time enabling. Please keep in mind.

Signed-off-by: Anson Huang <b20788@freescale.com>

diff --git a/arch/arm/mach-mx6/headsmp.S b/arch/arm/mach-mx6/headsmp.S
index 3adc6e8a14dd97ecc71915425a8c18b5a6feb346..d9fca6a575a538846aa6de5d3cb0047a1d23e583 100644 (file)
--- a/arch/arm/mach-mx6/headsmp.S
+++ b/arch/arm/mach-mx6/headsmp.S
@@ -115,6 +115,9 @@ ENTRY(mx6_secondary_startup)
        offset is passed from GPR parameter, currently we store
        it at r8, future code change should avoid using r8.
 *****************************************************************************/
+       /* Invalidate L1 I-cache first */
+       mov     r1,     #0x0
+       mcr p15, 0, r1, c7, c5, 0 @ Invalidate I-Cache
        /* count the offset value and store it in r8 */
        ldr r3, =mx6_secondary_startup
        mrc     p15, 0, r0, c0, c0, 5

diff --git a/arch/arm/mach-mx6/mx6q_suspend.S b/arch/arm/mach-mx6/mx6q_suspend.S
index 31bccf15e29e2708d2fc120b48c74aa6a8f131ef..29d5a76e86ce6c50cbad85c43b2dea60c8b4f5f3 100644 (file)
--- a/arch/arm/mach-mx6/mx6q_suspend.S
+++ b/arch/arm/mach-mx6/mx6q_suspend.S
@@ -460,8 +460,10 @@ when SOC exit stop mode, arm core restart from here, currently
 are running with MMU off.
 ****************************************************************/
 resume:
+       /* Invalidate L1 I-cache first */
+       mov     r1,     #0x0
+       mcr p15, 0, r1, c7, c5, 0 @ Invalidate I-Cache
        ldr     r0, =SRC_BASE_ADDR
-       mov     r1, #0x0
        str     r1, [r0, #SRC_GPR1_OFFSET] /* clear SRC_GPR1 */
        ldr     r0, [r0, #SRC_GPR2_OFFSET]