int rval = QLA_SUCCESS;
uint32_t cnt;
- if ((RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0) {
- WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET |
- HCCRX_CLR_HOST_INT);
- RD_REG_DWORD(®->hccr); /* PCI Posting. */
- WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE);
- for (cnt = 30000;
- (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0 &&
- rval == QLA_SUCCESS; cnt--) {
- if (cnt)
- udelay(100);
- else
- rval = QLA_FUNCTION_TIMEOUT;
- }
+ if (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE)
+ return rval;
+
+ WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE);
+ for (cnt = 30000; (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0 &&
+ rval == QLA_SUCCESS; cnt--) {
+ if (cnt)
+ udelay(100);
+ else
+ rval = QLA_FUNCTION_TIMEOUT;
}
return rval;