Merge remote-tracking branch 'drm/drm-next'

Conflicts:
	drivers/gpu/drm/i915/i915_gem_gtt.c

diff --cc drivers/gpu/drm/i915/i915_drv.h
Simple merge

diff --cc drivers/gpu/drm/i915/i915_gem_gtt.c
index 154b0f8bb88de02addd24d21e51494728897a622,0d514ff9b94c4221ccf4ce853a7642a2715fb948..127b8f94bb9e2692a9cc9f20a033d2e5bd399cca
--- 1/drivers/gpu/drm/i915/i915_gem_gtt.c
--- 2/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@@ -62,62 -48,13 +62,9 @@@ static int sanitize_enable_ppgtt(struc
        }
  #endif
  
 -      /* Full ppgtt disabled by default for now due to issues. */
 -      if (full)
 -              return HAS_PPGTT(dev) && (i915.enable_ppgtt == 2);
 -      else
 -              return HAS_ALIASING_PPGTT(dev);
 +      return HAS_ALIASING_PPGTT(dev) ? 1 : 0;
  }
  
- #define GEN6_PPGTT_PD_ENTRIES 512
- #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
- typedef uint64_t gen8_gtt_pte_t;
- typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
- 
- /* PPGTT stuff */
- #define GEN6_GTT_ADDR_ENCODE(addr)    ((addr) | (((addr) >> 28) & 0xff0))
- #define HSW_GTT_ADDR_ENCODE(addr)     ((addr) | (((addr) >> 28) & 0x7f0))
- 
- #define GEN6_PDE_VALID                        (1 << 0)
- /* gen6+ has bit 11-4 for physical addr bit 39-32 */
- #define GEN6_PDE_ADDR_ENCODE(addr)    GEN6_GTT_ADDR_ENCODE(addr)
- 
- #define GEN6_PTE_VALID                        (1 << 0)
- #define GEN6_PTE_UNCACHED             (1 << 1)
- #define HSW_PTE_UNCACHED              (0)
- #define GEN6_PTE_CACHE_LLC            (2 << 1)
- #define GEN7_PTE_CACHE_L3_LLC         (3 << 1)
- #define GEN6_PTE_ADDR_ENCODE(addr)    GEN6_GTT_ADDR_ENCODE(addr)
- #define HSW_PTE_ADDR_ENCODE(addr)     HSW_GTT_ADDR_ENCODE(addr)
- 
- /* Cacheability Control is a 4-bit value. The low three bits are stored in *
-  * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
-  */
- #define HSW_CACHEABILITY_CONTROL(bits)        ((((bits) & 0x7) << 1) | \
-                                        (((bits) & 0x8) << (11 - 3)))
- #define HSW_WB_LLC_AGE3                       HSW_CACHEABILITY_CONTROL(0x2)
- #define HSW_WB_LLC_AGE0                       HSW_CACHEABILITY_CONTROL(0x3)
- #define HSW_WB_ELLC_LLC_AGE0          HSW_CACHEABILITY_CONTROL(0xb)
- #define HSW_WB_ELLC_LLC_AGE3          HSW_CACHEABILITY_CONTROL(0x8)
- #define HSW_WT_ELLC_LLC_AGE0          HSW_CACHEABILITY_CONTROL(0x6)
- #define HSW_WT_ELLC_LLC_AGE3          HSW_CACHEABILITY_CONTROL(0x7)
- 
- #define GEN8_PTES_PER_PAGE            (PAGE_SIZE / sizeof(gen8_gtt_pte_t))
- #define GEN8_PDES_PER_PAGE            (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t))
- 
- /* GEN8 legacy style addressis defined as a 3 level page table:
-  * 31:30 | 29:21 | 20:12 |  11:0
-  * PDPE  |  PDE  |  PTE  | offset
-  * The difference as compared to normal x86 3 level page table is the PDPEs are
-  * programmed via register.
-  */
- #define GEN8_PDPE_SHIFT                       30
- #define GEN8_PDPE_MASK                        0x3
- #define GEN8_PDE_SHIFT                        21
- #define GEN8_PDE_MASK                 0x1ff
- #define GEN8_PTE_SHIFT                        12
- #define GEN8_PTE_MASK                 0x1ff
- 
- #define PPAT_UNCACHED_INDEX           (_PAGE_PWT | _PAGE_PCD)
- #define PPAT_CACHED_PDE_INDEX         0 /* WB LLC */
- #define PPAT_CACHED_INDEX             _PAGE_PAT /* WB LLCeLLC */
- #define PPAT_DISPLAY_ELLC_INDEX               _PAGE_PCD /* WT eLLC */
  
  static void ppgtt_bind_vma(struct i915_vma *vma,
                           enum i915_cache_level cache_level,
@@@ -2041,15 -1962,11 +1972,20 @@@ int i915_gem_gtt_init(struct drm_devic
                 gtt->base.total >> 20);
        DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
        DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
 +      /*
 +       * i915.enable_ppgtt is read-only, so do an early pass to validate the
 +       * user's requested state against the hardware/driver capabilities.  We
 +       * do this now so that we can print out any log messages once rather
 +       * than every time we check intel_enable_ppgtt().
 +       */
 +      i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
 +      DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
 +
+ #ifdef CONFIG_INTEL_IOMMU
+       if (intel_iommu_gfx_mapped)
+               DRM_INFO("VT-d active for gfx access\n");
+ #endif
+ 
        return 0;
  }
  

diff --cc drivers/gpu/drm/i915/intel_display.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_dp.c
Simple merge