ARM: LPAE: add ISBs around MMU enabling code

Before we enable the MMU, we must ensure that the TTBR registers contain
sane values. After the MMU has been enabled, we jump to the *virtual*
address of the following function, so we also need to ensure that the
SCTLR write has taken effect.

This patch adds ISB instructions around the SCTLR write to ensure the
visibility of the above.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index e95a5989602ae3fcf54f56257ce35739593d5f86..716c7bac756a78a10258a657a0ed8c6bbf886bba 100644 (file)
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -551,6 +551,7 @@ __armv7_mmu_cache_on:
                mcrne   p15, 0, r3, c2, c0, 0   @ load page table pointer
                mcrne   p15, 0, r1, c3, c0, 0   @ load domain access control
 #endif
+               mcr     p15, 0, r0, c7, c5, 4   @ ISB
                mcr     p15, 0, r0, c1, c0, 0   @ load control register
                mrc     p15, 0, r0, c1, c0, 0   @ and read it back
                mov     r0, #0

diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 29035e86a59db0d4c46ab315a9350780dbfe2999..b6e65dedfd716db5e336451868af811e34a684dc 100644 (file)
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -186,6 +186,17 @@
 #define ALT_UP_B(label) b label
 #endif
 
+/*
+ * Instruction barrier
+ */
+       .macro  instr_sync
+#if __LINUX_ARM_ARCH__ >= 7
+       isb
+#elif __LINUX_ARM_ARCH__ == 6
+       mcr     p15, 0, r0, c7, c5, 4
+#endif
+       .endm
+
 /*
  * SMP data memory barrier
  */

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 742b6108a00168b8ed8c391c6d8e8b1b9c438fc6..d8231b26610a98581ca5842a59aa5c487bc2657d 100644 (file)
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -396,8 +396,10 @@ ENDPROC(__enable_mmu)
        .align  5
 __turn_mmu_on:
        mov     r0, r0
+       instr_sync
        mcr     p15, 0, r0, c1, c0, 0           @ write control reg
        mrc     p15, 0, r3, c0, c0, 0           @ read id reg
+       instr_sync
        mov     r3, r3
        mov     r3, r13
        mov     pc, r3

diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index dc902f2c68457b0f3277b8112a7a1e867106cde8..ecece65251fadb3ea9e4adacbc8ac0d388c2d3d9 100644 (file)
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -85,8 +85,10 @@ ENDPROC(cpu_resume_mmu)
        .ltorg
        .align  5
 cpu_resume_turn_mmu_on:
+       instr_sync
        mcr     p15, 0, r1, c1, c0, 0   @ turn on MMU, I-cache, etc
        mrc     p15, 0, r1, c0, c0, 0   @ read id reg
+       instr_sync
        mov     r1, r1
        mov     r1, r1
        mov     pc, r3                  @ jump to virtual address