ENGR00155759 [MX6]MMDC clock should be always on

1. We should enable mmdc_ch0 clock in init to make
  its usecount > 0, or ipu's parent is mmdc_ch0,
  when ipu enable/disable clock, mmdc_ch0 will be
  also enable/disable, cause system hang when disable.
2. Remove build warning of unuse variable.

Signed-off-by: Anson Huang <b20788@freescale.com>

diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c
index 3a83c772fc64a10c8d9f4da7d4274caf796d85db..4a56fd640ee8aad12a835dd46a2017b1cfc9a07b 100644 (file)
--- a/arch/arm/mach-mx6/clock.c
+++ b/arch/arm/mach-mx6/clock.c
@@ -3937,7 +3937,6 @@ static struct clk pcie_clk = {
 static int _clk_sata_enable(struct clk *clk)
 {
        unsigned int reg;
-       unsigned int cyclecount;
 
        /* Clear Power Down and Enable PLLs */
        reg = __raw_readl(PLL8_ENET_BASE_ADDR);
@@ -4144,6 +4143,10 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
                clk_debug_register(lookups[i].clk);
        }
 
+       /* enable mmdc_ch0_axi_clk to make sure the usecount is > 0
+        * or ipu's parent is mmdc_ch0_axi_clk, if ipu disable clk,
+        * mmdc_ch0_axi_clk will also be disabled, system will hang */
+       clk_enable(&mmdc_ch0_axi_clk[0]);
        /* Initialize Audio and Video PLLs to valid frequency (650MHz). */
        clk_set_rate(&pll4_audio_main_clk, 650000000);
        clk_set_rate(&pll5_video_main_clk, 650000000);