]> git.karo-electronics.de Git - mv-sheeva.git/commitdiff
Merge branch 'next-s5pv310' into for-next
authorKukjin Kim <kgene.kim@samsung.com>
Mon, 3 Jan 2011 09:59:54 +0000 (18:59 +0900)
committerKukjin Kim <kgene.kim@samsung.com>
Mon, 3 Jan 2011 09:59:54 +0000 (18:59 +0900)
Conflicts:
arch/arm/mach-s5pv310/Makefile

60 files changed:
arch/arm/mach-s3c64xx/clock.c
arch/arm/mach-s3c64xx/dev-audio.c
arch/arm/mach-s3c64xx/irq-eint.c
arch/arm/mach-s5p6442/dev-audio.c
arch/arm/mach-s5p6442/include/mach/map.h
arch/arm/mach-s5p6442/mach-smdk6442.c
arch/arm/mach-s5p6442/setup-i2c0.c
arch/arm/mach-s5p64x0/Makefile
arch/arm/mach-s5p64x0/clock-s5p6440.c
arch/arm/mach-s5p64x0/clock-s5p6450.c
arch/arm/mach-s5p64x0/dev-audio.c
arch/arm/mach-s5p64x0/gpiolib.c [moved from arch/arm/mach-s5p64x0/gpio.c with 58% similarity]
arch/arm/mach-s5p64x0/include/mach/map.h
arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
arch/arm/mach-s5p64x0/mach-smdk6440.c
arch/arm/mach-s5p64x0/mach-smdk6450.c
arch/arm/mach-s5pc100/dev-audio.c
arch/arm/mach-s5pc100/include/mach/map.h
arch/arm/mach-s5pv210/Kconfig
arch/arm/mach-s5pv210/clock.c
arch/arm/mach-s5pv210/cpu.c
arch/arm/mach-s5pv210/dev-audio.c
arch/arm/mach-s5pv210/include/mach/irqs.h
arch/arm/mach-s5pv210/include/mach/map.h
arch/arm/mach-s5pv210/include/mach/regs-clock.h
arch/arm/mach-s5pv210/mach-smdkc110.c
arch/arm/mach-s5pv210/mach-smdkv210.c
arch/arm/mach-s5pv310/Kconfig
arch/arm/mach-s5pv310/Makefile
arch/arm/mach-s5pv310/clock.c
arch/arm/mach-s5pv310/dev-audio.c [new file with mode: 0644]
arch/arm/mach-s5pv310/dma.c [new file with mode: 0644]
arch/arm/mach-s5pv310/include/mach/dma.h [new file with mode: 0644]
arch/arm/mach-s5pv310/include/mach/irqs.h
arch/arm/mach-s5pv310/include/mach/map.h
arch/arm/mach-s5pv310/include/mach/regs-srom.h [deleted file]
arch/arm/mach-s5pv310/irq-eint.c
arch/arm/mach-s5pv310/mach-smdkc210.c
arch/arm/mach-s5pv310/mach-smdkv310.c
arch/arm/plat-s3c24xx/irq.c
arch/arm/plat-s5p/Kconfig
arch/arm/plat-s5p/Makefile
arch/arm/plat-s5p/cpu.c
arch/arm/plat-s5p/dev-csis0.c [new file with mode: 0644]
arch/arm/plat-s5p/dev-csis1.c [new file with mode: 0644]
arch/arm/plat-s5p/include/plat/csis.h [new file with mode: 0644]
arch/arm/plat-s5p/include/plat/regs-srom.h [new file with mode: 0644]
arch/arm/plat-s5p/irq-eint.c
arch/arm/plat-samsung/Kconfig
arch/arm/plat-samsung/Makefile
arch/arm/plat-samsung/gpiolib.c
arch/arm/plat-samsung/include/plat/audio.h
arch/arm/plat-samsung/include/plat/devs.h
arch/arm/plat-samsung/include/plat/gpio-core.h
arch/arm/plat-samsung/include/plat/pd.h [new file with mode: 0644]
arch/arm/plat-samsung/include/plat/pm.h
arch/arm/plat-samsung/irq-uart.c
arch/arm/plat-samsung/irq-vic-timer.c
arch/arm/plat-samsung/pd.c [new file with mode: 0644]
arch/arm/plat-samsung/pm.c

index 7e03f0ae2fc821d8400846f4eb6dd8ea0b21256b..1c98d2ff2ed66e783bb63e0267eef60da69ba213 100644 (file)
@@ -695,7 +695,7 @@ static struct clksrc_clk clksrcs[] = {
        }, {
                .clk    = {
                        .name           = "audio-bus",
-                       .id             = -1,  /* There's only one IISv4 port */
+                       .id             = 2,
                        .ctrlbit        = S3C6410_CLKCON_SCLK_AUDIO2,
                        .enable         = s3c64xx_sclk_ctrl,
                },
index 76426a32c013947aabffafc97d22b68efe63e54b..7618627b98f5c6b53a1d97d89133fe828bfa7f7b 100644 (file)
 #include <plat/audio.h>
 #include <plat/gpio-cfg.h>
 
-static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev)
+static const char *rclksrc[] = {
+       [0] = "iis",
+       [1] = "audio-bus",
+};
+
+static int s3c64xx_i2s_cfg_gpio(struct platform_device *pdev)
 {
        unsigned int base;
 
@@ -33,6 +38,12 @@ static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev)
        case 1:
                base = S3C64XX_GPE(0);
                break;
+       case 2:
+               s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C_GPIO_SFN(5));
+               s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C_GPIO_SFN(5));
+               s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C_GPIO_SFN(5));
+               s3c_gpio_cfgpin_range(S3C64XX_GPH(6), 4, S3C_GPIO_SFN(5));
+               return 0;
        default:
                printk(KERN_DEBUG "Invalid I2S Controller number: %d\n",
                        pdev->id);
@@ -44,16 +55,6 @@ static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev)
        return 0;
 }
 
-static int s3c64xx_i2sv4_cfg_gpio(struct platform_device *pdev)
-{
-       s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C_GPIO_SFN(5));
-       s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C_GPIO_SFN(5));
-       s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C_GPIO_SFN(5));
-       s3c_gpio_cfgpin_range(S3C64XX_GPH(6), 4, S3C_GPIO_SFN(5));
-
-       return 0;
-}
-
 static struct resource s3c64xx_iis0_resource[] = {
        [0] = {
                .start = S3C64XX_PA_IIS0,
@@ -72,17 +73,22 @@ static struct resource s3c64xx_iis0_resource[] = {
        },
 };
 
-static struct s3c_audio_pdata s3c_i2s0_pdata = {
-       .cfg_gpio = s3c64xx_i2sv3_cfg_gpio,
+static struct s3c_audio_pdata i2sv3_pdata = {
+       .cfg_gpio = s3c64xx_i2s_cfg_gpio,
+       .type = {
+               .i2s = {
+                       .src_clk = rclksrc,
+               },
+       },
 };
 
 struct platform_device s3c64xx_device_iis0 = {
-       .name             = "s3c64xx-iis",
+       .name             = "samsung-i2s",
        .id               = 0,
        .num_resources    = ARRAY_SIZE(s3c64xx_iis0_resource),
        .resource         = s3c64xx_iis0_resource,
        .dev = {
-               .platform_data = &s3c_i2s0_pdata,
+               .platform_data = &i2sv3_pdata,
        },
 };
 EXPORT_SYMBOL(s3c64xx_device_iis0);
@@ -105,17 +111,13 @@ static struct resource s3c64xx_iis1_resource[] = {
        },
 };
 
-static struct s3c_audio_pdata s3c_i2s1_pdata = {
-       .cfg_gpio = s3c64xx_i2sv3_cfg_gpio,
-};
-
 struct platform_device s3c64xx_device_iis1 = {
-       .name             = "s3c64xx-iis",
+       .name             = "samsung-i2s",
        .id               = 1,
        .num_resources    = ARRAY_SIZE(s3c64xx_iis1_resource),
        .resource         = s3c64xx_iis1_resource,
        .dev = {
-               .platform_data = &s3c_i2s1_pdata,
+               .platform_data = &i2sv3_pdata,
        },
 };
 EXPORT_SYMBOL(s3c64xx_device_iis1);
@@ -138,17 +140,23 @@ static struct resource s3c64xx_iisv4_resource[] = {
        },
 };
 
-static struct s3c_audio_pdata s3c_i2sv4_pdata = {
-       .cfg_gpio = s3c64xx_i2sv4_cfg_gpio,
+static struct s3c_audio_pdata i2sv4_pdata = {
+       .cfg_gpio = s3c64xx_i2s_cfg_gpio,
+       .type = {
+               .i2s = {
+                       .quirks = QUIRK_PRI_6CHAN,
+                       .src_clk = rclksrc,
+               },
+       },
 };
 
 struct platform_device s3c64xx_device_iisv4 = {
-       .name             = "s3c64xx-iis-v4",
-       .id               = -1,
+       .name = "samsung-i2s",
+       .id = 2,
        .num_resources    = ARRAY_SIZE(s3c64xx_iisv4_resource),
        .resource         = s3c64xx_iisv4_resource,
        .dev = {
-               .platform_data = &s3c_i2sv4_pdata,
+               .platform_data = &i2sv4_pdata,
        },
 };
 EXPORT_SYMBOL(s3c64xx_device_iisv4);
index 5682d6a7f4af9ea74eb8887ac6f7f95d547df57b..2ead8189da7438d900c573eb62ca447968dd7e09 100644 (file)
 #include <plat/pm.h>
 
 #define eint_offset(irq)       ((irq) - IRQ_EINT(0))
-#define eint_irq_to_bit(irq)   (1 << eint_offset(irq))
+#define eint_irq_to_bit(irq)   ((u32)(1 << eint_offset(irq)))
 
-static inline void s3c_irq_eint_mask(unsigned int irq)
+static inline void s3c_irq_eint_mask(struct irq_data *data)
 {
        u32 mask;
 
        mask = __raw_readl(S3C64XX_EINT0MASK);
-       mask |= eint_irq_to_bit(irq);
+       mask |= (u32)data->chip_data;
        __raw_writel(mask, S3C64XX_EINT0MASK);
 }
 
-static void s3c_irq_eint_unmask(unsigned int irq)
+static void s3c_irq_eint_unmask(struct irq_data *data)
 {
        u32 mask;
 
        mask = __raw_readl(S3C64XX_EINT0MASK);
-       mask &= ~eint_irq_to_bit(irq);
+       mask &= ~((u32)data->chip_data);
        __raw_writel(mask, S3C64XX_EINT0MASK);
 }
 
-static inline void s3c_irq_eint_ack(unsigned int irq)
+static inline void s3c_irq_eint_ack(struct irq_data *data)
 {
-       __raw_writel(eint_irq_to_bit(irq), S3C64XX_EINT0PEND);
+       __raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
 }
 
-static void s3c_irq_eint_maskack(unsigned int irq)
+static void s3c_irq_eint_maskack(struct irq_data *data)
 {
        /* compiler should in-line these */
-       s3c_irq_eint_mask(irq);
-       s3c_irq_eint_ack(irq);
+       s3c_irq_eint_mask(data);
+       s3c_irq_eint_ack(data);
 }
 
-static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
+static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
 {
-       int offs = eint_offset(irq);
+       int offs = eint_offset(data->irq);
        int pin, pin_val;
        int shift;
        u32 ctrl, mask;
@@ -140,12 +140,12 @@ static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
 
 static struct irq_chip s3c_irq_eint = {
        .name           = "s3c-eint",
-       .mask           = s3c_irq_eint_mask,
-       .unmask         = s3c_irq_eint_unmask,
-       .mask_ack       = s3c_irq_eint_maskack,
-       .ack            = s3c_irq_eint_ack,
-       .set_type       = s3c_irq_eint_set_type,
-       .set_wake       = s3c_irqext_wake,
+       .irq_mask       = s3c_irq_eint_mask,
+       .irq_unmask     = s3c_irq_eint_unmask,
+       .irq_mask_ack   = s3c_irq_eint_maskack,
+       .irq_ack        = s3c_irq_eint_ack,
+       .irq_set_type   = s3c_irq_eint_set_type,
+       .irq_set_wake   = s3c_irqext_wake,
 };
 
 /* s3c_irq_demux_eint
@@ -198,6 +198,7 @@ static int __init s3c64xx_init_irq_eint(void)
 
        for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
                set_irq_chip(irq, &s3c_irq_eint);
+               set_irq_chip_data(irq, (void *)eint_irq_to_bit(irq));
                set_irq_handler(irq, handle_level_irq);
                set_irq_flags(irq, IRQF_VALID);
        }
index 3462197ff352bb786200618611c2b847b753e345..8719dc41fe32447fd0c02727fd2235910017e90a 100644 (file)
@@ -29,7 +29,7 @@ static int s5p6442_cfg_i2s(struct platform_device *pdev)
                base = S5P6442_GPC1(0);
                break;
 
-       case -1:
+       case 0:
                base = S5P6442_GPC0(0);
                break;
 
@@ -42,8 +42,19 @@ static int s5p6442_cfg_i2s(struct platform_device *pdev)
        return 0;
 }
 
-static struct s3c_audio_pdata s3c_i2s_pdata = {
+static const char *rclksrc_v35[] = {
+       [0] = "busclk",
+       [1] = "i2sclk",
+};
+
+static struct s3c_audio_pdata i2sv35_pdata = {
        .cfg_gpio = s5p6442_cfg_i2s,
+       .type = {
+               .i2s = {
+                       .quirks = QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR,
+                       .src_clk = rclksrc_v35,
+               },
+       },
 };
 
 static struct resource s5p6442_iis0_resource[] = {
@@ -62,15 +73,34 @@ static struct resource s5p6442_iis0_resource[] = {
                .end   = DMACH_I2S0_RX,
                .flags = IORESOURCE_DMA,
        },
+       [3] = {
+               .start = DMACH_I2S0S_TX,
+               .end = DMACH_I2S0S_TX,
+               .flags = IORESOURCE_DMA,
+       },
 };
 
 struct platform_device s5p6442_device_iis0 = {
-       .name             = "s3c64xx-iis-v4",
-       .id               = -1,
+       .name = "samsung-i2s",
+       .id = 0,
        .num_resources    = ARRAY_SIZE(s5p6442_iis0_resource),
        .resource         = s5p6442_iis0_resource,
        .dev = {
-               .platform_data = &s3c_i2s_pdata,
+               .platform_data = &i2sv35_pdata,
+       },
+};
+
+static const char *rclksrc_v3[] = {
+       [0] = "iis",
+       [1] = "sclk_audio",
+};
+
+static struct s3c_audio_pdata i2sv3_pdata = {
+       .cfg_gpio = s5p6442_cfg_i2s,
+       .type = {
+               .i2s = {
+                       .src_clk = rclksrc_v3,
+               },
        },
 };
 
@@ -93,12 +123,12 @@ static struct resource s5p6442_iis1_resource[] = {
 };
 
 struct platform_device s5p6442_device_iis1 = {
-       .name             = "s3c64xx-iis",
+       .name             = "samsung-i2s",
        .id               = 1,
        .num_resources    = ARRAY_SIZE(s5p6442_iis1_resource),
        .resource         = s5p6442_iis1_resource,
        .dev = {
-               .platform_data = &s3c_i2s_pdata,
+               .platform_data = &i2sv3_pdata,
        },
 };
 
index 31fb2e68d527915080df5f9ff498c835218f972c..203dd5a18bd585681518067a0f6c0a43c3ecd280 100644 (file)
@@ -28,6 +28,9 @@
 #define S5P6442_PA_VIC1                (0xE4100000)
 #define S5P6442_PA_VIC2                (0xE4200000)
 
+#define S5P6442_PA_SROMC       (0xE7000000)
+#define S5P_PA_SROMC           S5P6442_PA_SROMC
+
 #define S5P6442_PA_MDMA                0xE8000000
 #define S5P6442_PA_PDMA                0xE9000000
 
index 819fd80d00afc74a34c2741409de363bd14ecde7..e69f137b0a39394ade5945730c91da63eaf86bb3 100644 (file)
@@ -12,6 +12,7 @@
 #include <linux/types.h>
 #include <linux/init.h>
 #include <linux/serial_core.h>
+#include <linux/i2c.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -25,6 +26,7 @@
 #include <plat/s5p6442.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/iic.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define SMDK6442_UCON_DEFAULT  (S3C2410_UCON_TXILEVEL |        \
@@ -65,10 +67,15 @@ static struct s3c2410_uartcfg smdk6442_uartcfgs[] __initdata = {
 };
 
 static struct platform_device *smdk6442_devices[] __initdata = {
+       &s3c_device_i2c0,
        &s5p6442_device_iis0,
        &s3c_device_wdt,
 };
 
+static struct i2c_board_info smdk6442_i2c_devs0[] __initdata = {
+       { I2C_BOARD_INFO("wm8580", 0x1b), },
+};
+
 static void __init smdk6442_map_io(void)
 {
        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -78,6 +85,9 @@ static void __init smdk6442_map_io(void)
 
 static void __init smdk6442_machine_init(void)
 {
+       s3c_i2c0_set_platdata(NULL);
+       i2c_register_board_info(0, smdk6442_i2c_devs0,
+                       ARRAY_SIZE(smdk6442_i2c_devs0));
        platform_add_devices(smdk6442_devices, ARRAY_SIZE(smdk6442_devices));
 }
 
index 662695dd7761bea83c5bd5b7e91f3b38eb337878..aad85656b0ccc6256bc3eb823c212982bd99d345 100644 (file)
 
 #include <linux/kernel.h>
 #include <linux/types.h>
+#include <linux/gpio.h>
 
 struct platform_device; /* don't need the contents */
 
+#include <plat/gpio-cfg.h>
 #include <plat/iic.h>
 
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
 {
-       /* Will be populated later */
+       s3c_gpio_cfgall_range(S5P6442_GPD1(0), 2,
+                             S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
 }
index 2655829e6bf8b6460ee8c4e56835f35b1180720d..ae6bf6feba89cdbedac7550d9662e7fc54fe2919 100644 (file)
@@ -12,9 +12,9 @@ obj-                          :=
 
 # Core support for S5P64X0 system
 
-obj-$(CONFIG_ARCH_S5P64X0)     += cpu.o init.o clock.o dma.o
+obj-$(CONFIG_ARCH_S5P64X0)     += cpu.o init.o clock.o dma.o gpiolib.o
 obj-$(CONFIG_ARCH_S5P64X0)     += setup-i2c0.o
-obj-$(CONFIG_CPU_S5P6440)      += clock-s5p6440.o gpio.o
+obj-$(CONFIG_CPU_S5P6440)      += clock-s5p6440.o
 obj-$(CONFIG_CPU_S5P6450)      += clock-s5p6450.o
 
 # machine support
index e4883dc1c8d76d08958a127ff5b45f367dc5927a..40137c6f0488c4ad5a2b75120f443a66232ebc97 100644 (file)
@@ -261,7 +261,7 @@ static struct clk init_clocks_disable[] = {
                .enable         = s5p64x0_pclk_ctrl,
                .ctrlbit        = (1 << 25),
        }, {
-               .name           = "i2s_v40",
+               .name           = "iis",
                .id             = 0,
                .parent         = &clk_pclk_low.clk,
                .enable         = s5p64x0_pclk_ctrl,
@@ -419,7 +419,7 @@ static struct clksrc_sources clkset_audio = {
 static struct clksrc_clk clksrcs[] = {
        {
                .clk    = {
-                       .name           = "mmc_bus",
+                       .name           = "sclk_mmc",
                        .id             = 0,
                        .ctrlbit        = (1 << 24),
                        .enable         = s5p64x0_sclk_ctrl,
@@ -429,7 +429,7 @@ static struct clksrc_clk clksrcs[] = {
                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
        }, {
                .clk    = {
-                       .name           = "mmc_bus",
+                       .name           = "sclk_mmc",
                        .id             = 1,
                        .ctrlbit        = (1 << 25),
                        .enable         = s5p64x0_sclk_ctrl,
@@ -439,7 +439,7 @@ static struct clksrc_clk clksrcs[] = {
                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
        }, {
                .clk    = {
-                       .name           = "mmc_bus",
+                       .name           = "sclk_mmc",
                        .id             = 2,
                        .ctrlbit        = (1 << 26),
                        .enable         = s5p64x0_sclk_ctrl,
index 7dbf3c968f53d88697c3e000d8de53ba11fc0c0e..3f5ac93c455ef278d3526580044f6d44f69a23d6 100644 (file)
@@ -230,6 +230,12 @@ static struct clk init_clocks_disable[] = {
                .parent         = &clk_pclk_low.clk,
                .enable         = s5p64x0_pclk_ctrl,
                .ctrlbit        = (1 << 5),
+       }, {
+               .name           = "rtc",
+               .id             = -1,
+               .parent         = &clk_pclk_low.clk,
+               .enable         = s5p64x0_pclk_ctrl,
+               .ctrlbit        = (1 << 6),
        }, {
                .name           = "adc",
                .id             = -1,
@@ -256,10 +262,22 @@ static struct clk init_clocks_disable[] = {
                .ctrlbit        = (1 << 22),
        }, {
                .name           = "iis",
-               .id             = -1,
+               .id             = 0,
                .parent         = &clk_pclk_low.clk,
                .enable         = s5p64x0_pclk_ctrl,
                .ctrlbit        = (1 << 26),
+       }, {
+               .name           = "iis",
+               .id             = 1,
+               .parent         = &clk_pclk_low.clk,
+               .enable         = s5p64x0_pclk_ctrl,
+               .ctrlbit        = (1 << 15),
+       }, {
+               .name           = "iis",
+               .id             = 2,
+               .parent         = &clk_pclk_low.clk,
+               .enable         = s5p64x0_pclk_ctrl,
+               .ctrlbit        = (1 << 16),
        }, {
                .name           = "i2c",
                .id             = 1,
index 396bacc0a39a67289bec66f96225924dcc09f00d..35f1f226dabba9b99e88624f826eb1b2385c0b29 100644 (file)
 #include <mach/dma.h>
 #include <mach/irqs.h>
 
+static const char *rclksrc[] = {
+       [0] = "iis",
+       [1] = "sclk_audio2",
+};
+
 static int s5p6440_cfg_i2s(struct platform_device *pdev)
 {
-       /* configure GPIO for i2s port */
        switch (pdev->id) {
-       case -1:
-               s3c_gpio_cfgpin_range(S5P6440_GPR(4), 5, S3C_GPIO_SFN(5));
-               s3c_gpio_cfgpin_range(S5P6440_GPR(13), 2, S3C_GPIO_SFN(5));
+       case 0:
+               s3c_gpio_cfgpin_range(S5P6440_GPC(4), 2, S3C_GPIO_SFN(5));
+               s3c_gpio_cfgpin(S5P6440_GPC(7), S3C_GPIO_SFN(5));
+               s3c_gpio_cfgpin_range(S5P6440_GPH(6), 4, S3C_GPIO_SFN(5));
                break;
-
        default:
                printk(KERN_ERR "Invalid Device %d\n", pdev->id);
                return -EINVAL;
@@ -36,17 +40,58 @@ static int s5p6440_cfg_i2s(struct platform_device *pdev)
        return 0;
 }
 
+static struct s3c_audio_pdata s5p6440_i2s_pdata = {
+       .cfg_gpio = s5p6440_cfg_i2s,
+       .type = {
+               .i2s = {
+                       .quirks = QUIRK_PRI_6CHAN,
+                       .src_clk = rclksrc,
+               },
+       },
+};
+
+static struct resource s5p64x0_i2s0_resource[] = {
+       [0] = {
+               .start  = S5P64X0_PA_I2S,
+               .end    = S5P64X0_PA_I2S + 0x100 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = DMACH_I2S0_TX,
+               .end    = DMACH_I2S0_TX,
+               .flags  = IORESOURCE_DMA,
+       },
+       [2] = {
+               .start  = DMACH_I2S0_RX,
+               .end    = DMACH_I2S0_RX,
+               .flags  = IORESOURCE_DMA,
+       },
+};
+
+struct platform_device s5p6440_device_iis = {
+       .name           = "samsung-i2s",
+       .id             = 0,
+       .num_resources  = ARRAY_SIZE(s5p64x0_i2s0_resource),
+       .resource       = s5p64x0_i2s0_resource,
+       .dev = {
+               .platform_data = &s5p6440_i2s_pdata,
+       },
+};
+
 static int s5p6450_cfg_i2s(struct platform_device *pdev)
 {
-       /* configure GPIO for i2s port */
        switch (pdev->id) {
-       case -1:
-               s3c_gpio_cfgpin(S5P6450_GPB(4), S3C_GPIO_SFN(5));
+       case 0:
                s3c_gpio_cfgpin_range(S5P6450_GPR(4), 5, S3C_GPIO_SFN(5));
                s3c_gpio_cfgpin_range(S5P6450_GPR(13), 2, S3C_GPIO_SFN(5));
-
                break;
-
+       case 1:
+               s3c_gpio_cfgpin(S5P6440_GPB(4), S3C_GPIO_SFN(5));
+               s3c_gpio_cfgpin_range(S5P6450_GPC(0), 4, S3C_GPIO_SFN(5));
+               break;
+       case 2:
+               s3c_gpio_cfgpin_range(S5P6450_GPK(0), 5, S3C_GPIO_SFN(5));
+               break;
        default:
                printk(KERN_ERR "Invalid Device %d\n", pdev->id);
                return -EINVAL;
@@ -55,47 +100,86 @@ static int s5p6450_cfg_i2s(struct platform_device *pdev)
        return 0;
 }
 
-static struct s3c_audio_pdata s5p6440_i2s_pdata = {
-       .cfg_gpio = s5p6440_cfg_i2s,
+static struct s3c_audio_pdata s5p6450_i2s0_pdata = {
+       .cfg_gpio = s5p6450_cfg_i2s,
+       .type = {
+               .i2s = {
+                       .quirks = QUIRK_PRI_6CHAN,
+                       .src_clk = rclksrc,
+               },
+       },
+};
+
+struct platform_device s5p6450_device_iis0 = {
+       .name           = "samsung-i2s",
+       .id             = 0,
+       .num_resources  = ARRAY_SIZE(s5p64x0_i2s0_resource),
+       .resource       = s5p64x0_i2s0_resource,
+       .dev = {
+               .platform_data = &s5p6450_i2s0_pdata,
+       },
 };
 
 static struct s3c_audio_pdata s5p6450_i2s_pdata = {
        .cfg_gpio = s5p6450_cfg_i2s,
+       .type = {
+               .i2s = {
+                       .src_clk = rclksrc,
+               },
+       },
 };
 
-static struct resource s5p64x0_iis0_resource[] = {
+static struct resource s5p6450_i2s1_resource[] = {
        [0] = {
-               .start  = S5P64X0_PA_I2S,
-               .end    = S5P64X0_PA_I2S + 0x100 - 1,
+               .start  = S5P6450_PA_I2S1,
+               .end    = S5P6450_PA_I2S1 + 0x100 - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-               .start  = DMACH_I2S0_TX,
-               .end    = DMACH_I2S0_TX,
+               .start  = DMACH_I2S1_TX,
+               .end    = DMACH_I2S1_TX,
                .flags  = IORESOURCE_DMA,
        },
        [2] = {
-               .start  = DMACH_I2S0_RX,
-               .end    = DMACH_I2S0_RX,
+               .start  = DMACH_I2S1_RX,
+               .end    = DMACH_I2S1_RX,
                .flags  = IORESOURCE_DMA,
        },
 };
 
-struct platform_device s5p6440_device_iis = {
-       .name           = "s3c64xx-iis-v4",
-       .id             = -1,
-       .num_resources  = ARRAY_SIZE(s5p64x0_iis0_resource),
-       .resource       = s5p64x0_iis0_resource,
+struct platform_device s5p6450_device_iis1 = {
+       .name           = "samsung-i2s",
+       .id             = 1,
+       .num_resources  = ARRAY_SIZE(s5p6450_i2s1_resource),
+       .resource       = s5p6450_i2s1_resource,
        .dev = {
-               .platform_data = &s5p6440_i2s_pdata,
+               .platform_data = &s5p6450_i2s_pdata,
        },
 };
 
-struct platform_device s5p6450_device_iis0 = {
-       .name           = "s3c64xx-iis-v4",
-       .id             = -1,
-       .num_resources  = ARRAY_SIZE(s5p64x0_iis0_resource),
-       .resource       = s5p64x0_iis0_resource,
+static struct resource s5p6450_i2s2_resource[] = {
+       [0] = {
+               .start  = S5P6450_PA_I2S2,
+               .end    = S5P6450_PA_I2S2 + 0x100 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = DMACH_I2S2_TX,
+               .end    = DMACH_I2S2_TX,
+               .flags  = IORESOURCE_DMA,
+       },
+       [2] = {
+               .start  = DMACH_I2S2_RX,
+               .end    = DMACH_I2S2_RX,
+               .flags  = IORESOURCE_DMA,
+       },
+};
+
+struct platform_device s5p6450_device_iis2 = {
+       .name           = "samsung-i2s",
+       .id             = 2,
+       .num_resources  = ARRAY_SIZE(s5p6450_i2s2_resource),
+       .resource       = s5p6450_i2s2_resource,
        .dev = {
                .platform_data = &s5p6450_i2s_pdata,
        },
similarity index 58%
rename from arch/arm/mach-s5p64x0/gpio.c
rename to arch/arm/mach-s5p64x0/gpiolib.c
index 39159dd5a29ac7bf091e457a03d6eed14ef6573d..e7fb3b004e77b6f3ce90121a41074fa075ddb489 100644 (file)
@@ -1,4 +1,4 @@
-/* linux/arch/arm/mach-s5p64x0/gpio.c
+/* linux/arch/arm/mach-s5p64x0/gpiolib.c
  *
  * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
  *             http://www.samsung.com
 
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
+#include <mach/regs-clock.h>
 
 #include <plat/gpio-core.h>
 #include <plat/gpio-cfg.h>
 #include <plat/gpio-cfg-helpers.h>
 
-/* To be implemented S5P6450 GPIO */
-
 /*
  * S5P6440 GPIO bank summary:
  *
  * P   8       2Bit    Yes     8
  * R   15      4Bit[2] Yes     8
  *
+ * S5P6450 GPIO bank summary:
+ *
+ * Bank        GPIOs   Style   SlpCon  ExtInt Group
+ * A   6       4Bit    Yes     1
+ * B   7       4Bit    Yes     1
+ * C   8       4Bit    Yes     2
+ * D   8       4Bit    Yes     None
+ * F   2       2Bit    Yes     None
+ * G   14      4Bit[2] Yes     5
+ * H   10      4Bit[2] Yes     6
+ * I   16      2Bit    Yes     None
+ * J   12      2Bit    Yes     None
+ * K   5       4Bit    Yes     None
+ * N   16      2Bit    No      IRQ_EINT
+ * P   11      2Bit    Yes     8
+ * Q   14      2Bit    Yes     None
+ * R   15      4Bit[2] Yes     None
+ * S   8       2Bit    Yes     None
+ *
  * [1] BANKF pins 14,15 do not form part of the external interrupt sources
  * [2] BANK has two control registers, GPxCON0 and GPxCON1
  */
@@ -190,7 +208,7 @@ static struct s3c_gpio_cfg s5p64x0_gpio_cfgs[] = {
 
 static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
        {
-               .base   = S5P6440_GPA_BASE,
+               .base   = S5P64X0_GPA_BASE,
                .config = &s5p64x0_gpio_cfgs[1],
                .chip   = {
                        .base   = S5P6440_GPA(0),
@@ -198,7 +216,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
                        .label  = "GPA",
                },
        }, {
-               .base   = S5P6440_GPB_BASE,
+               .base   = S5P64X0_GPB_BASE,
                .config = &s5p64x0_gpio_cfgs[1],
                .chip   = {
                        .base   = S5P6440_GPB(0),
@@ -206,7 +224,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
                        .label  = "GPB",
                },
        }, {
-               .base   = S5P6440_GPC_BASE,
+               .base   = S5P64X0_GPC_BASE,
                .config = &s5p64x0_gpio_cfgs[1],
                .chip   = {
                        .base   = S5P6440_GPC(0),
@@ -214,7 +232,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
                        .label  = "GPC",
                },
        }, {
-               .base   = S5P6440_GPG_BASE,
+               .base   = S5P64X0_GPG_BASE,
                .config = &s5p64x0_gpio_cfgs[1],
                .chip   = {
                        .base   = S5P6440_GPG(0),
@@ -226,7 +244,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
 
 static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
        {
-               .base   = S5P6440_GPH_BASE + 0x4,
+               .base   = S5P64X0_GPH_BASE + 0x4,
                .config = &s5p64x0_gpio_cfgs[1],
                .chip   = {
                        .base   = S5P6440_GPH(0),
@@ -238,7 +256,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
 
 static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = {
        {
-               .base   = S5P6440_GPR_BASE + 0x4,
+               .base   = S5P64X0_GPR_BASE + 0x4,
                .config = &s5p64x0_gpio_cfgs[2],
                .chip   = {
                        .base   = S5P6440_GPR(0),
@@ -250,7 +268,7 @@ static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = {
 
 static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
        {
-               .base   = S5P6440_GPF_BASE,
+               .base   = S5P64X0_GPF_BASE,
                .config = &s5p64x0_gpio_cfgs[5],
                .chip   = {
                        .base   = S5P6440_GPF(0),
@@ -258,7 +276,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
                        .label  = "GPF",
                },
        }, {
-               .base   = S5P6440_GPI_BASE,
+               .base   = S5P64X0_GPI_BASE,
                .config = &s5p64x0_gpio_cfgs[3],
                .chip   = {
                        .base   = S5P6440_GPI(0),
@@ -266,7 +284,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
                        .label  = "GPI",
                },
        }, {
-               .base   = S5P6440_GPJ_BASE,
+               .base   = S5P64X0_GPJ_BASE,
                .config = &s5p64x0_gpio_cfgs[3],
                .chip   = {
                        .base   = S5P6440_GPJ(0),
@@ -274,7 +292,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
                        .label  = "GPJ",
                },
        }, {
-               .base   = S5P6440_GPN_BASE,
+               .base   = S5P64X0_GPN_BASE,
                .config = &s5p64x0_gpio_cfgs[4],
                .chip   = {
                        .base   = S5P6440_GPN(0),
@@ -282,7 +300,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
                        .label  = "GPN",
                },
        }, {
-               .base   = S5P6440_GPP_BASE,
+               .base   = S5P64X0_GPP_BASE,
                .config = &s5p64x0_gpio_cfgs[5],
                .chip   = {
                        .base   = S5P6440_GPP(0),
@@ -292,6 +310,142 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
        },
 };
 
+static struct s3c_gpio_chip s5p6450_gpio_4bit[] = {
+       {
+               .base   = S5P64X0_GPA_BASE,
+               .config = &s5p64x0_gpio_cfgs[1],
+               .chip   = {
+                       .base   = S5P6450_GPA(0),
+                       .ngpio  = S5P6450_GPIO_A_NR,
+                       .label  = "GPA",
+               },
+       }, {
+               .base   = S5P64X0_GPB_BASE,
+               .config = &s5p64x0_gpio_cfgs[1],
+               .chip   = {
+                       .base   = S5P6450_GPB(0),
+                       .ngpio  = S5P6450_GPIO_B_NR,
+                       .label  = "GPB",
+               },
+       }, {
+               .base   = S5P64X0_GPC_BASE,
+               .config = &s5p64x0_gpio_cfgs[1],
+               .chip   = {
+                       .base   = S5P6450_GPC(0),
+                       .ngpio  = S5P6450_GPIO_C_NR,
+                       .label  = "GPC",
+               },
+       }, {
+               .base   = S5P6450_GPD_BASE,
+               .config = &s5p64x0_gpio_cfgs[1],
+               .chip   = {
+                       .base   = S5P6450_GPD(0),
+                       .ngpio  = S5P6450_GPIO_D_NR,
+                       .label  = "GPD",
+               },
+       }, {
+               .base   = S5P6450_GPK_BASE,
+               .config = &s5p64x0_gpio_cfgs[1],
+               .chip   = {
+                       .base   = S5P6450_GPK(0),
+                       .ngpio  = S5P6450_GPIO_K_NR,
+                       .label  = "GPK",
+               },
+       },
+};
+
+static struct s3c_gpio_chip s5p6450_gpio_4bit2[] = {
+       {
+               .base   = S5P64X0_GPG_BASE + 0x4,
+               .config = &s5p64x0_gpio_cfgs[1],
+               .chip   = {
+                       .base   = S5P6450_GPG(0),
+                       .ngpio  = S5P6450_GPIO_G_NR,
+                       .label  = "GPG",
+               },
+       }, {
+               .base   = S5P64X0_GPH_BASE + 0x4,
+               .config = &s5p64x0_gpio_cfgs[1],
+               .chip   = {
+                       .base   = S5P6450_GPH(0),
+                       .ngpio  = S5P6450_GPIO_H_NR,
+                       .label  = "GPH",
+               },
+       },
+};
+
+static struct s3c_gpio_chip s5p6450_gpio_rbank_4bit2[] = {
+       {
+               .base   = S5P64X0_GPR_BASE + 0x4,
+               .config = &s5p64x0_gpio_cfgs[2],
+               .chip   = {
+                       .base   = S5P6450_GPR(0),
+                       .ngpio  = S5P6450_GPIO_R_NR,
+                       .label  = "GPR",
+               },
+       },
+};
+
+static struct s3c_gpio_chip s5p6450_gpio_2bit[] = {
+       {
+               .base   = S5P64X0_GPF_BASE,
+               .config = &s5p64x0_gpio_cfgs[5],
+               .chip   = {
+                       .base   = S5P6450_GPF(0),
+                       .ngpio  = S5P6450_GPIO_F_NR,
+                       .label  = "GPF",
+               },
+       }, {
+               .base   = S5P64X0_GPI_BASE,
+               .config = &s5p64x0_gpio_cfgs[3],
+               .chip   = {
+                       .base   = S5P6450_GPI(0),
+                       .ngpio  = S5P6450_GPIO_I_NR,
+                       .label  = "GPI",
+               },
+       }, {
+               .base   = S5P64X0_GPJ_BASE,
+               .config = &s5p64x0_gpio_cfgs[3],
+               .chip   = {
+                       .base   = S5P6450_GPJ(0),
+                       .ngpio  = S5P6450_GPIO_J_NR,
+                       .label  = "GPJ",
+               },
+       }, {
+               .base   = S5P64X0_GPN_BASE,
+               .config = &s5p64x0_gpio_cfgs[4],
+               .chip   = {
+                       .base   = S5P6450_GPN(0),
+                       .ngpio  = S5P6450_GPIO_N_NR,
+                       .label  = "GPN",
+               },
+       }, {
+               .base   = S5P64X0_GPP_BASE,
+               .config = &s5p64x0_gpio_cfgs[5],
+               .chip   = {
+                       .base   = S5P6450_GPP(0),
+                       .ngpio  = S5P6450_GPIO_P_NR,
+                       .label  = "GPP",
+               },
+       }, {
+               .base   = S5P6450_GPQ_BASE,
+               .config = &s5p64x0_gpio_cfgs[4],
+               .chip   = {
+                       .base   = S5P6450_GPQ(0),
+                       .ngpio  = S5P6450_GPIO_Q_NR,
+                       .label  = "GPQ",
+               },
+       }, {
+               .base   = S5P6450_GPS_BASE,
+               .config = &s5p64x0_gpio_cfgs[5],
+               .chip   = {
+                       .base   = S5P6450_GPS(0),
+                       .ngpio  = S5P6450_GPIO_S_NR,
+                       .label  = "GPS",
+               },
+       },
+};
+
 void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
 {
        for (; nr_chips > 0; nr_chips--, chipcfg++) {
@@ -317,26 +471,41 @@ static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
        }
 }
 
-static int __init s5p6440_gpiolib_init(void)
+static int __init s5p64x0_gpiolib_init(void)
 {
-       struct s3c_gpio_chip *chips = s5p6440_gpio_2bit;
-       int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit);
+       unsigned int chipid;
+
+       chipid = __raw_readl(S5P64X0_SYS_ID);
 
        s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
                                ARRAY_SIZE(s5p64x0_gpio_cfgs));
 
-       for (; nr_chips > 0; nr_chips--, chips++)
-               s3c_gpiolib_add(chips);
+       if ((chipid & 0xff000) == 0x50000) {
+               samsung_gpiolib_add_2bit_chips(s5p6450_gpio_2bit,
+                                       ARRAY_SIZE(s5p6450_gpio_2bit));
+
+               samsung_gpiolib_add_4bit_chips(s5p6450_gpio_4bit,
+                                       ARRAY_SIZE(s5p6450_gpio_4bit));
 
-       samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit,
-                               ARRAY_SIZE(s5p6440_gpio_4bit));
+               samsung_gpiolib_add_4bit2_chips(s5p6450_gpio_4bit2,
+                                       ARRAY_SIZE(s5p6450_gpio_4bit2));
 
-       samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
-                               ARRAY_SIZE(s5p6440_gpio_4bit2));
+               s5p64x0_gpio_add_rbank_4bit2(s5p6450_gpio_rbank_4bit2,
+                                       ARRAY_SIZE(s5p6450_gpio_rbank_4bit2));
+       } else {
+               samsung_gpiolib_add_2bit_chips(s5p6440_gpio_2bit,
+                                       ARRAY_SIZE(s5p6440_gpio_2bit));
 
-       s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2,
-                               ARRAY_SIZE(s5p6440_gpio_rbank_4bit2));
+               samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit,
+                                       ARRAY_SIZE(s5p6440_gpio_4bit));
+
+               samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
+                                       ARRAY_SIZE(s5p6440_gpio_4bit2));
+
+               s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2,
+                                       ARRAY_SIZE(s5p6440_gpio_rbank_4bit2));
+       }
 
        return 0;
 }
-arch_initcall(s5p6440_gpiolib_init);
+core_initcall(s5p64x0_gpiolib_init);
index 31e534156e062b29fbd5181232c3cf79ce73aea1..a9365e5ba614a0056c903589365383fe9c142747 100644 (file)
@@ -29,6 +29,9 @@
 #define S5P64X0_PA_VIC0                (0xE4000000)
 #define S5P64X0_PA_VIC1                (0xE4100000)
 
+#define S5P64X0_PA_SROMC       (0xE7000000)
+#define S5P_PA_SROMC           S5P64X0_PA_SROMC
+
 #define S5P64X0_PA_PDMA                (0xE9000000)
 
 #define S5P64X0_PA_TIMER       (0xEA000000)
@@ -63,6 +66,8 @@
 #define S5P64X0_PA_HSMMC(x)    (0xED800000 + ((x) * 0x100000))
 
 #define S5P64X0_PA_I2S         (0xF2000000)
+#define S5P6450_PA_I2S1                0xF2800000
+#define S5P6450_PA_I2S2                0xF2900000
 
 #define S5P64X0_PA_PCM         (0xF2100000)
 
index 85f448e20a8b22cc537f3c844ac16e0612418f4f..0953ef6b1c771ebdd3a1a16ee08729d1f1f5f5a5 100644 (file)
 
 #include <mach/map.h>
 
-/* Will be implemented S5P6442 GPIOlib */
-
 /* Base addresses for each of the banks */
 
-#define S5P6440_GPA_BASE               (S5P_VA_GPIO + 0x0000)
-#define S5P6440_GPB_BASE               (S5P_VA_GPIO + 0x0020)
-#define S5P6440_GPC_BASE               (S5P_VA_GPIO + 0x0040)
-#define S5P6440_GPF_BASE               (S5P_VA_GPIO + 0x00A0)
-#define S5P6440_GPG_BASE               (S5P_VA_GPIO + 0x00C0)
-#define S5P6440_GPH_BASE               (S5P_VA_GPIO + 0x00E0)
-#define S5P6440_GPI_BASE               (S5P_VA_GPIO + 0x0100)
-#define S5P6440_GPJ_BASE               (S5P_VA_GPIO + 0x0120)
-#define S5P6440_GPN_BASE               (S5P_VA_GPIO + 0x0830)
-#define S5P6440_GPP_BASE               (S5P_VA_GPIO + 0x0160)
-#define S5P6440_GPR_BASE               (S5P_VA_GPIO + 0x0290)
-
-#define S5P6440_EINT0CON0              (S5P_VA_GPIO + 0x900)
-#define S5P6440_EINT0FLTCON0           (S5P_VA_GPIO + 0x910)
-#define S5P6440_EINT0FLTCON1           (S5P_VA_GPIO + 0x914)
-#define S5P6440_EINT0MASK              (S5P_VA_GPIO + 0x920)
-#define S5P6440_EINT0PEND              (S5P_VA_GPIO + 0x924)
-
-/* for LCD */
-
-#define S5P6440_SPCON_LCD_SEL_RGB      (1 << 0)
-#define S5P6440_SPCON_LCD_SEL_MASK     (3 << 0)
-
-/*
- * These set of macros are not really useful for the
- * GPF/GPI/GPJ/GPN/GPP, useful for others set of GPIO's (4 bit)
- */
-
-#define S5P6440_GPIO_CONMASK(__gpio)   (0xf << ((__gpio) * 4))
-#define S5P6440_GPIO_INPUT(__gpio)     (0x0 << ((__gpio) * 4))
-#define S5P6440_GPIO_OUTPUT(__gpio)    (0x1 << ((__gpio) * 4))
-
-/*
- * Use these macros for GPF/GPI/GPJ/GPN/GPP set of GPIO (2 bit)
- */
-
-#define S5P6440_GPIO2_CONMASK(__gpio)  (0x3 << ((__gpio) * 2))
-#define S5P6440_GPIO2_INPUT(__gpio)    (0x0 << ((__gpio) * 2))
-#define S5P6440_GPIO2_OUTPUT(__gpio)   (0x1 << ((__gpio) * 2))
+#define S5P64X0_GPA_BASE               (S5P_VA_GPIO + 0x0000)
+#define S5P64X0_GPB_BASE               (S5P_VA_GPIO + 0x0020)
+#define S5P64X0_GPC_BASE               (S5P_VA_GPIO + 0x0040)
+#define S5P64X0_GPF_BASE               (S5P_VA_GPIO + 0x00A0)
+#define S5P64X0_GPG_BASE               (S5P_VA_GPIO + 0x00C0)
+#define S5P64X0_GPH_BASE               (S5P_VA_GPIO + 0x00E0)
+#define S5P64X0_GPI_BASE               (S5P_VA_GPIO + 0x0100)
+#define S5P64X0_GPJ_BASE               (S5P_VA_GPIO + 0x0120)
+#define S5P64X0_GPN_BASE               (S5P_VA_GPIO + 0x0830)
+#define S5P64X0_GPP_BASE               (S5P_VA_GPIO + 0x0160)
+#define S5P64X0_GPR_BASE               (S5P_VA_GPIO + 0x0290)
+
+#define S5P6450_GPD_BASE               (S5P_VA_GPIO + 0x0060)
+#define S5P6450_GPK_BASE               (S5P_VA_GPIO + 0x0140)
+#define S5P6450_GPQ_BASE               (S5P_VA_GPIO + 0x0180)
+#define S5P6450_GPS_BASE               (S5P_VA_GPIO + 0x0300)
 
 #endif /* __ASM_ARCH_REGS_GPIO_H */
index 87c3f03c618c4c7057e052b89909df24711e91ad..e9802755daebf6143b8054a4ecc559f789875dc1 100644 (file)
@@ -117,6 +117,7 @@ static struct s3c2410_platform_i2c s5p6440_i2c1_data __initdata = {
 
 static struct i2c_board_info smdk6440_i2c_devs0[] __initdata = {
        { I2C_BOARD_INFO("24c08", 0x50), },
+       { I2C_BOARD_INFO("wm8580", 0x1b), },
 };
 
 static struct i2c_board_info smdk6440_i2c_devs1[] __initdata = {
index d609f5af2b9803882ad5119e9220a06733aa83a1..b78f56292780b3b25c9ad2ac2aa48c84a4d3feca 100644 (file)
@@ -135,6 +135,7 @@ static struct s3c2410_platform_i2c s5p6450_i2c1_data __initdata = {
 };
 
 static struct i2c_board_info smdk6450_i2c_devs0[] __initdata = {
+       { I2C_BOARD_INFO("wm8580", 0x1b), },
        { I2C_BOARD_INFO("24c08", 0x50), },     /* Samsung KS24C080C EEPROM */
 };
 
index 564e195ec493355737f4bb90a92af18f77f2ae1e..10ab275ebd63b3b574af212253402b4feeb6e091 100644 (file)
@@ -23,17 +23,14 @@ static int s5pc100_cfg_i2s(struct platform_device *pdev)
 {
        /* configure GPIO for i2s port */
        switch (pdev->id) {
+       case 0: /* Dedicated pins */
+               break;
        case 1:
                s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(2));
                break;
-
        case 2:
                s3c_gpio_cfgpin_range(S5PC100_GPG3(0), 5, S3C_GPIO_SFN(4));
                break;
-
-       case -1: /* Dedicated pins */
-               break;
-
        default:
                printk(KERN_ERR "Invalid Device %d\n", pdev->id);
                return -EINVAL;
@@ -42,8 +39,20 @@ static int s5pc100_cfg_i2s(struct platform_device *pdev)
        return 0;
 }
 
-static struct s3c_audio_pdata s3c_i2s_pdata = {
+static const char *rclksrc_v5[] = {
+       [0] = "iis",
+       [1] = "i2sclkd2",
+};
+
+static struct s3c_audio_pdata i2sv5_pdata = {
        .cfg_gpio = s5pc100_cfg_i2s,
+       .type = {
+               .i2s = {
+                       .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
+                                        | QUIRK_NEED_RSTCLR,
+                       .src_clk = rclksrc_v5,
+               },
+       },
 };
 
 static struct resource s5pc100_iis0_resource[] = {
@@ -62,15 +71,34 @@ static struct resource s5pc100_iis0_resource[] = {
                .end   = DMACH_I2S0_RX,
                .flags = IORESOURCE_DMA,
        },
+       [3] = {
+               .start = DMACH_I2S0S_TX,
+               .end = DMACH_I2S0S_TX,
+               .flags = IORESOURCE_DMA,
+       },
 };
 
 struct platform_device s5pc100_device_iis0 = {
-       .name             = "s3c64xx-iis-v4",
-       .id               = -1,
+       .name = "samsung-i2s",
+       .id = 0,
        .num_resources    = ARRAY_SIZE(s5pc100_iis0_resource),
        .resource         = s5pc100_iis0_resource,
        .dev = {
-               .platform_data = &s3c_i2s_pdata,
+               .platform_data = &i2sv5_pdata,
+       },
+};
+
+static const char *rclksrc_v3[] = {
+       [0] = "iis",
+       [1] = "sclk_audio",
+};
+
+static struct s3c_audio_pdata i2sv3_pdata = {
+       .cfg_gpio = s5pc100_cfg_i2s,
+       .type = {
+               .i2s = {
+                       .src_clk = rclksrc_v3,
+               },
        },
 };
 
@@ -93,12 +121,12 @@ static struct resource s5pc100_iis1_resource[] = {
 };
 
 struct platform_device s5pc100_device_iis1 = {
-       .name             = "s3c64xx-iis",
+       .name             = "samsung-i2s",
        .id               = 1,
        .num_resources    = ARRAY_SIZE(s5pc100_iis1_resource),
        .resource         = s5pc100_iis1_resource,
        .dev = {
-               .platform_data = &s3c_i2s_pdata,
+               .platform_data = &i2sv3_pdata,
        },
 };
 
@@ -121,12 +149,12 @@ static struct resource s5pc100_iis2_resource[] = {
 };
 
 struct platform_device s5pc100_device_iis2 = {
-       .name             = "s3c64xx-iis",
+       .name             = "samsung-i2s",
        .id               = 2,
        .num_resources    = ARRAY_SIZE(s5pc100_iis2_resource),
        .resource         = s5pc100_iis2_resource,
        .dev = {
-               .platform_data = &s3c_i2s_pdata,
+               .platform_data = &i2sv3_pdata,
        },
 };
 
index 32e9cab5c8645b0481f092dc3c77eeb2109ceb2e..328467b346aa8915617da405d0ac771a7068c14d 100644 (file)
@@ -55,6 +55,8 @@
 #define S5PC100_VA_VIC_OFFSET  0x10000
 #define S5PC1XX_VA_VIC(x)      (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
 
+#define S5PC100_PA_SROMC       (0xE7000000)
+#define S5P_PA_SROMC           S5PC100_PA_SROMC
 
 #define S5PC100_PA_ONENAND     (0xE7100000)
 
index 862f239a0fdbba45ad4fb895548fac66063ec404..53aabef1e9cee70db39946003b096d102a410650 100644 (file)
@@ -118,6 +118,7 @@ menu "S5PV210 Machines"
 config MACH_SMDKV210
        bool "SMDKV210"
        select CPU_S5PV210
+       select S3C_DEV_FB
        select S3C_DEV_HSMMC
        select S3C_DEV_HSMMC1
        select S3C_DEV_HSMMC2
@@ -130,6 +131,7 @@ config MACH_SMDKV210
        select SAMSUNG_DEV_IDE
        select SAMSUNG_DEV_KEYPAD
        select SAMSUNG_DEV_TS
+       select S5PV210_SETUP_FB_24BPP
        select S5PV210_SETUP_I2C1
        select S5PV210_SETUP_I2C2
        select S5PV210_SETUP_IDE
index 019c3a69b0e476ca3af20f7d47ff076481f54e60..dab6ef3b6ca90a78c25cfe43877b5947633b9b8e 100644 (file)
@@ -467,20 +467,20 @@ static struct clk init_clocks_disable[] = {
                .enable         = s5pv210_clk_ip3_ctrl,
                .ctrlbit        = (1<<21),
        }, {
-               .name           = "i2s_v50",
+               .name           = "iis",
                .id             = 0,
                .parent         = &clk_p,
                .enable         = s5pv210_clk_ip3_ctrl,
                .ctrlbit        = (1<<4),
        }, {
-               .name           = "i2s_v32",
-               .id             = 0,
+               .name           = "iis",
+               .id             = 1,
                .parent         = &clk_p,
                .enable         = s5pv210_clk_ip3_ctrl,
                .ctrlbit        = (1 << 5),
        }, {
-               .name           = "i2s_v32",
-               .id             = 1,
+               .name           = "iis",
+               .id             = 2,
                .parent         = &clk_p,
                .enable         = s5pv210_clk_ip3_ctrl,
                .ctrlbit        = (1 << 6),
@@ -525,6 +525,12 @@ static struct clk init_clocks[] = {
                .parent         = &clk_pclk_psys.clk,
                .enable         = s5pv210_clk_ip3_ctrl,
                .ctrlbit        = (1 << 20),
+       }, {
+               .name           = "sromc",
+               .id             = -1,
+               .parent         = &clk_hclk_psys.clk,
+               .enable         = s5pv210_clk_ip1_ctrl,
+               .ctrlbit        = (1 << 26),
        },
 };
 
index 8eb480e201b054bfa4eed1408b5e0f02961a4b20..61e6c24b90ac5ecdf551dc870af850ac83708053 100644 (file)
@@ -80,11 +80,6 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
                .pfn            = __phys_to_pfn(S3C_PA_UART),
                .length         = SZ_512K,
                .type           = MT_DEVICE,
-       }, {
-               .virtual        = (unsigned long)S5P_VA_SROMC,
-               .pfn            = __phys_to_pfn(S5PV210_PA_SROMC),
-               .length         = SZ_4K,
-               .type           = MT_DEVICE,
        }, {
                .virtual        = (unsigned long)S5P_VA_DMC0,
                .pfn            = __phys_to_pfn(S5PV210_PA_DMC0),
index 1303fcb12b517b7b71b3ef03876b9cd0635dfd8f..ddd2704b34679e70d6d20dc7fb4dc70f7ace1bec 100644 (file)
 #include <mach/dma.h>
 #include <mach/irqs.h>
 
+static const char *rclksrc[] = {
+       [0] = "busclk",
+       [1] = "i2sclk",
+};
+
 static int s5pv210_cfg_i2s(struct platform_device *pdev)
 {
        /* configure GPIO for i2s port */
        switch (pdev->id) {
+       case 0:
+               s3c_gpio_cfgpin_range(S5PV210_GPI(0), 7, S3C_GPIO_SFN(2));
+               break;
        case 1:
                s3c_gpio_cfgpin_range(S5PV210_GPC0(0), 5, S3C_GPIO_SFN(2));
                break;
-
        case 2:
                s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 5, S3C_GPIO_SFN(4));
                break;
-
-       case -1:
-               s3c_gpio_cfgpin_range(S5PV210_GPI(0), 7, S3C_GPIO_SFN(2));
-               break;
-
        default:
                printk(KERN_ERR "Invalid Device %d\n", pdev->id);
                return -EINVAL;
@@ -43,8 +45,15 @@ static int s5pv210_cfg_i2s(struct platform_device *pdev)
        return 0;
 }
 
-static struct s3c_audio_pdata s3c_i2s_pdata = {
+static struct s3c_audio_pdata i2sv5_pdata = {
        .cfg_gpio = s5pv210_cfg_i2s,
+       .type = {
+               .i2s = {
+                       .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
+                                        | QUIRK_NEED_RSTCLR,
+                       .src_clk = rclksrc,
+               },
+       },
 };
 
 static struct resource s5pv210_iis0_resource[] = {
@@ -63,15 +72,34 @@ static struct resource s5pv210_iis0_resource[] = {
                .end   = DMACH_I2S0_RX,
                .flags = IORESOURCE_DMA,
        },
+       [3] = {
+               .start = DMACH_I2S0S_TX,
+               .end = DMACH_I2S0S_TX,
+               .flags = IORESOURCE_DMA,
+       },
 };
 
 struct platform_device s5pv210_device_iis0 = {
-       .name             = "s3c64xx-iis-v4",
-       .id               = -1,
+       .name = "samsung-i2s",
+       .id = 0,
        .num_resources    = ARRAY_SIZE(s5pv210_iis0_resource),
        .resource         = s5pv210_iis0_resource,
        .dev = {
-               .platform_data = &s3c_i2s_pdata,
+               .platform_data = &i2sv5_pdata,
+       },
+};
+
+static const char *rclksrc_v3[] = {
+       [0] = "iis",
+       [1] = "audio-bus",
+};
+
+static struct s3c_audio_pdata i2sv3_pdata = {
+       .cfg_gpio = s5pv210_cfg_i2s,
+       .type = {
+               .i2s = {
+                       .src_clk = rclksrc_v3,
+               },
        },
 };
 
@@ -94,12 +122,12 @@ static struct resource s5pv210_iis1_resource[] = {
 };
 
 struct platform_device s5pv210_device_iis1 = {
-       .name             = "s3c64xx-iis",
+       .name             = "samsung-i2s",
        .id               = 1,
        .num_resources    = ARRAY_SIZE(s5pv210_iis1_resource),
        .resource         = s5pv210_iis1_resource,
        .dev = {
-               .platform_data = &s3c_i2s_pdata,
+               .platform_data = &i2sv3_pdata,
        },
 };
 
@@ -122,12 +150,12 @@ static struct resource s5pv210_iis2_resource[] = {
 };
 
 struct platform_device s5pv210_device_iis2 = {
-       .name             = "s3c64xx-iis",
+       .name             = "samsung-i2s",
        .id               = 2,
        .num_resources    = ARRAY_SIZE(s5pv210_iis2_resource),
        .resource         = s5pv210_iis2_resource,
        .dev = {
-               .platform_data = &s3c_i2s_pdata,
+               .platform_data = &i2sv3_pdata,
        },
 };
 
index 119b95fdc3cef1c945124f4e8cc21e89b3854f65..26710b35ef87184f5a4c66f295d00c93847e0508 100644 (file)
@@ -65,7 +65,7 @@
 #define IRQ_HSMMC0             S5P_IRQ_VIC1(26)
 #define IRQ_HSMMC1             S5P_IRQ_VIC1(27)
 #define IRQ_HSMMC2             S5P_IRQ_VIC1(28)
-#define IRQ_MIPICSI            S5P_IRQ_VIC1(29)
+#define IRQ_MIPI_CSIS          S5P_IRQ_VIC1(29)
 #define IRQ_MIPIDSI            S5P_IRQ_VIC1(30)
 #define IRQ_ONENAND_AUDI       S5P_IRQ_VIC1(31)
 
 #define IRQ_LCD_FIFO           IRQ_LCD0
 #define IRQ_LCD_VSYNC          IRQ_LCD1
 #define IRQ_LCD_SYSTEM         IRQ_LCD2
+#define IRQ_MIPI_CSIS0         IRQ_MIPI_CSIS
 
 #endif /* ASM_ARCH_IRQS_H */
index 861d7fe11fc99db6ee0427adcf5babe028c04806..3611492ad681dbb59394031ed3270723b7cfd5f8 100644 (file)
@@ -16,6 +16,8 @@
 #include <plat/map-base.h>
 #include <plat/map-s5p.h>
 
+#define S5PV210_PA_SROM_BANK5  (0xA8000000)
+
 #define S5PC110_PA_ONENAND     (0xB0000000)
 #define S5P_PA_ONENAND         S5PC110_PA_ONENAND
 
@@ -60,6 +62,7 @@
 #define S3C_VA_UARTx(x)                (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
 
 #define S5PV210_PA_SROMC       (0xE8000000)
+#define S5P_PA_SROMC           S5PV210_PA_SROMC
 
 #define S5PV210_PA_CFCON       (0xE8200000)
 
 #define S5PV210_PA_DMC0                (0xF0000000)
 #define S5PV210_PA_DMC1                (0xF1400000)
 
+#define S5PV210_PA_MIPI_CSIS   0xFA600000
+
 /* compatibiltiy defines. */
 #define S3C_PA_UART            S5PV210_PA_UART
 #define S3C_PA_HSMMC0          S5PV210_PA_HSMMC(0)
 #define S5P_PA_FIMC0           S5PV210_PA_FIMC0
 #define S5P_PA_FIMC1           S5PV210_PA_FIMC1
 #define S5P_PA_FIMC2           S5PV210_PA_FIMC2
+#define S5P_PA_MIPI_CSIS0      S5PV210_PA_MIPI_CSIS
 
 #define SAMSUNG_PA_ADC         S5PV210_PA_ADC
 #define SAMSUNG_PA_CFCON       S5PV210_PA_CFCON
index ebaabe021af911e642eb0d830b913d37fec6e5d4..4c45b74def5f0fb5063edf1a7bcbea615f54099b 100644 (file)
 #define S5P_MDNIE_SEL          S5P_CLKREG(0x7008)
 #define S5P_MIPI_PHY_CON0      S5P_CLKREG(0x7200)
 #define S5P_MIPI_PHY_CON1      S5P_CLKREG(0x7204)
-#define S5P_MIPI_CONTROL       S5P_CLKREG(0xE814)
+#define S5P_MIPI_DPHY_CONTROL  S5P_CLKREG(0xE814)
 
 #define S5P_IDLE_CFG_TL_MASK   (3 << 30)
 #define S5P_IDLE_CFG_TM_MASK   (3 << 28)
 #define S5P_OTHERS_RET_UART            (1 << 28)
 #define S5P_OTHERS_USB_SIG_MASK                (1 << 16)
 
-/* MIPI */
-#define S5P_MIPI_DPHY_EN               (3)
-
 /* S5P_DAC_CONTROL */
 #define S5P_DAC_ENABLE                 (1)
 #define S5P_DAC_DISABLE                        (0)
index 5dd1681c069e582f0f6cb7a61f26e5f6f041ca7c..bb20a14da100c132e6646dbae2f4ecaff3176441 100644 (file)
@@ -94,6 +94,7 @@ static struct platform_device *smdkc110_devices[] __initdata = {
 
 static struct i2c_board_info smdkc110_i2c_devs0[] __initdata = {
        { I2C_BOARD_INFO("24c08", 0x50), },     /* Samsung S524AD0XD1 */
+       { I2C_BOARD_INFO("wm8580", 0x1b), },
 };
 
 static struct i2c_board_info smdkc110_i2c_devs1[] __initdata = {
index 1fbc45b2a4326e89c3de305c9c6a33840b99351b..88e45223c8af6bb338e5fb864fb9cfca90142bf8 100644 (file)
 #include <linux/init.h>
 #include <linux/serial_core.h>
 #include <linux/sysdev.h>
+#include <linux/dm9000.h>
+#include <linux/fb.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 
+#include <video/platform_lcd.h>
+
 #include <mach/map.h>
 #include <mach/regs-clock.h>
+#include <mach/regs-fb.h>
 
 #include <plat/regs-serial.h>
+#include <plat/regs-srom.h>
+#include <plat/gpio-cfg.h>
 #include <plat/s5pv210.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
@@ -33,6 +42,7 @@
 #include <plat/iic.h>
 #include <plat/keypad.h>
 #include <plat/pm.h>
+#include <plat/fb.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define SMDKV210_UCON_DEFAULT  (S3C2410_UCON_TXILEVEL |        \
@@ -102,12 +112,106 @@ static struct samsung_keypad_platdata smdkv210_keypad_data __initdata = {
        .cols           = 8,
 };
 
+static struct resource smdkv210_dm9000_resources[] = {
+       [0] = {
+               .start  = S5PV210_PA_SROM_BANK5,
+               .end    = S5PV210_PA_SROM_BANK5,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = S5PV210_PA_SROM_BANK5 + 2,
+               .end    = S5PV210_PA_SROM_BANK5 + 2,
+               .flags  = IORESOURCE_MEM,
+       },
+       [2] = {
+               .start  = IRQ_EINT(9),
+               .end    = IRQ_EINT(9),
+               .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
+       },
+};
+
+static struct dm9000_plat_data smdkv210_dm9000_platdata = {
+       .flags          = DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM,
+       .dev_addr       = { 0x00, 0x09, 0xc0, 0xff, 0xec, 0x48 },
+};
+
+struct platform_device smdkv210_dm9000 = {
+       .name           = "dm9000",
+       .id             = -1,
+       .num_resources  = ARRAY_SIZE(smdkv210_dm9000_resources),
+       .resource       = smdkv210_dm9000_resources,
+       .dev            = {
+               .platform_data  = &smdkv210_dm9000_platdata,
+       },
+};
+
+static void smdkv210_lte480wv_set_power(struct plat_lcd_data *pd,
+                                       unsigned int power)
+{
+       if (power) {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+               gpio_request(S5PV210_GPD0(3), "GPD0");
+               gpio_direction_output(S5PV210_GPD0(3), 1);
+               gpio_free(S5PV210_GPD0(3));
+#endif
+
+               /* fire nRESET on power up */
+               gpio_request(S5PV210_GPH0(6), "GPH0");
+
+               gpio_direction_output(S5PV210_GPH0(6), 1);
+
+               gpio_set_value(S5PV210_GPH0(6), 0);
+               mdelay(10);
+
+               gpio_set_value(S5PV210_GPH0(6), 1);
+               mdelay(10);
+
+               gpio_free(S5PV210_GPH0(6));
+       } else {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+               gpio_request(S5PV210_GPD0(3), "GPD0");
+               gpio_direction_output(S5PV210_GPD0(3), 0);
+               gpio_free(S5PV210_GPD0(3));
+#endif
+       }
+}
+
+static struct plat_lcd_data smdkv210_lcd_lte480wv_data = {
+       .set_power      = smdkv210_lte480wv_set_power,
+};
+
+static struct platform_device smdkv210_lcd_lte480wv = {
+       .name                   = "platform-lcd",
+       .dev.parent             = &s3c_device_fb.dev,
+       .dev.platform_data      = &smdkv210_lcd_lte480wv_data,
+};
+
+static struct s3c_fb_pd_win smdkv210_fb_win0 = {
+       .win_mode = {
+               .left_margin    = 13,
+               .right_margin   = 8,
+               .upper_margin   = 7,
+               .lower_margin   = 5,
+               .hsync_len      = 3,
+               .vsync_len      = 1,
+               .xres           = 800,
+               .yres           = 480,
+       },
+       .max_bpp        = 32,
+       .default_bpp    = 24,
+};
+
+static struct s3c_fb_platdata smdkv210_lcd0_pdata __initdata = {
+       .win[0]         = &smdkv210_fb_win0,
+       .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+       .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+       .setup_gpio     = s5pv210_fb_gpio_setup_24bpp,
+};
+
 static struct platform_device *smdkv210_devices[] __initdata = {
-       &s5pv210_device_iis0,
-       &s5pv210_device_ac97,
-       &s5pv210_device_spdif,
        &s3c_device_adc,
        &s3c_device_cfcon,
+       &s3c_device_fb,
        &s3c_device_hsmmc0,
        &s3c_device_hsmmc1,
        &s3c_device_hsmmc2,
@@ -115,14 +219,37 @@ static struct platform_device *smdkv210_devices[] __initdata = {
        &s3c_device_i2c0,
        &s3c_device_i2c1,
        &s3c_device_i2c2,
-       &samsung_device_keypad,
        &s3c_device_rtc,
        &s3c_device_ts,
        &s3c_device_wdt,
+       &s5pv210_device_ac97,
+       &s5pv210_device_iis0,
+       &s5pv210_device_spdif,
+       &samsung_device_keypad,
+       &smdkv210_dm9000,
+       &smdkv210_lcd_lte480wv,
 };
 
+static void __init smdkv210_dm9000_init(void)
+{
+       unsigned int tmp;
+
+       gpio_request(S5PV210_MP01(5), "nCS5");
+       s3c_gpio_cfgpin(S5PV210_MP01(5), S3C_GPIO_SFN(2));
+       gpio_free(S5PV210_MP01(5));
+
+       tmp = (5 << S5P_SROM_BCX__TACC__SHIFT);
+       __raw_writel(tmp, S5P_SROM_BC5);
+
+       tmp = __raw_readl(S5P_SROM_BW);
+       tmp &= (S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS5__SHIFT);
+       tmp |= (1 << S5P_SROM_BW__NCS5__SHIFT);
+       __raw_writel(tmp, S5P_SROM_BW);
+}
+
 static struct i2c_board_info smdkv210_i2c_devs0[] __initdata = {
        { I2C_BOARD_INFO("24c08", 0x50), },     /* Samsung S524AD0XD1 */
+       { I2C_BOARD_INFO("wm8580", 0x1b), },
 };
 
 static struct i2c_board_info smdkv210_i2c_devs1[] __initdata = {
@@ -150,6 +277,8 @@ static void __init smdkv210_machine_init(void)
 {
        s3c_pm_init();
 
+       smdkv210_dm9000_init();
+
        samsung_keypad_set_platdata(&smdkv210_keypad_data);
        s3c24xx_ts_set_platdata(&s3c_ts_platform);
 
@@ -165,6 +294,8 @@ static void __init smdkv210_machine_init(void)
 
        s3c_ide_set_platdata(&smdkv210_ide_pdata);
 
+       s3c_fb_set_platdata(&smdkv210_lcd0_pdata);
+
        platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices));
 }
 
index e0cef3fd165ef2816e323e598049493ea08425e9..b7aa3cd2198af023b15d31dec738d8aff5b37041 100644 (file)
@@ -11,6 +11,7 @@ if ARCH_S5PV310
 
 config CPU_S5PV310
        bool
+       select S3C_PL330_DMA
        help
          Enable S5PV310 CPU support
 
@@ -74,11 +75,13 @@ config MACH_SMDKC210
        select CPU_S5PV310
        select S3C_DEV_RTC
        select S3C_DEV_WDT
+       select S3C_DEV_I2C1
        select S3C_DEV_HSMMC
        select S3C_DEV_HSMMC1
        select S3C_DEV_HSMMC2
        select S3C_DEV_HSMMC3
        select S5PV310_DEV_PD
+       select S5PV310_SETUP_I2C1
        select S5PV310_SETUP_SDHCI
        help
          Machine support for Samsung SMDKC210
@@ -107,11 +110,13 @@ config MACH_SMDKV310
        select CPU_S5PV310
        select S3C_DEV_RTC
        select S3C_DEV_WDT
+       select S3C_DEV_I2C1
        select S3C_DEV_HSMMC
        select S3C_DEV_HSMMC1
        select S3C_DEV_HSMMC2
        select S3C_DEV_HSMMC3
        select S5PV310_DEV_PD
+       select S5PV310_SETUP_I2C1
        select S5PV310_SETUP_SDHCI
        help
          Machine support for Samsung SMDKV310
index ef9650827136210dcab68496e79887d6029188d7..651f1933e22856c121a55cc2740d6dd522ded72c 100644 (file)
@@ -13,7 +13,7 @@ obj-                          :=
 # Core support for S5PV310 system
 
 obj-$(CONFIG_CPU_S5PV310)      += cpu.o init.o clock.o irq-combiner.o
-obj-$(CONFIG_CPU_S5PV310)      += setup-i2c0.o time.o gpiolib.o irq-eint.o
+obj-$(CONFIG_CPU_S5PV310)      += setup-i2c0.o time.o gpiolib.o irq-eint.o dma.o
 obj-$(CONFIG_CPU_FREQ)         += cpufreq.o
 
 obj-$(CONFIG_SMP)              += platsmp.o headsmp.o
index 752a07ed7c19cc5517d290a6b11cefc474b3241b..753fa446587652f89c2baef4967b2d26db2c1305 100644 (file)
@@ -466,6 +466,16 @@ static struct clk init_clocks_disable[] = {
                .id             = -1,
                .enable         = s5pv310_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 10),
+       }, {
+               .name           = "pdma",
+               .id             = 0,
+               .enable         = s5pv310_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 0),
+       }, {
+               .name           = "pdma",
+               .id             = 1,
+               .enable         = s5pv310_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 1),
        }, {
                .name           = "adc",
                .id             = -1,
@@ -506,6 +516,26 @@ static struct clk init_clocks_disable[] = {
                .id             = 2,
                .enable         = s5pv310_clk_ip_peril_ctrl,
                .ctrlbit        = (1 << 18),
+       }, {
+               .name           = "iis",
+               .id             = 0,
+               .enable         = s5pv310_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 19),
+       }, {
+               .name           = "iis",
+               .id             = 1,
+               .enable         = s5pv310_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 20),
+       }, {
+               .name           = "iis",
+               .id             = 2,
+               .enable         = s5pv310_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 21),
+       }, {
+               .name           = "ac97",
+               .id             = -1,
+               .enable         = s5pv310_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 27),
        }, {
                .name           = "fimg2d",
                .id             = -1,
diff --git a/arch/arm/mach-s5pv310/dev-audio.c b/arch/arm/mach-s5pv310/dev-audio.c
new file mode 100644 (file)
index 0000000..a196424
--- /dev/null
@@ -0,0 +1,364 @@
+/* linux/arch/arm/mach-s5pv310/dev-audio.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co. Ltd
+ *     Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/gpio.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/audio.h>
+
+#include <mach/map.h>
+#include <mach/dma.h>
+#include <mach/irqs.h>
+
+static const char *rclksrc[] = {
+       [0] = "busclk",
+       [1] = "i2sclk",
+};
+
+static int s5pv310_cfg_i2s(struct platform_device *pdev)
+{
+       /* configure GPIO for i2s port */
+       switch (pdev->id) {
+       case 0:
+               s3c_gpio_cfgpin_range(S5PV310_GPZ(0), 7, S3C_GPIO_SFN(2));
+               break;
+       case 1:
+               s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(2));
+               break;
+       case 2:
+               s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 5, S3C_GPIO_SFN(4));
+               break;
+       default:
+               printk(KERN_ERR "Invalid Device %d\n", pdev->id);
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+static struct s3c_audio_pdata i2sv5_pdata = {
+       .cfg_gpio = s5pv310_cfg_i2s,
+       .type = {
+               .i2s = {
+                       .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
+                                        | QUIRK_NEED_RSTCLR,
+                       .src_clk = rclksrc,
+               },
+       },
+};
+
+static struct resource s5pv310_i2s0_resource[] = {
+       [0] = {
+               .start  = S5PV310_PA_I2S0,
+               .end    = S5PV310_PA_I2S0 + 0x100 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = DMACH_I2S0_TX,
+               .end    = DMACH_I2S0_TX,
+               .flags  = IORESOURCE_DMA,
+       },
+       [2] = {
+               .start  = DMACH_I2S0_RX,
+               .end    = DMACH_I2S0_RX,
+               .flags  = IORESOURCE_DMA,
+       },
+       [3] = {
+               .start  = DMACH_I2S0S_TX,
+               .end    = DMACH_I2S0S_TX,
+               .flags  = IORESOURCE_DMA,
+       },
+};
+
+struct platform_device s5pv310_device_i2s0 = {
+       .name = "samsung-i2s",
+       .id = 0,
+       .num_resources = ARRAY_SIZE(s5pv310_i2s0_resource),
+       .resource = s5pv310_i2s0_resource,
+       .dev = {
+               .platform_data = &i2sv5_pdata,
+       },
+};
+
+static const char *rclksrc_v3[] = {
+       [0] = "sclk_i2s",
+       [1] = "no_such_clock",
+};
+
+static struct s3c_audio_pdata i2sv3_pdata = {
+       .cfg_gpio = s5pv310_cfg_i2s,
+       .type = {
+               .i2s = {
+                       .quirks = QUIRK_NO_MUXPSR,
+                       .src_clk = rclksrc_v3,
+               },
+       },
+};
+
+static struct resource s5pv310_i2s1_resource[] = {
+       [0] = {
+               .start  = S5PV310_PA_I2S1,
+               .end    = S5PV310_PA_I2S1 + 0x100 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = DMACH_I2S1_TX,
+               .end    = DMACH_I2S1_TX,
+               .flags  = IORESOURCE_DMA,
+       },
+       [2] = {
+               .start  = DMACH_I2S1_RX,
+               .end    = DMACH_I2S1_RX,
+               .flags  = IORESOURCE_DMA,
+       },
+};
+
+struct platform_device s5pv310_device_i2s1 = {
+       .name = "samsung-i2s",
+       .id = 1,
+       .num_resources = ARRAY_SIZE(s5pv310_i2s1_resource),
+       .resource = s5pv310_i2s1_resource,
+       .dev = {
+               .platform_data = &i2sv3_pdata,
+       },
+};
+
+static struct resource s5pv310_i2s2_resource[] = {
+       [0] = {
+               .start  = S5PV310_PA_I2S2,
+               .end    = S5PV310_PA_I2S2 + 0x100 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = DMACH_I2S2_TX,
+               .end    = DMACH_I2S2_TX,
+               .flags  = IORESOURCE_DMA,
+       },
+       [2] = {
+               .start  = DMACH_I2S2_RX,
+               .end    = DMACH_I2S2_RX,
+               .flags  = IORESOURCE_DMA,
+       },
+};
+
+struct platform_device s5pv310_device_i2s2 = {
+       .name = "samsung-i2s",
+       .id = 2,
+       .num_resources = ARRAY_SIZE(s5pv310_i2s2_resource),
+       .resource = s5pv310_i2s2_resource,
+       .dev = {
+               .platform_data = &i2sv3_pdata,
+       },
+};
+
+/* PCM Controller platform_devices */
+
+static int s5pv310_pcm_cfg_gpio(struct platform_device *pdev)
+{
+       switch (pdev->id) {
+       case 0:
+               s3c_gpio_cfgpin_range(S5PV310_GPZ(0), 5, S3C_GPIO_SFN(3));
+               break;
+       case 1:
+               s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(3));
+               break;
+       case 2:
+               s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 5, S3C_GPIO_SFN(3));
+               break;
+       default:
+               printk(KERN_DEBUG "Invalid PCM Controller number!");
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+static struct s3c_audio_pdata s3c_pcm_pdata = {
+       .cfg_gpio = s5pv310_pcm_cfg_gpio,
+};
+
+static struct resource s5pv310_pcm0_resource[] = {
+       [0] = {
+               .start  = S5PV310_PA_PCM0,
+               .end    = S5PV310_PA_PCM0 + 0x100 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = DMACH_PCM0_TX,
+               .end    = DMACH_PCM0_TX,
+               .flags  = IORESOURCE_DMA,
+       },
+       [2] = {
+               .start  = DMACH_PCM0_RX,
+               .end    = DMACH_PCM0_RX,
+               .flags  = IORESOURCE_DMA,
+       },
+};
+
+struct platform_device s5pv310_device_pcm0 = {
+       .name = "samsung-pcm",
+       .id = 0,
+       .num_resources = ARRAY_SIZE(s5pv310_pcm0_resource),
+       .resource = s5pv310_pcm0_resource,
+       .dev = {
+               .platform_data = &s3c_pcm_pdata,
+       },
+};
+
+static struct resource s5pv310_pcm1_resource[] = {
+       [0] = {
+               .start  = S5PV310_PA_PCM1,
+               .end    = S5PV310_PA_PCM1 + 0x100 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = DMACH_PCM1_TX,
+               .end    = DMACH_PCM1_TX,
+               .flags  = IORESOURCE_DMA,
+       },
+       [2] = {
+               .start  = DMACH_PCM1_RX,
+               .end    = DMACH_PCM1_RX,
+               .flags  = IORESOURCE_DMA,
+       },
+};
+
+struct platform_device s5pv310_device_pcm1 = {
+       .name = "samsung-pcm",
+       .id = 1,
+       .num_resources = ARRAY_SIZE(s5pv310_pcm1_resource),
+       .resource = s5pv310_pcm1_resource,
+       .dev = {
+               .platform_data = &s3c_pcm_pdata,
+       },
+};
+
+static struct resource s5pv310_pcm2_resource[] = {
+       [0] = {
+               .start  = S5PV310_PA_PCM2,
+               .end    = S5PV310_PA_PCM2 + 0x100 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = DMACH_PCM2_TX,
+               .end    = DMACH_PCM2_TX,
+               .flags  = IORESOURCE_DMA,
+       },
+       [2] = {
+               .start  = DMACH_PCM2_RX,
+               .end    = DMACH_PCM2_RX,
+               .flags  = IORESOURCE_DMA,
+       },
+};
+
+struct platform_device s5pv310_device_pcm2 = {
+       .name = "samsung-pcm",
+       .id = 2,
+       .num_resources = ARRAY_SIZE(s5pv310_pcm2_resource),
+       .resource = s5pv310_pcm2_resource,
+       .dev = {
+               .platform_data = &s3c_pcm_pdata,
+       },
+};
+
+/* AC97 Controller platform devices */
+
+static int s5pv310_ac97_cfg_gpio(struct platform_device *pdev)
+{
+       return s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(4));
+}
+
+static struct resource s5pv310_ac97_resource[] = {
+       [0] = {
+               .start  = S5PV310_PA_AC97,
+               .end    = S5PV310_PA_AC97 + 0x100 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = DMACH_AC97_PCMOUT,
+               .end    = DMACH_AC97_PCMOUT,
+               .flags  = IORESOURCE_DMA,
+       },
+       [2] = {
+               .start  = DMACH_AC97_PCMIN,
+               .end    = DMACH_AC97_PCMIN,
+               .flags  = IORESOURCE_DMA,
+       },
+       [3] = {
+               .start  = DMACH_AC97_MICIN,
+               .end    = DMACH_AC97_MICIN,
+               .flags  = IORESOURCE_DMA,
+       },
+       [4] = {
+               .start  = IRQ_AC97,
+               .end    = IRQ_AC97,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct s3c_audio_pdata s3c_ac97_pdata = {
+       .cfg_gpio = s5pv310_ac97_cfg_gpio,
+};
+
+static u64 s5pv310_ac97_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device s5pv310_device_ac97 = {
+       .name = "samsung-ac97",
+       .id = -1,
+       .num_resources = ARRAY_SIZE(s5pv310_ac97_resource),
+       .resource = s5pv310_ac97_resource,
+       .dev = {
+               .platform_data = &s3c_ac97_pdata,
+               .dma_mask = &s5pv310_ac97_dmamask,
+               .coherent_dma_mask = DMA_BIT_MASK(32),
+       },
+};
+
+/* S/PDIF Controller platform_device */
+
+static int s5pv310_spdif_cfg_gpio(struct platform_device *pdev)
+{
+       s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 2, S3C_GPIO_SFN(3));
+
+       return 0;
+}
+
+static struct resource s5pv310_spdif_resource[] = {
+       [0] = {
+               .start  = S5PV310_PA_SPDIF,
+               .end    = S5PV310_PA_SPDIF + 0x100 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = DMACH_SPDIF,
+               .end    = DMACH_SPDIF,
+               .flags  = IORESOURCE_DMA,
+       },
+};
+
+static struct s3c_audio_pdata samsung_spdif_pdata = {
+       .cfg_gpio = s5pv310_spdif_cfg_gpio,
+};
+
+static u64 s5pv310_spdif_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device s5pv310_device_spdif = {
+       .name = "samsung-spdif",
+       .id = -1,
+       .num_resources = ARRAY_SIZE(s5pv310_spdif_resource),
+       .resource = s5pv310_spdif_resource,
+       .dev = {
+               .platform_data = &samsung_spdif_pdata,
+               .dma_mask = &s5pv310_spdif_dmamask,
+               .coherent_dma_mask = DMA_BIT_MASK(32),
+       },
+};
diff --git a/arch/arm/mach-s5pv310/dma.c b/arch/arm/mach-s5pv310/dma.c
new file mode 100644 (file)
index 0000000..20066c7
--- /dev/null
@@ -0,0 +1,168 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *     Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <plat/devs.h>
+#include <plat/irqs.h>
+
+#include <mach/map.h>
+#include <mach/irqs.h>
+
+#include <plat/s3c-pl330-pdata.h>
+
+static u64 dma_dmamask = DMA_BIT_MASK(32);
+
+static struct resource s5pv310_pdma0_resource[] = {
+       [0] = {
+               .start  = S5PV310_PA_PDMA0,
+               .end    = S5PV310_PA_PDMA0 + SZ_4K,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = IRQ_PDMA0,
+               .end    = IRQ_PDMA0,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct s3c_pl330_platdata s5pv310_pdma0_pdata = {
+       .peri = {
+               [0] = DMACH_PCM0_RX,
+               [1] = DMACH_PCM0_TX,
+               [2] = DMACH_PCM2_RX,
+               [3] = DMACH_PCM2_TX,
+               [4] = DMACH_MSM_REQ0,
+               [5] = DMACH_MSM_REQ2,
+               [6] = DMACH_SPI0_RX,
+               [7] = DMACH_SPI0_TX,
+               [8] = DMACH_SPI2_RX,
+               [9] = DMACH_SPI2_TX,
+               [10] = DMACH_I2S0S_TX,
+               [11] = DMACH_I2S0_RX,
+               [12] = DMACH_I2S0_TX,
+               [13] = DMACH_I2S2_RX,
+               [14] = DMACH_I2S2_TX,
+               [15] = DMACH_UART0_RX,
+               [16] = DMACH_UART0_TX,
+               [17] = DMACH_UART2_RX,
+               [18] = DMACH_UART2_TX,
+               [19] = DMACH_UART4_RX,
+               [20] = DMACH_UART4_TX,
+               [21] = DMACH_SLIMBUS0_RX,
+               [22] = DMACH_SLIMBUS0_TX,
+               [23] = DMACH_SLIMBUS2_RX,
+               [24] = DMACH_SLIMBUS2_TX,
+               [25] = DMACH_SLIMBUS4_RX,
+               [26] = DMACH_SLIMBUS4_TX,
+               [27] = DMACH_AC97_MICIN,
+               [28] = DMACH_AC97_PCMIN,
+               [29] = DMACH_AC97_PCMOUT,
+               [30] = DMACH_MAX,
+               [31] = DMACH_MAX,
+       },
+};
+
+static struct platform_device s5pv310_device_pdma0 = {
+       .name           = "s3c-pl330",
+       .id             = 0,
+       .num_resources  = ARRAY_SIZE(s5pv310_pdma0_resource),
+       .resource       = s5pv310_pdma0_resource,
+       .dev            = {
+               .dma_mask = &dma_dmamask,
+               .coherent_dma_mask = DMA_BIT_MASK(32),
+               .platform_data = &s5pv310_pdma0_pdata,
+       },
+};
+
+static struct resource s5pv310_pdma1_resource[] = {
+       [0] = {
+               .start  = S5PV310_PA_PDMA1,
+               .end    = S5PV310_PA_PDMA1 + SZ_4K,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = IRQ_PDMA1,
+               .end    = IRQ_PDMA1,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct s3c_pl330_platdata s5pv310_pdma1_pdata = {
+       .peri = {
+               [0] = DMACH_PCM0_RX,
+               [1] = DMACH_PCM0_TX,
+               [2] = DMACH_PCM1_RX,
+               [3] = DMACH_PCM1_TX,
+               [4] = DMACH_MSM_REQ1,
+               [5] = DMACH_MSM_REQ3,
+               [6] = DMACH_SPI1_RX,
+               [7] = DMACH_SPI1_TX,
+               [8] = DMACH_I2S0S_TX,
+               [9] = DMACH_I2S0_RX,
+               [10] = DMACH_I2S0_TX,
+               [11] = DMACH_I2S1_RX,
+               [12] = DMACH_I2S1_TX,
+               [13] = DMACH_UART0_RX,
+               [14] = DMACH_UART0_TX,
+               [15] = DMACH_UART1_RX,
+               [16] = DMACH_UART1_TX,
+               [17] = DMACH_UART3_RX,
+               [18] = DMACH_UART3_TX,
+               [19] = DMACH_SLIMBUS1_RX,
+               [20] = DMACH_SLIMBUS1_TX,
+               [21] = DMACH_SLIMBUS3_RX,
+               [22] = DMACH_SLIMBUS3_TX,
+               [23] = DMACH_SLIMBUS5_RX,
+               [24] = DMACH_SLIMBUS5_TX,
+               [25] = DMACH_SLIMBUS0AUX_RX,
+               [26] = DMACH_SLIMBUS0AUX_TX,
+               [27] = DMACH_SPDIF,
+               [28] = DMACH_MAX,
+               [29] = DMACH_MAX,
+               [30] = DMACH_MAX,
+               [31] = DMACH_MAX,
+       },
+};
+
+static struct platform_device s5pv310_device_pdma1 = {
+       .name           = "s3c-pl330",
+       .id             = 1,
+       .num_resources  = ARRAY_SIZE(s5pv310_pdma1_resource),
+       .resource       = s5pv310_pdma1_resource,
+       .dev            = {
+               .dma_mask = &dma_dmamask,
+               .coherent_dma_mask = DMA_BIT_MASK(32),
+               .platform_data = &s5pv310_pdma1_pdata,
+       },
+};
+
+static struct platform_device *s5pv310_dmacs[] __initdata = {
+       &s5pv310_device_pdma0,
+       &s5pv310_device_pdma1,
+};
+
+static int __init s5pv310_dma_init(void)
+{
+       platform_add_devices(s5pv310_dmacs, ARRAY_SIZE(s5pv310_dmacs));
+
+       return 0;
+}
+arch_initcall(s5pv310_dma_init);
diff --git a/arch/arm/mach-s5pv310/include/mach/dma.h b/arch/arm/mach-s5pv310/include/mach/dma.h
new file mode 100644 (file)
index 0000000..81209eb
--- /dev/null
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *     Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __MACH_DMA_H
+#define __MACH_DMA_H
+
+/* This platform uses the common S3C DMA API driver for PL330 */
+#include <plat/s3c-dma-pl330.h>
+
+#endif /* __MACH_DMA_H */
index f9a2830620d8990325335084a6e6ca2ce1a1ca9f..1dd130a3478277934c3a12742fe0400ee94cb18c 100644 (file)
@@ -55,6 +55,9 @@
 #define COMBINER_GROUP(x)      ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(64))
 #define COMBINER_IRQ(x, y)     (COMBINER_GROUP(x) + y)
 
+#define IRQ_PDMA0              COMBINER_IRQ(21, 0)
+#define IRQ_PDMA1              COMBINER_IRQ(21, 1)
+
 #define IRQ_TIMER0_VIC         COMBINER_IRQ(22, 0)
 #define IRQ_TIMER1_VIC         COMBINER_IRQ(22, 1)
 #define IRQ_TIMER2_VIC         COMBINER_IRQ(22, 2)
@@ -84,6 +87,9 @@
 #define IRQ_HSMMC2             COMBINER_IRQ(29, 2)
 #define IRQ_HSMMC3             COMBINER_IRQ(29, 3)
 
+#define IRQ_MIPI_CSIS0         COMBINER_IRQ(30, 0)
+#define IRQ_MIPI_CSIS1         COMBINER_IRQ(30, 1)
+
 #define IRQ_ONENAND_AUDI       COMBINER_IRQ(34, 0)
 
 #define IRQ_MCT_L1             COMBINER_IRQ(35, 3)
index 7be1a43a21968aa23921f1cbaf04b13dedb04ea0..33bcff2a9568b5cb30b43325189cae65963e6ba2 100644 (file)
 #define S5PV310_PA_GIC_DIST            (0x10501000)
 #define S5PV310_PA_L2CC                        (0x10502000)
 
+/* DMA */
+#define S5PV310_PA_MDMA                0x10810000
+#define S5PV310_PA_PDMA0       0x12680000
+#define S5PV310_PA_PDMA1       0x12690000
+
 #define S5PV310_PA_GPIO1               (0x11400000)
 #define S5PV310_PA_GPIO2               (0x11000000)
 #define S5PV310_PA_GPIO3               (0x03860000)
 
+#define S5PV310_PA_MIPI_CSIS0          0x11880000
+#define S5PV310_PA_MIPI_CSIS1          0x11890000
+
 #define S5PV310_PA_HSMMC(x)            (0x12510000 + ((x) * 0x10000))
 
 #define S5PV310_PA_SROMC               (0x12570000)
+#define S5P_PA_SROMC                   S5PV310_PA_SROMC
+
+/* S/PDIF */
+#define S5PV310_PA_SPDIF       0xE1100000
+
+/* I2S */
+#define S5PV310_PA_I2S0                0x03830000
+#define S5PV310_PA_I2S1                0xE3100000
+#define S5PV310_PA_I2S2                0xE2A00000
+
+/* PCM */
+#define S5PV310_PA_PCM0                0x03840000
+#define S5PV310_PA_PCM1                0x13980000
+#define S5PV310_PA_PCM2                0x13990000
+
+/* AC97 */
+#define S5PV310_PA_AC97                0x139A0000
 
 #define S5PV310_PA_UART                        (0x13800000)
 
 #define S3C_PA_IIC7                    S5PV310_PA_IIC(7)
 #define S3C_PA_RTC                     S5PV310_PA_RTC
 #define S3C_PA_WDT                     S5PV310_PA_WATCHDOG
+#define S5P_PA_MIPI_CSIS0              S5PV310_PA_MIPI_CSIS0
+#define S5P_PA_MIPI_CSIS1              S5PV310_PA_MIPI_CSIS1
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-srom.h b/arch/arm/mach-s5pv310/include/mach/regs-srom.h
deleted file mode 100644 (file)
index 1898b3e..0000000
+++ /dev/null
@@ -1,50 +0,0 @@
-/* linux/arch/arm/mach-s5pv310/include/mach/regs-srom.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * S5PV310 - SROMC register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_SROM_H
-#define __ASM_ARCH_REGS_SROM_H __FILE__
-
-#include <mach/map.h>
-
-#define S5PV310_SROMREG(x)     (S5P_VA_SROMC + (x))
-
-#define S5PV310_SROM_BW                S5PV310_SROMREG(0x0)
-#define S5PV310_SROM_BC0       S5PV310_SROMREG(0x4)
-#define S5PV310_SROM_BC1       S5PV310_SROMREG(0x8)
-#define S5PV310_SROM_BC2       S5PV310_SROMREG(0xc)
-#define S5PV310_SROM_BC3       S5PV310_SROMREG(0x10)
-
-/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
-
-#define S5PV310_SROM_BW__DATAWIDTH__SHIFT      0
-#define S5PV310_SROM_BW__ADDRMODE__SHIFT       1
-#define S5PV310_SROM_BW__WAITENABLE__SHIFT     2
-#define S5PV310_SROM_BW__BYTEENABLE__SHIFT     3
-
-#define S5PV310_SROM_BW__CS_MASK               0xf
-
-#define S5PV310_SROM_BW__NCS0__SHIFT           0
-#define S5PV310_SROM_BW__NCS1__SHIFT           4
-#define S5PV310_SROM_BW__NCS2__SHIFT           8
-#define S5PV310_SROM_BW__NCS3__SHIFT           12
-
-/* applies to same to BCS0 - BCS3 */
-
-#define S5PV310_SROM_BCX__PMC__SHIFT           0
-#define S5PV310_SROM_BCX__TACP__SHIFT          4
-#define S5PV310_SROM_BCX__TCAH__SHIFT          8
-#define S5PV310_SROM_BCX__TCOH__SHIFT          12
-#define S5PV310_SROM_BCX__TACC__SHIFT          16
-#define S5PV310_SROM_BCX__TCOS__SHIFT          24
-#define S5PV310_SROM_BCX__TACS__SHIFT          28
-
-#endif /* __ASM_ARCH_REGS_SROM_H */
index 5877503e92c3a75a6015a874eaadcf1f0c8d62c8..f5a415edc0b6839291680ac3d68c3b2991237d96 100644 (file)
@@ -152,7 +152,7 @@ static struct irq_chip s5pv310_irq_eint = {
        .ack            = s5pv310_irq_eint_ack,
        .set_type       = s5pv310_irq_eint_set_type,
 #ifdef CONFIG_PM
-       .set_wake       = s3c_irqext_wake,
+       .irq_set_wake   = s3c_irqext_wake,
 #endif
 };
 
index f65e668ceae9e0b6ed7b5b48f8a9bedfb2ccd5f7..9262966cd2690c56daab5b5672f7060f9efa9528 100644 (file)
 #include <linux/platform_device.h>
 #include <linux/smsc911x.h>
 #include <linux/io.h>
+#include <linux/i2c.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
 #include <plat/regs-serial.h>
+#include <plat/regs-srom.h>
 #include <plat/s5pv310.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/sdhci.h>
+#include <plat/iic.h>
 #include <plat/pd.h>
 
 #include <mach/map.h>
-#include <mach/regs-srom.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define SMDKC210_UCON_DEFAULT  (S3C2410_UCON_TXILEVEL |        \
@@ -140,14 +142,20 @@ static struct platform_device smdkc210_smsc911x = {
        },
 };
 
+static struct i2c_board_info i2c_devs1[] __initdata = {
+       {I2C_BOARD_INFO("wm8994", 0x1a),},
+};
+
 static struct platform_device *smdkc210_devices[] __initdata = {
        &s3c_device_hsmmc0,
        &s3c_device_hsmmc1,
        &s3c_device_hsmmc2,
        &s3c_device_hsmmc3,
+       &s3c_device_i2c1,
        &s3c_device_rtc,
        &s3c_device_wdt,
-       &smdkc210_smsc911x,
+       &s5pv310_device_ac97,
+       &s5pv310_device_i2s0,
        &s5pv310_device_pd[PD_MFC],
        &s5pv310_device_pd[PD_G3D],
        &s5pv310_device_pd[PD_LCD0],
@@ -155,6 +163,7 @@ static struct platform_device *smdkc210_devices[] __initdata = {
        &s5pv310_device_pd[PD_CAM],
        &s5pv310_device_pd[PD_TV],
        &s5pv310_device_pd[PD_GPS],
+       &smdkc210_smsc911x,
 };
 
 static void __init smdkc210_smsc911x_init(void)
@@ -162,23 +171,22 @@ static void __init smdkc210_smsc911x_init(void)
        u32 cs1;
 
        /* configure nCS1 width to 16 bits */
-       cs1 = __raw_readl(S5PV310_SROM_BW) &
-                   ~(S5PV310_SROM_BW__CS_MASK <<
-                                   S5PV310_SROM_BW__NCS1__SHIFT);
-       cs1 |= ((1 << S5PV310_SROM_BW__DATAWIDTH__SHIFT) |
-               (1 << S5PV310_SROM_BW__WAITENABLE__SHIFT) |
-               (1 << S5PV310_SROM_BW__BYTEENABLE__SHIFT)) <<
-               S5PV310_SROM_BW__NCS1__SHIFT;
-       __raw_writel(cs1, S5PV310_SROM_BW);
+       cs1 = __raw_readl(S5P_SROM_BW) &
+               ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
+       cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
+               (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
+               (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
+               S5P_SROM_BW__NCS1__SHIFT;
+       __raw_writel(cs1, S5P_SROM_BW);
 
        /* set timing for nCS1 suitable for ethernet chip */
-       __raw_writel((0x1 << S5PV310_SROM_BCX__PMC__SHIFT) |
-                    (0x9 << S5PV310_SROM_BCX__TACP__SHIFT) |
-                    (0xc << S5PV310_SROM_BCX__TCAH__SHIFT) |
-                    (0x1 << S5PV310_SROM_BCX__TCOH__SHIFT) |
-                    (0x6 << S5PV310_SROM_BCX__TACC__SHIFT) |
-                    (0x1 << S5PV310_SROM_BCX__TCOS__SHIFT) |
-                    (0x1 << S5PV310_SROM_BCX__TACS__SHIFT), S5PV310_SROM_BC1);
+       __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
+                    (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
+                    (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
+                    (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
+                    (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
+                    (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
+                    (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
 }
 
 static void __init smdkc210_map_io(void)
@@ -190,6 +198,9 @@ static void __init smdkc210_map_io(void)
 
 static void __init smdkc210_machine_init(void)
 {
+       s3c_i2c1_set_platdata(NULL);
+       i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
+
        smdkc210_smsc911x_init();
 
        s3c_sdhci0_set_platdata(&smdkc210_hsmmc0_pdata);
index 19aa3e3c011d103c639c9159bb348a5c8b78b904..3eb029ca2073a60a903191a9e9186909e0cc2ba7 100644 (file)
 #include <linux/platform_device.h>
 #include <linux/smsc911x.h>
 #include <linux/io.h>
+#include <linux/i2c.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
 #include <plat/regs-serial.h>
+#include <plat/regs-srom.h>
 #include <plat/s5pv310.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/sdhci.h>
+#include <plat/iic.h>
 #include <plat/pd.h>
 
 #include <mach/map.h>
-#include <mach/regs-srom.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define SMDKV310_UCON_DEFAULT  (S3C2410_UCON_TXILEVEL |        \
@@ -140,14 +142,20 @@ static struct platform_device smdkv310_smsc911x = {
        },
 };
 
+static struct i2c_board_info i2c_devs1[] __initdata = {
+       {I2C_BOARD_INFO("wm8994", 0x1a),},
+};
+
 static struct platform_device *smdkv310_devices[] __initdata = {
        &s3c_device_hsmmc0,
        &s3c_device_hsmmc1,
        &s3c_device_hsmmc2,
        &s3c_device_hsmmc3,
+       &s3c_device_i2c1,
        &s3c_device_rtc,
        &s3c_device_wdt,
-       &smdkv310_smsc911x,
+       &s5pv310_device_ac97,
+       &s5pv310_device_i2s0,
        &s5pv310_device_pd[PD_MFC],
        &s5pv310_device_pd[PD_G3D],
        &s5pv310_device_pd[PD_LCD0],
@@ -155,6 +163,7 @@ static struct platform_device *smdkv310_devices[] __initdata = {
        &s5pv310_device_pd[PD_CAM],
        &s5pv310_device_pd[PD_TV],
        &s5pv310_device_pd[PD_GPS],
+       &smdkv310_smsc911x,
 };
 
 static void __init smdkv310_smsc911x_init(void)
@@ -162,23 +171,22 @@ static void __init smdkv310_smsc911x_init(void)
        u32 cs1;
 
        /* configure nCS1 width to 16 bits */
-       cs1 = __raw_readl(S5PV310_SROM_BW) &
-                   ~(S5PV310_SROM_BW__CS_MASK <<
-                                   S5PV310_SROM_BW__NCS1__SHIFT);
-       cs1 |= ((1 << S5PV310_SROM_BW__DATAWIDTH__SHIFT) |
-               (1 << S5PV310_SROM_BW__WAITENABLE__SHIFT) |
-               (1 << S5PV310_SROM_BW__BYTEENABLE__SHIFT)) <<
-               S5PV310_SROM_BW__NCS1__SHIFT;
-       __raw_writel(cs1, S5PV310_SROM_BW);
+       cs1 = __raw_readl(S5P_SROM_BW) &
+               ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
+       cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
+               (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
+               (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
+               S5P_SROM_BW__NCS1__SHIFT;
+       __raw_writel(cs1, S5P_SROM_BW);
 
        /* set timing for nCS1 suitable for ethernet chip */
-       __raw_writel((0x1 << S5PV310_SROM_BCX__PMC__SHIFT) |
-                    (0x9 << S5PV310_SROM_BCX__TACP__SHIFT) |
-                    (0xc << S5PV310_SROM_BCX__TCAH__SHIFT) |
-                    (0x1 << S5PV310_SROM_BCX__TCOH__SHIFT) |
-                    (0x6 << S5PV310_SROM_BCX__TACC__SHIFT) |
-                    (0x1 << S5PV310_SROM_BCX__TCOS__SHIFT) |
-                    (0x1 << S5PV310_SROM_BCX__TACS__SHIFT), S5PV310_SROM_BC1);
+       __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
+                    (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
+                    (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
+                    (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
+                    (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
+                    (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
+                    (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
 }
 
 static void __init smdkv310_map_io(void)
@@ -190,6 +198,9 @@ static void __init smdkv310_map_io(void)
 
 static void __init smdkv310_machine_init(void)
 {
+       s3c_i2c1_set_platdata(NULL);
+       i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
+
        smdkv310_smsc911x_init();
 
        s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata);
index ad0d44ef1f9393623a7516d33428dc04cf2912ef..91ce38393ba69dea399b5c7cd3d58f652518a432 100644 (file)
@@ -238,7 +238,7 @@ static struct irq_chip s3c_irqext_chip = {
        .unmask         = s3c_irqext_unmask,
        .ack            = s3c_irqext_ack,
        .set_type       = s3c_irqext_type,
-       .set_wake       = s3c_irqext_wake
+       .irq_set_wake   = s3c_irqext_wake
 };
 
 static struct irq_chip s3c_irq_eint0t4 = {
index 65dbfa8e0a860ecb27e9a804c391a23af23f0e2e..6a161f317a7935613209f04493ee08df4e30fc9f 100644 (file)
@@ -56,3 +56,13 @@ config S5P_DEV_ONENAND
        bool
        help
          Compile in platform device definition for OneNAND controller
+
+config S5P_DEV_CSIS0
+       bool
+       help
+         Compile in platform device definitions for MIPI-CSIS channel 0
+
+config S5P_DEV_CSIS1
+       bool
+       help
+         Compile in platform device definitions for MIPI-CSIS channel 1
index de65238a7aefc3ec423bde8ee00d65e391208543..2b73173781039dd1e1e5d6871364b2724accd855 100644 (file)
@@ -28,3 +28,5 @@ obj-$(CONFIG_S5P_DEV_FIMC0)   += dev-fimc0.o
 obj-$(CONFIG_S5P_DEV_FIMC1)    += dev-fimc1.o
 obj-$(CONFIG_S5P_DEV_FIMC2)    += dev-fimc2.o
 obj-$(CONFIG_S5P_DEV_ONENAND)  += dev-onenand.o
+obj-$(CONFIG_S5P_DEV_CSIS0)    += dev-csis0.o
+obj-$(CONFIG_S5P_DEV_CSIS1)    += dev-csis1.o
index 74f7f5a5446cdaf4bdc9a3212f1dc9679611abfb..047d31c1bbd88efe2b3c31dbc35dc8e034d1f794 100644 (file)
@@ -108,6 +108,11 @@ static struct map_desc s5p_iodesc[] __initdata = {
                .pfn            = __phys_to_pfn(S3C_PA_WDT),
                .length         = SZ_4K,
                .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_SROMC,
+               .pfn            = __phys_to_pfn(S5P_PA_SROMC),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
        },
 };
 
diff --git a/arch/arm/plat-s5p/dev-csis0.c b/arch/arm/plat-s5p/dev-csis0.c
new file mode 100644 (file)
index 0000000..dfab1c8
--- /dev/null
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ *
+ * S5P series device definition for MIPI-CSIS channel 0
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <mach/map.h>
+
+static struct resource s5p_mipi_csis0_resource[] = {
+       [0] = {
+               .start = S5P_PA_MIPI_CSIS0,
+               .end   = S5P_PA_MIPI_CSIS0 + SZ_4K - 1,
+               .flags = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start = IRQ_MIPI_CSIS0,
+               .end   = IRQ_MIPI_CSIS0,
+               .flags = IORESOURCE_IRQ,
+       }
+};
+
+struct platform_device s5p_device_mipi_csis0 = {
+       .name             = "s5p-mipi-csis",
+       .id               = 0,
+       .num_resources    = ARRAY_SIZE(s5p_mipi_csis0_resource),
+       .resource         = s5p_mipi_csis0_resource,
+};
diff --git a/arch/arm/plat-s5p/dev-csis1.c b/arch/arm/plat-s5p/dev-csis1.c
new file mode 100644 (file)
index 0000000..e3053f2
--- /dev/null
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ *
+ * S5P series device definition for MIPI-CSIS channel 1
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <mach/map.h>
+
+static struct resource s5p_mipi_csis1_resource[] = {
+       [0] = {
+               .start = S5P_PA_MIPI_CSIS1,
+               .end   = S5P_PA_MIPI_CSIS1 + SZ_4K - 1,
+               .flags = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start = IRQ_MIPI_CSIS1,
+               .end   = IRQ_MIPI_CSIS1,
+               .flags = IORESOURCE_IRQ,
+       },
+};
+
+struct platform_device s5p_device_mipi_csis1 = {
+       .name             = "s5p-mipi-csis",
+       .id               = 1,
+       .num_resources    = ARRAY_SIZE(s5p_mipi_csis1_resource),
+       .resource         = s5p_mipi_csis1_resource,
+};
diff --git a/arch/arm/plat-s5p/include/plat/csis.h b/arch/arm/plat-s5p/include/plat/csis.h
new file mode 100644 (file)
index 0000000..51e308c
--- /dev/null
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ *
+ * S5P series MIPI CSI slave device support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef PLAT_S5P_CSIS_H_
+#define PLAT_S5P_CSIS_H_ __FILE__
+
+/**
+ * struct s5p_platform_mipi_csis - platform data for MIPI-CSIS
+ * @clk_rate: bus clock frequency
+ * @lanes: number of data lanes used
+ * @alignment: data alignment in bits
+ * @hs_settle: HS-RX settle time
+ */
+struct s5p_platform_mipi_csis {
+       unsigned long clk_rate;
+       u8 lanes;
+       u8 alignment;
+       u8 hs_settle;
+};
+
+#endif /* PLAT_S5P_CSIS_H_ */
diff --git a/arch/arm/plat-s5p/include/plat/regs-srom.h b/arch/arm/plat-s5p/include/plat/regs-srom.h
new file mode 100644 (file)
index 0000000..f121ab5
--- /dev/null
@@ -0,0 +1,54 @@
+/* linux/arch/arm/plat-s5p/include/plat/regs-srom.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * S5P SROMC register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_S5P_REGS_SROM_H
+#define __ASM_PLAT_S5P_REGS_SROM_H __FILE__
+
+#include <mach/map.h>
+
+#define S5P_SROMREG(x)         (S5P_VA_SROMC + (x))
+
+#define S5P_SROM_BW            S5P_SROMREG(0x0)
+#define S5P_SROM_BC0           S5P_SROMREG(0x4)
+#define S5P_SROM_BC1           S5P_SROMREG(0x8)
+#define S5P_SROM_BC2           S5P_SROMREG(0xc)
+#define S5P_SROM_BC3           S5P_SROMREG(0x10)
+#define S5P_SROM_BC4           S5P_SROMREG(0x14)
+#define S5P_SROM_BC5           S5P_SROMREG(0x18)
+
+/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
+
+#define S5P_SROM_BW__DATAWIDTH__SHIFT          0
+#define S5P_SROM_BW__ADDRMODE__SHIFT           1
+#define S5P_SROM_BW__WAITENABLE__SHIFT         2
+#define S5P_SROM_BW__BYTEENABLE__SHIFT         3
+
+#define S5P_SROM_BW__CS_MASK                   0xf
+
+#define S5P_SROM_BW__NCS0__SHIFT               0
+#define S5P_SROM_BW__NCS1__SHIFT               4
+#define S5P_SROM_BW__NCS2__SHIFT               8
+#define S5P_SROM_BW__NCS3__SHIFT               12
+#define S5P_SROM_BW__NCS4__SHIFT               16
+#define S5P_SROM_BW__NCS5__SHIFT               20
+
+/* applies to same to BCS0 - BCS3 */
+
+#define S5P_SROM_BCX__PMC__SHIFT               0
+#define S5P_SROM_BCX__TACP__SHIFT              4
+#define S5P_SROM_BCX__TCAH__SHIFT              8
+#define S5P_SROM_BCX__TCOH__SHIFT              12
+#define S5P_SROM_BCX__TACC__SHIFT              16
+#define S5P_SROM_BCX__TCOS__SHIFT              24
+#define S5P_SROM_BCX__TACS__SHIFT              28
+
+#endif /* __ASM_PLAT_S5P_REGS_SROM_H */
index 752f1a645f9dcfad3c69e7d0c5ca8ddf71dc5d45..f2f2e1ccd0e6269171678f6194d3aedcf94cf961 100644 (file)
@@ -125,7 +125,7 @@ static struct irq_chip s5p_irq_eint = {
        .ack            = s5p_irq_eint_ack,
        .set_type       = s5p_irq_eint_set_type,
 #ifdef CONFIG_PM
-       .set_wake       = s3c_irqext_wake,
+       .irq_set_wake   = s3c_irqext_wake,
 #endif
 };
 
@@ -194,7 +194,7 @@ static struct irq_chip s5p_irq_vic_eint = {
        .ack            = s5p_irq_vic_eint_ack,
        .set_type       = s5p_irq_eint_set_type,
 #ifdef CONFIG_PM
-       .set_wake       = s3c_irqext_wake,
+       .irq_set_wake   = s3c_irqext_wake,
 #endif
 };
 
index dcd6eff4ee53840e8082ce4ae84b08a7e3cef4e8..2ebf4157d93ada4712650dbd4fe770b5a0e78713 100644 (file)
@@ -333,4 +333,12 @@ config SAMSUNG_WAKEMASK
          and above. This code allows a set of interrupt to wakeup-mask
          mappings. See <plat/wakeup-mask.h>
 
+comment "Power Domain"
+
+config SAMSUNG_PD
+       bool "Samsung Power Domain"
+       depends on PM_RUNTIME
+       help
+         Say Y here if you want to control Power Domain by Runtime PM.
+
 endif
index afcce474af8e86d692a5a579387055bcf808cc3c..09dbd78b56f5e998b3c98f30c21235a8421c8ffe 100644 (file)
@@ -73,6 +73,10 @@ obj-$(CONFIG_SAMSUNG_PM_CHECK)       += pm-check.o
 
 obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o
 
+# PD support
+
+obj-$(CONFIG_SAMSUNG_PD)       += pd.o
+
 # PWM support
 
 obj-$(CONFIG_HAVE_PWM)         += pwm.o
index c354089254fc3defb523ff5e1ee6ed17dce3b3ed..ea37c04617884b467f2b009a839276a5a0aa1697 100644 (file)
@@ -197,3 +197,10 @@ void __init samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
                s3c_gpiolib_add(chip);
        }
 }
+
+void __init samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip,
+                                          int nr_chips)
+{
+       for (; nr_chips > 0; nr_chips--, chip++)
+               s3c_gpiolib_add(chip);
+}
index 7712ff6336f4f9721ff67a5b2da03c885ebc8ca1..a0826ed2f9febc680611c52c2d08b20844441d35 100644 (file)
@@ -25,10 +25,34 @@ extern void s3c64xx_ac97_setup_gpio(int);
 #define S5PC100_SPDIF_GPG3 1
 extern void s5pc100_spdif_setup_gpio(int);
 
+struct samsung_i2s {
+/* If the Primary DAI has 5.1 Channels */
+#define QUIRK_PRI_6CHAN                (1 << 0)
+/* If the I2S block has a Stereo Overlay Channel */
+#define QUIRK_SEC_DAI          (1 << 1)
+/*
+ * If the I2S block has no internal prescalar or MUX (I2SMOD[10] bit)
+ * The Machine driver must provide suitably set clock to the I2S block.
+ */
+#define QUIRK_NO_MUXPSR                (1 << 2)
+#define QUIRK_NEED_RSTCLR      (1 << 3)
+       /* Quirks of the I2S controller */
+       u32 quirks;
+
+       /*
+        * Array of clock names that can be used to generate I2S signals.
+        * Also corresponds to clocks of I2SMOD[10]
+        */
+       const char **src_clk;
+};
+
 /**
  * struct s3c_audio_pdata - common platform data for audio device drivers
  * @cfg_gpio: Callback function to setup mux'ed pins in I2S/PCM/AC97 mode
  */
 struct s3c_audio_pdata {
        int (*cfg_gpio)(struct platform_device *);
+       union {
+               struct samsung_i2s i2s;
+       } type;
 };
index 4dad6e24e970b1de5b4a8e899f371b8bebecc3a0..165fa8496c9ea68c4711b09ba798d9e6fb7d75d1 100644 (file)
@@ -96,6 +96,16 @@ extern struct platform_device s5pv210_device_iis1;
 extern struct platform_device s5pv210_device_iis2;
 extern struct platform_device s5pv210_device_spdif;
 
+extern struct platform_device s5pv310_device_ac97;
+extern struct platform_device s5pv310_device_pcm0;
+extern struct platform_device s5pv310_device_pcm1;
+extern struct platform_device s5pv310_device_pcm2;
+extern struct platform_device s5pv310_device_i2s0;
+extern struct platform_device s5pv310_device_i2s1;
+extern struct platform_device s5pv310_device_i2s2;
+extern struct platform_device s5pv310_device_spdif;
+extern struct platform_device s5pv310_device_pd[];
+
 extern struct platform_device s5p6442_device_pcm0;
 extern struct platform_device s5p6442_device_pcm1;
 extern struct platform_device s5p6442_device_iis0;
@@ -106,6 +116,8 @@ extern struct platform_device s5p6440_device_pcm;
 extern struct platform_device s5p6440_device_iis;
 
 extern struct platform_device s5p6450_device_iis0;
+extern struct platform_device s5p6450_device_iis1;
+extern struct platform_device s5p6450_device_iis2;
 extern struct platform_device s5p6450_device_pcm0;
 
 extern struct platform_device s5pc100_device_ac97;
@@ -122,7 +134,8 @@ extern struct platform_device s5p_device_fimc0;
 extern struct platform_device s5p_device_fimc1;
 extern struct platform_device s5p_device_fimc2;
 
-extern struct platform_device s5pv310_device_pd[];
+extern struct platform_device s5p_device_mipi_csis0;
+extern struct platform_device s5p_device_mipi_csis1;
 
 /* s3c2440 specific devices */
 
index 13a22b8861efd58bf45f3ca4155d57aa647f320e..dac35d0a711dd41f97bf21356e61c47149463455 100644 (file)
@@ -118,6 +118,8 @@ extern void samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip,
                                           int nr_chips);
 extern void samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
                                            int nr_chips);
+extern void samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip,
+                                          int nr_chips);
 
 extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip);
 extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip);
diff --git a/arch/arm/plat-samsung/include/plat/pd.h b/arch/arm/plat-samsung/include/plat/pd.h
new file mode 100644 (file)
index 0000000..5f0ad85
--- /dev/null
@@ -0,0 +1,30 @@
+/* linux/arch/arm/plat-samsung/include/plat/pd.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_SAMSUNG_PD_H
+#define __ASM_PLAT_SAMSUNG_PD_H __FILE__
+
+struct samsung_pd_info {
+       int (*enable)(struct device *dev);
+       int (*disable)(struct device *dev);
+       void __iomem *base;
+};
+
+enum s5pv310_pd_block {
+       PD_MFC,
+       PD_G3D,
+       PD_LCD0,
+       PD_LCD1,
+       PD_TV,
+       PD_CAM,
+       PD_GPS
+};
+
+#endif /* __ASM_PLAT_SAMSUNG_PD_H */
index 245836d919312b0fd050aff3ba8a59ca64739040..d9025e377675b6c323d28355b616d0c718cd1c9d 100644 (file)
@@ -15,6 +15,8 @@
  * management
 */
 
+#include <linux/irq.h>
+
 #ifdef CONFIG_PM
 
 extern __init int s3c_pm_init(void);
@@ -100,7 +102,7 @@ extern void s3c_pm_do_restore(struct sleep_save *ptr, int count);
 extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count);
 
 #ifdef CONFIG_PM
-extern int s3c_irqext_wake(unsigned int irqno, unsigned int state);
+extern int s3c_irqext_wake(struct irq_data *data, unsigned int state);
 extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state);
 extern int s3c24xx_irq_resume(struct sys_device *dev);
 #else
index 4f8c102674ae25e342abffd0ca78952961e9eaed..da31d785cbd1649220f557e03c62ebf4dbf26340 100644 (file)
@@ -28,9 +28,9 @@
  * are consecutive when looking up the interrupt in the demux routines.
  */
 
-static inline void __iomem *s3c_irq_uart_base(unsigned int irq)
+static inline void __iomem *s3c_irq_uart_base(struct irq_data *data)
 {
-       struct s3c_uart_irq *uirq = get_irq_chip_data(irq);
+       struct s3c_uart_irq *uirq = data->chip_data;
        return uirq->regs;
 }
 
@@ -39,10 +39,10 @@ static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
        return irq & 3;
 }
 
-static void s3c_irq_uart_mask(unsigned int irq)
+static void s3c_irq_uart_mask(struct irq_data *data)
 {
-       void __iomem *regs = s3c_irq_uart_base(irq);
-       unsigned int bit = s3c_irq_uart_bit(irq);
+       void __iomem *regs = s3c_irq_uart_base(data);
+       unsigned int bit = s3c_irq_uart_bit(data->irq);
        u32 reg;
 
        reg = __raw_readl(regs + S3C64XX_UINTM);
@@ -50,10 +50,10 @@ static void s3c_irq_uart_mask(unsigned int irq)
        __raw_writel(reg, regs + S3C64XX_UINTM);
 }
 
-static void s3c_irq_uart_maskack(unsigned int irq)
+static void s3c_irq_uart_maskack(struct irq_data *data)
 {
-       void __iomem *regs = s3c_irq_uart_base(irq);
-       unsigned int bit = s3c_irq_uart_bit(irq);
+       void __iomem *regs = s3c_irq_uart_base(data);
+       unsigned int bit = s3c_irq_uart_bit(data->irq);
        u32 reg;
 
        reg = __raw_readl(regs + S3C64XX_UINTM);
@@ -62,10 +62,10 @@ static void s3c_irq_uart_maskack(unsigned int irq)
        __raw_writel(1 << bit, regs + S3C64XX_UINTP);
 }
 
-static void s3c_irq_uart_unmask(unsigned int irq)
+static void s3c_irq_uart_unmask(struct irq_data *data)
 {
-       void __iomem *regs = s3c_irq_uart_base(irq);
-       unsigned int bit = s3c_irq_uart_bit(irq);
+       void __iomem *regs = s3c_irq_uart_base(data);
+       unsigned int bit = s3c_irq_uart_bit(data->irq);
        u32 reg;
 
        reg = __raw_readl(regs + S3C64XX_UINTM);
@@ -73,10 +73,10 @@ static void s3c_irq_uart_unmask(unsigned int irq)
        __raw_writel(reg, regs + S3C64XX_UINTM);
 }
 
-static void s3c_irq_uart_ack(unsigned int irq)
+static void s3c_irq_uart_ack(struct irq_data *data)
 {
-       void __iomem *regs = s3c_irq_uart_base(irq);
-       unsigned int bit = s3c_irq_uart_bit(irq);
+       void __iomem *regs = s3c_irq_uart_base(data);
+       unsigned int bit = s3c_irq_uart_bit(data->irq);
 
        __raw_writel(1 << bit, regs + S3C64XX_UINTP);
 }
@@ -99,10 +99,10 @@ static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
 
 static struct irq_chip s3c_irq_uart = {
        .name           = "s3c-uart",
-       .mask           = s3c_irq_uart_mask,
-       .unmask         = s3c_irq_uart_unmask,
-       .mask_ack       = s3c_irq_uart_maskack,
-       .ack            = s3c_irq_uart_ack,
+       .irq_mask       = s3c_irq_uart_mask,
+       .irq_unmask     = s3c_irq_uart_unmask,
+       .irq_mask_ack   = s3c_irq_uart_maskack,
+       .irq_ack        = s3c_irq_uart_ack,
 };
 
 static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
index 0270519fcabca2b0e89be165858bd8b3c304fd2b..7ce77ddb729d6282d0309881e480c317668f62ec 100644 (file)
@@ -29,38 +29,41 @@ static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc)
 
 /* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
 
-static void s3c_irq_timer_mask(unsigned int irq)
+static void s3c_irq_timer_mask(struct irq_data *data)
 {
        u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
+       u32 mask = (u32)data->chip_data;
 
        reg &= 0x1f;  /* mask out pending interrupts */
-       reg &= ~(1 << (irq - IRQ_TIMER0));
+       reg &= ~mask;
        __raw_writel(reg, S3C64XX_TINT_CSTAT);
 }
 
-static void s3c_irq_timer_unmask(unsigned int irq)
+static void s3c_irq_timer_unmask(struct irq_data *data)
 {
        u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
+       u32 mask = (u32)data->chip_data;
 
        reg &= 0x1f;  /* mask out pending interrupts */
-       reg |= 1 << (irq - IRQ_TIMER0);
+       reg |= mask;
        __raw_writel(reg, S3C64XX_TINT_CSTAT);
 }
 
-static void s3c_irq_timer_ack(unsigned int irq)
+static void s3c_irq_timer_ack(struct irq_data *data)
 {
        u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
+       u32 mask = (u32)data->chip_data;
 
        reg &= 0x1f;
-       reg |= (1 << 5) << (irq - IRQ_TIMER0);
+       reg |= mask << 5;
        __raw_writel(reg, S3C64XX_TINT_CSTAT);
 }
 
 static struct irq_chip s3c_irq_timer = {
        .name           = "s3c-timer",
-       .mask           = s3c_irq_timer_mask,
-       .unmask         = s3c_irq_timer_unmask,
-       .ack            = s3c_irq_timer_ack,
+       .irq_mask       = s3c_irq_timer_mask,
+       .irq_unmask     = s3c_irq_timer_unmask,
+       .irq_ack        = s3c_irq_timer_ack,
 };
 
 /**
@@ -79,6 +82,7 @@ void __init s3c_init_vic_timer_irq(unsigned int parent_irq,
        set_irq_chained_handler(parent_irq, s3c_irq_demux_vic_timer);
 
        set_irq_chip(timer_irq, &s3c_irq_timer);
+       set_irq_chip_data(timer_irq, (void *)(1 << (timer_irq - IRQ_TIMER0)));
        set_irq_handler(timer_irq, handle_level_irq);
        set_irq_flags(timer_irq, IRQF_VALID);
 
diff --git a/arch/arm/plat-samsung/pd.c b/arch/arm/plat-samsung/pd.c
new file mode 100644 (file)
index 0000000..efe1d56
--- /dev/null
@@ -0,0 +1,95 @@
+/* linux/arch/arm/plat-samsung/pd.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Samsung Power domain support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/pm_runtime.h>
+
+#include <plat/pd.h>
+
+static int samsung_pd_probe(struct platform_device *pdev)
+{
+       struct samsung_pd_info *pdata = pdev->dev.platform_data;
+       struct device *dev = &pdev->dev;
+
+       if (!pdata) {
+               dev_err(dev, "no device data specified\n");
+               return -ENOENT;
+       }
+
+       pm_runtime_set_active(dev);
+       pm_runtime_enable(dev);
+
+       dev_info(dev, "power domain registered\n");
+       return 0;
+}
+
+static int __devexit samsung_pd_remove(struct platform_device *pdev)
+{
+       struct device *dev = &pdev->dev;
+
+       pm_runtime_disable(dev);
+       return 0;
+}
+
+static int samsung_pd_runtime_suspend(struct device *dev)
+{
+       struct samsung_pd_info *pdata = dev->platform_data;
+       int ret = 0;
+
+       if (pdata->disable)
+               ret = pdata->disable(dev);
+
+       dev_dbg(dev, "suspended\n");
+       return ret;
+}
+
+static int samsung_pd_runtime_resume(struct device *dev)
+{
+       struct samsung_pd_info *pdata = dev->platform_data;
+       int ret = 0;
+
+       if (pdata->enable)
+               ret = pdata->enable(dev);
+
+       dev_dbg(dev, "resumed\n");
+       return ret;
+}
+
+static const struct dev_pm_ops samsung_pd_pm_ops = {
+       .runtime_suspend        = samsung_pd_runtime_suspend,
+       .runtime_resume         = samsung_pd_runtime_resume,
+};
+
+static struct platform_driver samsung_pd_driver = {
+       .driver         = {
+               .name           = "samsung-pd",
+               .owner          = THIS_MODULE,
+               .pm             = &samsung_pd_pm_ops,
+       },
+       .probe          = samsung_pd_probe,
+       .remove         = __devexit_p(samsung_pd_remove),
+};
+
+static int __init samsung_pd_init(void)
+{
+       int ret;
+
+       ret = platform_driver_register(&samsung_pd_driver);
+       if (ret)
+               printk(KERN_ERR "%s: failed to add PD driver\n", __func__);
+
+       return ret;
+}
+arch_initcall(samsung_pd_init);
index 27cfca5976993c0aa8f04f999885f109c897e4ac..eaa57dc969ae2da9e0525794b1713dba00d662c0 100644 (file)
@@ -136,15 +136,15 @@ static void s3c_pm_restore_uarts(void) { }
 unsigned long s3c_irqwake_intmask      = 0xffffffffL;
 unsigned long s3c_irqwake_eintmask     = 0xffffffffL;
 
-int s3c_irqext_wake(unsigned int irqno, unsigned int state)
+int s3c_irqext_wake(struct irq_data *data, unsigned int state)
 {
-       unsigned long bit = 1L << IRQ_EINT_BIT(irqno);
+       unsigned long bit = 1L << IRQ_EINT_BIT(data->irq);
 
        if (!(s3c_irqwake_eintallow & bit))
                return -ENOENT;
 
        printk(KERN_INFO "wake %s for irq %d\n",
-              state ? "enabled" : "disabled", irqno);
+              state ? "enabled" : "disabled", data->irq);
 
        if (!state)
                s3c_irqwake_eintmask |= bit;