static struct clk *pll1_sw_clk;
static struct clk *pll3_sw_clk;
static struct clk *pll2_200;
-static struct clk *mmdc_ch0_axi;
+struct clk *mmdc_ch0_axi;
static struct clk *pll3_540;
static struct delayed_work low_bus_freq_handler;
u32 div;
unsigned long flags;
- spin_lock_irqsave(&freq_lock, flags);
-
if (high_bus_freq_mode) {
/* Set periph_clk to be sourced from OSC_CLK */
/* Set AXI to 24MHz. */
low_bus_freq_mode = 1;
audio_bus_freq_mode = 0;
}
- spin_unlock_irqrestore(&freq_lock, flags);
}
high_bus_freq_mode = 0;
u32 reg;
unsigned long flags;
- spin_lock_irqsave(&freq_lock, flags);
/* Change DDR freq in IRAM. */
mx6sl_ddr_freq_change_iram(ddr_normal_rate, low_bus_freq_mode);
high_bus_freq_mode = 1;
low_bus_freq_mode = 0;
audio_bus_freq_mode = 0;
- spin_unlock_irqrestore(&freq_lock, flags);
} else {
clk_enable(pll3);
if (high_bus_freq) {
u32 reg; \
unsigned long flags; \
int result = 1; \
- spin_lock_irqsave(&mx6sl_clk_lock, flags); \
gpt_rate = clk_get_rate(&gpt_clk[0]); \
gpt_ticks = timeout / (1000000000 / gpt_rate); \
reg = __raw_readl(timer_base + V2_TSTAT);\
} \
} \
} \
- spin_unlock_irqrestore(&mx6sl_clk_lock, flags); \
result; \
})
return -EINVAL;
}
- axi_org_parent = clk_get_parent(axi_clk);
- clk_set_parent(axi_clk, periph_clk);
-
if (state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY) {
if (pm_data && pm_data->suspend_enter)
pm_data->suspend_enter();
extern unsigned int gpc_wake_irq[4];
static void __iomem *gpc_base = IO_ADDRESS(GPC_BASE_ADDR);
-static struct clk *ddr_clk;
+extern struct clk *mmdc_ch0_axi;
volatile unsigned int num_cpu_idle;
volatile unsigned int num_cpu_idle_lock = 0x0;
ca9_do_idle();
} else {
if (low_bus_freq_mode || audio_bus_freq_mode) {
- u32 ddr_usecount;
- if (ddr_clk == NULL)
- ddr_clk = clk_get(NULL ,
- "mmdc_ch0_axi");
- ddr_usecount = clk_get_usecount(ddr_clk);
+ u32 ddr_usecount;
+ if ((mmdc_ch0_axi != NULL) && ddr_usecount)
+ ddr_usecount = clk_get_usecount(mmdc_ch0_axi);
if (cpu_is_mx6sl() && low_bus_freq_mode
&& ddr_usecount == 1) {