ARM: LPAE: Add context switching support

With LPAE, TTBRx registers are 64-bit. The ASID is stored in TTBR0
rather than a separate Context ID register. This patch makes the
necessary changes to handle context switching on LPAE.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index b0ee9ba3cfab41a52853eca727466abff88ddf27..fcdb1017cdc6c9775b80083afe71479d922ff092 100644 (file)
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -22,6 +22,21 @@ unsigned int cpu_last_asid = ASID_FIRST_VERSION;
 DEFINE_PER_CPU(struct mm_struct *, current_mm);
 #endif
 
+#ifdef CONFIG_ARM_LPAE
+#define cpu_set_asid(asid) {                                           \
+       unsigned long ttbl, ttbh;                                       \
+       asm volatile(                                                   \
+       "       mrrc    p15, 0, %0, %1, c2              @ read TTBR0\n" \
+       "       mov     %1, %2, lsl #(48 - 32)          @ set ASID\n"   \
+       "       mcrr    p15, 0, %0, %1, c2              @ set TTBR0\n"  \
+       : "=&r" (ttbl), "=&r" (ttbh)                                    \
+       : "r" (asid & ~ASID_MASK));                                     \
+}
+#else
+#define cpu_set_asid(asid) \
+       asm("   mcr     p15, 0, %0, c13, c0, 1\n" : : "r" (asid))
+#endif
+
 /*
  * We fork()ed a process, and we need a new context for the child
  * to run in.  We reserve version 0 for initial tasks so we will
@@ -37,7 +52,7 @@ void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
 static void flush_context(void)
 {
        /* set the reserved ASID before flushing the TLB */
-       asm("mcr        p15, 0, %0, c13, c0, 1\n" : : "r" (0));
+       cpu_set_asid(0);
        isb();
        local_flush_tlb_all();
        if (icache_is_vivt_asid_tagged()) {
@@ -99,7 +114,7 @@ static void reset_context(void *info)
        set_mm_context(mm, asid);
 
        /* set the new ASID */
-       asm("mcr        p15, 0, %0, c13, c0, 1\n" : : "r" (mm->context.id));
+       cpu_set_asid(mm->context.id);
        isb();
 }
 

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 3c3867850a3011d1e163d347a25ffbabc4aa4dc7..ac72d89683df768e2d70b1eed0a54b2f46238360 100644 (file)
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -101,8 +101,13 @@ ENDPROC(cpu_v7_dcache_clean_area)
  */
 ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_MMU
-       mov     r2, #0
        ldr     r1, [r1, #MM_CONTEXT_ID]        @ get mm->context.id
+       mov     r2, #0
+#ifdef CONFIG_ARM_LPAE
+       and     r3, r1, #0xff
+       mov     r3, r3, lsl #(48 - 32)          @ ASID
+       mcrr    p15, 0, r0, r3, c2              @ set TTB 0
+#else  /* !CONFIG_ARM_LPAE */
        ALT_SMP(orr     r0, r0, #TTB_FLAGS_SMP)
        ALT_UP(orr      r0, r0, #TTB_FLAGS_UP)
 #ifdef CONFIG_ARM_ERRATA_430973
@@ -113,12 +118,13 @@ ENTRY(cpu_v7_switch_mm)
 #endif
        mcr     p15, 0, r2, c13, c0, 1          @ set reserved context ID
        isb
-1:     mcr     p15, 0, r0, c2, c0, 0           @ set TTB 0
+       mcr     p15, 0, r0, c2, c0, 0           @ set TTB 0
        isb
 #ifdef CONFIG_ARM_ERRATA_754322
        dsb
 #endif
        mcr     p15, 0, r1, c13, c0, 1          @ set context ID
+#endif /* CONFIG_ARM_LPAE */
        isb
 #endif
        mov     pc, lr