dmaengine: dw: fix a typo for bitfields of CTL_LO

The offset of SINC should be 9, not 7, here fix this
typo.

Signed-off-by: Jie Yang <yang.jie@intel.com>
Acked-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>

diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
index 241ff2b1402bf95572d053c09616414ba5eb2044..0a50c18d85b8bbfb9c5574f61ebba50d57f2d617 100644 (file)
--- a/drivers/dma/dw/regs.h
+++ b/drivers/dma/dw/regs.h
@@ -150,7 +150,7 @@ enum dw_dma_msize {
 #define DWC_CTLL_DST_INC       (0<<7)          /* DAR update/not */
 #define DWC_CTLL_DST_DEC       (1<<7)
 #define DWC_CTLL_DST_FIX       (2<<7)
-#define DWC_CTLL_SRC_INC       (0<<7)          /* SAR update/not */
+#define DWC_CTLL_SRC_INC       (0<<9)          /* SAR update/not */
 #define DWC_CTLL_SRC_DEC       (1<<9)
 #define DWC_CTLL_SRC_FIX       (2<<9)
 #define DWC_CTLL_DST_MSIZE(n)  ((n)<<11)       /* burst, #elements */