PCI: mvebu - The bridge secondary status register should be 0

There are no writable bits in the secondary status register, only
write 1 to clear bits. The driver never sets any of the write 1 to
clear bits so the status register should always be 0, just remove
the set from the write path.

Someday the write 1 to clear bits should be copied/cleared directly
from registers in the HW.

Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index 3da8f16b38988153907e76401b9dee9c8972baca..20c470cb77be2ba02204abdc162c5a0b477b7cf1 100644 (file)
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -516,7 +516,6 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
                 */
                bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
                bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
-               bridge->secondary_status = value >> 16;
                mvebu_pcie_handle_iobase_change(port);
                break;