Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux...

Conflicts:
	arch/arm/mach-shmobile/clock-sh73a0.c

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

diff --combined arch/arm/mach-shmobile/clock-sh73a0.c
index 8ea8c810144bf335256d5f73e1bf9bd0880c947b,1370a89ca358ba548c80ae5ed3ec29b52156b501..34944d01bf1ed99db00a49f4b9845271ddce3a3e
--- 1/arch/arm/mach-shmobile/clock-sh73a0.c
--- 2/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@@ -92,24 -92,6 +92,24 @@@ static struct clk_ops div2_clk_ops = 
        .recalc         = div2_recalc,
  };
  
 +static unsigned long div7_recalc(struct clk *clk)
 +{
 +      return clk->parent->rate / 7;
 +}
 +
 +static struct clk_ops div7_clk_ops = {
 +      .recalc         = div7_recalc,
 +};
 +
 +static unsigned long div13_recalc(struct clk *clk)
 +{
 +      return clk->parent->rate / 13;
 +}
 +
 +static struct clk_ops div13_clk_ops = {
 +      .recalc         = div13_recalc,
 +};
 +
  /* Divide extal1 by two */
  static struct clk extal1_div2_clk = {
        .ops            = &div2_clk_ops,
@@@ -131,6 -113,7 +131,7 @@@ static struct clk main_clk = 
        .ops            = &main_clk_ops,
  };
  
+ /* Divide Main clock by two */
  static struct clk main_div2_clk = {
        .ops            = &div2_clk_ops,
        .parent         = &main_clk,
@@@ -191,29 -174,12 +192,29 @@@ static struct clk pll3_clk = 
        .enable_bit     = 3,
  };
  
 -/* Divide PLL1 by two */
 +/* Divide PLL */
  static struct clk pll1_div2_clk = {
        .ops            = &div2_clk_ops,
        .parent         = &pll1_clk,
  };
  
 +static struct clk pll1_div7_clk = {
 +      .ops            = &div7_clk_ops,
 +      .parent         = &pll1_clk,
 +};
 +
 +static struct clk pll1_div13_clk = {
 +      .ops            = &div13_clk_ops,
 +      .parent         = &pll1_clk,
 +};
 +
 +/* External input clock */
 +struct clk sh73a0_extcki_clk = {
 +};
 +
 +struct clk sh73a0_extalr_clk = {
 +};
 +
  static struct clk *main_clks[] = {
        &r_clk,
        &sh73a0_extal1_clk,
@@@ -227,10 -193,6 +228,10 @@@
        &pll2_clk,
        &pll3_clk,
        &pll1_div2_clk,
 +      &pll1_div7_clk,
 +      &pll1_div13_clk,
 +      &sh73a0_extcki_clk,
 +      &sh73a0_extalr_clk,
  };
  
  static void div4_kick(struct clk *clk)
@@@ -284,84 -246,27 +285,84 @@@ enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3
        DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
        DIV6_NR };
  
 +static struct clk *vck_parent[8] = {
 +      [0] = &pll1_div2_clk,
 +      [1] = &pll2_clk,
 +      [2] = &sh73a0_extcki_clk,
 +      [3] = &sh73a0_extal2_clk,
 +      [4] = &main_div2_clk,
 +      [5] = &sh73a0_extalr_clk,
 +      [6] = &main_clk,
 +};
 +
 +static struct clk *pll_parent[4] = {
 +      [0] = &pll1_div2_clk,
 +      [1] = &pll2_clk,
 +      [2] = &pll1_div13_clk,
 +};
 +
 +static struct clk *hsi_parent[4] = {
 +      [0] = &pll1_div2_clk,
 +      [1] = &pll2_clk,
 +      [2] = &pll1_div7_clk,
 +};
 +
 +static struct clk *pll_extal2_parent[] = {
 +      [0] = &pll1_div2_clk,
 +      [1] = &pll2_clk,
 +      [2] = &sh73a0_extal2_clk,
 +      [3] = &sh73a0_extal2_clk,
 +};
 +
 +static struct clk *dsi_parent[8] = {
 +      [0] = &pll1_div2_clk,
 +      [1] = &pll2_clk,
 +      [2] = &main_clk,
 +      [3] = &sh73a0_extal2_clk,
 +      [4] = &sh73a0_extcki_clk,
 +};
 +
  static struct clk div6_clks[DIV6_NR] = {
 -      [DIV6_VCK1] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR1, 0),
 -      [DIV6_VCK2] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR2, 0),
 -      [DIV6_VCK3] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR3, 0),
 -      [DIV6_ZB1] = SH_CLK_DIV6(&pll1_div2_clk, ZBCKCR, CLK_ENABLE_ON_INIT),
 -      [DIV6_FLCTL] = SH_CLK_DIV6(&pll1_div2_clk, FLCKCR, 0),
 -      [DIV6_SDHI0] = SH_CLK_DIV6(&pll1_div2_clk, SD0CKCR, 0),
 -      [DIV6_SDHI1] = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0),
 -      [DIV6_SDHI2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
 -      [DIV6_FSIA] = SH_CLK_DIV6(&pll1_div2_clk, FSIACKCR, 0),
 -      [DIV6_FSIB] = SH_CLK_DIV6(&pll1_div2_clk, FSIBCKCR, 0),
 -      [DIV6_SUB] = SH_CLK_DIV6(&sh73a0_extal2_clk, SUBCKCR, 0),
 -      [DIV6_SPUA] = SH_CLK_DIV6(&pll1_div2_clk, SPUACKCR, 0),
 -      [DIV6_SPUV] = SH_CLK_DIV6(&pll1_div2_clk, SPUVCKCR, 0),
 -      [DIV6_MSU] = SH_CLK_DIV6(&pll1_div2_clk, MSUCKCR, 0),
 -      [DIV6_HSI] = SH_CLK_DIV6(&pll1_div2_clk, HSICKCR, 0),
 -      [DIV6_MFG1] = SH_CLK_DIV6(&pll1_div2_clk, MFCK1CR, 0),
 -      [DIV6_MFG2] = SH_CLK_DIV6(&pll1_div2_clk, MFCK2CR, 0),
 -      [DIV6_DSIT] = SH_CLK_DIV6(&pll1_div2_clk, DSITCKCR, 0),
 -      [DIV6_DSI0P] = SH_CLK_DIV6(&pll1_div2_clk, DSI0PCKCR, 0),
 -      [DIV6_DSI1P] = SH_CLK_DIV6(&pll1_div2_clk, DSI1PCKCR, 0),
 +      [DIV6_VCK1] = SH_CLK_DIV6_EXT(VCLKCR1, 0,
 +                      vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
 +      [DIV6_VCK2] = SH_CLK_DIV6_EXT(VCLKCR2, 0,
 +                      vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
 +      [DIV6_VCK3] = SH_CLK_DIV6_EXT(VCLKCR3, 0,
 +                      vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
-       [DIV6_ZB1] = SH_CLK_DIV6_EXT(ZBCKCR, 0,
++      [DIV6_ZB1] = SH_CLK_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT,
 +                      pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
 +      [DIV6_FLCTL] = SH_CLK_DIV6_EXT(FLCKCR, 0,
 +                      pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
 +      [DIV6_SDHI0] = SH_CLK_DIV6_EXT(SD0CKCR, 0,
 +                      pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
 +      [DIV6_SDHI1] = SH_CLK_DIV6_EXT(SD1CKCR, 0,
 +                      pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
 +      [DIV6_SDHI2] = SH_CLK_DIV6_EXT(SD2CKCR, 0,
 +                      pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
 +      [DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0,
 +                      pll_parent, ARRAY_SIZE(pll_parent), 6, 1),
 +      [DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0,
 +                      pll_parent, ARRAY_SIZE(pll_parent), 6, 1),
 +      [DIV6_SUB] = SH_CLK_DIV6_EXT(SUBCKCR, 0,
 +                      pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
 +      [DIV6_SPUA] = SH_CLK_DIV6_EXT(SPUACKCR, 0,
 +                      pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
 +      [DIV6_SPUV] = SH_CLK_DIV6_EXT(SPUVCKCR, 0,
 +                      pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
 +      [DIV6_MSU] = SH_CLK_DIV6_EXT(MSUCKCR, 0,
 +                      pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
 +      [DIV6_HSI] = SH_CLK_DIV6_EXT(HSICKCR, 0,
 +                      hsi_parent, ARRAY_SIZE(hsi_parent), 6, 2),
 +      [DIV6_MFG1] = SH_CLK_DIV6_EXT(MFCK1CR, 0,
 +                      pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
 +      [DIV6_MFG2] = SH_CLK_DIV6_EXT(MFCK2CR, 0,
 +                      pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
 +      [DIV6_DSIT] = SH_CLK_DIV6_EXT(DSITCKCR, 0,
 +                      pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
 +      [DIV6_DSI0P] = SH_CLK_DIV6_EXT(DSI0PCKCR, 0,
 +                      dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3),
 +      [DIV6_DSI1P] = SH_CLK_DIV6_EXT(DSI1PCKCR, 0,
 +                      dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3),
  };
  
  enum { MSTP001,
@@@ -370,6 -275,7 +371,7 @@@
        MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
        MSTP331, MSTP329, MSTP325, MSTP323, MSTP318,
        MSTP314, MSTP313, MSTP312, MSTP311,
+       MSTP303, MSTP302, MSTP301, MSTP300,
        MSTP411, MSTP410, MSTP403,
        MSTP_NR };
  
@@@ -403,6 -309,10 +405,10 @@@ static struct clk mstp_clks[MSTP_NR] = 
        [MSTP313] = MSTP(&div6_clks[DIV6_SDHI1], SMSTPCR3, 13, 0), /* SDHI1 */
        [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */
        [MSTP311] = MSTP(&div6_clks[DIV6_SDHI2], SMSTPCR3, 11, 0), /* SDHI2 */
+       [MSTP303] = MSTP(&main_div2_clk, SMSTPCR3, 3, 0), /* TPU1 */
+       [MSTP302] = MSTP(&main_div2_clk, SMSTPCR3, 2, 0), /* TPU2 */
+       [MSTP301] = MSTP(&main_div2_clk, SMSTPCR3, 1, 0), /* TPU3 */
+       [MSTP300] = MSTP(&main_div2_clk, SMSTPCR3, 0, 0), /* TPU4 */
        [MSTP411] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */
        [MSTP410] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */
        [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
@@@ -452,6 -362,10 +458,10 @@@ static struct clk_lookup lookups[] = 
        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
        CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */
+       CLKDEV_DEV_ID("leds-renesas-tpu.12", &mstp_clks[MSTP303]), /* TPU1 */
+       CLKDEV_DEV_ID("leds-renesas-tpu.21", &mstp_clks[MSTP302]), /* TPU2 */
+       CLKDEV_DEV_ID("leds-renesas-tpu.30", &mstp_clks[MSTP301]), /* TPU3 */
+       CLKDEV_DEV_ID("leds-renesas-tpu.41", &mstp_clks[MSTP300]), /* TPU4 */
        CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */
        CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */
        CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
@@@ -489,7 -403,7 +499,7 @@@ void __init sh73a0_clock_init(void
                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
  
        if (!ret)
 -              ret = sh_clk_div6_register(div6_clks, DIV6_NR);
 +              ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
  
        if (!ret)
                ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);

diff --combined arch/arm/mach-shmobile/include/mach/common.h
index d055d054ef897e9c8b2fcfb947bc3db5b4e5ccfc,be78a2c73db4784a598f180b076cc239e693e0c9..13a18d343ecbc090fd847e66ff2d8f030a75b0bc
--- 1/arch/arm/mach-shmobile/include/mach/common.h
--- 2/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@@ -7,7 -7,6 +7,6 @@@ extern void shmobile_secondary_vector(v
  struct clk;
  extern int clk_init(void);
  extern void shmobile_handle_irq_intc(struct pt_regs *);
- extern void shmobile_handle_irq_gic(struct pt_regs *);
  extern struct platform_suspend_ops shmobile_suspend_ops;
  struct cpuidle_driver;
  extern void (*shmobile_cpuidle_modes[])(void);
@@@ -35,8 -34,8 +34,8 @@@ extern void sh7372_add_standard_devices
  extern void sh7372_clock_init(void);
  extern void sh7372_pinmux_init(void);
  extern void sh7372_pm_init(void);
- extern void sh7372_resume_core_standby_a3sm(void);
- extern int sh7372_do_idle_a3sm(unsigned long unused);
+ extern void sh7372_resume_core_standby_sysc(void);
+ extern int sh7372_do_idle_sysc(unsigned long sleep_mode);
  extern struct clk sh7372_extal1_clk;
  extern struct clk sh7372_extal2_clk;
  
@@@ -47,8 -46,6 +46,8 @@@ extern void sh73a0_clock_init(void)
  extern void sh73a0_pinmux_init(void);
  extern struct clk sh73a0_extal1_clk;
  extern struct clk sh73a0_extal2_clk;
 +extern struct clk sh73a0_extcki_clk;
 +extern struct clk sh73a0_extalr_clk;
  
  extern unsigned int sh73a0_get_core_count(void);
  extern void sh73a0_secondary_init(unsigned int cpu);