drm/amdgpu: Support DRM_MODE_PAGE_FLIP_ASYNC (v2)

When this flag is set, we program the hardware to execute the flip
during horizontal blank (i.e. for the next scanline) instead of during
vertical blank (i.e. for the next frame).

Ported from radeon commit:
drm/radeon: Support DRM_MODE_PAGE_FLIP_ASYNC

v2: drop DAL change for upstream

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 6589d43bd094daf13ab4d7062f7213ad2749d85a..ac26b13678b1b5f31c879365a0f9319007a0315a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -727,6 +727,7 @@ struct amdgpu_flip_work {
        unsigned                        shared_count;
        struct fence                    **shared;
        struct fence_cb                 cb;
+       bool                            async;
 };
 
 
@@ -2243,7 +2244,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
-#define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
+#define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index c835abe65df38927e4362aafb515e422a706e5d2..726803069fefcd01a38713f17d9defb5b6374328 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -132,7 +132,7 @@ static void amdgpu_flip_work_func(struct work_struct *__work)
                                 vblank->linedur_ns / 1000, stat, vpos, hpos);
 
        /* Do the flip (mmio) */
-       adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base);
+       adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async);
 
        /* Set the flip status */
        amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
@@ -197,6 +197,7 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc,
        work->event = event;
        work->adev = adev;
        work->crtc_id = amdgpu_crtc->crtc_id;
+       work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
 
        /* schedule unpin of the old buffer */
        old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index 8a253aa0b551741c262bf173e0da7fef22ff443d..6b1d7d3065645719787255395487c04f0dc8b11e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -283,7 +283,7 @@ struct amdgpu_display_funcs {
        u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);
        /* pageflipping */
        void (*page_flip)(struct amdgpu_device *adev,
-                        int crtc_id, u64 crtc_base);
+                         int crtc_id, u64 crtc_base, bool async);
        int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc,
                                        u32 *vbl, u32 *position);
        /* display topology setup */

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 8af5fbc60e5b15f4287ad7679c3ced3cdc8aab76..578328860396f65244c54e631af2a98541be909e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -284,10 +284,16 @@ static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
  * surface base address.
  */
 static void dce_v10_0_page_flip(struct amdgpu_device *adev,
-                             int crtc_id, u64 crtc_base)
+                               int crtc_id, u64 crtc_base, bool async)
 {
        struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
+       u32 tmp;
 
+       /* flip at hsync for async, default is vsync */
+       tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
+       tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
+                           GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
+       WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
        /* update the primary scanout address */
        WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
               upper_32_bits(crtc_base));
@@ -2211,6 +2217,14 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
 
        dce_v10_0_vga_enable(crtc, false);
 
+       /* Make sure surface address is updated at vertical blank rather than
+        * horizontal blank
+        */
+       tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
+       tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
+                           GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
+       WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
+
        WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
               upper_32_bits(fb_location));
        WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
@@ -2261,13 +2275,6 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
        WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
               (viewport_w << 16) | viewport_h);
 
-       /* pageflip setup */
-       /* make sure flip is at vb rather than hb */
-       tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
-       tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
-                           GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
-       WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
-
        /* set pageflip to happen only at start of vblank interval (front porch) */
        WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
 
@@ -2992,6 +2999,8 @@ static int dce_v10_0_sw_init(void *handle)
 
        adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
 
+       adev->ddev->mode_config.async_page_flip = true;
+
        adev->ddev->mode_config.max_width = 16384;
        adev->ddev->mode_config.max_height = 16384;
 

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index e7b951f00421f106216e2ffbcecf07c837966624..60bfeb1b956e01f181a7f9129ecd3f4634a0a2b1 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -302,10 +302,17 @@ static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
  * surface base address.
  */
 static void dce_v11_0_page_flip(struct amdgpu_device *adev,
-                             int crtc_id, u64 crtc_base)
+                               int crtc_id, u64 crtc_base, bool async)
 {
        struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
+       u32 tmp;
 
+       /* flip at hsync for async, default is vsync */
+       /* use UPDATE_IMMEDIATE_EN instead for async? */
+       tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
+       tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
+                           GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
+       WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
        /* update the scanout addresses */
        WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
               upper_32_bits(crtc_base));
@@ -2185,6 +2192,14 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
 
        dce_v11_0_vga_enable(crtc, false);
 
+       /* Make sure surface address is updated at vertical blank rather than
+        * horizontal blank
+        */
+       tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
+       tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
+                           GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
+       WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
+
        WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
               upper_32_bits(fb_location));
        WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
@@ -2235,13 +2250,6 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
        WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
               (viewport_w << 16) | viewport_h);
 
-       /* pageflip setup */
-       /* make sure flip is at vb rather than hb */
-       tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
-       tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
-                           GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
-       WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
-
        /* set pageflip to happen only at start of vblank interval (front porch) */
        WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
 
@@ -3042,6 +3050,8 @@ static int dce_v11_0_sw_init(void *handle)
 
        adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
 
+       adev->ddev->mode_config.async_page_flip = true;
+
        adev->ddev->mode_config.max_width = 16384;
        adev->ddev->mode_config.max_height = 16384;
 

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 25e6af03c4065a59d73e9d747e071b9f6d59b0be..c73993472059a6fc3280984426cebb18f6f304eb 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -233,10 +233,13 @@ static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
  * surface base address.
  */
 static void dce_v8_0_page_flip(struct amdgpu_device *adev,
-                             int crtc_id, u64 crtc_base)
+                              int crtc_id, u64 crtc_base, bool async)
 {
        struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 
+       /* flip at hsync for async, default is vsync */
+       WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
+              GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
        /* update the primary scanout addresses */
        WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
               upper_32_bits(crtc_base));
@@ -1999,7 +2002,7 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
        uint32_t fb_format, fb_pitch_pixels;
        u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
        u32 pipe_config;
-       u32 tmp, viewport_w, viewport_h;
+       u32 viewport_w, viewport_h;
        int r;
        bool bypass_lut = false;
 
@@ -2135,6 +2138,11 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
 
        dce_v8_0_vga_enable(crtc, false);
 
+       /* Make sure surface address is updated at vertical blank rather than
+        * horizontal blank
+        */
+       WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
+
        WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
               upper_32_bits(fb_location));
        WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
@@ -2182,12 +2190,6 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
        WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
               (viewport_w << 16) | viewport_h);
 
-       /* pageflip setup */
-       /* make sure flip is at vb rather than hb */
-       tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
-       tmp &= ~GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK;
-       WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
-
        /* set pageflip to happen only at start of vblank interval (front porch) */
        WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
 
@@ -2902,6 +2904,8 @@ static int dce_v8_0_sw_init(void *handle)
 
        adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
 
+       adev->ddev->mode_config.async_page_flip = true;
+
        adev->ddev->mode_config.max_width = 16384;
        adev->ddev->mode_config.max_height = 16384;