drm/i915: Use masked write for Context Status Buffer Pointer

This register needs to be updated with masked writes.

This was found by code inspection and comparison with Bspec and
doesn't seem to fix any known issue.

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
[danvet: Add note about impact.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 99bba8ece464bd5f9844e28e70fb96851797dd75..29347e7a9565af669da8cacee76da2829e9f5547 100644 (file)
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -521,7 +521,7 @@ void intel_lrc_irq_handler(struct intel_engine_cs *ring)
        ring->next_context_status_buffer = write_pointer % 6;
 
        I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
-                  ((u32)ring->next_context_status_buffer & 0x07) << 8);
+                  _MASKED_FIELD(0x07 << 8, ((u32)ring->next_context_status_buffer & 0x07) << 8));
 }
 
 static int execlists_context_queue(struct drm_i915_gem_request *request)