Merge remote-tracking branch 'drm/drm-next'

Conflicts:
	drivers/gpu/drm/i915/i915_dma.c
	drivers/gpu/drm/i915/intel_sdvo.c

diff --cc drivers/gpu/drm/ast/ast_mode.c
Simple merge

diff --cc drivers/gpu/drm/drm_crtc.c
Simple merge

diff --cc drivers/gpu/drm/drm_edid.c
Simple merge

diff --cc drivers/gpu/drm/exynos/exynos_drm_vidi.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_dma.c
index 914c0dfabe6048113abc150b38e06a107eb33c5b,2c09900e326746a41a52f3079aefa62d4dd66fae..8bd7c9a22d01f83cc5f536520fb418a7bef12034
--- 1/drivers/gpu/drm/i915/i915_dma.c
--- 2/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@@ -1586,8 -1606,7 +1606,8 @@@ int i915_driver_load(struct drm_device 
  
        spin_lock_init(&dev_priv->irq_lock);
        spin_lock_init(&dev_priv->error_lock);
-       spin_lock_init(&dev_priv->rps_lock);
+       spin_lock_init(&dev_priv->rps.lock);
 +      spin_lock_init(&dev_priv->dpio_lock);
  
        if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
                dev_priv->num_pipe = 3;

diff --cc drivers/gpu/drm/i915/i915_gem.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_gem_gtt.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_irq.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_display.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_dp.c
index ace757af913366db3e7cff4e670fa9c804c84d08,c59710db653e57d2b772d95617e7ad4da96c16d7..1f8b25b22c1957ed58ec363f72e6feb95faee2e1
--- 1/drivers/gpu/drm/i915/intel_dp.c
--- 2/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@@ -2508,35 -2521,41 +2521,37 @@@ intel_dp_init(struct drm_device *dev, i
        intel_connector_attach_encoder(intel_connector, intel_encoder);
        drm_sysfs_connector_add(connector);
  
+       intel_encoder->enable = intel_enable_dp;
+       intel_encoder->disable = intel_disable_dp;
+       intel_encoder->get_hw_state = intel_dp_get_hw_state;
+       intel_connector->get_hw_state = intel_connector_get_hw_state;
+ 
        /* Set up the DDC bus. */
-       switch (output_reg) {
-               case DP_A:
-                       name = "DPDDC-A";
-                       break;
-               case DP_B:
-               case PCH_DP_B:
-                       dev_priv->hotplug_supported_mask |=
-                               DPB_HOTPLUG_INT_STATUS;
-                       name = "DPDDC-B";
-                       break;
-               case DP_C:
-               case PCH_DP_C:
-                       dev_priv->hotplug_supported_mask |=
-                               DPC_HOTPLUG_INT_STATUS;
-                       name = "DPDDC-C";
-                       break;
-               case DP_D:
-               case PCH_DP_D:
-                       dev_priv->hotplug_supported_mask |=
-                               DPD_HOTPLUG_INT_STATUS;
-                       name = "DPDDC-D";
-                       break;
+       switch (port) {
+       case PORT_A:
+               name = "DPDDC-A";
+               break;
+       case PORT_B:
+               dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
+               name = "DPDDC-B";
+               break;
+       case PORT_C:
+               dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
+               name = "DPDDC-C";
+               break;
+       case PORT_D:
+               dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
+               name = "DPDDC-D";
+               break;
+       default:
+               WARN(1, "Invalid port %c\n", port_name(port));
+               break;
        }
  
 -      intel_dp_i2c_init(intel_dp, intel_connector, name);
 -
        /* Cache some DPCD data in the eDP case */
        if (is_edp(intel_dp)) {
 -              bool ret;
                struct edp_power_seq    cur, vbt;
                u32 pp_on, pp_off, pp_div;
 -              struct edid *edid;
  
                pp_on = I915_READ(PCH_PP_ON_DELAYS);
                pp_off = I915_READ(PCH_PP_OFF_DELAYS);

diff --cc drivers/gpu/drm/i915/intel_hdmi.c
index 12dc3308ab8c982f063a4b5b0e7dcc8dd2b3519b,5d02aad0de8ed1967c1a143d3fcb04874f2f8078..d39ed58d4a12bf801e1a5821d5bb26ec0736c894
--- 1/drivers/gpu/drm/i915/intel_hdmi.c
--- 2/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@@ -652,12 -654,67 +654,66 @@@ static void intel_enable_hdmi(struct in
                POSTING_READ(intel_hdmi->sdvox_reg);
        }
  
-       if (mode != DRM_MODE_DPMS_ON) {
-               temp &= ~enable_bits;
-       } else {
-               temp |= enable_bits;
+       temp |= enable_bits;
+ 
+       I915_WRITE(intel_hdmi->sdvox_reg, temp);
+       POSTING_READ(intel_hdmi->sdvox_reg);
+ 
+       /* HW workaround, need to write this twice for issue that may result
+        * in first write getting masked.
+        */
+       if (HAS_PCH_SPLIT(dev)) {
+               I915_WRITE(intel_hdmi->sdvox_reg, temp);
+               POSTING_READ(intel_hdmi->sdvox_reg);
+       }
+ }
+ 
+ static void intel_disable_hdmi(struct intel_encoder *encoder)
+ {
+       struct drm_device *dev = encoder->base.dev;
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
+       u32 temp;
+       u32 enable_bits = SDVO_ENABLE;
+ 
 -      if (intel_hdmi->has_audio)
 -              enable_bits |= SDVO_AUDIO_ENABLE;
++      enable_bits |= SDVO_AUDIO_ENABLE;
+ 
+       temp = I915_READ(intel_hdmi->sdvox_reg);
+ 
+       /* HW workaround for IBX, we need to move the port to transcoder A
+        * before disabling it. */
+       if (HAS_PCH_IBX(dev)) {
+               struct drm_crtc *crtc = encoder->base.crtc;
+               int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
+ 
+               if (temp & SDVO_PIPE_B_SELECT) {
+                       temp &= ~SDVO_PIPE_B_SELECT;
+                       I915_WRITE(intel_hdmi->sdvox_reg, temp);
+                       POSTING_READ(intel_hdmi->sdvox_reg);
+ 
+                       /* Again we need to write this twice. */
+                       I915_WRITE(intel_hdmi->sdvox_reg, temp);
+                       POSTING_READ(intel_hdmi->sdvox_reg);
+ 
+                       /* Transcoder selection bits only update
+                        * effectively on vblank. */
+                       if (crtc)
+                               intel_wait_for_vblank(dev, pipe);
+                       else
+                               msleep(50);
+               }
+       }
+ 
+       /* HW workaround, need to toggle enable bit off and on for 12bpc, but
+        * we do this anyway which shows more stable in testing.
+        */
+       if (HAS_PCH_SPLIT(dev)) {
+               I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
+               POSTING_READ(intel_hdmi->sdvox_reg);
        }
  
+       temp &= ~enable_bits;
+ 
        I915_WRITE(intel_hdmi->sdvox_reg, temp);
        POSTING_READ(intel_hdmi->sdvox_reg);
  

diff --cc drivers/gpu/drm/i915/intel_lvds.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_pm.c
Simple merge

diff --cc drivers/gpu/drm/radeon/atombios_dp.c
Simple merge

diff --cc drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
Simple merge

diff --cc drivers/staging/omapdrm/omap_connector.c
index 55e9c865585058e9195e3eeef9aa8c554b57c886,9c2287b71d29dbea4da97af0a0518e37f6086083..38be186c249a8ed8e3fbed927ec6ed17633ea2f1
--- 1/drivers/staging/omapdrm/omap_connector.c
--- 2/drivers/staging/omapdrm/omap_connector.c
+++ b/drivers/staging/omapdrm/omap_connector.c
@@@ -203,14 -180,11 +203,11 @@@ static int omap_connector_get_modes(str
                } else {
                        drm_mode_connector_update_edid_property(
                                        connector, NULL);
-                       connector->display_info.raw_edid = NULL;
-                       kfree(edid);
                }
+               kfree(edid);
        } else {
                struct drm_display_mode *mode = drm_mode_create(dev);
 -              struct omap_video_timings timings;
 +              struct omap_video_timings timings = {0};
  
                dssdrv->get_timings(dssdev, &timings);
  

diff --cc include/drm/drm_crtc.h
Simple merge

diff --cc include/drm/drm_fourcc.h
index f4621184a9b404f8f7a81dfb130258def67cbd58,fac7235281f11c8526e4559b6897497bbd54c2cc..646ae5f39f42a75b7ac5dcf2cf7cafd51cf3341b
--- 1/include/drm/drm_fourcc.h
--- 2/include/drm/drm_fourcc.h
+++ b/include/drm/drm_fourcc.h
@@@ -106,8 -106,11 +106,10 @@@
  #define DRM_FORMAT_NV21               fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
  #define DRM_FORMAT_NV16               fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
  #define DRM_FORMAT_NV61               fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
+ #define DRM_FORMAT_NV24               fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
+ #define DRM_FORMAT_NV42               fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
  
 -/* 2 non contiguous plane YCbCr */
 -#define DRM_FORMAT_NV12M      fourcc_code('N', 'M', '1', '2') /* 2x2 subsampled Cr:Cb plane */
 +/* special NV12 tiled format */
  #define DRM_FORMAT_NV12MT     fourcc_code('T', 'M', '1', '2') /* 2x2 subsampled Cr:Cb plane 64x32 macroblocks */
  
  /*