extern struct cpu_op *(*get_cpu_op)(int *op);
extern int lp_high_freq;
extern int lp_med_freq;
-extern int mx6q_revision(void);
void __iomem *apll_base;
static struct clk pll1_sys_main_clk;
void __iomem *ccm_base;
static int cpu_silicon_rev = -1;
-#define SI_REV_OFFSET 0x48
+#define MX6_USB_ANALOG_DIGPROG 0x260
-static int get_mx6q_srev(void)
+static int mx6_get_srev(void)
{
- void __iomem *romcp = ioremap(BOOT_ROM_BASE_ADDR, SZ_8K);
+ void __iomem *anatop = MX6_IO_ADDRESS(ANATOP_BASE_ADDR);
u32 rev;
- if (!romcp) {
- cpu_silicon_rev = -EINVAL;
- return 0;
- }
-
- rev = __raw_readl(romcp + SI_REV_OFFSET);
+ rev = __raw_readl(anatop + MX6_USB_ANALOG_DIGPROG);
rev &= 0xff;
- iounmap(romcp);
- if (rev == 0x10)
+ if (rev == 0)
return IMX_CHIP_REVISION_1_0;
- else if (rev == 0x11)
+ else if (rev == 1)
return IMX_CHIP_REVISION_1_1;
- else if (rev == 0x20)
- return IMX_CHIP_REVISION_2_0;
- return 0;
+
+ return IMX_CHIP_REVISION_UNKNOWN;
}
/*
* Returns:
* the silicon revision of the cpu
- * -EINVAL - not a mx50
*/
int mx6q_revision(void)
{
return -EINVAL;
if (cpu_silicon_rev == -1)
- cpu_silicon_rev = get_mx6q_srev();
+ cpu_silicon_rev = mx6_get_srev();
return cpu_silicon_rev;
}
EXPORT_SYMBOL(mx6q_revision);
+/*
+ * Returns:
+ * the silicon revision of the cpu
+ */
+int mx6dl_revision(void)
+{
+ if (!cpu_is_mx6dl())
+ return -EINVAL;
+
+ if (cpu_silicon_rev == -1)
+ cpu_silicon_rev = mx6_get_srev();
+
+ return cpu_silicon_rev;
+}
+EXPORT_SYMBOL(mx6dl_revision);
+
static int __init post_cpu_init(void)
{
unsigned int reg;
u32 cpu_type = readl(IO_ADDRESS(ANATOP_BASE_ADDR + 0x260));
cpu_type >>= 16;
- if (cpu_type == 0x63)
+ if (cpu_type == 0x63) {
mxc_set_cpu_type(MXC_CPU_MX6Q);
- else if (cpu_type == 0x61)
+ imx_print_silicon_rev("i.MX6Q", mx6q_revision());
+ } else if (cpu_type == 0x61) {
mxc_set_cpu_type(MXC_CPU_MX6DL);
- else
+ imx_print_silicon_rev("i.MX6DL/SOLO", mx6dl_revision());
+ } else
pr_err("Unknown CPU type: %x\n", cpu_type);
}
#define MODULE_SFTRST (1 << 31)
extern unsigned int gpc_wake_irq[4];
-extern int mx6q_revision(void);
static void __iomem *gpc_base = IO_ADDRESS(GPC_BASE_ADDR);
/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
#include <linux/module.h>
#include <mach/clock.h>
+#include <mach/hardware.h>
unsigned int __mxc_cpu_type;
EXPORT_SYMBOL(__mxc_cpu_type);
__mxc_cpu_type = type;
}
+void imx_print_silicon_rev(const char *cpu, int srev)
+{
+ if (srev == IMX_CHIP_REVISION_UNKNOWN)
+ pr_info("CPU identified as %s, unknown revision\n", cpu);
+ else
+ pr_info("CPU identified as %s, silicon rev %d.%d\n",
+ cpu, (srev >> 4) & 0xf, srev & 0xf);
+}
+
int mxc_jtag_enabled; /* OFF: 0 (default), ON: 1 */
int uart_at_24; /* OFF: 0 (default); ON: 1 */
/*
extern void mx6_cpu_regulator_init(void);
extern int mx6q_sabreauto_init_pfuze100(u32 int_gpio);
extern int mx6q_sabresd_init_pfuze100(u32 int_gpio);
+extern void imx_print_silicon_rev(const char *cpu, int srev);
#endif
#define MX6Q_DMA_REQ_SSI3_TX0 46
#define MX6Q_DMA_REQ_DTCP 47
+#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
+extern int mx6q_revision(void);
+extern int mx6dl_revision(void);
+#endif
+
#endif /* __ASM_ARCH_MXC_MX6_H__ */
#endif
#ifndef __ASSEMBLY__
-#ifdef CONFIG_SOC_IMX6Q
-extern int mx6q_revision(void);
-#else
-#define mx6q_revision(void) (0)
-#endif
struct cpu_op {
u32 pll_reg;
static void __iomem *timer_base;
-#ifdef CONFIG_ARCH_MX6
-extern int mx6q_revision(void);
-#endif
-
static inline void gpt_irq_disable(void)
{
unsigned int tmp;