next-level-cache = <&L2_0>;
clocks = <&a53cc 1>;
clock-latency = <200000>;
+ cpu-supply = <&pm8916_s2>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L2_0>;
clocks = <&a53cc 1>;
clock-latency = <200000>;
+ cpu-supply = <&pm8916_s2>;
};
CPU2: cpu@2 {
next-level-cache = <&L2_0>;
clocks = <&a53cc 1>;
clock-latency = <200000>;
+ cpu-supply = <&pm8916_s2>;
};
CPU3: cpu@3 {
next-level-cache = <&L2_0>;
clocks = <&a53cc 1>;
clock-latency = <200000>;
+ cpu-supply = <&pm8916_s2>;
};
};