ARM: imx6q: use pll2_pfd2_396m as the enfc_sel's parent

The gpmi-nand driver can support the ONFI nand chip's EDO (extra data out)
mode in the asynchrounous mode. In the asynchrounous mode 5, the gpmi
needs 100MHz clock for the IO. But with the pll2_pfd0_352m, we can not
get the 100MHz clock.

So choose pll2_pfd2_396m as enfc_sel's parent.

Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index bbc71f57b92be3dc46df50cc0978f596573a68d0..744327fc5e2b8f5d9e53fe29c26cd9e0f8b0eb36 100644 (file)
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -404,6 +404,13 @@ int __init mx6q_clocks_init(void)
        clk_register_clkdev(clk[ahb], "ahb", NULL);
        clk_register_clkdev(clk[cko1], "cko1", NULL);
 
+       /*
+        * The gpmi needs 100MHz frequency in the EDO/Sync mode,
+        * We can not get the 100MHz from the pll2_pfd0_352m.
+        * So choose pll2_pfd2_396m as enfc_sel's parent.
+        */
+       clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]);
+
        for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
                clk_prepare_enable(clk[clks_init_on[i]]);