i2c: mxs: Set I2C timing registers for mxs-i2c

This patch configures the I2C bus timing registers according
to information passed via DT. Currently, 100kHz and 400kHz
modes are supported.

The TIMING2 register value is wrong in the documentation for
i.MX28! This was found and fixed by:
  Shawn Guo <shawn.guo@linaro.org>

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>

diff --git a/Documentation/devicetree/bindings/i2c/i2c-mxs.txt b/Documentation/devicetree/bindings/i2c/i2c-mxs.txt
index 1bfc02de1b0cc9900827be41386429638c0548d7..30ac3a0557f7d8c99a3660cbaf6ef2d718f3f3a9 100644 (file)
--- a/Documentation/devicetree/bindings/i2c/i2c-mxs.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-mxs.txt
@@ -4,6 +4,8 @@ Required properties:
 - compatible: Should be "fsl,<chip>-i2c"
 - reg: Should contain registers location and length
 - interrupts: Should contain ERROR and DMA interrupts
+- clock-frequency: Desired I2C bus clock frequency in Hz.
+                   Only 100000Hz and 400000Hz modes are supported.
 
 Examples:
 
@@ -13,4 +15,5 @@ i2c0: i2c@80058000 {
        compatible = "fsl,imx28-i2c";
        reg = <0x80058000 2000>;
        interrupts = <111 68>;
+       clock-frequency = <100000>;
 };

diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 4634cb861a597d115b5f6dab784da3a616c81b01..9af1606b5d3cb3a2d4865f7df65dbca583528830 100644 (file)
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -381,6 +381,7 @@
                                compatible = "fsl,imx28-i2c";
                                reg = <0x80058000 2000>;
                                interrupts = <111 68>;
+                               clock-frequency = <100000>;
                                status = "disabled";
                        };
 
@@ -390,6 +391,7 @@
                                compatible = "fsl,imx28-i2c";
                                reg = <0x8005a000 2000>;
                                interrupts = <110 69>;
+                               clock-frequency = <100000>;
                                status = "disabled";
                        };
 

diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c
index 02ce1faeeeef9997d54ada8dbf763950f0653d7d..088c5c1ed17dfe831c4345ee8f02dd0ef4e1c82d 100644 (file)
--- a/drivers/i2c/busses/i2c-mxs.c
+++ b/drivers/i2c/busses/i2c-mxs.c
@@ -46,6 +46,10 @@
 #define MXS_I2C_CTRL0_DIRECTION                        0x00010000
 #define MXS_I2C_CTRL0_XFER_COUNT(v)            ((v) & 0x0000FFFF)
 
+#define MXS_I2C_TIMING0                (0x10)
+#define MXS_I2C_TIMING1                (0x20)
+#define MXS_I2C_TIMING2                (0x30)
+
 #define MXS_I2C_CTRL1          (0x40)
 #define MXS_I2C_CTRL1_SET      (0x44)
 #define MXS_I2C_CTRL1_CLR      (0x48)
@@ -97,6 +101,35 @@
 #define MXS_CMD_I2C_READ       (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
                                 MXS_I2C_CTRL0_MASTER_MODE)
 
+struct mxs_i2c_speed_config {
+       uint32_t        timing0;
+       uint32_t        timing1;
+       uint32_t        timing2;
+};
+
+/*
+ * Timing values for the default 24MHz clock supplied into the i2c block.
+ *
+ * The bus can operate at 95kHz or at 400kHz with the following timing
+ * register configurations. The 100kHz mode isn't present because it's
+ * values are not stated in the i.MX233/i.MX28 datasheet. The 95kHz mode
+ * shall be close enough replacement. Therefore when the bus is configured
+ * for 100kHz operation, 95kHz timing settings are actually loaded.
+ *
+ * For details, see i.MX233 [25.4.2 - 25.4.4] and i.MX28 [27.5.2 - 27.5.4].
+ */
+static const struct mxs_i2c_speed_config mxs_i2c_95kHz_config = {
+       .timing0        = 0x00780030,
+       .timing1        = 0x00800030,
+       .timing2        = 0x00300030,
+};
+
+static const struct mxs_i2c_speed_config mxs_i2c_400kHz_config = {
+       .timing0        = 0x000f0007,
+       .timing1        = 0x001f000f,
+       .timing2        = 0x00300030,
+};
+
 /**
  * struct mxs_i2c_dev - per device, private MXS-I2C data
  *
@@ -112,11 +145,17 @@ struct mxs_i2c_dev {
        struct completion cmd_complete;
        u32 cmd_err;
        struct i2c_adapter adapter;
+       const struct mxs_i2c_speed_config *speed;
 };
 
 static void mxs_i2c_reset(struct mxs_i2c_dev *i2c)
 {
        stmp_reset_block(i2c->regs);
+
+       writel(i2c->speed->timing0, i2c->regs + MXS_I2C_TIMING0);
+       writel(i2c->speed->timing1, i2c->regs + MXS_I2C_TIMING1);
+       writel(i2c->speed->timing2, i2c->regs + MXS_I2C_TIMING2);
+
        writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
        writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE,
                        i2c->regs + MXS_I2C_QUEUECTRL_SET);
@@ -319,6 +358,28 @@ static const struct i2c_algorithm mxs_i2c_algo = {
        .functionality = mxs_i2c_func,
 };
 
+static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
+{
+       uint32_t speed;
+       struct device *dev = i2c->dev;
+       struct device_node *node = dev->of_node;
+       int ret;
+
+       if (!node)
+               return -EINVAL;
+
+       i2c->speed = &mxs_i2c_95kHz_config;
+       ret = of_property_read_u32(node, "clock-frequency", &speed);
+       if (ret)
+               dev_warn(dev, "No I2C speed selected, using 100kHz\n");
+       else if (speed == 400000)
+               i2c->speed = &mxs_i2c_400kHz_config;
+       else if (speed != 100000)
+               dev_warn(dev, "Unsupported I2C speed selected, using 100kHz\n");
+
+       return 0;
+}
+
 static int __devinit mxs_i2c_probe(struct platform_device *pdev)
 {
        struct device *dev = &pdev->dev;
@@ -358,6 +419,11 @@ static int __devinit mxs_i2c_probe(struct platform_device *pdev)
                return err;
 
        i2c->dev = dev;
+
+       err = mxs_i2c_get_ofdata(i2c);
+       if (err)
+               return err;
+
        platform_set_drvdata(pdev, i2c);
 
        /* Do reset to enforce correct startup after pinmuxing */