ARM: socfpga: add reset for the Arria 10 platform

Since the Arria10's reset register offset is different from the Cyclone/Arria 5,
it's best to add a new DT_MACHINE_START() for the Arria10.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: use altera_a10_dt_match for the A10 machine desc

diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index 7259c37327025bb60ff2e81654a2b338ab1db37d..5bc6ea87cdf74bc7e916c297c1144d585564dfd3 100644 (file)
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -25,6 +25,7 @@
 #define SOCFPGA_RSTMGR_MODPERRST       0x14
 #define SOCFPGA_RSTMGR_BRGMODRST       0x1c
 
+#define SOCFPGA_A10_RSTMGR_CTRL                0xC
 #define SOCFPGA_A10_RSTMGR_MODMPURST   0x20
 
 /* System Manager bits */

diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 19643a756c48b68b8eb57ca328785d55921ff7d7..a1c0efaa87944c096c1ab3c92d4adbef71c2e804 100644 (file)
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -74,6 +74,19 @@ static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
        writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
 }
 
+static void socfpga_arria10_restart(enum reboot_mode mode, const char *cmd)
+{
+       u32 temp;
+
+       temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
+
+       if (mode == REBOOT_HARD)
+               temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
+       else
+               temp |= RSTMGR_CTRL_SWWARMRSTREQ;
+       writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
+}
+
 static const char *altera_dt_match[] = {
        "altr,socfpga",
        NULL
@@ -86,3 +99,16 @@ DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
        .restart        = socfpga_cyclone5_restart,
        .dt_compat      = altera_dt_match,
 MACHINE_END
+
+static const char *altera_a10_dt_match[] = {
+       "altr,socfpga-arria10",
+       NULL
+};
+
+DT_MACHINE_START(SOCFPGA_A10, "Altera SOCFPGA Arria10")
+       .l2c_aux_val    = 0,
+       .l2c_aux_mask   = ~0,
+       .init_irq       = socfpga_init_irq,
+       .restart        = socfpga_arria10_restart,
+       .dt_compat      = altera_a10_dt_match,
+MACHINE_END