Merge remote-tracking branch 'mvebu/for-next'

Conflicts:
	arch/arm/boot/dts/kirkwood.dtsi
	drivers/pci/host/Kconfig
	drivers/pci/host/pci-mvebu.c

diff --cc arch/arm/boot/dts/Makefile
Simple merge

diff --cc drivers/pci/host/Kconfig
index 3d950481112634fc847d61fef187efc86503a189,492eec933f0ab9ee4421bf64b732e1a02c691cb7..43186feb4294598b570727e5382263fbffbb1d0d
--- 1/drivers/pci/host/Kconfig
--- 2/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@@ -3,8 -3,7 +3,8 @@@ menu "PCI host controller drivers
  
  config PCI_MVEBU
        bool "Marvell EBU PCIe controller"
-       depends on ARCH_MVEBU || ARCH_KIRKWOOD
+       depends on ARCH_MVEBU || ARCH_DOVE || ARCH_KIRKWOOD
 +      depends on OF
  
  config PCIE_DW
        bool

diff --cc drivers/pci/host/pci-mvebu.c
index 729d5a101d621ece6d36b425ad213a48a57a859f,4cb870a3c74324a6c819e95706094b027e090971..d66530e7cb63cd6197c8d4018c693a1d455b327c
--- 1/drivers/pci/host/pci-mvebu.c
--- 2/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@@ -873,11 -904,46 +904,47 @@@ static int mvebu_pcie_probe(struct plat
                        continue;
                }
  
+               port->reset_gpio = of_get_named_gpio_flags(child,
+                                                  "reset-gpios", 0, &flags);
+               if (gpio_is_valid(port->reset_gpio)) {
+                       u32 reset_udelay = 20000;
+ 
+                       port->reset_active_low = flags & OF_GPIO_ACTIVE_LOW;
+                       port->reset_name = kasprintf(GFP_KERNEL,
+                                    "pcie%d.%d-reset", port->port, port->lane);
+                       of_property_read_u32(child, "reset-delay-us",
+                                            &reset_udelay);
+ 
+                       ret = devm_gpio_request_one(&pdev->dev,
+                           port->reset_gpio, GPIOF_DIR_OUT, port->reset_name);
+                       if (ret) {
+                               if (ret == -EPROBE_DEFER)
+                                       return ret;
+                               continue;
+                       }
+ 
+                       gpio_set_value(port->reset_gpio,
+                                      (port->reset_active_low) ? 1 : 0);
+                       msleep(reset_udelay/1000);
+               }
+ 
+               port->clk = of_clk_get_by_name(child, NULL);
+               if (IS_ERR(port->clk)) {
+                       dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
+                              port->port, port->lane);
+                       continue;
+               }
+ 
+               ret = clk_prepare_enable(port->clk);
+               if (ret)
+                       continue;
+ 
                port->base = mvebu_pcie_map_registers(pdev, child, port);
 -              if (!port->base) {
 +              if (IS_ERR(port->base)) {
                        dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
                                port->port, port->lane);
+                       clk_disable_unprepare(port->clk);
 +                      port->base = NULL;
                        continue;
                }