__raw_writel(reg_val, EPDC_TCE_VSCAN);
}
-void epdc_init_settings(struct mxc_epdc_fb_data *fb_data)
+static void epdc_init_settings(struct mxc_epdc_fb_data *fb_data)
{
struct imx_epdc_fb_mode *epdc_mode = fb_data->cur_mode;
struct fb_var_screeninfo *screeninfo = &fb_data->epdc_fb_var;
int num_ce;
int i;
+ /* Enable clocks to access EPDC regs */
+ clk_enable(fb_data->epdc_clk_axi);
+
/* Reset */
__raw_writel(EPDC_CTRL_SFTRST, EPDC_CTRL_SET);
while (!(__raw_readl(EPDC_CTRL) & EPDC_CTRL_CLKGATE))
reg_val = ((0 << EPDC_GPIO_PWRCTRL_OFFSET) & EPDC_GPIO_PWRCTRL_MASK)
| ((0 << EPDC_GPIO_BDR_OFFSET) & EPDC_GPIO_BDR_MASK);
__raw_writel(reg_val, EPDC_GPIO);
+
+ __raw_writel(fb_data->waveform_buffer_phys, EPDC_WVADDR);
+ __raw_writel(fb_data->working_buffer_phys, EPDC_WB_ADDR);
+ __raw_writel(fb_data->working_buffer_phys, EPDC_WB_ADDR_TCE);
+
+ /* Disable clock */
+ clk_disable(fb_data->epdc_clk_axi);
}
static void epdc_powerup(struct mxc_epdc_fb_data *fb_data)
{
/* Initialize EPDC, passing pointer to EPDC registers */
epdc_init_settings(fb_data);
- __raw_writel(fb_data->waveform_buffer_phys, EPDC_WVADDR);
- __raw_writel(fb_data->working_buffer_phys, EPDC_WB_ADDR);
- __raw_writel(fb_data->working_buffer_phys, EPDC_WB_ADDR_TCE);
fb_data->in_init = true;
epdc_powerup(fb_data);
draw_mode0(fb_data);
struct mxc_epdc_fb_data *data = platform_get_drvdata(pdev);
int ret;
+ data->pwrdown_delay = FB_POWERDOWN_DISABLE;
ret = mxc_epdc_fb_blank(FB_BLANK_POWERDOWN, &data->info);
if (ret)
goto out;
struct mxc_epdc_fb_data *data = platform_get_drvdata(pdev);
mxc_epdc_fb_blank(FB_BLANK_UNBLANK, &data->info);
+ epdc_init_settings(data);
+ data->updates_active = false;
+
return 0;
}
#else
mxc_spdc_t *data = platform_get_drvdata(pdev);
int ret;
+ data->pwrdown_delay = FB_POWERDOWN_DISABLE;
ret = mxc_spdc_fb_blank(FB_BLANK_POWERDOWN, &data->info);
return ret;
mxc_spdc_t *data = platform_get_drvdata(pdev);
mxc_spdc_fb_blank(FB_BLANK_UNBLANK, &data->info);
+ spdc_init_sequence(data);
+
return 0;
}
#else