Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index 2b7468923125e0895342da6d6b0905fba926a750..cfc1023f4fcb5d267c8d80b3e6159057cde323df 100644 (file)
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -575,15 +575,17 @@ int misc_init_r(void)
 #endif /* !defined(CONFIG_ARCHES) */
 
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+extern void __ft_board_setup(void *blob, bd_t *bd);
+
 void ft_board_setup(void *blob, bd_t *bd)
 {
        u32 val[4];
        int rc;
 
-       ft_cpu_setup(blob, bd);
+       __ft_board_setup(blob, bd);
 
        /* Fixup NOR mapping */
-       val[0] = 0;                             /* chip select number */
+       val[0] = CONFIG_SYS_NOR_CS;             /* chip select number */
        val[1] = 0;                             /* always 0 */
        val[2] = CONFIG_SYS_FLASH_BASE_PHYS_L;          /* we fixed up this address */
        val[3] = gd->bd->bi_flashsize;

diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index 33788cc9006cc16df6c7ae3e0bdd53e4e8199be5..2ab23365a537e8c53702313fcd43eca6322613f2 100644 (file)
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -60,6 +60,14 @@
                       "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);     \
        } while (0)
 
+#define PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(mnemonic)                     \
+       do {                                                            \
+               u32 data;                                               \
+               data = mfdcr(SDRAM_##mnemonic);                         \
+               printf("%20s[%02x] = 0x%08X\n",                         \
+                      "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);     \
+       } while (0)
+
 #if defined(CONFIG_440)
 /*
  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2
@@ -714,11 +722,11 @@ static void check_mem_type(unsigned long *dimm_populated,
                                spd_ddr_init_hang ();
                                break;
                        case 7:
-                               debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
+                               debug("DIMM slot %lu: DDR1 SDRAM detected\n", dimm_num);
                                dimm_populated[dimm_num] = SDRAM_DDR1;
                                break;
                        case 8:
-                               debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
+                               debug("DIMM slot %lu: DDR2 SDRAM detected\n", dimm_num);
                                dimm_populated[dimm_num] = SDRAM_DDR2;
                                break;
                        default:
@@ -796,7 +804,7 @@ static void check_frequency(unsigned long *dimm_populated,
                        else
                                cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
                                        ((tcyc_reg & 0x0F)*10);
-                       debug("cycle_time=%d [10 picoseconds]\n", cycle_time);
+                       debug("cycle_time=%lu [10 picoseconds]\n", cycle_time);
 
                        if  (cycle_time > (calc_cycle_time + 10)) {
                                /*
@@ -1407,7 +1415,7 @@ static void program_mode(unsigned long *dimm_populated,
 
        mfsdr(SDR0_DDR0, sdr_ddrpll);
        sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
-       debug("sdram_freq=%d\n", sdram_freq);
+       debug("sdram_freq=%lu\n", sdram_freq);
 
        /*------------------------------------------------------------------
         * Handle the timing.  We need to find the worst case timing of all
@@ -1437,7 +1445,7 @@ static void program_mode(unsigned long *dimm_populated,
 
                        /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /*  not used in this loop. */
                        cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
-                       debug("cas_bit[SPD byte 18]=%02x\n", cas_bit);
+                       debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit);
 
                        /* For a particular DIMM, grab the three CAS values it supports */
                        for (cas_index = 0; cas_index < 3; cas_index++) {
@@ -1469,7 +1477,7 @@ static void program_mode(unsigned long *dimm_populated,
                                                (((tcyc_reg & 0xF0) >> 4) * 100) +
                                                ((tcyc_reg & 0x0F)*10);
                                }
-                               debug("cas_index=%d: cycle_time_ns_x_100=%d\n", cas_index,
+                               debug("cas_index=%lu: cycle_time_ns_x_100=%lu\n", cas_index,
                                      cycle_time_ns_x_100[cas_index]);
                        }
 
@@ -1580,9 +1588,9 @@ static void program_mode(unsigned long *dimm_populated,
        cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
        cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
        cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
-       debug("cycle_3_0_clk=%d\n", cycle_3_0_clk);
-       debug("cycle_4_0_clk=%d\n", cycle_4_0_clk);
-       debug("cycle_5_0_clk=%d\n", cycle_5_0_clk);
+       debug("cycle_3_0_clk=%lu\n", cycle_3_0_clk);
+       debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk);
+       debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk);
 
        if (sdram_ddr1 == TRUE) { /* DDR1 */
                if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
@@ -2797,13 +2805,13 @@ calibration_loop:
        }
 
        mfsdram(SDRAM_DLCR, val);
-       debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
+       debug("%s[%d] DLCR: 0x%08lX\n", __FUNCTION__, __LINE__, val);
        mfsdram(SDRAM_RQDC, val);
-       debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
+       debug("%s[%d] RQDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
        mfsdram(SDRAM_RFDC, val);
-       debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
+       debug("%s[%d] RFDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
        mfsdram(SDRAM_RDCC, val);
-       debug("%s[%d] RDCC: 0x%08X\n", __FUNCTION__, __LINE__, val);
+       debug("%s[%d] RDCC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
 }
 #else /* calibration test with hardvalues */
 /*-----------------------------------------------------------------------------+
@@ -3196,10 +3204,10 @@ inline void ppc4xx_ibm_ddr2_register_dump(void)
 
 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
      defined(CONFIG_460EX) || defined(CONFIG_460GT))
-       PPC4xx_IBM_DDR2_DUMP_REGISTER(R0BAS);
-       PPC4xx_IBM_DDR2_DUMP_REGISTER(R1BAS);
-       PPC4xx_IBM_DDR2_DUMP_REGISTER(R2BAS);
-       PPC4xx_IBM_DDR2_DUMP_REGISTER(R3BAS);
+       PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R0BAS);
+       PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R1BAS);
+       PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R2BAS);
+       PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R3BAS);
 #endif /* (defined(CONFIG_440SP) || ... */
 #if defined(CONFIG_405EX)
        PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR);

diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c
index 99b8e2f8824a4b17df44c9f195c2f419586786e6..31ca85dc5552777e567890fbb6bb2972a0f1294a 100644 (file)
--- a/cpu/ppc4xx/4xx_pci.c
+++ b/cpu/ppc4xx/4xx_pci.c
@@ -99,6 +99,19 @@ ushort pmc405_pci_subsys_deviceid(void);
 
 /*#define DEBUG*/
 
+int __is_pci_host(struct pci_controller *hose)
+{
+#if defined(CONFIG_405GP)
+       if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
+               return 1;
+#elif defined (CONFIG_405EP)
+       if (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN)
+               return 1;
+#endif
+       return 0;
+}
+int is_pci_host(struct pci_controller *hose) __attribute__((weak, alias("__is_pci_host")));
+
 /*-----------------------------------------------------------------------------+
  * pci_init.  Initializes the 405GP PCI Configuration regs.
  *-----------------------------------------------------------------------------*/
@@ -270,7 +283,7 @@ void pci_405gp_init(struct pci_controller *hose)
         */
        pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
 #ifdef CONFIG_CPCI405
-       if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
+       if (is_pci_host(hose))
                pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
        else
                pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID2);
@@ -295,7 +308,7 @@ void pci_405gp_init(struct pci_controller *hose)
 
 #if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
-       if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) ||
+       if (is_pci_host(hose) ||
            (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
 #endif
        {
@@ -325,7 +338,7 @@ void pci_405gp_init(struct pci_controller *hose)
         * Scan the PCI bus and configure devices found.
         *--------------------------------------------------------------------------*/
 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
-       if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) ||
+       if (is_pci_host(hose) ||
            (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
 #endif
        {

diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index 06f44ad376fb7931e897f5562d30cd963314dd96..fb3837c3df7befa480a7fc2ad30b180e41c49019 100644 (file)
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -54,6 +54,7 @@ int __get_cpu_num(void)
 }
 int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num")));
 
+#if defined(CONFIG_PCI)
 #if defined(CONFIG_405GP) || \
     defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
@@ -76,6 +77,7 @@ static int pci_async_enabled(void)
 #endif
 }
 #endif
+#endif /* CONFIG_PCI */
 
 #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
     !defined(CONFIG_405) && !defined(CONFIG_405EX)

diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index ac96fc28f77522098123822b0c185cdabe9c9cf3..582c781cacf66436b92d4597ddfb7a12f9e765a4 100644 (file)
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -2021,6 +2021,7 @@ pci_wait:
 ! Output r3 = none
 !-----------------------------------------------------------------------------
 */
+       .globl  pll_write
 pll_write:
        mfdcr  r5, CPC0_UCR
        andis. r5,r5,0xFFFF

diff --git a/cpu/ppc4xx/uic.c b/cpu/ppc4xx/uic.c
index a95d1cb17d9ef34d37db7ca2c7f388025e29b416..d298b312ceed7963e3a5125645d538374e938a49 100644 (file)
--- a/cpu/ppc4xx/uic.c
+++ b/cpu/ppc4xx/uic.c
@@ -164,7 +164,7 @@ void pic_irq_enable(unsigned int vec)
        else if (vec >= 96)
                mtdcr(uic3er, mfdcr(uic3er) | UIC_MASK(vec));
 
-       debug("Install interrupt for vector %d ==> %p\n", vec, handler);
+       debug("Install interrupt vector %d\n", vec);
 }
 
 void pic_irq_disable(unsigned int vec)

diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index d814012c415ee08e952e7397d8eff5b2f18bd902..48c51988af4ce0ed7e1baac6c598d039a5b632f0 100644 (file)
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -132,9 +132,11 @@
  */
 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define        CONFIG_ENV_IS_IN_FLASH  1       /* use FLASH for environment vars */
+#define CONFIG_SYS_NOR_CS              0       /* NOR chip connected to CSx */
 #define CONFIG_SYS_NAND_CS             3       /* NAND chip connected to CSx */
 #else
 #define        CONFIG_ENV_IS_IN_NAND   1       /* use NAND for environment vars  */
+#define CONFIG_SYS_NOR_CS              3       /* NOR chip connected to CSx */
 #define CONFIG_SYS_NAND_CS             0       /* NAND chip connected to CSx */
 #define CONFIG_ENV_IS_EMBEDDED 1       /* use embedded environment */
 #endif