pinctrl: exynos: Add BUS1 pin controller for exynos7

USB and Power regulator on Exynos7 require gpios available
in BUS1 pin controller block.
So adding the BUS1 pinctrl support.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index 742e4726e8610e566d738a1536f28a9e8678a66a..c88ba35bef267379d432c01d4a933ca90e82ca41 100644 (file)
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -180,6 +180,7 @@ Aliases for controllers compatible with "samsung,exynos7-pinctrl":
 - pinctrl5: pin controller of ESE block,
 - pinctrl6: pin controller of FSYS0 block,
 - pinctrl7: pin controller of FSYS1 block,
+- pinctrl8: pin controller of BUS1 block,
 
 Example: A pin-controller node with pin banks:
 

diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index becb3792977be8d2d26814006755358942d8dc76..2a85cb442f9b857ef9e746c327d9dd1345a2f742 100644 (file)
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1300,6 +1300,20 @@ static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
        EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
 };
 
+/* pin banks of exynos7 pin-controller - BUS1 */
+static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
+       EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),
+       EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04),
+       EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08),
+       EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c),
+       EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10),
+       EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14),
+       EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18),
+       EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c),
+       EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20),
+       EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24),
+};
+
 const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
        {
                /* pin-controller instance 0 Alive data */
@@ -1342,5 +1356,10 @@ const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
                .pin_banks      = exynos7_pin_banks7,
                .nr_banks       = ARRAY_SIZE(exynos7_pin_banks7),
                .eint_gpio_init = exynos_eint_gpio_init,
+       }, {
+               /* pin-controller instance 8 BUS1 data */
+               .pin_banks      = exynos7_pin_banks8,
+               .nr_banks       = ARRAY_SIZE(exynos7_pin_banks8),
+               .eint_gpio_init = exynos_eint_gpio_init,
        },
 };