Merge branch 'v2.6.35-omap-mailbox-for-next' of git://gitorious.org/~doyu/lk/mainline...

Conflicts:
	arch/arm/mach-omap1/devices.c

diff --git a/Documentation/arm/memory.txt b/Documentation/arm/memory.txt
index eb0fae18ffb12a805bb81eb2c5005a773d499d2b..771d48d3b335a1419f1ec363d540c77ad6d75fbc 100644 (file)
--- a/Documentation/arm/memory.txt
+++ b/Documentation/arm/memory.txt
@@ -33,7 +33,13 @@ ffff0000     ffff0fff        CPU vector page.
 
 fffe0000       fffeffff        XScale cache flush area.  This is used
                                in proc-xscale.S to flush the whole data
-                               cache.  Free for other usage on non-XScale.
+                               cache. (XScale does not have TCM.)
+
+fffe8000       fffeffff        DTCM mapping area for platforms with
+                               DTCM mounted inside the CPU.
+
+fffe0000       fffe7fff        ITCM mapping area for platforms with
+                               ITCM mounted inside the CPU.
 
 fff00000       fffdffff        Fixmap mapping region.  Addresses provided
                                by fix_to_virt() will be located here.

diff --git a/Documentation/arm/tcm.txt b/Documentation/arm/tcm.txt
index 77fd9376e6d73b4cc47d39afb8d7b01ad4b00120..7c15871c1885df512a87493c8fbfc3c1df6cc610 100644 (file)
--- a/Documentation/arm/tcm.txt
+++ b/Documentation/arm/tcm.txt
@@ -19,8 +19,8 @@ defines a CPUID_TCM register that you can read out from the
 system control coprocessor. Documentation from ARM can be found
 at http://infocenter.arm.com, search for "TCM Status Register"
 to see documents for all CPUs. Reading this register you can
-determine if ITCM (bit 0) and/or DTCM (bit 16) is present in the
-machine.
+determine if ITCM (bits 1-0) and/or DTCM (bit 17-16) is present
+in the machine.
 
 There is further a TCM region register (search for "TCM Region
 Registers" at the ARM site) that can report and modify the location
@@ -35,7 +35,15 @@ The TCM memory can then be remapped to another address again using
 the MMU, but notice that the TCM if often used in situations where
 the MMU is turned off. To avoid confusion the current Linux
 implementation will map the TCM 1 to 1 from physical to virtual
-memory in the location specified by the machine.
+memory in the location specified by the kernel. Currently Linux
+will map ITCM to 0xfffe0000 and on, and DTCM to 0xfffe8000 and
+on, supporting a maximum of 32KiB of ITCM and 32KiB of DTCM.
+
+Newer versions of the region registers also support dividing these
+TCMs in two separate banks, so for example an 8KiB ITCM is divided
+into two 4KiB banks with its own control registers. The idea is to
+be able to lock and hide one of the banks for use by the secure
+world (TrustZone).
 
 TCM is used for a few things:
 
@@ -65,18 +73,18 @@ in <asm/tcm.h>. Using this interface it is possible to:
   memory. Such a heap is great for things like saving
   device state when shutting off device power domains.
 
-A machine that has TCM memory shall select HAVE_TCM in
-arch/arm/Kconfig for itself, and then the
-rest of the functionality will depend on the physical
-location and size of ITCM and DTCM to be defined in
-mach/memory.h for the machine. Code that needs to use
-TCM shall #include <asm/tcm.h> If the TCM is not located
-at the place given in memory.h it will be moved using
-the TCM Region registers.
+A machine that has TCM memory shall select HAVE_TCM from
+arch/arm/Kconfig for itself. Code that needs to use TCM shall
+#include <asm/tcm.h>
 
 Functions to go into itcm can be tagged like this:
 int __tcmfunc foo(int bar);
 
+Since these are marked to become long_calls and you may want
+to have functions called locally inside the TCM without
+wasting space, there is also the __tcmlocalfunc prefix that
+will make the call relative.
+
 Variables to go into dtcm can be tagged like this:
 int __tcmdata foo;
 

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 98922f7d2d1236dd7fd29fa404447b46189c0222..e39caa8b0c93e323c9c1e2feda7bb90fd1a3a4a1 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -10,6 +10,7 @@ config ARM
        default y
        select HAVE_AOUT
        select HAVE_IDE
+       select HAVE_MEMBLOCK
        select RTC_LIB
        select SYS_SUPPORTS_APM_EMULATION
        select GENERIC_ATOMIC64 if (!CPU_32v6K)
@@ -24,6 +25,7 @@ config ARM
        select HAVE_KERNEL_LZMA
        select HAVE_PERF_EVENTS
        select PERF_USE_VMALLOC
+       select HAVE_REGS_AND_STACK_ACCESS_API
        help
          The ARM series is a line of low-power-consumption RISC chip designs
          licensed by ARM Ltd and targeted at embedded applications and
@@ -55,7 +57,7 @@ config GENERIC_CLOCKEVENTS
 config GENERIC_CLOCKEVENTS_BROADCAST
        bool
        depends on GENERIC_CLOCKEVENTS
-       default y if SMP && !LOCAL_TIMERS
+       default y if SMP
 
 config HAVE_TCM
        bool
@@ -301,6 +303,7 @@ config ARCH_CNS3XXX
        select CPU_V6
        select GENERIC_CLOCKEVENTS
        select ARM_GIC
+       select PCI_DOMAINS if PCI
        help
          Support for Cavium Networks CNS3XXX platform.
 
@@ -439,21 +442,6 @@ config ARCH_IXP4XX
        help
          Support for Intel's IXP4XX (XScale) family of processors.
 
-config ARCH_L7200
-       bool "LinkUp-L7200"
-       select CPU_ARM720T
-       select FIQ
-       select ARCH_USES_GETTIMEOFFSET
-       help
-         Say Y here if you intend to run this kernel on a LinkUp Systems
-         L7200 Software Development Board which uses an ARM720T processor.
-         Information on this board can be obtained at:
-
-         <http://www.linkupsys.com/>
-
-         If you have any questions or comments about the Linux kernel port
-         to this board, send e-mail to <sjhill@cotw.com>.
-
 config ARCH_DOVE
        bool "Marvell Dove"
        select PCI
@@ -482,6 +470,19 @@ config ARCH_LOKI
        help
          Support for the Marvell Loki (88RC8480) SoC.
 
+config ARCH_LPC32XX
+       bool "NXP LPC32XX"
+       select CPU_ARM926T
+       select ARCH_REQUIRE_GPIOLIB
+       select HAVE_IDE
+       select ARM_AMBA
+       select USB_ARCH_HAS_OHCI
+       select COMMON_CLKDEV
+       select GENERIC_TIME
+       select GENERIC_CLOCKEVENTS
+       help
+         Support for the NXP LPC32XX family of processors
+
 config ARCH_MV78XX0
        bool "Marvell MV78xx0"
        select CPU_FEROCEON
@@ -586,6 +587,7 @@ config ARCH_MSM
        bool "Qualcomm MSM"
        select HAVE_CLK
        select GENERIC_CLOCKEVENTS
+       select ARCH_REQUIRE_GPIOLIB
        help
          Support for Qualcomm MSM/QSD based systems.  This runs on the
          apps processor of the MSM/QSD and depends on a shared memory
@@ -719,7 +721,6 @@ config ARCH_SHARK
 config ARCH_LH7A40X
        bool "Sharp LH7A40X"
        select CPU_ARM922T
-       select ARCH_DISCONTIGMEM_ENABLE if !LH7A40X_CONTIGMEM
        select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM
        select ARCH_USES_GETTIMEOFFSET
        help
@@ -845,6 +846,8 @@ source "arch/arm/mach-lh7a40x/Kconfig"
 
 source "arch/arm/mach-loki/Kconfig"
 
+source "arch/arm/mach-lpc32xx/Kconfig"
+
 source "arch/arm/mach-msm/Kconfig"
 
 source "arch/arm/mach-mv78xx0/Kconfig"
@@ -1031,11 +1034,6 @@ endmenu
 
 source "arch/arm/common/Kconfig"
 
-config FORCE_MAX_ZONEORDER
-       int
-       depends on SA1111
-       default "9"
-
 menu "Bus support"
 
 config ARM_AMBA
@@ -1060,7 +1058,7 @@ config ISA_DMA_API
        bool
 
 config PCI
-       bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE
+       bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX
        help
          Find out whether you have a PCI motherboard. PCI is the name of a
          bus system, i.e. the way the CPU talks to the other stuff inside
@@ -1172,9 +1170,10 @@ config HOTPLUG_CPU
 config LOCAL_TIMERS
        bool "Use local timer interrupts"
        depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \
-               REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || ARCH_U8500)
+               REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
+               ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
        default y
-       select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500)
+       select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_VEXPRESS || ARCH_OMAP4 || ARCH_U8500)
        help
          Enable support for local timers on SMP platforms, rather then the
          legacy IPI broadcast method.  Local timers allows the system
@@ -1185,10 +1184,10 @@ source kernel/Kconfig.preempt
 
 config HZ
        int
-       default 128 if ARCH_L7200
        default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PV210
        default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
        default AT91_TIMER_HZ if ARCH_AT91
+       default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
        default 100
 
 config THUMB2_KERNEL
@@ -1241,10 +1240,6 @@ config OABI_COMPAT
 config ARCH_HAS_HOLES_MEMORYMODEL
        bool
 
-# Discontigmem is deprecated
-config ARCH_DISCONTIGMEM_ENABLE
-       bool
-
 config ARCH_SPARSEMEM_ENABLE
        bool
 
@@ -1252,13 +1247,7 @@ config ARCH_SPARSEMEM_DEFAULT
        def_bool ARCH_SPARSEMEM_ENABLE
 
 config ARCH_SELECT_MEMORY_MODEL
-       def_bool ARCH_DISCONTIGMEM_ENABLE && ARCH_SPARSEMEM_ENABLE
-
-config NODES_SHIFT
-       int
-       default "4" if ARCH_LH7A40X
-       default "2"
-       depends on NEED_MULTIPLE_NODES
+       def_bool ARCH_SPARSEMEM_ENABLE
 
 config HIGHMEM
        bool "High Memory Support (EXPERIMENTAL)"
@@ -1290,8 +1279,33 @@ config HW_PERF_EVENTS
          Enable hardware performance counter support for perf events. If
          disabled, perf events will use software events only.
 
+config SPARSE_IRQ
+       def_bool n
+       help
+         This enables support for sparse irqs. This is useful in general
+         as most CPUs have a fairly sparse array of IRQ vectors, which
+         the irq_desc then maps directly on to. Systems with a high
+         number of off-chip IRQs will want to treat this as
+         experimental until they have been independently verified.
+
 source "mm/Kconfig"
 
+config FORCE_MAX_ZONEORDER
+       int "Maximum zone order" if ARCH_SHMOBILE
+       range 11 64 if ARCH_SHMOBILE
+       default "9" if SA1111
+       default "11"
+       help
+         The kernel memory allocator divides physically contiguous memory
+         blocks into "zones", where each zone is a power of two number of
+         pages.  This option selects the largest power of two that the kernel
+         keeps in the memory allocator.  If you need to allocate very large
+         blocks of physically contiguous memory, then you may need to
+         increase this value.
+
+         This config option is actually maximum order plus one. For example,
+         a value of 11 means that the largest free memory block is 2^10 pages.
+
 config LEDS
        bool "Timer and CPU usage LEDs"
        depends on ARCH_CDB89712 || ARCH_EBSA110 || \
@@ -1375,6 +1389,24 @@ config UACCESS_WITH_MEMCPY
          However, if the CPU data cache is using a write-allocate mode,
          this option is unlikely to provide any performance gain.
 
+config CC_STACKPROTECTOR
+       bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
+       help
+         This option turns on the -fstack-protector GCC feature. This
+         feature puts, at the beginning of functions, a canary value on
+         the stack just before the return address, and validates
+         the value just before actually returning.  Stack based buffer
+         overflows (that need to overwrite this return address) now also
+         overwrite the canary, which gets detected and the attack is then
+         neutralized via a kernel panic.
+         This feature requires gcc version 4.2 or above.
+
+config DEPRECATED_PARAM_STRUCT
+       bool "Provide old way to pass kernel parameters"
+       help
+         This was deprecated in 2001 and announced to live on for 5 years.
+         Some old boot loaders still use this way.
+
 endmenu
 
 menu "Boot options"
@@ -1485,6 +1517,105 @@ config ATAGS_PROC
          Should the atags used to boot the kernel be exported in an "atags"
          file in procfs. Useful with kexec.
 
+config AUTO_ZRELADDR
+       bool "Auto calculation of the decompressed kernel image address"
+       depends on !ZBOOT_ROM && !ARCH_U300
+       help
+         ZRELADDR is the physical address where the decompressed kernel
+         image will be placed. If AUTO_ZRELADDR is selected, the address
+         will be determined at run-time by masking the current IP with
+         0xf8000000. This assumes the zImage being placed in the first 128MB
+         from start of memory.
+
+config ZRELADDR
+       hex "Physical address of the decompressed kernel image"
+       depends on !AUTO_ZRELADDR
+       default 0x00008000 if ARCH_BCMRING ||\
+               ARCH_CNS3XXX ||\
+               ARCH_DOVE ||\
+               ARCH_EBSA110 ||\
+               ARCH_FOOTBRIDGE ||\
+               ARCH_INTEGRATOR ||\
+               ARCH_IOP13XX ||\
+               ARCH_IOP33X ||\
+               ARCH_IXP2000 ||\
+               ARCH_IXP23XX ||\
+               ARCH_IXP4XX ||\
+               ARCH_KIRKWOOD ||\
+               ARCH_KS8695 ||\
+               ARCH_LOKI ||\
+               ARCH_MMP ||\
+               ARCH_MV78XX0 ||\
+               ARCH_NOMADIK ||\
+               ARCH_NUC93X ||\
+               ARCH_NS9XXX ||\
+               ARCH_ORION5X ||\
+               ARCH_SPEAR3XX ||\
+               ARCH_SPEAR6XX ||\
+               ARCH_U8500 ||\
+               ARCH_VERSATILE ||\
+               ARCH_W90X900
+       default 0x08008000 if ARCH_MX1 ||\
+               ARCH_SHARK
+       default 0x10008000 if ARCH_MSM ||\
+               ARCH_OMAP1 ||\
+               ARCH_RPC
+       default 0x20008000 if ARCH_S5P6440 ||\
+               ARCH_S5P6442 ||\
+               ARCH_S5PC100 ||\
+               ARCH_S5PV210
+       default 0x30008000 if ARCH_S3C2410 ||\
+               ARCH_S3C2400 ||\
+               ARCH_S3C2412 ||\
+               ARCH_S3C2416 ||\
+               ARCH_S3C2440 ||\
+               ARCH_S3C2443
+       default 0x40008000 if ARCH_STMP378X ||\
+               ARCH_STMP37XX ||\
+               ARCH_SH7372 ||\
+               ARCH_SH7377
+       default 0x50008000 if ARCH_S3C64XX ||\
+               ARCH_SH7367
+       default 0x60008000 if ARCH_VEXPRESS
+       default 0x80008000 if ARCH_MX25 ||\
+               ARCH_MX3 ||\
+               ARCH_NETX ||\
+               ARCH_OMAP2PLUS ||\
+               ARCH_PNX4008
+       default 0x90008000 if ARCH_MX5 ||\
+               ARCH_MX91231
+       default 0xa0008000 if ARCH_IOP32X ||\
+               ARCH_PXA ||\
+               MACH_MX27
+       default 0xc0008000 if ARCH_LH7A40X ||\
+               MACH_MX21
+       default 0xf0008000 if ARCH_AAEC2000 ||\
+               ARCH_L7200
+       default 0xc0028000 if ARCH_CLPS711X
+       default 0x70008000 if ARCH_AT91 && (ARCH_AT91CAP9 || ARCH_AT91SAM9G45)
+       default 0x20008000 if ARCH_AT91 && !(ARCH_AT91CAP9 || ARCH_AT91SAM9G45)
+       default 0xc0008000 if ARCH_DAVINCI && ARCH_DAVINCI_DA8XX
+       default 0x80008000 if ARCH_DAVINCI && !ARCH_DAVINCI_DA8XX
+       default 0x00008000 if ARCH_EP93XX && EP93XX_SDCE3_SYNC_PHYS_OFFSET
+       default 0xc0008000 if ARCH_EP93XX && EP93XX_SDCE0_PHYS_OFFSET
+       default 0xd0008000 if ARCH_EP93XX && EP93XX_SDCE1_PHYS_OFFSET
+       default 0xe0008000 if ARCH_EP93XX && EP93XX_SDCE2_PHYS_OFFSET
+       default 0xf0008000 if ARCH_EP93XX && EP93XX_SDCE3_ASYNC_PHYS_OFFSET
+       default 0x00008000 if ARCH_GEMINI && GEMINI_MEM_SWAP
+       default 0x10008000 if ARCH_GEMINI && !GEMINI_MEM_SWAP
+       default 0x70008000 if ARCH_REALVIEW && REALVIEW_HIGH_PHYS_OFFSET
+       default 0x00008000 if ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET
+       default 0xc0208000 if ARCH_SA1100 && SA1111
+       default 0xc0008000 if ARCH_SA1100 && !SA1111
+       default 0x30108000 if ARCH_S3C2410 && PM_H1940
+       default 0x28E08000 if ARCH_U300 && MACH_U300_SINGLE_RAM
+       default 0x48008000 if ARCH_U300 && !MACH_U300_SINGLE_RAM
+       help
+         ZRELADDR is the physical address where the decompressed kernel
+         image will be placed. ZRELADDR has to be specified when the
+         assumption of AUTO_ZRELADDR is not valid, or when ZBOOT_ROM is
+         selected.
+
 endmenu
 
 menu "CPU Power Management"

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 64ba313724d2377fda7e439e130d7ad69dd1a83c..63d998e8c672ef4488eb72df2cfdcce2f7ae502f 100644 (file)
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -34,6 +34,10 @@ ifeq ($(CONFIG_FRAME_POINTER),y)
 KBUILD_CFLAGS  +=-fno-omit-frame-pointer -mapcs -mno-sched-prolog
 endif
 
+ifeq ($(CONFIG_CC_STACKPROTECTOR),y)
+KBUILD_CFLAGS  +=-fstack-protector
+endif
+
 ifeq ($(CONFIG_CPU_BIG_ENDIAN),y)
 KBUILD_CPPFLAGS        += -mbig-endian
 AS             += -EB
@@ -139,14 +143,14 @@ machine-$(CONFIG_ARCH_IXP23XX)            := ixp23xx
 machine-$(CONFIG_ARCH_IXP4XX)          := ixp4xx
 machine-$(CONFIG_ARCH_KIRKWOOD)                := kirkwood
 machine-$(CONFIG_ARCH_KS8695)          := ks8695
-machine-$(CONFIG_ARCH_L7200)           := l7200
 machine-$(CONFIG_ARCH_LH7A40X)         := lh7a40x
 machine-$(CONFIG_ARCH_LOKI)            := loki
+machine-$(CONFIG_ARCH_LPC32XX)         := lpc32xx
 machine-$(CONFIG_ARCH_MMP)             := mmp
 machine-$(CONFIG_ARCH_MSM)             := msm
 machine-$(CONFIG_ARCH_MV78XX0)         := mv78xx0
-machine-$(CONFIG_ARCH_MX1)             := mx1
-machine-$(CONFIG_ARCH_MX2)             := mx2
+machine-$(CONFIG_ARCH_MX1)             := imx
+machine-$(CONFIG_ARCH_MX2)             := imx
 machine-$(CONFIG_ARCH_MX25)            := mx25
 machine-$(CONFIG_ARCH_MX3)             := mx3
 machine-$(CONFIG_ARCH_MX5)             := mx5

diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index 4a590f4113e2af044ea1764aeb0681ad7f50a74c..f705213caa881af9c07e181c0d2a3a1a26a5d98a 100644 (file)
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -14,18 +14,16 @@
 MKIMAGE         := $(srctree)/scripts/mkuboot.sh
 
 ifneq ($(MACHINE),)
-include $(srctree)/$(MACHINE)/Makefile.boot
+-include $(srctree)/$(MACHINE)/Makefile.boot
 endif
 
 # Note: the following conditions must always be true:
-#   ZRELADDR == virt_to_phys(PAGE_OFFSET + TEXT_OFFSET)
 #   PARAMS_PHYS must be within 4MB of ZRELADDR
 #   INITRD_PHYS must be in RAM
-ZRELADDR    := $(zreladdr-y)
 PARAMS_PHYS := $(params_phys-y)
 INITRD_PHYS := $(initrd_phys-y)
 
-export ZRELADDR INITRD_PHYS PARAMS_PHYS
+export INITRD_PHYS PARAMS_PHYS
 
 targets := Image zImage xipImage bootpImage uImage
 
@@ -67,7 +65,7 @@ quiet_cmd_uimage = UIMAGE  $@
 ifeq ($(CONFIG_ZBOOT_ROM),y)
 $(obj)/uImage: LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT)
 else
-$(obj)/uImage: LOADADDR=$(ZRELADDR)
+$(obj)/uImage: LOADADDR=$(CONFIG_ZRELADDR)
 endif
 
 ifeq ($(CONFIG_THUMB2_KERNEL),y)

diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 864a002137fed0bbc42efe7b4f2dc787a06ba48a..7636c9b3f9a7899f9209d9a82fa78de8a6dc9b17 100644 (file)
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -4,6 +4,7 @@
 # create a compressed vmlinuz image from the original vmlinux
 #
 
+AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET)
 HEAD   = head.o
 OBJS   = misc.o decompress.o
 FONTC  = $(srctree)/drivers/video/console/font_acorn_8x8.c
@@ -19,10 +20,6 @@ ifeq ($(CONFIG_ARCH_SHARK),y)
 OBJS           += head-shark.o ofw-shark.o
 endif
 
-ifeq ($(CONFIG_ARCH_L7200),y)
-OBJS           += head-l7200.o
-endif
-
 ifeq ($(CONFIG_ARCH_P720T),y)
 # Borrow this code from SA1100
 OBJS           += head-sa1100.o
@@ -82,19 +79,9 @@ endif
 EXTRA_CFLAGS  := -fpic -fno-builtin
 EXTRA_AFLAGS  := -Wa,-march=all
 
-# Supply ZRELADDR, INITRD_PHYS and PARAMS_PHYS to the decompressor via
-# linker symbols.  We only define initrd_phys and params_phys if the
-# machine class defined the corresponding makefile variable.
-LDFLAGS_vmlinux := --defsym zreladdr=$(ZRELADDR)
 ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
 LDFLAGS_vmlinux += --be8
 endif
-ifneq ($(INITRD_PHYS),)
-LDFLAGS_vmlinux += --defsym initrd_phys=$(INITRD_PHYS)
-endif
-ifneq ($(PARAMS_PHYS),)
-LDFLAGS_vmlinux += --defsym params_phys=$(PARAMS_PHYS)
-endif
 # ?
 LDFLAGS_vmlinux += -p
 # Report unresolved symbol references

diff --git a/arch/arm/boot/compressed/Makefile.debug b/arch/arm/boot/compressed/Makefile.debug
deleted file mode 100644 (file)
index 491a037..0000000
--- a/arch/arm/boot/compressed/Makefile.debug
+++ /dev/null
@@ -1,23 +0,0 @@
-#
-# linux/arch/arm/boot/compressed/Makefile
-#
-# create a compressed vmlinux image from the original vmlinux
-#
-
-COMPRESSED_EXTRA=../../lib/ll_char_wr.o
-OBJECTS=misc-debug.o ll_char_wr.aout.o
-
-CFLAGS=-D__KERNEL__ -O2 -DSTDC_HEADERS -DSTANDALONE_DEBUG -Wall -I../../../../include -c
-
-test-gzip: piggy.aout.o $(OBJECTS)
-       $(CC) -o $@ $(OBJECTS) piggy.aout.o
-
-misc-debug.o: misc.c
-       $(CC) $(CFLAGS) -o $@ misc.c
-
-piggy.aout.o: piggy.o
-       arm-linuxelf-objcopy --change-leading-char -I elf32-arm -O arm-aout32-linux piggy.o piggy.aout.o
-
-ll_char_wr.aout.o: $(COMPRESSED_EXTRA)
-       arm-linuxelf-objcopy --change-leading-char -I elf32-arm -O arm-aout32-linux $(COMPRESSED_EXTRA) ll_char_wr.aout.o
-

diff --git a/arch/arm/boot/compressed/head-l7200.S b/arch/arm/boot/compressed/head-l7200.S
deleted file mode 100644 (file)
index d0e3b20..0000000
--- a/arch/arm/boot/compressed/head-l7200.S
+++ /dev/null
@@ -1,29 +0,0 @@
-/* 
- * linux/arch/arm/boot/compressed/head-l7200.S
- * 
- * Copyright (C) 2000 Steve Hill <sjhill@cotw.com>
- * 
- * Some code borrowed from Nicolas Pitre's 'head-sa1100.S' file. This
- * is merged with head.S by the linker.
- */
-
-#include <asm/mach-types.h>
-
-#ifndef CONFIG_ARCH_L7200
-#error What am I doing here...
-#endif
-
-               .section        ".start", "ax"
-
-__L7200_start:
-               mov     r0, #0x00100000         @ FLASH address of initrd
-               mov     r2, #0xf1000000         @ RAM address of initrd
-               add     r3, r2, #0x00700000     @ Size of initrd 
-1:
-               ldmia   r0!, {r4, r5, r6, r7}
-               stmia   r2!, {r4, r5, r6, r7}
-               cmp     r2, r3
-               ble     1b
-
-               mov     r8, #0                  @ Zero it out
-               mov     r7, #MACH_TYPE_L7200    @ Set architecture ID

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index c5191b1532e8284cbeac17cef819522863a90743..abf4d65acf6243de88d3a0df342afabce87436e2 100644 (file)
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -170,9 +170,16 @@ not_angel:
 
                .text
                adr     r0, LC0
- ARM(          ldmia   r0, {r1, r2, r3, r4, r5, r6, r11, ip, sp})
- THUMB(                ldmia   r0, {r1, r2, r3, r4, r5, r6, r11, ip}   )
+ ARM(          ldmia   r0, {r1, r2, r3, r5, r6, r11, ip, sp})
+ THUMB(                ldmia   r0, {r1, r2, r3, r5, r6, r11, ip}       )
  THUMB(                ldr     sp, [r0, #32]                           )
+#ifdef CONFIG_AUTO_ZRELADDR
+               @ determine final kernel image address
+               and     r4, pc, #0xf8000000
+               add     r4, r4, #TEXT_OFFSET
+#else
+               ldr     r4, =CONFIG_ZRELADDR
+#endif
                subs    r0, r0, r1              @ calculate the delta offset
 
                                                @ if delta is zero, we are
@@ -310,18 +317,17 @@ wont_overwrite:   mov     r0, r4
 LC0:           .word   LC0                     @ r1
                .word   __bss_start             @ r2
                .word   _end                    @ r3
-               .word   zreladdr                @ r4
                .word   _start                  @ r5
                .word   _image_size             @ r6
                .word   _got_start              @ r11
                .word   _got_end                @ ip
-               .word   user_stack+4096         @ sp
+               .word   user_stack_end          @ sp
 LC1:           .word   reloc_end - reloc_start
                .size   LC0, . - LC0
 
 #ifdef CONFIG_ARCH_RPC
                .globl  params
-params:                ldr     r0, =params_phys
+params:                ldr     r0, =0x10000100         @ params_phys for RPC
                mov     pc, lr
                .ltorg
                .align
@@ -339,9 +345,8 @@ params:             ldr     r0, =params_phys
  *  r4 = kernel execution address
  *  r7 = architecture number
  *  r8 = atags pointer
- *  r9 = run-time address of "start"  (???)
  * On exit,
- *  r1, r2, r3, r9, r10, r12 corrupted
+ *  r0, r1, r2, r3, r9, r10, r12 corrupted
  * This routine must preserve:
  *  r4, r5, r6, r7, r8
  */
@@ -396,12 +401,18 @@ __armv3_mpu_cache_on:
 
                mov     r0, #0
                mcr     p15, 0, r0, c7, c0, 0   @ invalidate whole cache v3
+               /*
+                * ?? ARMv3 MMU does not allow reading the control register,
+                * does this really work on ARMv3 MPU?
+                */
                mrc     p15, 0, r0, c1, c0, 0   @ read control reg
                                                @ .... .... .... WC.M
                orr     r0, r0, #0x000d         @ .... .... .... 11.1
+               /* ?? this overwrites the value constructed above? */
                mov     r0, #0
                mcr     p15, 0, r0, c1, c0, 0   @ write control reg
 
+               /* ?? invalidate for the second time? */
                mcr     p15, 0, r0, c7, c0, 0   @ invalidate whole cache v3
                mov     pc, lr
 
@@ -771,8 +782,10 @@ proc_types:
  * Turn off the Cache and MMU.  ARMv3 does not support
  * reading the control register, but ARMv4 does.
  *
- * On exit, r0, r1, r2, r3, r9, r12 corrupted
- * This routine must preserve: r4, r6, r7
+ * On exit,
+ *  r0, r1, r2, r3, r9, r12 corrupted
+ * This routine must preserve:
+ *  r4, r6, r7
  */
                .align  5
 cache_off:     mov     r3, #12                 @ cache_off function
@@ -845,7 +858,7 @@ __armv3_mmu_cache_off:
  * Clean and flush the cache to maintain consistency.
  *
  * On exit,
- *  r1, r2, r3, r9, r11, r12 corrupted
+ *  r1, r2, r3, r9, r10, r11, r12 corrupted
  * This routine must preserve:
  *  r0, r4, r5, r6, r7
  */
@@ -988,7 +1001,7 @@ no_cache_id:
 __armv3_mmu_cache_flush:
 __armv3_mpu_cache_flush:
                mov     r1, #0
-               mcr     p15, 0, r0, c7, c0, 0   @ invalidate whole cache v3
+               mcr     p15, 0, r1, c7, c0, 0   @ invalidate whole cache v3
                mov     pc, lr
 
 /*
@@ -1001,6 +1014,7 @@ __armv3_mpu_cache_flush:
 phexbuf:       .space  12
                .size   phexbuf, . - phexbuf
 
+@ phex corrupts {r0, r1, r2, r3}
 phex:          adr     r3, phexbuf
                mov     r2, #0
                strb    r2, [r3, r1]
@@ -1015,6 +1029,7 @@ phex:             adr     r3, phexbuf
                strb    r2, [r3, r1]
                b       1b
 
+@ puts corrupts {r0, r1, r2, r3}
 puts:          loadsp  r3, r1
 1:             ldrb    r2, [r0], #1
                teq     r2, #0
@@ -1029,12 +1044,14 @@ puts:           loadsp  r3, r1
                teq     r0, #0
                bne     1b
                mov     pc, lr
+@ putc corrupts {r0, r1, r2, r3}
 putc:
                mov     r2, r0
                mov     r0, #0
                loadsp  r3, r1
                b       2b
 
+@ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
 memdump:       mov     r12, r0
                mov     r10, lr
                mov     r11, #0
@@ -1070,3 +1087,4 @@ reloc_end:
                .align
                .section ".stack", "w"
 user_stack:    .space  4096
+user_stack_end:

diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index d2b2ef41cd4ff7ac32bf91e4e947cc57993cbb2d..e653a6d3c8d90dae62ee3da745bfce67c34d27fb 100644 (file)
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -28,9 +28,6 @@ unsigned int __machine_arch_type;
 
 #include <asm/unaligned.h>
 
-#ifdef STANDALONE_DEBUG
-#define putstr printf
-#else
 
 static void putstr(const char *ptr);
 extern void error(char *x);
@@ -116,7 +113,6 @@ static void putstr(const char *ptr)
        flush();
 }
 
-#endif
 
 void *memcpy(void *__dest, __const void *__src, size_t __n)
 {
@@ -186,7 +182,6 @@ asmlinkage void __div0(void)
 
 extern void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x));
 
-#ifndef STANDALONE_DEBUG
 
 unsigned long
 decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
@@ -211,18 +206,3 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
        putstr(" done, booting the kernel.\n");
        return output_ptr;
 }
-#else
-
-char output_buffer[1500*1024];
-
-int main()
-{
-       output_data = output_buffer;
-
-       putstr("Uncompressing Linux...");
-       decompress(input_data, input_data_end - input_data,
-                       NULL, NULL, output_data, NULL, error);
-       putstr("done.\n");
-       return 0;
-}
-#endif

diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 337741f734ac08d7f438e5d6240293adf3c5c366..7dfa9a85bc0c875b11567025f68e92bd768d7419 100644 (file)
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -108,6 +108,51 @@ static void gic_unmask_irq(unsigned int irq)
        spin_unlock(&irq_controller_lock);
 }
 
+static int gic_set_type(unsigned int irq, unsigned int type)
+{
+       void __iomem *base = gic_dist_base(irq);
+       unsigned int gicirq = gic_irq(irq);
+       u32 enablemask = 1 << (gicirq % 32);
+       u32 enableoff = (gicirq / 32) * 4;
+       u32 confmask = 0x2 << ((gicirq % 16) * 2);
+       u32 confoff = (gicirq / 16) * 4;
+       bool enabled = false;
+       u32 val;
+
+       /* Interrupt configuration for SGIs can't be changed */
+       if (gicirq < 16)
+               return -EINVAL;
+
+       if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
+               return -EINVAL;
+
+       spin_lock(&irq_controller_lock);
+
+       val = readl(base + GIC_DIST_CONFIG + confoff);
+       if (type == IRQ_TYPE_LEVEL_HIGH)
+               val &= ~confmask;
+       else if (type == IRQ_TYPE_EDGE_RISING)
+               val |= confmask;
+
+       /*
+        * As recommended by the spec, disable the interrupt before changing
+        * the configuration
+        */
+       if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
+               writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
+               enabled = true;
+       }
+
+       writel(val, base + GIC_DIST_CONFIG + confoff);
+
+       if (enabled)
+               writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
+
+       spin_unlock(&irq_controller_lock);
+
+       return 0;
+}
+
 #ifdef CONFIG_SMP
 static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val)
 {
@@ -161,6 +206,7 @@ static struct irq_chip gic_chip = {
        .ack            = gic_ack_irq,
        .mask           = gic_mask_irq,
        .unmask         = gic_unmask_irq,
+       .set_type       = gic_set_type,
 #ifdef CONFIG_SMP
        .set_affinity   = gic_set_cpu,
 #endif

diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
index 9eaf65f43642e6886b3ab4bae43e7821aad285b6..517d50ddbeb3153d102e426fc915405bae76012b 100644 (file)
--- a/arch/arm/common/sa1111.c
+++ b/arch/arm/common/sa1111.c
@@ -185,13 +185,10 @@ static struct sa1111_dev_info sa1111_devices[] = {
        },
 };
 
-void __init sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes)
+void __init sa1111_adjust_zones(unsigned long *size, unsigned long *holes)
 {
        unsigned int sz = SZ_1M >> PAGE_SHIFT;
 
-       if (node != 0)
-               sz = 0;
-
        size[1] = size[0] - sz;
        size[0] = sz;
 }

diff --git a/arch/arm/configs/am3517_evm_defconfig b/arch/arm/configs/am3517_evm_defconfig
deleted file mode 100644 (file)
index ad2bc50..0000000
--- a/arch/arm/configs/am3517_evm_defconfig
+++ /dev/null
@@ -1,127 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP3=y
-CONFIG_OMAP_RESET_CLOCKS=y
-# CONFIG_OMAP_MCBSP is not set
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_ARCH_OMAP3430=y
-CONFIG_MACH_OMAP3517EVM=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8"
-CONFIG_FPE_NWFPE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_BINFMT_MISC=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_CAN=y
-CONFIG_CAN_RAW=y
-CONFIG_CAN_BCM=y
-CONFIG_CAN_VCAN=y
-CONFIG_CAN_DEV=y
-CONFIG_CAN_CALC_BITTIMING=y
-CONFIG_CAN_TI_HECC=y
-CONFIG_CAN_DEBUG_DEVICES=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-# CONFIG_MISC_DEVICES is not set
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_TI_DAVINCI_EMAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=32
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_OMAP=y
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_OMAP2_DSS=y
-CONFIG_OMAP2_VRAM_SIZE=4
-CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4
-CONFIG_FB_OMAP2=y
-CONFIG_PANEL_GENERIC=y
-CONFIG_PANEL_SHARP_LQ043T1DG01=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QFMT_V2=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_LL=y
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=y
-CONFIG_LIBCRC32C=y

diff --git a/arch/arm/configs/cm_t35_defconfig b/arch/arm/configs/cm_t35_defconfig
deleted file mode 100644 (file)
index 8bb0633..0000000
--- a/arch/arm/configs/cm_t35_defconfig
+++ /dev/null
@@ -1,157 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP3=y
-CONFIG_OMAP_RESET_CLOCKS=y
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_ARCH_OMAP3430=y
-CONFIG_MACH_CM_T35=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_FPE_NWFPE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_BINFMT_MISC=y
-CONFIG_PM=y
-CONFIG_PM_RUNTIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_LIB80211=m
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_FW_LOADER=m
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_OMAP2=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMSC911X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_KEYBOARD_TWL4030=m
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=m
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=32
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_OMAP=y
-CONFIG_SPI=y
-CONFIG_SPI_OMAP24XX=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_TWL4030=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_OMAP_WATCHDOG=y
-CONFIG_TWL4030_CORE=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TWL4030=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_SUSPEND=y
-# CONFIG_USB_OTG_WHITELIST is not set
-CONFIG_USB_MON=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_OTG=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_TEST=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
-CONFIG_TWL4030_USB=y
-CONFIG_MMC=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_TWL4030=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QFMT_V2=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_NTFS_FS=m
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_UTF8=m
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_LL=y
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=y
-CONFIG_LIBCRC32C=y

diff --git a/arch/arm/configs/devkit8000_defconfig b/arch/arm/configs/devkit8000_defconfig
deleted file mode 100644 (file)
index 786cbe4..0000000
--- a/arch/arm/configs/devkit8000_defconfig
+++ /dev/null
@@ -1,184 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_LZMA=y
-CONFIG_EMBEDDED=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP3=y
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_ARCH_OMAP3430=y
-CONFIG_MACH_DEVKIT8000=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyS2,115200n8 root=/dev/nfs nfsroot=192.168.1.1:home/nfsroot/current,home/nfsroot/current ip=dhcp rw noinitrd root  delay=3"
-CONFIG_FPE_NWFPE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=y
-CONFIG_BT=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_OMAP2=y
-CONFIG_MTD_UBI=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=40960
-# CONFIG_MISC_DEVICES is not set
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_DM9000=y
-CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_KEYBOARD_MATRIX=y
-CONFIG_KEYBOARD_TWL4030=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-CONFIG_SERIO_RAW=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=32
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_RAW_DRIVER=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_OMAP=y
-CONFIG_SPI=y
-CONFIG_SPI_OMAP24XX=y
-CONFIG_GPIO_TWL4030=y
-# CONFIG_HWMON is not set
-CONFIG_TWL4030_CORE=y
-CONFIG_TWL4030_POWER=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TWL4030=y
-CONFIG_FB=y
-CONFIG_FB_FOREIGN_ENDIAN=y
-CONFIG_FB_OMAP_BOOTLOADER_INIT=y
-CONFIG_OMAP2_DSS=y
-CONFIG_FB_OMAP2=y
-CONFIG_PANEL_GENERIC=y
-CONFIG_DISPLAY_SUPPORT=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_SOC=y
-CONFIG_SND_OMAP_SOC=y
-CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE=y
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-# CONFIG_USB_DEVICE_CLASS is not set
-# CONFIG_USB_OTG_WHITELIST is not set
-CONFIG_USB_MON=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_OTG=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_USB_MUSB_DEBUG=y
-CONFIG_USB_STORAGE=m
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DEBUG=y
-CONFIG_USB_ETH=m
-# CONFIG_USB_ETH_RNDIS is not set
-CONFIG_TWL4030_USB=y
-CONFIG_MMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_PLTFM=m
-CONFIG_MMC_OMAP_HS=y
-CONFIG_MMC_SPI=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_TWL4030=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QFMT_V2=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_UBIFS_FS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_T10DIF=m
-CONFIG_LIBCRC32C=y

diff --git a/arch/arm/configs/igep0020_defconfig b/arch/arm/configs/igep0020_defconfig
deleted file mode 100644 (file)
index fcda057..0000000
--- a/arch/arm/configs/igep0020_defconfig
+++ /dev/null
@@ -1,179 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP3=y
-CONFIG_OMAP_RESET_CLOCKS=y
-# CONFIG_OMAP_MUX is not set
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_ARCH_OMAP3430=y
-CONFIG_MACH_IGEP0020=y
-CONFIG_ARM_THUMBEE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_BINFMT_MISC=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_BT=m
-CONFIG_BT_L2CAP=m
-CONFIG_BT_SCO=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=m
-CONFIG_BT_HCIUART=m
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_BCSP=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIVHCI=m
-CONFIG_BT_MRVL=m
-CONFIG_BT_MRVL_SDIO=m
-CONFIG_CFG80211=y
-CONFIG_MAC80211=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_STANDALONE is not set
-CONFIG_CONNECTOR=y
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_ONENAND=y
-CONFIG_MTD_ONENAND_OMAP2=y
-CONFIG_MTD_ONENAND_2X_PROGRAM=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-# CONFIG_MISC_DEVICES is not set
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMSC911X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_LIBERTAS=y
-CONFIG_LIBERTAS_SDIO=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=32
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_OMAP=y
-CONFIG_SPI=y
-CONFIG_SPI_OMAP24XX=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_TWL4030=y
-CONFIG_POWER_SUPPLY=y
-# CONFIG_HWMON is not set
-CONFIG_SSB=m
-CONFIG_TWL4030_CORE=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TWL4030=y
-CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_OMAP2_DSS=y
-CONFIG_OMAP2_VRAM_SIZE=14
-# CONFIG_OMAP2_DSS_DEBUG_SUPPORT is not set
-# CONFIG_OMAP2_DSS_VENC is not set
-CONFIG_OMAP2_DSS_DSI=y
-CONFIG_OMAP2_DSS_USE_DSI_PLL=y
-CONFIG_FB_OMAP2=y
-# CONFIG_FB_OMAP2_DEBUG_SUPPORT is not set
-CONFIG_PANEL_GENERIC=y
-CONFIG_DISPLAY_SUPPORT=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_OMAP_SOC=y
-CONFIG_SND_OMAP_SOC_IGEP0020=y
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_MMC=y
-CONFIG_MMC_DEBUG=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QFMT_V2=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_LL=y
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=y
-CONFIG_CRC_T10DIF=y
-CONFIG_CRC_ITU_T=m
-CONFIG_LIBCRC32C=y

diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index f2e3a9088df6d43880779071e30dff09f695f37d..ccc9c9959b82baf75d0faa04769a85e79ac23d51 100644 (file)
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -13,11 +13,19 @@ CONFIG_MACH_RD88F6192_NAS=y
 CONFIG_MACH_RD88F6281=y
 CONFIG_MACH_MV88F6281GTW_GE=y
 CONFIG_MACH_SHEEVAPLUG=y
+CONFIG_MACH_ESATA_SHEEVAPLUG=y
+CONFIG_MACH_GURUPLUG=y
 CONFIG_MACH_TS219=y
 CONFIG_MACH_TS41X=y
 CONFIG_MACH_OPENRD_BASE=y
 CONFIG_MACH_OPENRD_CLIENT=y
+CONFIG_MACH_OPENRD_ULTIMATE=y
 CONFIG_MACH_NETSPACE_V2=y
+CONFIG_MACH_INETSPACE_V2=y
+CONFIG_MACH_NETSPACE_MAX_V2=y
+CONFIG_MACH_NET2BIG_V2=y
+CONFIG_MACH_NET5BIG_V2=y
+CONFIG_MACH_T5325=y
 # CONFIG_CPU_FEROCEON_OLD_ID is not set
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y

diff --git a/arch/arm/configs/lusl7200_defconfig b/arch/arm/configs/lusl7200_defconfig
deleted file mode 100644 (file)
index 816fc42..0000000
--- a/arch/arm/configs/lusl7200_defconfig
+++ /dev/null
@@ -1,23 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_HOTPLUG is not set
-CONFIG_MODULES=y
-CONFIG_ARCH_L7200=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_ZBOOT_ROM_TEXT=0x00010000
-CONFIG_ZBOOT_ROM_BSS=0xf03e0000
-CONFIG_ZBOOT_ROM=y
-CONFIG_CMDLINE="console=tty0 console=ttyLU1,115200 root=/dev/ram initrd=0xf1000000,0x005dac7b mem=32M"
-CONFIG_BINFMT_AOUT=y
-CONFIG_BLK_DEV_RAM=y
-# CONFIG_INPUT is not set
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_NONSTANDARD=y
-CONFIG_EXT2_FS=y
-CONFIG_DEBUG_USER=y
-# CONFIG_CRC32 is not set

diff --git a/arch/arm/configs/omap3_beagle_defconfig b/arch/arm/configs/omap3_beagle_defconfig
deleted file mode 100644 (file)
index aa24172..0000000
--- a/arch/arm/configs/omap3_beagle_defconfig
+++ /dev/null
@@ -1,134 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP3=y
-# CONFIG_OMAP_MUX is not set
-# CONFIG_OMAP_MCBSP is not set
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_ARCH_OMAP3430=y
-CONFIG_MACH_OMAP3_BEAGLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8"
-CONFIG_FPE_NWFPE=y
-CONFIG_VFP=y
-CONFIG_BINFMT_MISC=y
-CONFIG_PM=y
-CONFIG_PM_RUNTIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-# CONFIG_MISC_DEVICES is not set
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=32
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_OMAP=y
-CONFIG_GPIO_TWL4030=y
-# CONFIG_HWMON is not set
-CONFIG_TWL4030_CORE=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TWL4030=y
-CONFIG_FB=y
-CONFIG_FB_OMAP=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_SUSPEND=y
-# CONFIG_USB_OTG_WHITELIST is not set
-CONFIG_USB_MON=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_OTG=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
-CONFIG_TWL4030_USB=y
-CONFIG_MMC=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_RTC_CLASS=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QFMT_V2=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRC_CCITT=y
-CONFIG_LIBCRC32C=y

diff --git a/arch/arm/configs/omap3_evm_defconfig b/arch/arm/configs/omap3_evm_defconfig
deleted file mode 100644 (file)
index 3b072e8..0000000
--- a/arch/arm/configs/omap3_evm_defconfig
+++ /dev/null
@@ -1,160 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP3=y
-CONFIG_OMAP_RESET_CLOCKS=y
-# CONFIG_OMAP_MCBSP is not set
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_ARCH_OMAP3430=y
-CONFIG_MACH_OMAP3EVM=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8"
-CONFIG_FPE_NWFPE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_BINFMT_MISC=y
-CONFIG_PM=y
-CONFIG_PM_DEBUG=y
-CONFIG_PM_RUNTIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_ONENAND=y
-CONFIG_MTD_ONENAND_VERIFY_WRITE=y
-CONFIG_MTD_ONENAND_OMAP2=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-# CONFIG_MISC_DEVICES is not set
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMSC911X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_TWL4030=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=32
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_OMAP=y
-CONFIG_SPI=y
-CONFIG_SPI_OMAP24XX=y
-CONFIG_GPIO_TWL4030=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_OMAP_WATCHDOG=y
-CONFIG_TWL4030_CORE=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TWL4030=y
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-CONFIG_FB=y
-CONFIG_OMAP2_DSS=y
-CONFIG_OMAP2_VRAM_SIZE=4
-# CONFIG_OMAP2_DSS_DEBUG_SUPPORT is not set
-CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4
-CONFIG_FB_OMAP2=y
-# CONFIG_FB_OMAP2_DEBUG_SUPPORT is not set
-CONFIG_PANEL_GENERIC=y
-CONFIG_PANEL_SHARP_LS037V7DW01=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_SUSPEND=y
-# CONFIG_USB_OTG_WHITELIST is not set
-CONFIG_USB_MON=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_OTG=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_TEST=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ZERO=m
-CONFIG_MMC=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QFMT_V2=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_LL=y
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=y
-CONFIG_LIBCRC32C=y

diff --git a/arch/arm/configs/omap3_pandora_defconfig b/arch/arm/configs/omap3_pandora_defconfig
deleted file mode 100644 (file)
index d5a6226..0000000
--- a/arch/arm/configs/omap3_pandora_defconfig
+++ /dev/null
@@ -1,158 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP3=y
-# CONFIG_OMAP_MUX is not set
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_ARCH_OMAP3430=y
-CONFIG_MACH_OMAP3_PANDORA=y
-CONFIG_ARM_THUMBEE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE=" debug "
-CONFIG_FPE_NWFPE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_BINFMT_MISC=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_OMAP2=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=800
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
-CONFIG_INPUT_JOYDEV=y
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-CONFIG_KEYBOARD_TWL4030=y
-# CONFIG_MOUSE_PS2 is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_TWL4030_PWRBUTTON=y
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=32
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_OMAP=y
-CONFIG_SPI=y
-CONFIG_SPI_OMAP24XX=y
-CONFIG_GPIO_TWL4030=y
-# CONFIG_HWMON is not set
-CONFIG_TWL4030_CORE=y
-CONFIG_TWL4030_POWER=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_DEBUG=y
-CONFIG_REGULATOR_TWL4030=y
-CONFIG_VIDEO_OUTPUT_CONTROL=y
-CONFIG_FB=y
-CONFIG_OMAP2_DSS=y
-CONFIG_FB_OMAP2=y
-CONFIG_PANEL_TPO_TD043MTEA1=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_VERBOSE_PRINTK=y
-CONFIG_SND_SOC=y
-CONFIG_SND_OMAP_SOC=y
-CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=y
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_PERIPHERAL=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
-CONFIG_TWL4030_USB=y
-CONFIG_MMC=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_TWL4030=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_QUOTA=y
-CONFIG_QFMT_V2=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_CIFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_CRYPTO_CRC32C=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
-CONFIG_CRC_CCITT=y

diff --git a/arch/arm/configs/omap3_stalker_lks_defconfig b/arch/arm/configs/omap3_stalker_lks_defconfig
deleted file mode 100644 (file)
index 1d1ab0b..0000000
--- a/arch/arm/configs/omap3_stalker_lks_defconfig
+++ /dev/null
@@ -1,150 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP3=y
-CONFIG_OMAP_RESET_CLOCKS=y
-# CONFIG_OMAP_MCBSP is not set
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_ARCH_OMAP3430=y
-CONFIG_MACH_SBC3530=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8"
-CONFIG_FPE_NWFPE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_BINFMT_MISC=y
-CONFIG_PM=y
-CONFIG_PM_DEBUG=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_ONENAND=y
-CONFIG_MTD_ONENAND_VERIFY_WRITE=y
-CONFIG_MTD_ONENAND_OMAP2=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-# CONFIG_MISC_DEVICES is not set
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMSC911X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_TWL4030=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=32
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_OMAP=y
-CONFIG_SPI=y
-CONFIG_SPI_OMAP24XX=y
-CONFIG_GPIO_TWL4030=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_OMAP_WATCHDOG=y
-CONFIG_TWL4030_CORE=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TWL4030=y
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-# CONFIG_USB_OTG_WHITELIST is not set
-CONFIG_USB_MON=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_OTG=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_TEST=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ZERO=m
-CONFIG_TWL4030_USB=y
-CONFIG_MMC=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QFMT_V2=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_LL=y
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=y
-CONFIG_LIBCRC32C=y

diff --git a/arch/arm/configs/omap3_touchbook_defconfig b/arch/arm/configs/omap3_touchbook_defconfig
deleted file mode 100644 (file)
index e988ecc..0000000
--- a/arch/arm/configs/omap3_touchbook_defconfig
+++ /dev/null
@@ -1,621 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_TASKSTATS=y
-CONFIG_TASK_DELAY_ACCT=y
-CONFIG_TASK_XACCT=y
-CONFIG_TASK_IO_ACCOUNTING=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=15
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_COMPAT_BRK is not set
-CONFIG_SLAB=y
-CONFIG_PROFILING=y
-CONFIG_OPROFILE=y
-CONFIG_MODULES=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP3=y
-CONFIG_OMAP_RESET_CLOCKS=y
-# CONFIG_OMAP_MUX is not set
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_ARCH_OMAP3430=y
-CONFIG_MACH_OMAP3_TOUCHBOOK=y
-CONFIG_ARM_THUMBEE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_LEDS=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE=" debug "
-CONFIG_KEXEC=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_BINFMT_AOUT=m
-CONFIG_BINFMT_MISC=y
-CONFIG_PM=y
-CONFIG_PM_DEBUG=y
-CONFIG_PM_RUNTIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_NET_IPIP=m
-CONFIG_NET_IPGRE=m
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_IPCOMP=m
-CONFIG_INET_DIAG=m
-CONFIG_TCP_CONG_ADVANCED=y
-CONFIG_TCP_CONG_HSTCP=m
-CONFIG_TCP_CONG_HYBLA=m
-CONFIG_TCP_CONG_SCALABLE=m
-CONFIG_TCP_CONG_LP=m
-CONFIG_TCP_CONG_VENO=m
-CONFIG_TCP_CONG_YEAH=m
-CONFIG_TCP_CONG_ILLINOIS=m
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_MIP6=m
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
-CONFIG_IPV6_TUNNEL=m
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_IPV6_SUBTREES=y
-CONFIG_IPV6_MROUTE=y
-CONFIG_NETFILTER=y
-CONFIG_NETFILTER_NETLINK_QUEUE=m
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_UDPLITE=m
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-CONFIG_NF_CONNTRACK_NETBIOS_NS=m
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SANE=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_OWNER=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_RATEEST=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_RECENT=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_TIME=m
-CONFIG_NETFILTER_XT_MATCH_U32=m
-CONFIG_IP_VS=m
-CONFIG_IP_VS_IPV6=y
-CONFIG_IP_VS_DEBUG=y
-CONFIG_IP_VS_PROTO_TCP=y
-CONFIG_IP_VS_PROTO_UDP=y
-CONFIG_IP_VS_PROTO_ESP=y
-CONFIG_IP_VS_PROTO_AH=y
-CONFIG_IP_VS_RR=m
-CONFIG_IP_VS_WRR=m
-CONFIG_IP_VS_LC=m
-CONFIG_IP_VS_WLC=m
-CONFIG_IP_VS_LBLC=m
-CONFIG_IP_VS_LBLCR=m
-CONFIG_IP_VS_DH=m
-CONFIG_IP_VS_SH=m
-CONFIG_IP_VS_SED=m
-CONFIG_IP_VS_NQ=m
-CONFIG_IP_VS_FTP=m
-CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_QUEUE=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_AH=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_NF_NAT=m
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_NF_NAT_SNMP_BASIC=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_TTL=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-CONFIG_NF_CONNTRACK_IPV6=m
-CONFIG_IP6_NF_QUEUE=m
-CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_AH=m
-CONFIG_IP6_NF_MATCH_EUI64=m
-CONFIG_IP6_NF_MATCH_FRAG=m
-CONFIG_IP6_NF_MATCH_OPTS=m
-CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_MH=m
-CONFIG_IP6_NF_MATCH_RT=m
-CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_TARGET_LOG=m
-CONFIG_IP6_NF_FILTER=m
-CONFIG_IP6_NF_TARGET_REJECT=m
-CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_RAW=m
-CONFIG_IP_DCCP=m
-CONFIG_IP_SCTP=m
-CONFIG_TIPC=m
-CONFIG_ATM=m
-CONFIG_ATM_CLIP=m
-CONFIG_ATM_LANE=m
-CONFIG_ATM_MPOA=m
-CONFIG_ATM_BR2684=m
-CONFIG_BRIDGE=m
-CONFIG_VLAN_8021Q=m
-CONFIG_VLAN_8021Q_GVRP=y
-CONFIG_WAN_ROUTER=m
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_CBQ=m
-CONFIG_NET_SCH_HTB=m
-CONFIG_NET_SCH_HFSC=m
-CONFIG_NET_SCH_ATM=m
-CONFIG_NET_SCH_PRIO=m
-CONFIG_NET_SCH_MULTIQ=m
-CONFIG_NET_SCH_RED=m
-CONFIG_NET_SCH_SFQ=m
-CONFIG_NET_SCH_TEQL=m
-CONFIG_NET_SCH_TBF=m
-CONFIG_NET_SCH_GRED=m
-CONFIG_NET_SCH_DSMARK=m
-CONFIG_NET_SCH_NETEM=m
-CONFIG_NET_SCH_DRR=m
-CONFIG_NET_CLS_BASIC=m
-CONFIG_NET_CLS_TCINDEX=m
-CONFIG_NET_CLS_ROUTE4=m
-CONFIG_NET_CLS_FW=m
-CONFIG_NET_CLS_U32=m
-CONFIG_CLS_U32_PERF=y
-CONFIG_CLS_U32_MARK=y
-CONFIG_NET_CLS_RSVP=m
-CONFIG_NET_CLS_RSVP6=m
-CONFIG_NET_CLS_FLOW=m
-CONFIG_NET_CLS_IND=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIBTUSB=y
-CONFIG_BT_HCIBTSDIO=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_BCSP=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM203X=y
-CONFIG_BT_HCIBPA10X=y
-CONFIG_BT_HCIBFUSB=y
-CONFIG_AF_RXRPC=m
-CONFIG_CFG80211=m
-CONFIG_LIB80211=y
-CONFIG_MAC80211=m
-CONFIG_MAC80211_RC_PID=y
-# CONFIG_MAC80211_RC_MINSTREL is not set
-CONFIG_WIMAX=m
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_OMAP2=y
-CONFIG_MTD_NAND_PLATFORM=y
-CONFIG_MTD_UBI=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_EEPROM_93CX6=y
-CONFIG_RAID_ATTRS=m
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=y
-CONFIG_BLK_DEV_SR_VENDOR=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_CHR_DEV_SCH=m
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_ISCSI_TCP=m
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID10=m
-CONFIG_MD_RAID456=m
-CONFIG_MD_MULTIPATH=m
-CONFIG_MD_FAULTY=m
-CONFIG_BLK_DEV_DM=m
-CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
-CONFIG_DM_MIRROR=m
-CONFIG_DM_ZERO=m
-CONFIG_DM_MULTIPATH=m
-CONFIG_DM_DELAY=m
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-CONFIG_BONDING=m
-CONFIG_MACVLAN=m
-CONFIG_EQUALIZER=m
-CONFIG_TUN=m
-CONFIG_VETH=m
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_ATM_DRIVERS is not set
-CONFIG_PPP=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_MPPE=m
-CONFIG_PPPOE=m
-CONFIG_NETCONSOLE=m
-CONFIG_NETCONSOLE_DYNAMIC=y
-CONFIG_NETPOLL_TRAP=y
-CONFIG_INPUT_FF_MEMLESS=y
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_TWL4030_PWRBUTTON=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=32
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_OMAP=y
-CONFIG_SPI=y
-CONFIG_SPI_OMAP24XX=y
-CONFIG_SPI_SPIDEV=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_TWL4030=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_BQ27x00=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_OMAP_WATCHDOG=y
-CONFIG_TWL4030_CORE=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TWL4030=y
-CONFIG_FB=y
-CONFIG_DISPLAY_SUPPORT=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_LOGO=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_SEQUENCER=m
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_SEQUENCER_OSS=y
-CONFIG_SND_HRTIMER=m
-# CONFIG_SND_ARM is not set
-CONFIG_SND_USB_AUDIO=y
-CONFIG_SND_USB_CAIAQ=m
-CONFIG_SND_USB_CAIAQ_INPUT=y
-CONFIG_SND_SOC=y
-CONFIG_SND_OMAP_SOC=y
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_SUSPEND=y
-# CONFIG_USB_OTG_WHITELIST is not set
-CONFIG_USB_MON=y
-CONFIG_USB_OXU210HP_HCD=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_OTG=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_WDM=m
-CONFIG_USB_TMC=m
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_AIRCABLE=m
-CONFIG_USB_SERIAL_ARK3116=m
-CONFIG_USB_SERIAL_BELKIN=m
-CONFIG_USB_SERIAL_CH341=m
-CONFIG_USB_SERIAL_WHITEHEAT=m
-CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-CONFIG_USB_SERIAL_CYPRESS_M8=m
-CONFIG_USB_SERIAL_EMPEG=m
-CONFIG_USB_SERIAL_FTDI_SIO=m
-CONFIG_USB_SERIAL_FUNSOFT=m
-CONFIG_USB_SERIAL_VISOR=m
-CONFIG_USB_SERIAL_IPAQ=m
-CONFIG_USB_SERIAL_IR=m
-CONFIG_USB_SERIAL_EDGEPORT=m
-CONFIG_USB_SERIAL_EDGEPORT_TI=m
-CONFIG_USB_SERIAL_GARMIN=m
-CONFIG_USB_SERIAL_IPW=m
-CONFIG_USB_SERIAL_IUU=m
-CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-CONFIG_USB_SERIAL_KEYSPAN=m
-CONFIG_USB_SERIAL_KEYSPAN_MPR=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19=y
-CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
-CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
-CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
-CONFIG_USB_SERIAL_KLSI=m
-CONFIG_USB_SERIAL_KOBIL_SCT=m
-CONFIG_USB_SERIAL_MCT_U232=m
-CONFIG_USB_SERIAL_MOS7720=m
-CONFIG_USB_SERIAL_MOS7840=m
-CONFIG_USB_SERIAL_MOTOROLA=m
-CONFIG_USB_SERIAL_NAVMAN=m
-CONFIG_USB_SERIAL_PL2303=m
-CONFIG_USB_SERIAL_OTI6858=m
-CONFIG_USB_SERIAL_SPCP8X5=m
-CONFIG_USB_SERIAL_HP4X=m
-CONFIG_USB_SERIAL_SAFE=m
-CONFIG_USB_SERIAL_SIEMENS_MPI=m
-CONFIG_USB_SERIAL_SIERRAWIRELESS=m
-CONFIG_USB_SERIAL_TI=m
-CONFIG_USB_SERIAL_CYBERJACK=m
-CONFIG_USB_SERIAL_XIRCOM=m
-CONFIG_USB_SERIAL_OPTION=m
-CONFIG_USB_SERIAL_OMNINET=m
-CONFIG_USB_SERIAL_OPTICON=m
-CONFIG_USB_SERIAL_DEBUG=m
-CONFIG_USB_EMI62=m
-CONFIG_USB_EMI26=m
-CONFIG_USB_SISUSBVGA=m
-CONFIG_USB_SISUSBVGA_CON=y
-CONFIG_USB_TEST=m
-CONFIG_USB_GADGET=m
-CONFIG_USB_GADGET_DEBUG_FS=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_ZERO_HNPTEST=y
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_MIDI_GADGET=m
-CONFIG_USB_G_PRINTER=m
-CONFIG_USB_CDC_COMPOSITE=m
-CONFIG_USB_GPIO_VBUS=y
-CONFIG_TWL4030_USB=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_SDIO_UART=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_MMC_SPI=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=m
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_BACKLIGHT=m
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_TWL4030=y
-CONFIG_UIO=m
-CONFIG_UIO_PDRV=m
-CONFIG_UIO_PDRV_GENIRQ=m
-CONFIG_STAGING=y
-# CONFIG_STAGING_EXCLUDE_BUILD is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=m
-CONFIG_REISERFS_FS=m
-CONFIG_REISERFS_PROC_INFO=y
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_JFS_FS=m
-CONFIG_XFS_FS=m
-CONFIG_INOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QFMT_V2=y
-CONFIG_AUTOFS4_FS=m
-CONFIG_FUSE_FS=y
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_NTFS_FS=m
-CONFIG_NTFS_RW=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_FS_XATTR=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_RUBIN=y
-CONFIG_JFFS2_CMODE_FAVOURLZO=y
-CONFIG_UBIFS_FS=y
-CONFIG_UBIFS_FS_XATTR=y
-CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-CONFIG_SQUASHFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V3_ACL=y
-CONFIG_NFSD_V4=y
-CONFIG_CIFS=m
-CONFIG_CIFS_STATS=y
-CONFIG_CIFS_STATS2=y
-CONFIG_CIFS_EXPERIMENTAL=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_MINIX_SUBPARTITION=y
-CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_UNIXWARE_DISKLABEL=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_NLS_UTF8=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-CONFIG_TIMER_STATS=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_CRYPTO_FIPS=y
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_CRYPTD=m
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_CCM=m
-CONFIG_CRYPTO_GCM=m
-CONFIG_CRYPTO_CTS=m
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_XTS=m
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MICHAEL_MIC=y
-CONFIG_CRYPTO_RMD128=m
-CONFIG_CRYPTO_RMD160=m
-CONFIG_CRYPTO_RMD256=m
-CONFIG_CRYPTO_RMD320=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_AES=y
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_ARC4=y
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_CAMELLIA=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_SALSA20=m
-CONFIG_CRYPTO_SEED=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRC_CCITT=y
-CONFIG_CRC_T10DIF=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
-CONFIG_LIBCRC32C=y

diff --git a/arch/arm/configs/omap_2430sdp_defconfig b/arch/arm/configs/omap_2430sdp_defconfig
deleted file mode 100644 (file)
index 0cf4147..0000000
--- a/arch/arm/configs/omap_2430sdp_defconfig
+++ /dev/null
@@ -1,136 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP2=y
-# CONFIG_OMAP_MUX_WARNINGS is not set
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_ARCH_OMAP2430=y
-CONFIG_MACH_OMAP_2430SDP=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/ram0 rw console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
-CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_MISC=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IPV6 is not set
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_ONENAND=y
-CONFIG_MTD_ONENAND_VERIFY_WRITE=y
-CONFIG_MTD_ONENAND_OMAP2=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_SCSI=m
-CONFIG_BLK_DEV_SD=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_TWL4030=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=32
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_OMAP=y
-CONFIG_SPI=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_OMAP_WATCHDOG=y
-CONFIG_TWL4030_CORE=y
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_OMAP=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_USB=m
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_MON=m
-CONFIG_USB_MUSB_HDRC=m
-CONFIG_USB_MUSB_OTG=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_USB_STORAGE=m
-CONFIG_USB_GADGET=m
-CONFIG_USB_GADGET_DEBUG_FILES=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_MMC=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QFMT_V2=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_TIMER_STATS=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRC_CCITT=y
-CONFIG_LIBCRC32C=y

diff --git a/arch/arm/configs/omap_3430sdp_defconfig b/arch/arm/configs/omap_3430sdp_defconfig
deleted file mode 100644 (file)
index 5dbe595..0000000
--- a/arch/arm/configs/omap_3430sdp_defconfig
+++ /dev/null
@@ -1,178 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP3=y
-CONFIG_OMAP_RESET_CLOCKS=y
-CONFIG_OMAP_MUX_DEBUG=y
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_ARCH_OMAP3430=y
-CONFIG_MACH_OMAP_3430SDP=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyS2,115200 root=/dev/mmcblk0p3 rootwait debug"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_STAT_DETAILS=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_FPE_NWFPE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_BINFMT_MISC=y
-CONFIG_PM=y
-CONFIG_PM_RUNTIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_NAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=32
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_OMAP=y
-CONFIG_SPI=y
-CONFIG_SPI_OMAP24XX=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_TWL4030=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_OMAP_WATCHDOG=y
-CONFIG_TWL4030_WATCHDOG=y
-CONFIG_TWL4030_CORE=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TWL4030=y
-CONFIG_FB=y
-CONFIG_OMAP2_DSS=y
-CONFIG_OMAP2_VRAM_SIZE=4
-CONFIG_FB_OMAP2=y
-CONFIG_PANEL_GENERIC=y
-CONFIG_PANEL_SHARP_LS037V7DW01=y
-CONFIG_DISPLAY_SUPPORT=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_SUSPEND=y
-# CONFIG_USB_OTG_WHITELIST is not set
-CONFIG_USB_MON=y
-CONFIG_USB_EHCI_HCD=m
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_OTG=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_TEST=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_CDC_COMPOSITE=m
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_SDIO_UART=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_TWL4030=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QFMT_V2=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_FTRACE is not set
-# CONFIG_ARM_UNWIND is not set
-CONFIG_DEBUG_LL=y
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=y
-CONFIG_LIBCRC32C=y

diff --git a/arch/arm/configs/omap_3630sdp_defconfig b/arch/arm/configs/omap_3630sdp_defconfig
deleted file mode 100644 (file)
index 8e8f4e9..0000000
--- a/arch/arm/configs/omap_3630sdp_defconfig
+++ /dev/null
@@ -1,154 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP3=y
-CONFIG_OMAP_MUX_DEBUG=y
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_ARCH_OMAP3430=y
-CONFIG_MACH_OMAP_3630SDP=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8"
-CONFIG_FPE_NWFPE=y
-CONFIG_VFP=y
-CONFIG_BINFMT_MISC=y
-CONFIG_PM=y
-CONFIG_PM_DEBUG=y
-CONFIG_PM_VERBOSE=y
-CONFIG_PM_RUNTIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_CONNECTOR=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-CONFIG_SMSC_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=32
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_OMAP=y
-CONFIG_SPI=y
-CONFIG_SPI_OMAP24XX=y
-CONFIG_GPIO_TWL4030=y
-CONFIG_W1=y
-CONFIG_POWER_SUPPLY=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_TWL4030_CORE=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TWL4030=y
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_SUSPEND=y
-# CONFIG_USB_OTG_WHITELIST is not set
-CONFIG_USB_MON=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_OTG=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_USB_MUSB_DEBUG=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_TEST=m
-CONFIG_USB_GADGET=m
-CONFIG_USB_GADGET_DEBUG=y
-CONFIG_USB_GADGET_DEBUG_FILES=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_AUDIO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_CDC_COMPOSITE=m
-CONFIG_TWL4030_USB=y
-CONFIG_MMC=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_RTC_CLASS=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QFMT_V2=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_LL=y
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=y
-CONFIG_CRC_T10DIF=y
-CONFIG_LIBCRC32C=y

diff --git a/arch/arm/configs/omap_apollon_2420_defconfig b/arch/arm/configs/omap_apollon_2420_defconfig
deleted file mode 100644 (file)
index 0b24858..0000000
--- a/arch/arm/configs/omap_apollon_2420_defconfig
+++ /dev/null
@@ -1,92 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP2=y
-# CONFIG_OMAP_MCBSP is not set
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_ARCH_OMAP2420=y
-CONFIG_MACH_OMAP_APOLLON=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_PREEMPT=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
-CONFIG_VFP=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_ONENAND=y
-CONFIG_MTD_ONENAND_GENERIC=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=32
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_SPI=y
-CONFIG_SPI_OMAP24XX=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_OMAP_WATCHDOG=y
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_OMAP=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_HID is not set
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
-CONFIG_USB_FILE_STORAGE=m
-CONFIG_MMC=y
-CONFIG_MMC_OMAP=y
-CONFIG_EXT2_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_MUTEXES=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
-CONFIG_CRC_CCITT=y
-CONFIG_LIBCRC32C=y

diff --git a/arch/arm/configs/omap_h4_2420_defconfig b/arch/arm/configs/omap_h4_2420_defconfig
deleted file mode 100644 (file)
index 858f93a..0000000
--- a/arch/arm/configs/omap_h4_2420_defconfig
+++ /dev/null
@@ -1,107 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP2=y
-CONFIG_OMAP_MUX_DEBUG=y
-CONFIG_ARCH_OMAP2420=y
-CONFIG_MACH_OMAP_H4=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/ram0 rw console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
-CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_MISC=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=y
-CONFIG_IRLAN=y
-CONFIG_IRCOMM=y
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_OMAP=y
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=32
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_I2C=y
-CONFIG_I2C_OMAP=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_OMAP_WATCHDOG=y
-CONFIG_MENELAUS=y
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_OMAP=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_MMC=y
-CONFIG_MMC_OMAP=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QFMT_V2=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_LL=y
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_LIBCRC32C=y

diff --git a/arch/arm/configs/omap_ldp_defconfig b/arch/arm/configs/omap_ldp_defconfig
deleted file mode 100644 (file)
index c7bb558..0000000
--- a/arch/arm/configs/omap_ldp_defconfig
+++ /dev/null
@@ -1,135 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP3=y
-CONFIG_OMAP_MUX_DEBUG=y
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_ARCH_OMAP3430=y
-CONFIG_MACH_OMAP_LDP=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8"
-CONFIG_FPE_NWFPE=y
-CONFIG_VFP=y
-CONFIG_BINFMT_MISC=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_CONNECTOR=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-CONFIG_SMSC_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMSC911X=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=32
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_OMAP=y
-CONFIG_SPI=y
-CONFIG_SPI_OMAP24XX=y
-CONFIG_GPIO_TWL4030=y
-CONFIG_W1=y
-CONFIG_POWER_SUPPLY=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_TWL4030_CORE=y
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_TILEBLITTING=y
-CONFIG_FB_OMAP=y
-CONFIG_FB_OMAP_LCD_VGA=y
-CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=4
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_LCD_PLATFORM=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_RTC_CLASS=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QFMT_V2=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_LL=y
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRC_CCITT=y
-CONFIG_CRC_T10DIF=y
-CONFIG_LIBCRC32C=y

diff --git a/arch/arm/configs/omap_zoom2_defconfig b/arch/arm/configs/omap_zoom2_defconfig
deleted file mode 100644 (file)
index 0a7ed44..0000000
--- a/arch/arm/configs/omap_zoom2_defconfig
+++ /dev/null
@@ -1,143 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP3=y
-CONFIG_OMAP_MUX_DEBUG=y
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_ARCH_OMAP3430=y
-CONFIG_MACH_OMAP_ZOOM2=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8"
-CONFIG_FPE_NWFPE=y
-CONFIG_VFP=y
-CONFIG_BINFMT_MISC=y
-CONFIG_PM=y
-CONFIG_PM_DEBUG=y
-CONFIG_PM_VERBOSE=y
-CONFIG_PM_RUNTIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_CONNECTOR=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-CONFIG_SMSC_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMSC911X=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_KEYBOARD_TWL4030=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=32
-CONFIG_SERIAL_8250_RUNTIME_UARTS=1
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_OMAP=y
-CONFIG_SPI=y
-CONFIG_SPI_OMAP24XX=y
-CONFIG_GPIO_TWL4030=y
-CONFIG_W1=y
-CONFIG_POWER_SUPPLY=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_TWL4030_CORE=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TWL4030=y
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_SUSPEND=y
-# CONFIG_USB_OTG_WHITELIST is not set
-CONFIG_USB_MON=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_OTG=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_USB_MUSB_DEBUG=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DEBUG=y
-CONFIG_USB_GADGET_DEBUG_FILES=y
-CONFIG_USB_ZERO=m
-CONFIG_TWL4030_USB=y
-CONFIG_MMC=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_RTC_CLASS=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QFMT_V2=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_LL=y
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=y
-CONFIG_CRC_T10DIF=y
-CONFIG_LIBCRC32C=y

diff --git a/arch/arm/configs/omap_zoom3_defconfig b/arch/arm/configs/omap_zoom3_defconfig
deleted file mode 100644 (file)
index f8085b0..0000000
--- a/arch/arm/configs/omap_zoom3_defconfig
+++ /dev/null
@@ -1,155 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP3=y
-CONFIG_OMAP_MUX_DEBUG=y
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_ARCH_OMAP3430=y
-CONFIG_MACH_OMAP_ZOOM3=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8"
-CONFIG_FPE_NWFPE=y
-CONFIG_VFP=y
-CONFIG_BINFMT_MISC=y
-CONFIG_PM=y
-CONFIG_PM_DEBUG=y
-CONFIG_PM_VERBOSE=y
-CONFIG_PM_RUNTIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_CONNECTOR=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-CONFIG_SMSC_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMSC911X=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_KEYBOARD_TWL4030=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=32
-CONFIG_SERIAL_8250_RUNTIME_UARTS=1
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_OMAP=y
-CONFIG_SPI=y
-CONFIG_SPI_OMAP24XX=y
-CONFIG_GPIO_TWL4030=y
-CONFIG_W1=y
-CONFIG_POWER_SUPPLY=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_TWL4030_CORE=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TWL4030=y
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_SUSPEND=y
-# CONFIG_USB_OTG_WHITELIST is not set
-CONFIG_USB_MON=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_OTG=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_USB_MUSB_DEBUG=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_TEST=m
-CONFIG_USB_GADGET=m
-CONFIG_USB_GADGET_DEBUG=y
-CONFIG_USB_GADGET_DEBUG_FILES=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_AUDIO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_CDC_COMPOSITE=m
-CONFIG_TWL4030_USB=y
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_TWL4030=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QFMT_V2=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=y
-CONFIG_CRC_T10DIF=y
-CONFIG_LIBCRC32C=y

diff --git a/arch/arm/configs/overo_defconfig b/arch/arm/configs/overo_defconfig
deleted file mode 100644 (file)
index 6fa1b14..0000000
--- a/arch/arm/configs/overo_defconfig
+++ /dev/null
@@ -1,275 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_COMPAT_BRK is not set
-CONFIG_PROFILING=y
-CONFIG_OPROFILE=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP3=y
-# CONFIG_OMAP_MUX is not set
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_ARCH_OMAP3430=y
-CONFIG_MACH_OVERO=y
-CONFIG_ARM_THUMBEE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_LEDS=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE=" debug "
-CONFIG_KEXEC=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_STAT_DETAILS=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_BINFMT_AOUT=m
-CONFIG_BINFMT_MISC=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_LRO is not set
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_BCSP=y
-CONFIG_BT_HCIBCM203X=y
-CONFIG_BT_HCIBPA10X=y
-CONFIG_CFG80211=y
-CONFIG_MAC80211=y
-CONFIG_MAC80211_RC_PID=y
-CONFIG_MAC80211_RC_DEFAULT_PID=y
-CONFIG_MAC80211_LEDS=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_EEPROM_LEGACY=y
-CONFIG_RAID_ATTRS=m
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_SG=m
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID10=m
-CONFIG_MD_RAID456=m
-CONFIG_MD_MULTIPATH=m
-CONFIG_MD_FAULTY=m
-CONFIG_BLK_DEV_DM=m
-CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
-CONFIG_DM_MIRROR=m
-CONFIG_DM_ZERO=m
-CONFIG_DM_MULTIPATH=m
-CONFIG_DM_DELAY=m
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-CONFIG_TUN=m
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_USB_ZD1201=m
-CONFIG_RTL8187=m
-CONFIG_HOSTAP=m
-CONFIG_HOSTAP_FIRMWARE=y
-CONFIG_HOSTAP_FIRMWARE_NVRAM=y
-CONFIG_LIBERTAS=y
-CONFIG_LIBERTAS_USB=y
-CONFIG_LIBERTAS_SDIO=y
-CONFIG_LIBERTAS_DEBUG=y
-CONFIG_P54_COMMON=m
-CONFIG_P54_USB=m
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_USBNET=y
-CONFIG_USB_NET_DM9601=m
-CONFIG_USB_NET_GL620A=m
-CONFIG_USB_NET_NET1080=m
-CONFIG_USB_NET_PLUSB=m
-CONFIG_USB_NET_MCS7830=m
-CONFIG_USB_NET_RNDIS_HOST=m
-CONFIG_USB_NET_CDC_SUBSET=m
-CONFIG_USB_ALI_M5632=y
-CONFIG_USB_AN2720=y
-CONFIG_USB_EPSON2888=y
-CONFIG_USB_KC2190=y
-CONFIG_USB_NET_ZAURUS=m
-CONFIG_PPP=m
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_MPPE=m
-CONFIG_PPPOE=m
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=32
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_OMAP=y
-CONFIG_SPI=y
-CONFIG_SPI_OMAP24XX=y
-CONFIG_DEBUG_GPIO=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_POWER_SUPPLY=m
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_DISPLAY_SUPPORT=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_SEQUENCER=m
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_SEQUENCER_OSS=y
-CONFIG_SND_VERBOSE_PRINTK=y
-CONFIG_SND_DEBUG=y
-CONFIG_SND_USB_AUDIO=y
-CONFIG_SND_USB_CAIAQ=m
-CONFIG_SND_USB_CAIAQ_INPUT=y
-CONFIG_SND_SOC=y
-CONFIG_SND_OMAP_SOC=y
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_MUSB_PIO_ONLY=y
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_WDM=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=m
-CONFIG_USB_EMI62=m
-CONFIG_USB_EMI26=m
-CONFIG_USB_LEGOTOWER=m
-CONFIG_USB_LCD=m
-CONFIG_USB_LED=m
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_SDIO_UART=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_RTC_CLASS=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_XFS_FS=m
-CONFIG_INOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QFMT_V2=y
-CONFIG_FUSE_FS=m
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_FS_XATTR=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_RUBIN=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-CONFIG_TIMER_STATS=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_FTRACE is not set
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_CRYPTD=m
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_HMAC=m
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MICHAEL_MIC=y
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_CAMELLIA=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_DEFLATE=m
-CONFIG_CRC_CCITT=y
-CONFIG_CRC_T10DIF=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
-CONFIG_LIBCRC32C=y

diff --git a/arch/arm/configs/rx51_defconfig b/arch/arm/configs/rx51_defconfig
deleted file mode 100644 (file)
index ffaef43..0000000
--- a/arch/arm/configs/rx51_defconfig
+++ /dev/null
@@ -1,222 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_SLAB=y
-CONFIG_KPROBES=y
-CONFIG_MODULES=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP3=y
-CONFIG_OMAP_RESET_CLOCKS=y
-CONFIG_OMAP_MUX_DEBUG=y
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_ARCH_OMAP3430=y
-CONFIG_MACH_NOKIA_RX51=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="init=/sbin/preinit ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs rootflags=bulk_read,no_chk_data_crc rw console=ttyMTD,log console=tty0 console=ttyS2,115200n8"
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_BINFMT_MISC=y
-CONFIG_PM=y
-CONFIG_PM_DEBUG=y
-CONFIG_PM_RUNTIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_PHONET=y
-CONFIG_BT=m
-CONFIG_BT_L2CAP=m
-CONFIG_BT_SCO=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=m
-CONFIG_CFG80211=y
-CONFIG_MAC80211=m
-CONFIG_MAC80211_RC_PID=y
-# CONFIG_MAC80211_RC_MINSTREL is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_OOPS=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_ONENAND=y
-CONFIG_MTD_ONENAND_OMAP2=y
-CONFIG_MTD_UBI=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=m
-CONFIG_BLK_DEV_SD=m
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_SCSI_SCAN_ASYNC=y
-CONFIG_NETDEVICES=y
-CONFIG_TUN=m
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=m
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=m
-CONFIG_KEYBOARD_TWL4030=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_TWL4030_PWRBUTTON=y
-CONFIG_INPUT_UINPUT=m
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_OMAP=y
-CONFIG_SPI=y
-CONFIG_SPI_OMAP24XX=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_TWL4030=y
-CONFIG_WATCHDOG=y
-CONFIG_OMAP_WATCHDOG=m
-CONFIG_TWL4030_WATCHDOG=m
-CONFIG_TWL4030_CORE=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TWL4030=y
-CONFIG_FB=y
-CONFIG_OMAP2_DSS=y
-# CONFIG_OMAP2_DSS_DEBUG_SUPPORT is not set
-# CONFIG_OMAP2_DSS_DPI is not set
-# CONFIG_OMAP2_DSS_VENC is not set
-CONFIG_OMAP2_DSS_SDI=y
-CONFIG_FB_OMAP2=y
-CONFIG_PANEL_ACX565AKM=y
-CONFIG_DISPLAY_SUPPORT=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_OMAP_SOC=y
-CONFIG_HID=m
-CONFIG_USB_HID=m
-CONFIG_HID_A4TECH=m
-CONFIG_HID_APPLE=m
-CONFIG_HID_BELKIN=m
-CONFIG_HID_CHERRY=m
-CONFIG_HID_CHICONY=m
-CONFIG_HID_CYPRESS=m
-CONFIG_HID_EZKEY=m
-CONFIG_HID_GYRATION=m
-CONFIG_HID_LOGITECH=m
-CONFIG_HID_MICROSOFT=m
-CONFIG_HID_MONTEREY=m
-CONFIG_HID_PANTHERLORD=m
-CONFIG_HID_PETALYNX=m
-CONFIG_HID_SAMSUNG=m
-CONFIG_HID_SONY=m
-CONFIG_HID_SUNPLUS=m
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_SUSPEND=y
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_MON=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_OTG=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_USB_STORAGE=m
-CONFIG_USB_LIBUSUAL=y
-CONFIG_USB_TEST=m
-CONFIG_USB_GADGET=m
-CONFIG_USB_GADGET_DEBUG=y
-CONFIG_USB_GADGET_DEBUG_FILES=y
-CONFIG_USB_GADGET_DEBUG_FS=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_FILE_STORAGE=m
-CONFIG_USB_G_NOKIA=m
-CONFIG_TWL4030_USB=y
-CONFIG_MMC=m
-# CONFIG_MMC_BLOCK_BOUNCE is not set
-CONFIG_MMC_OMAP_HS=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=m
-CONFIG_RTC_CLASS=m
-CONFIG_RTC_DRV_TWL4030=m
-CONFIG_EXT2_FS=m
-CONFIG_EXT3_FS=m
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QFMT_V2=y
-CONFIG_FUSE_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_TMPFS=y
-CONFIG_UBIFS_FS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_TIMER_STATS=y
-CONFIG_PROVE_LOCKING=y
-CONFIG_LOCK_STAT=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SECURITY=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_AES=y
-CONFIG_CRYPTO_ARC4=y
-CONFIG_CRYPTO_DES=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=y
-CONFIG_CRC7=m
-CONFIG_LIBCRC32C=y

diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index 51662feb9f1dd03b8e1c8a3f7d208c063208aa89..6750b8e45a4914a59f6ef6cbbcb0cc84efe0ead0 100644 (file)
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -121,4 +121,8 @@ int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs);
 extern void elf_set_personality(const struct elf32_hdr *);
 #define SET_PERSONALITY(ex)    elf_set_personality(&(ex))
 
+struct mm_struct;
+extern unsigned long arch_randomize_brk(struct mm_struct *mm);
+#define arch_randomize_brk arch_randomize_brk
+
 #endif

diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h
index f7bd52b1c3654430351a5b7c5f2665e527979908..c1062c317103f706b9b2209fe8a5146c9ea4e7bf 100644 (file)
--- a/arch/arm/include/asm/hwcap.h
+++ b/arch/arm/include/asm/hwcap.h
@@ -19,6 +19,7 @@
 #define HWCAP_NEON     4096
 #define HWCAP_VFPv3    8192
 #define HWCAP_VFPv3D16 16384
+#define HWCAP_TLS      32768
 
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 /*

diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h
index 237282f7c762f3056b2ce76ab1a0e18d75a1499c..2721a5814cb93b56e0583722df184440c9497532 100644 (file)
--- a/arch/arm/include/asm/irq.h
+++ b/arch/arm/include/asm/irq.h
@@ -7,6 +7,8 @@
 #define irq_canonicalize(i)    (i)
 #endif
 
+#define NR_IRQS_LEGACY 16
+
 /*
  * Use this value to indicate lack of interrupt
  * capability

diff --git a/arch/arm/include/asm/kexec.h b/arch/arm/include/asm/kexec.h
index df15a0dc228e23da027667d3a992658daadf2305..8ec9ef5c3c7be25a2705451e8aab0a8205a47e67 100644 (file)
--- a/arch/arm/include/asm/kexec.h
+++ b/arch/arm/include/asm/kexec.h
@@ -19,10 +19,26 @@
 
 #ifndef __ASSEMBLY__
 
-struct kimage;
-/* Provide a dummy definition to avoid build failures. */
+/**
+ * crash_setup_regs() - save registers for the panic kernel
+ * @newregs: registers are saved here
+ * @oldregs: registers to be saved (may be %NULL)
+ *
+ * Function copies machine registers from @oldregs to @newregs. If @oldregs is
+ * %NULL then current registers are stored there.
+ */
 static inline void crash_setup_regs(struct pt_regs *newregs,
-                                        struct pt_regs *oldregs) { }
+                                   struct pt_regs *oldregs)
+{
+       if (oldregs) {
+               memcpy(newregs, oldregs, sizeof(*newregs));
+       } else {
+               __asm__ __volatile__ ("stmia %0, {r0 - r15}"
+                                     : : "r" (&newregs->ARM_r0));
+               __asm__ __volatile__ ("mrs %0, cpsr"
+                                     : "=r" (newregs->ARM_cpsr));
+       }
+}
 
 #endif /* __ASSEMBLY__ */
 

diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index c59842dc7cb8d8f2b3a3e140d3a17d8da575efe0..8a0dd18ba6427301ed4b802739a390dec64d12c2 100644 (file)
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -20,6 +20,7 @@ struct machine_desc {
         * by assembler code in head.S, head-common.S
         */
        unsigned int            nr;             /* architecture number  */
+       unsigned int            nr_irqs;        /* number of IRQs */
        unsigned int            phys_io;        /* start of physical io */
        unsigned int            io_pg_offst;    /* byte offset for io 
                                                 * page tabe entry      */
@@ -37,6 +38,7 @@ struct machine_desc {
        void                    (*fixup)(struct machine_desc *,
                                         struct tag *, char **,
                                         struct meminfo *);
+       void                    (*reserve)(void);/* reserve mem blocks  */
        void                    (*map_io)(void);/* IO mapping function  */
        void                    (*init_irq)(void);
        struct sys_timer        *timer;         /* system tick timer    */

diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h
index 8920b2d6e3b850634c501abe7f1512c6eea4a46f..ce3eee9fe26cbb055cbea6ab0d5567af4964b29a 100644 (file)
--- a/arch/arm/include/asm/mach/irq.h
+++ b/arch/arm/include/asm/mach/irq.h
@@ -17,6 +17,7 @@ struct seq_file;
 /*
  * This is internal.  Do not use it.
  */
+extern unsigned int arch_nr_irqs;
 extern void (*init_arch_irq)(void);
 extern void init_FIQ(void);
 extern int show_fiq_list(struct seq_file *, void *);

diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index 742c2aaeb02031d4d4e77dbf11e653910887343b..d2fedb5aeb1f381d74dbdfd29516fbbfd0ea4e13 100644 (file)
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -27,6 +27,8 @@ struct map_desc {
 #define MT_MEMORY              9
 #define MT_ROM                 10
 #define MT_MEMORY_NONCACHED    11
+#define MT_MEMORY_DTCM         12
+#define MT_MEMORY_ITCM         13
 
 #ifdef CONFIG_MMU
 extern void iotable_init(struct map_desc *, int);

diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index 52f0da1e97df28765c3dfe8a618a896727d5ec1b..16330bd0657cb172f5ff2d736ceb78c22dbdc23b 100644 (file)
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -46,6 +46,7 @@ struct pci_sys_data {
                                        /* IRQ mapping                          */
        int             (*map_irq)(struct pci_dev *, u8, u8);
        struct hw_pci   *hw;
+       void            *private_data;  /* platform controller private data     */
 };
 
 /*

diff --git a/arch/arm/include/asm/memblock.h b/arch/arm/include/asm/memblock.h
new file mode 100644 (file)
index 0000000..fdbc43b
--- /dev/null
+++ b/arch/arm/include/asm/memblock.h
@@ -0,0 +1,16 @@
+#ifndef _ASM_ARM_MEMBLOCK_H
+#define _ASM_ARM_MEMBLOCK_H
+
+#ifdef CONFIG_MMU
+extern phys_addr_t lowmem_end_addr;
+#define MEMBLOCK_REAL_LIMIT    lowmem_end_addr
+#else
+#define MEMBLOCK_REAL_LIMIT    0
+#endif
+
+struct meminfo;
+struct machine_desc;
+
+extern void arm_memblock_init(struct meminfo *, struct machine_desc *);
+
+#endif

diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 4312ee5e3d0b6d97b83f0655435c7514d43da671..23c2e8e5c0faaa09d81910456d4de63a96a513da 100644 (file)
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -123,6 +123,15 @@
 
 #endif /* !CONFIG_MMU */
 
+/*
+ * We fix the TCM memories max 32 KiB ITCM resp DTCM at these
+ * locations
+ */
+#ifdef CONFIG_HAVE_TCM
+#define ITCM_OFFSET    UL(0xfffe0000)
+#define DTCM_OFFSET    UL(0xfffe8000)
+#endif
+
 /*
  * Physical vs virtual RAM address space conversion.  These are
  * private definitions which should NOT be used outside memory.h
@@ -158,7 +167,7 @@
 #endif
 
 #ifndef arch_adjust_zones
-#define arch_adjust_zones(node,size,holes) do { } while (0)
+#define arch_adjust_zones(size,holes) do { } while (0)
 #elif !defined(CONFIG_ZONE_DMA)
 #error "custom arch_adjust_zones() requires CONFIG_ZONE_DMA"
 #endif
@@ -234,76 +243,11 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
  *  virt_to_page(k)    convert a _valid_ virtual address to struct page *
  *  virt_addr_valid(k) indicates whether a virtual address is valid
  */
-#ifndef CONFIG_DISCONTIGMEM
-
 #define ARCH_PFN_OFFSET                PHYS_PFN_OFFSET
 
 #define virt_to_page(kaddr)    pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
 #define virt_addr_valid(kaddr) ((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory)
 
-#define PHYS_TO_NID(addr)      (0)
-
-#else /* CONFIG_DISCONTIGMEM */
-
-/*
- * This is more complex.  We have a set of mem_map arrays spread
- * around in memory.
- */
-#include <linux/numa.h>
-
-#define arch_pfn_to_nid(pfn)   PFN_TO_NID(pfn)
-#define arch_local_page_offset(pfn, nid) LOCAL_MAP_NR((pfn) << PAGE_SHIFT)
-
-#define virt_to_page(kaddr)                                    \
-       (ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr))
-
-#define virt_addr_valid(kaddr) (KVADDR_TO_NID(kaddr) < MAX_NUMNODES)
-
-/*
- * Common discontigmem stuff.
- *  PHYS_TO_NID is used by the ARM kernel/setup.c
- */
-#define PHYS_TO_NID(addr)      PFN_TO_NID((addr) >> PAGE_SHIFT)
-
-/*
- * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
- * and returns the mem_map of that node.
- */
-#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
-
-/*
- * Given a page frame number, find the owning node of the memory
- * and returns the mem_map of that node.
- */
-#define PFN_TO_MAPBASE(pfn)    NODE_MEM_MAP(PFN_TO_NID(pfn))
-
-#ifdef NODE_MEM_SIZE_BITS
-#define NODE_MEM_SIZE_MASK     ((1 << NODE_MEM_SIZE_BITS) - 1)
-
-/*
- * Given a kernel address, find the home node of the underlying memory.
- */
-#define KVADDR_TO_NID(addr) \
-       (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MEM_SIZE_BITS)
-
-/*
- * Given a page frame number, convert it to a node id.
- */
-#define PFN_TO_NID(pfn) \
-       (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MEM_SIZE_BITS - PAGE_SHIFT))
-
-/*
- * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
- * and returns the index corresponding to the appropriate page in the
- * node's mem_map.
- */
-#define LOCAL_MAP_NR(addr) \
-       (((unsigned long)(addr) & NODE_MEM_SIZE_MASK) >> PAGE_SHIFT)
-
-#endif /* NODE_MEM_SIZE_BITS */
-
-#endif /* !CONFIG_DISCONTIGMEM */
-
 /*
  * Optional coherency support.  Currently used only by selected
  * Intel XSC3-based systems.

diff --git a/arch/arm/include/asm/mmzone.h b/arch/arm/include/asm/mmzone.h
deleted file mode 100644 (file)
index ae63a4f..0000000
--- a/arch/arm/include/asm/mmzone.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- *  arch/arm/include/asm/mmzone.h
- *
- *  1999-12-29 Nicolas Pitre           Created
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_MMZONE_H
-#define __ASM_MMZONE_H
-
-/*
- * Currently defined in arch/arm/mm/discontig.c
- */
-extern pg_data_t discontig_node_data[];
-
-/*
- * Return a pointer to the node data for node n.
- */
-#define NODE_DATA(nid)         (&discontig_node_data[nid])
-
-/*
- * NODE_MEM_MAP gives the kaddr for the mem_map of the node.
- */
-#define NODE_MEM_MAP(nid)      (NODE_DATA(nid)->node_mem_map)
-
-#include <mach/memory.h>
-
-#endif

diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 9dcb11e590268f8bef4230557f477edb656588f3..c974be8913a76dda0a25e8c8f5ad1e7f3a03610d 100644 (file)
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -184,6 +184,42 @@ extern unsigned long profile_pc(struct pt_regs *regs);
 #define predicate(x)           ((x) & 0xf0000000)
 #define PREDICATE_ALWAYS       0xe0000000
 
+/*
+ * kprobe-based event tracer support
+ */
+#include <linux/stddef.h>
+#include <linux/types.h>
+#define MAX_REG_OFFSET (offsetof(struct pt_regs, ARM_ORIG_r0))
+
+extern int regs_query_register_offset(const char *name);
+extern const char *regs_query_register_name(unsigned int offset);
+extern bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr);
+extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
+                                              unsigned int n);
+
+/**
+ * regs_get_register() - get register value from its offset
+ * @regs:         pt_regs from which register value is gotten
+ * @offset:    offset number of the register.
+ *
+ * regs_get_register returns the value of a register whose offset from @regs.
+ * The @offset is the offset of the register in struct pt_regs.
+ * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
+ */
+static inline unsigned long regs_get_register(struct pt_regs *regs,
+                                             unsigned int offset)
+{
+       if (unlikely(offset > MAX_REG_OFFSET))
+               return 0;
+       return *(unsigned long *)((unsigned long)regs + offset);
+}
+
+/* Valid only for Kernel mode traps. */
+static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
+{
+       return regs->ARM_sp;
+}
+
 #endif /* __KERNEL__ */
 
 #endif /* __ASSEMBLY__ */

diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
index f392fb4437afbd86b35807f16a152ab773df17f4..f1e5a9bca2491d982bda9fda1d40aa7b63b0cfd8 100644 (file)
--- a/arch/arm/include/asm/setup.h
+++ b/arch/arm/include/asm/setup.h
@@ -201,8 +201,7 @@ static struct tagtable __tagtable_##fn __tag = { tag, fn }
 struct membank {
        unsigned long start;
        unsigned long size;
-       unsigned short node;
-       unsigned short highmem;
+       unsigned int highmem;
 };
 
 struct meminfo {
@@ -212,9 +211,8 @@ struct meminfo {
 
 extern struct meminfo meminfo;
 
-#define for_each_nodebank(iter,mi,no)                  \
-       for (iter = 0; iter < (mi)->nr_banks; iter++)   \
-               if ((mi)->bank[iter].node == no)
+#define for_each_bank(iter,mi)                         \
+       for (iter = 0; iter < (mi)->nr_banks; iter++)
 
 #define bank_pfn_start(bank)   __phys_to_pfn((bank)->start)
 #define bank_pfn_end(bank)     __phys_to_pfn((bank)->start + (bank)->size)

diff --git a/arch/arm/include/asm/stackprotector.h b/arch/arm/include/asm/stackprotector.h
new file mode 100644 (file)
index 0000000..de00332
--- /dev/null
+++ b/arch/arm/include/asm/stackprotector.h
@@ -0,0 +1,38 @@
+/*
+ * GCC stack protector support.
+ *
+ * Stack protector works by putting predefined pattern at the start of
+ * the stack frame and verifying that it hasn't been overwritten when
+ * returning from the function.  The pattern is called stack canary
+ * and gcc expects it to be defined by a global variable called
+ * "__stack_chk_guard" on ARM.  This unfortunately means that on SMP
+ * we cannot have a different canary value per task.
+ */
+
+#ifndef _ASM_STACKPROTECTOR_H
+#define _ASM_STACKPROTECTOR_H 1
+
+#include <linux/random.h>
+#include <linux/version.h>
+
+extern unsigned long __stack_chk_guard;
+
+/*
+ * Initialize the stackprotector canary value.
+ *
+ * NOTE: this must only be called from functions that never return,
+ * and it must always be inlined.
+ */
+static __always_inline void boot_init_stack_canary(void)
+{
+       unsigned long canary;
+
+       /* Try to get a semi random initial value. */
+       get_random_bytes(&canary, sizeof(canary));
+       canary ^= LINUX_VERSION_CODE;
+
+       current->stack_canary = canary;
+       __stack_chk_guard = current->stack_canary;
+}
+
+#endif /* _ASM_STACKPROTECTOR_H */

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 5f4f48002734c2aa173ed8b8c0cd2294b64a8250..8ba1ccf82a0200283367db344ed79259f8d57c05 100644 (file)
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -83,7 +83,7 @@ void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
 
 void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
                                       struct pt_regs *),
-                    int sig, const char *name);
+                    int sig, int code, const char *name);
 
 #define xchg(ptr,x) \
        ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))

diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
new file mode 100644 (file)
index 0000000..e71d6ff
--- /dev/null
+++ b/arch/arm/include/asm/tls.h
@@ -0,0 +1,46 @@
+#ifndef __ASMARM_TLS_H
+#define __ASMARM_TLS_H
+
+#ifdef __ASSEMBLY__
+       .macro set_tls_none, tp, tmp1, tmp2
+       .endm
+
+       .macro set_tls_v6k, tp, tmp1, tmp2
+       mcr     p15, 0, \tp, c13, c0, 3         @ set TLS register
+       .endm
+
+       .macro set_tls_v6, tp, tmp1, tmp2
+       ldr     \tmp1, =elf_hwcap
+       ldr     \tmp1, [\tmp1, #0]
+       mov     \tmp2, #0xffff0fff
+       tst     \tmp1, #HWCAP_TLS               @ hardware TLS available?
+       mcrne   p15, 0, \tp, c13, c0, 3         @ yes, set TLS register
+       streq   \tp, [\tmp2, #-15]              @ set TLS value at 0xffff0ff0
+       .endm
+
+       .macro set_tls_software, tp, tmp1, tmp2
+       mov     \tmp1, #0xffff0fff
+       str     \tp, [\tmp1, #-15]              @ set TLS value at 0xffff0ff0
+       .endm
+#endif
+
+#ifdef CONFIG_TLS_REG_EMUL
+#define tls_emu                1
+#define has_tls_reg            1
+#define set_tls                set_tls_none
+#elif __LINUX_ARM_ARCH__ >= 7 ||                                       \
+       (__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
+#define tls_emu                0
+#define has_tls_reg            1
+#define set_tls                set_tls_v6k
+#elif __LINUX_ARM_ARCH__ == 6
+#define tls_emu                0
+#define has_tls_reg            (elf_hwcap & HWCAP_TLS)
+#define set_tls                set_tls_v6
+#else
+#define tls_emu                0
+#define has_tls_reg            0
+#define set_tls                set_tls_software
+#endif
+
+#endif /* __ASMARM_TLS_H */

diff --git a/arch/arm/include/asm/vfpmacros.h b/arch/arm/include/asm/vfpmacros.h
index 422f3cc204a27310f99d9b25adebb9f49d16e3d0..3d5fc41ae8d38a7743b3bee9c55490135c19dcea 100644 (file)
--- a/arch/arm/include/asm/vfpmacros.h
+++ b/arch/arm/include/asm/vfpmacros.h
@@ -3,6 +3,8 @@
  *
  * Assembler-only file containing VFP macros and register definitions.
  */
+#include <asm/hwcap.h>
+
 #include "vfp.h"
 
 @ Macros to allow building with old toolkits (with no VFP support)
@@ -22,11 +24,19 @@
        LDC     p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d0-d15}
 #endif
 #ifdef CONFIG_VFPv3
+#if __LINUX_ARM_ARCH__ <= 6
+       ldr     \tmp, =elf_hwcap                    @ may not have MVFR regs
+       ldr     \tmp, [\tmp, #0]
+       tst     \tmp, #HWCAP_VFPv3D16
+       ldceq   p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d16-d31}
+       addne   \base, \base, #32*4                 @ step over unused register space
+#else
        VFPFMRX \tmp, MVFR0                         @ Media and VFP Feature Register 0
        and     \tmp, \tmp, #MVFR0_A_SIMD_MASK      @ A_SIMD field
        cmp     \tmp, #2                            @ 32 x 64bit registers?
        ldceql  p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d16-d31}
        addne   \base, \base, #32*4                 @ step over unused register space
+#endif
 #endif
        .endm
 
@@ -38,10 +48,18 @@
        STC     p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d0-d15}
 #endif
 #ifdef CONFIG_VFPv3
+#if __LINUX_ARM_ARCH__ <= 6
+       ldr     \tmp, =elf_hwcap                    @ may not have MVFR regs
+       ldr     \tmp, [\tmp, #0]
+       tst     \tmp, #HWCAP_VFPv3D16
+       stceq   p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d16-d31}
+       addne   \base, \base, #32*4                 @ step over unused register space
+#else
        VFPFMRX \tmp, MVFR0                         @ Media and VFP Feature Register 0
        and     \tmp, \tmp, #MVFR0_A_SIMD_MASK      @ A_SIMD field
        cmp     \tmp, #2                            @ 32 x 64bit registers?
        stceql  p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d16-d31}
        addne   \base, \base, #32*4                 @ step over unused register space
+#endif
 #endif
        .endm

diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 26d302c28e1318b4aa5db81a491fcd6a82b0e6fa..980b78e31328156925f361cf5f6a2deac14c1500 100644 (file)
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -13,10 +13,12 @@ CFLAGS_REMOVE_return_address.o = -pg
 
 # Object file lists.
 
-obj-y          := compat.o elf.o entry-armv.o entry-common.o irq.o \
+obj-y          := elf.o entry-armv.o entry-common.o irq.o \
                   process.o ptrace.o return_address.o setup.o signal.o \
                   sys_arm.o stacktrace.o time.o traps.o
 
+obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += compat.o
+
 obj-$(CONFIG_LEDS)             += leds.o
 obj-$(CONFIG_OC_ETM)           += etm.o
 
@@ -39,6 +41,7 @@ obj-$(CONFIG_ARM_THUMBEE)     += thumbee.o
 obj-$(CONFIG_KGDB)             += kgdb.o
 obj-$(CONFIG_ARM_UNWIND)       += unwind.o
 obj-$(CONFIG_HAVE_TCM)         += tcm.o
+obj-$(CONFIG_CRASH_DUMP)       += crash_dump.o
 
 obj-$(CONFIG_CRUNCH)           += crunch.o crunch-bits.o
 AFLAGS_crunch-bits.o           := -Wa,-mcpu=ep9312

diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 883511522fca9e83be970c2611fd2ce5a1a75a41..85f2a019f77bc93b17e0c55bf60693d18a8e2ffa 100644 (file)
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -40,6 +40,9 @@
 int main(void)
 {
   DEFINE(TSK_ACTIVE_MM,                offsetof(struct task_struct, active_mm));
+#ifdef CONFIG_CC_STACKPROTECTOR
+  DEFINE(TSK_STACK_CANARY,     offsetof(struct task_struct, stack_canary));
+#endif
   BLANK();
   DEFINE(TI_FLAGS,             offsetof(struct thread_info, flags));
   DEFINE(TI_PREEMPT,           offsetof(struct thread_info, preempt_count));

diff --git a/arch/arm/kernel/compat.c b/arch/arm/kernel/compat.c
index 0a1385442f4344548bf20c5c0b28090f743e12b3..925652318b8b5df4cb7dce4383b99cee2640285b 100644 (file)
--- a/arch/arm/kernel/compat.c
+++ b/arch/arm/kernel/compat.c
@@ -217,10 +217,3 @@ void __init convert_to_tag_list(struct tag *tags)
        struct param_struct *params = (struct param_struct *)tags;
        build_tag_list(params, &params->u2);
 }
-
-void __init squash_mem_tags(struct tag *tag)
-{
-       for (; tag->hdr.size; tag = tag_next(tag))
-               if (tag->hdr.tag == ATAG_MEM)
-                       tag->hdr.tag = ATAG_NONE;
-}

diff --git a/arch/arm/kernel/compat.h b/arch/arm/kernel/compat.h
index 27e61a68bd1c5693909a4ac0dbbdb00c6663b684..39264ab1b9c640cd81447f4a54ec1f19c118fede 100644 (file)
--- a/arch/arm/kernel/compat.h
+++ b/arch/arm/kernel/compat.h
@@ -9,5 +9,3 @@
 */
 
 extern void convert_to_tag_list(struct tag *tags);
-
-extern void squash_mem_tags(struct tag *tag);

diff --git a/arch/arm/kernel/crash_dump.c b/arch/arm/kernel/crash_dump.c
new file mode 100644 (file)
index 0000000..cd3b853
--- /dev/null
+++ b/arch/arm/kernel/crash_dump.c
@@ -0,0 +1,60 @@
+/*
+ * arch/arm/kernel/crash_dump.c
+ *
+ * Copyright (C) 2010 Nokia Corporation.
+ * Author: Mika Westerberg
+ *
+ * This code is taken from arch/x86/kernel/crash_dump_64.c
+ *   Created by: Hariprasad Nellitheertha (hari@in.ibm.com)
+ *   Copyright (C) IBM Corporation, 2004. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/errno.h>
+#include <linux/crash_dump.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+
+/* stores the physical address of elf header of crash image */
+unsigned long long elfcorehdr_addr = ELFCORE_ADDR_MAX;
+
+/**
+ * copy_oldmem_page() - copy one page from old kernel memory
+ * @pfn: page frame number to be copied
+ * @buf: buffer where the copied page is placed
+ * @csize: number of bytes to copy
+ * @offset: offset in bytes into the page
+ * @userbuf: if set, @buf is int he user address space
+ *
+ * This function copies one page from old kernel memory into buffer pointed by
+ * @buf. If @buf is in userspace, set @userbuf to %1. Returns number of bytes
+ * copied or negative error in case of failure.
+ */
+ssize_t copy_oldmem_page(unsigned long pfn, char *buf,
+                        size_t csize, unsigned long offset,
+                        int userbuf)
+{
+       void *vaddr;
+
+       if (!csize)
+               return 0;
+
+       vaddr = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE);
+       if (!vaddr)
+               return -ENOMEM;
+
+       if (userbuf) {
+               if (copy_to_user(buf, vaddr + offset, csize)) {
+                       iounmap(vaddr);
+                       return -EFAULT;
+               }
+       } else {
+               memcpy(buf, vaddr + offset, csize);
+       }
+
+       iounmap(vaddr);
+       return csize;
+}

diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 3fd7861de4d16c508ee424e52281de0dc39a4db7..bb8e93a76407241042345c51273690f6cdc35578 100644 (file)
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -22,6 +22,7 @@
 #include <asm/thread_notify.h>
 #include <asm/unwind.h>
 #include <asm/unistd.h>
+#include <asm/tls.h>
 
 #include "entry-header.S"
 
@@ -735,11 +736,11 @@ ENTRY(__switch_to)
 #ifdef CONFIG_MMU
        ldr     r6, [r2, #TI_CPU_DOMAIN]
 #endif
-#if defined(CONFIG_HAS_TLS_REG)
-       mcr     p15, 0, r3, c13, c0, 3          @ set TLS register
-#elif !defined(CONFIG_TLS_REG_EMUL)
-       mov     r4, #0xffff0fff
-       str     r3, [r4, #-15]                  @ TLS val at 0xffff0ff0
+       set_tls r3, r4, r5
+#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
+       ldr     r7, [r2, #TI_TASK]
+       ldr     r8, =__stack_chk_guard
+       ldr     r7, [r7, #TSK_STACK_CANARY]
 #endif
 #ifdef CONFIG_MMU
        mcr     p15, 0, r6, c3, c0, 0           @ Set domain register
@@ -749,6 +750,9 @@ ENTRY(__switch_to)
        ldr     r0, =thread_notify_head
        mov     r1, #THREAD_NOTIFY_SWITCH
        bl      atomic_notifier_call_chain
+#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
+       str     r7, [r8]
+#endif
  THUMB(        mov     ip, r4                     )
        mov     r0, r5
  ARM(  ldmia   r4, {r4 - sl, fp, sp, pc}  )    @ Load all regs saved previously
@@ -1005,17 +1009,12 @@ kuser_cmpxchg_fixup:
  */
 
 __kuser_get_tls:                               @ 0xffff0fe0
-
-#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
-       ldr     r0, [pc, #(16 - 8)]             @ TLS stored at 0xffff0ff0
-#else
-       mrc     p15, 0, r0, c13, c0, 3          @ read TLS register
-#endif
+       ldr     r0, [pc, #(16 - 8)]     @ read TLS, set in kuser_get_tls_init
        usr_ret lr
-
-       .rep    5
-       .word   0                       @ pad up to __kuser_helper_version
-       .endr
+       mrc     p15, 0, r0, c13, c0, 3  @ 0xffff0fe8 hardware TLS code
+       .rep    4
+       .word   0                       @ 0xffff0ff0 software TLS value, then
+       .endr                           @ pad up to __kuser_helper_version
 
 /*
  * Reference declaration:

diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 3b3d2c80509c0bb4c3499f944414a11425f6e5e6..c0d5c3b3a760fa79624657ebc495b1d7b81b8c66 100644 (file)
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -47,12 +47,14 @@
 #define irq_finish(irq) do { } while (0)
 #endif
 
+unsigned int arch_nr_irqs;
 void (*init_arch_irq)(void) __initdata = NULL;
 unsigned long irq_err_count;
 
 int show_interrupts(struct seq_file *p, void *v)
 {
        int i = *(loff_t *) v, cpu;
+       struct irq_desc *desc;
        struct irqaction * action;
        unsigned long flags;
 
@@ -67,24 +69,25 @@ int show_interrupts(struct seq_file *p, void *v)
                seq_putc(p, '\n');
        }
 
-       if (i < NR_IRQS) {
-               raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
-               action = irq_desc[i].action;
+       if (i < nr_irqs) {
+               desc = irq_to_desc(i);
+               raw_spin_lock_irqsave(&desc->lock, flags);
+               action = desc->action;
                if (!action)
                        goto unlock;
 
                seq_printf(p, "%3d: ", i);
                for_each_present_cpu(cpu)
                        seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu));
-               seq_printf(p, " %10s", irq_desc[i].chip->name ? : "-");
+               seq_printf(p, " %10s", desc->chip->name ? : "-");
                seq_printf(p, "  %s", action->name);
                for (action = action->next; action; action = action->next)
                        seq_printf(p, ", %s", action->name);
 
                seq_putc(p, '\n');
 unlock:
-               raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
-       } else if (i == NR_IRQS) {
+               raw_spin_unlock_irqrestore(&desc->lock, flags);
+       } else if (i == nr_irqs) {
 #ifdef CONFIG_FIQ
                show_fiq_list(p, v);
 #endif
@@ -112,7 +115,7 @@ asmlinkage void __exception asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
         * Some hardware gives randomly wrong interrupts.  Rather
         * than crashing, do something sensible.
         */
-       if (unlikely(irq >= NR_IRQS)) {
+       if (unlikely(irq >= nr_irqs)) {
                if (printk_ratelimit())
                        printk(KERN_WARNING "Bad IRQ%u\n", irq);
                ack_bad_irq(irq);
@@ -132,12 +135,12 @@ void set_irq_flags(unsigned int irq, unsigned int iflags)
        struct irq_desc *desc;
        unsigned long flags;
 
-       if (irq >= NR_IRQS) {
+       if (irq >= nr_irqs) {
                printk(KERN_ERR "Trying to set irq flags for IRQ%d\n", irq);
                return;
        }
 
-       desc = irq_desc + irq;
+       desc = irq_to_desc(irq);
        raw_spin_lock_irqsave(&desc->lock, flags);
        desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
        if (iflags & IRQF_VALID)
@@ -151,14 +154,25 @@ void set_irq_flags(unsigned int irq, unsigned int iflags)
 
 void __init init_IRQ(void)
 {
+       struct irq_desc *desc;
        int irq;
 
-       for (irq = 0; irq < NR_IRQS; irq++)
-               irq_desc[irq].status |= IRQ_NOREQUEST | IRQ_NOPROBE;
+       for (irq = 0; irq < nr_irqs; irq++) {
+               desc = irq_to_desc_alloc_node(irq, 0);
+               desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE;
+       }
 
        init_arch_irq();
 }
 
+#ifdef CONFIG_SPARSE_IRQ
+int __init arch_probe_nr_irqs(void)
+{
+       nr_irqs = arch_nr_irqs ? arch_nr_irqs : NR_IRQS;
+       return 0;
+}
+#endif
+
 #ifdef CONFIG_HOTPLUG_CPU
 
 static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
@@ -178,10 +192,9 @@ static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
 void migrate_irqs(void)
 {
        unsigned int i, cpu = smp_processor_id();
+       struct irq_desc *desc;
 
-       for (i = 0; i < NR_IRQS; i++) {
-               struct irq_desc *desc = irq_desc + i;
-
+       for_each_irq_desc(i, desc) {
                if (desc->node == cpu) {
                        unsigned int newcpu = cpumask_any_and(desc->affinity,
                                                              cpu_online_mask);

diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index 598ca61e7bca8496a853128a433dc7d1dfba0edf..1fc74cbd1a193ee4dcd2fd50afdd279804d9e5fd 100644 (file)
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -37,12 +37,12 @@ void machine_kexec_cleanup(struct kimage *image)
 {
 }
 
-void machine_shutdown(void)
-{
-}
-
 void machine_crash_shutdown(struct pt_regs *regs)
 {
+       local_irq_disable();
+       crash_save_cpu(regs, smp_processor_id());
+
+       printk(KERN_INFO "Loading crashdump kernel...\n");
 }
 
 void machine_kexec(struct kimage *image)
@@ -74,7 +74,11 @@ void machine_kexec(struct kimage *image)
                           (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE);
        printk(KERN_INFO "Bye!\n");
 
-       cpu_proc_fin();
+       local_irq_disable();
+       local_fiq_disable();
        setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/
+       flush_cache_all();
+       cpu_proc_fin();
+       flush_cache_all();
        cpu_reset(reboot_code_buffer_phys);
 }

diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index a4a9cc88bec73a525a9edd4bdc7db94cea370ce9..401e38be1f787c16e7b36d6429406a05229d83da 100644 (file)
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -28,7 +28,9 @@
 #include <linux/tick.h>
 #include <linux/utsname.h>
 #include <linux/uaccess.h>
+#include <linux/random.h>
 
+#include <asm/cacheflush.h>
 #include <asm/leds.h>
 #include <asm/processor.h>
 #include <asm/system.h>
@@ -36,6 +38,12 @@
 #include <asm/stacktrace.h>
 #include <asm/mach/time.h>
 
+#ifdef CONFIG_CC_STACKPROTECTOR
+#include <linux/stackprotector.h>
+unsigned long __stack_chk_guard __read_mostly;
+EXPORT_SYMBOL(__stack_chk_guard);
+#endif
+
 static const char *processor_modes[] = {
   "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" ,
   "UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26",
@@ -84,10 +92,9 @@ __setup("hlt", hlt_setup);
 
 void arm_machine_restart(char mode, const char *cmd)
 {
-       /*
-        * Clean and disable cache, and turn off interrupts
-        */
-       cpu_proc_fin();
+       /* Disable interrupts first */
+       local_irq_disable();
+       local_fiq_disable();
 
        /*
         * Tell the mm system that we are going to reboot -
@@ -96,6 +103,15 @@ void arm_machine_restart(char mode, const char *cmd)
         */
        setup_mm_for_reboot(mode);
 
+       /* Clean and invalidate caches */
+       flush_cache_all();
+
+       /* Turn off caching */
+       cpu_proc_fin();
+
+       /* Push out any further dirty data, and ensure cache is empty */
+       flush_cache_all();
+
        /*
         * Now call the architecture specific reboot code.
         */
@@ -189,19 +205,29 @@ int __init reboot_setup(char *str)
 
 __setup("reboot=", reboot_setup);
 
-void machine_halt(void)
+void machine_shutdown(void)
 {
+#ifdef CONFIG_SMP
+       smp_send_stop();
+#endif
 }
 
+void machine_halt(void)
+{
+       machine_shutdown();
+       while (1);
+}
 
 void machine_power_off(void)
 {
+       machine_shutdown();
        if (pm_power_off)
                pm_power_off();
 }
 
 void machine_restart(char *cmd)
 {
+       machine_shutdown();
        arm_pm_restart(reboot_mode, cmd);
 }
 
@@ -426,3 +452,9 @@ unsigned long get_wchan(struct task_struct *p)
        } while (count ++ < 16);
        return 0;
 }
+
+unsigned long arch_randomize_brk(struct mm_struct *mm)
+{
+       unsigned long range_end = mm->brk + 0x02000000;
+       return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
+}

diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 3f562a7c0a99445f3747ec0d0198d4f53a4d83fd..f99d489822d50fb23e46f4e7760411b766e040e7 100644 (file)
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -52,6 +52,102 @@
 #define BREAKINST_THUMB        0xde01
 #endif
 
+struct pt_regs_offset {
+       const char *name;
+       int offset;
+};
+
+#define REG_OFFSET_NAME(r) \
+       {.name = #r, .offset = offsetof(struct pt_regs, ARM_##r)}
+#define REG_OFFSET_END {.name = NULL, .offset = 0}
+
+static const struct pt_regs_offset regoffset_table[] = {
+       REG_OFFSET_NAME(r0),
+       REG_OFFSET_NAME(r1),
+       REG_OFFSET_NAME(r2),
+       REG_OFFSET_NAME(r3),
+       REG_OFFSET_NAME(r4),
+       REG_OFFSET_NAME(r5),
+       REG_OFFSET_NAME(r6),
+       REG_OFFSET_NAME(r7),
+       REG_OFFSET_NAME(r8),
+       REG_OFFSET_NAME(r9),
+       REG_OFFSET_NAME(r10),
+       REG_OFFSET_NAME(fp),
+       REG_OFFSET_NAME(ip),
+       REG_OFFSET_NAME(sp),
+       REG_OFFSET_NAME(lr),
+       REG_OFFSET_NAME(pc),
+       REG_OFFSET_NAME(cpsr),
+       REG_OFFSET_NAME(ORIG_r0),
+       REG_OFFSET_END,
+};
+
+/**
+ * regs_query_register_offset() - query register offset from its name
+ * @name:      the name of a register
+ *
+ * regs_query_register_offset() returns the offset of a register in struct
+ * pt_regs from its name. If the name is invalid, this returns -EINVAL;
+ */
+int regs_query_register_offset(const char *name)
+{
+       const struct pt_regs_offset *roff;
+       for (roff = regoffset_table; roff->name != NULL; roff++)
+               if (!strcmp(roff->name, name))
+                       return roff->offset;
+       return -EINVAL;
+}
+
+/**
+ * regs_query_register_name() - query register name from its offset
+ * @offset:    the offset of a register in struct pt_regs.
+ *
+ * regs_query_register_name() returns the name of a register from its
+ * offset in struct pt_regs. If the @offset is invalid, this returns NULL;
+ */
+const char *regs_query_register_name(unsigned int offset)
+{
+       const struct pt_regs_offset *roff;
+       for (roff = regoffset_table; roff->name != NULL; roff++)
+               if (roff->offset == offset)
+                       return roff->name;
+       return NULL;
+}
+
+/**
+ * regs_within_kernel_stack() - check the address in the stack
+ * @regs:      pt_regs which contains kernel stack pointer.
+ * @addr:      address which is checked.
+ *
+ * regs_within_kernel_stack() checks @addr is within the kernel stack page(s).
+ * If @addr is within the kernel stack, it returns true. If not, returns false.
+ */
+bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr)
+{
+       return ((addr & ~(THREAD_SIZE - 1))  ==
+               (kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1)));
+}
+
+/**
+ * regs_get_kernel_stack_nth() - get Nth entry of the stack
+ * @regs:      pt_regs which contains kernel stack pointer.
+ * @n:         stack entry number.
+ *
+ * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which
+ * is specified by @regs. If the @n th entry is NOT in the kernel stack,
+ * this returns 0.
+ */
+unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n)
+{
+       unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs);
+       addr += n;
+       if (regs_within_kernel_stack(regs, (unsigned long)addr))
+               return *addr;
+       else
+               return 0;
+}
+
 /*
  * this routine will get a word off of the processes privileged stack.
  * the offset is how far from the base addr as stored in the THREAD.

diff --git a/arch/arm/kernel/relocate_kernel.S b/arch/arm/kernel/relocate_kernel.S
index 61930eb0902941030e3e180aca40f6f82697e39e..fd26f8d65151a949e6ecff394f0146258882b9d6 100644 (file)
--- a/arch/arm/kernel/relocate_kernel.S
+++ b/arch/arm/kernel/relocate_kernel.S
@@ -10,6 +10,12 @@ relocate_new_kernel:
        ldr     r0,kexec_indirection_page
        ldr     r1,kexec_start_address
 
+       /*
+        * If there is no indirection page (we are doing crashdumps)
+        * skip any relocation.
+        */
+       cmp     r0, #0
+       beq     2f
 
 0:     /* top, read another word for the indirection page */
        ldr     r3, [r0],#4

diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 122d999bdc7ca0c8f690355a101f59f1ea8152f8..d5231ae7355aa286bf5503e0180954f84e4f6022 100644 (file)
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -19,12 +19,15 @@
 #include <linux/seq_file.h>
 #include <linux/screen_info.h>
 #include <linux/init.h>
+#include <linux/kexec.h>
+#include <linux/crash_dump.h>
 #include <linux/root_dev.h>
 #include <linux/cpu.h>
 #include <linux/interrupt.h>
 #include <linux/smp.h>
 #include <linux/fs.h>
 #include <linux/proc_fs.h>
+#include <linux/memblock.h>
 
 #include <asm/unified.h>
 #include <asm/cpu.h>
@@ -44,7 +47,9 @@
 #include <asm/traps.h>
 #include <asm/unwind.h>
 
+#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
 #include "compat.h"
+#endif
 #include "atags.h"
 #include "tcm.h"
 
@@ -269,6 +274,21 @@ static void __init cacheid_init(void)
 extern struct proc_info_list *lookup_processor_type(unsigned int);
 extern struct machine_desc *lookup_machine_type(unsigned int);
 
+static void __init feat_v6_fixup(void)
+{
+       int id = read_cpuid_id();
+
+       if ((id & 0xff0f0000) != 0x41070000)
+               return;
+
+       /*
+        * HWCAP_TLS is available only on 1136 r1p0 and later,
+        * see also kuser_get_tls_init.
+        */
+       if ((((id >> 4) & 0xfff) == 0xb36) && (((id >> 20) & 3) == 0))
+               elf_hwcap &= ~HWCAP_TLS;
+}
+
 static void __init setup_processor(void)
 {
        struct proc_info_list *list;
@@ -311,6 +331,8 @@ static void __init setup_processor(void)
        elf_hwcap &= ~HWCAP_THUMB;
 #endif
 
+       feat_v6_fixup();
+
        cacheid_init();
        cpu_proc_init();
 }
@@ -402,13 +424,12 @@ static int __init arm_add_memory(unsigned long start, unsigned long size)
        size -= start & ~PAGE_MASK;
        bank->start = PAGE_ALIGN(start);
        bank->size  = size & PAGE_MASK;
-       bank->node  = PHYS_TO_NID(start);
 
        /*
         * Check whether this memory region has non-zero size or
         * invalid node number.
         */
-       if (bank->size == 0 || bank->node >= MAX_NUMNODES)
+       if (bank->size == 0)
                return -EINVAL;
 
        meminfo.nr_banks++;
@@ -663,6 +684,86 @@ static int __init customize_machine(void)
 }
 arch_initcall(customize_machine);
 
+#ifdef CONFIG_KEXEC
+static inline unsigned long long get_total_mem(void)
+{
+       unsigned long total;
+
+       total = max_low_pfn - min_low_pfn;
+       return total << PAGE_SHIFT;
+}
+
+/**
+ * reserve_crashkernel() - reserves memory are for crash kernel
+ *
+ * This function reserves memory area given in "crashkernel=" kernel command
+ * line parameter. The memory reserved is used by a dump capture kernel when
+ * primary kernel is crashing.
+ */
+static void __init reserve_crashkernel(void)
+{
+       unsigned long long crash_size, crash_base;
+       unsigned long long total_mem;
+       int ret;
+
+       total_mem = get_total_mem();
+       ret = parse_crashkernel(boot_command_line, total_mem,
+                               &crash_size, &crash_base);
+       if (ret)
+               return;
+
+       ret = reserve_bootmem(crash_base, crash_size, BOOTMEM_EXCLUSIVE);
+       if (ret < 0) {
+               printk(KERN_WARNING "crashkernel reservation failed - "
+                      "memory is in use (0x%lx)\n", (unsigned long)crash_base);
+               return;
+       }
+
+       printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
+              "for crashkernel (System RAM: %ldMB)\n",
+              (unsigned long)(crash_size >> 20),
+              (unsigned long)(crash_base >> 20),
+              (unsigned long)(total_mem >> 20));
+
+       crashk_res.start = crash_base;
+       crashk_res.end = crash_base + crash_size - 1;
+       insert_resource(&iomem_resource, &crashk_res);
+}
+#else
+static inline void reserve_crashkernel(void) {}
+#endif /* CONFIG_KEXEC */
+
+/*
+ * Note: elfcorehdr_addr is not just limited to vmcore. It is also used by
+ * is_kdump_kernel() to determine if we are booting after a panic. Hence
+ * ifdef it under CONFIG_CRASH_DUMP and not CONFIG_PROC_VMCORE.
+ */
+
+#ifdef CONFIG_CRASH_DUMP
+/*
+ * elfcorehdr= specifies the location of elf core header stored by the crashed
+ * kernel. This option will be passed by kexec loader to the capture kernel.
+ */
+static int __init setup_elfcorehdr(char *arg)
+{
+       char *end;
+
+       if (!arg)
+               return -EINVAL;
+
+       elfcorehdr_addr = memparse(arg, &end);
+       return end > arg ? 0 : -EINVAL;
+}
+early_param("elfcorehdr", setup_elfcorehdr);
+#endif /* CONFIG_CRASH_DUMP */
+
+static void __init squash_mem_tags(struct tag *tag)
+{
+       for (; tag->hdr.size; tag = tag_next(tag))
+               if (tag->hdr.tag == ATAG_MEM)
+                       tag->hdr.tag = ATAG_NONE;
+}
+
 void __init setup_arch(char **cmdline_p)
 {
        struct tag *tags = (struct tag *)&init_tags;
@@ -683,12 +784,14 @@ void __init setup_arch(char **cmdline_p)
        else if (mdesc->boot_params)
                tags = phys_to_virt(mdesc->boot_params);
 
+#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
        /*
         * If we have the old style parameters, convert them to
         * a tag list.
         */
        if (tags->hdr.tag != ATAG_CORE)
                convert_to_tag_list(tags);
+#endif
        if (tags->hdr.tag != ATAG_CORE)
                tags = (struct tag *)&init_tags;
 
@@ -716,12 +819,15 @@ void __init setup_arch(char **cmdline_p)
 
        parse_early_param();
 
+       arm_memblock_init(&meminfo, mdesc);
+
        paging_init(mdesc);
        request_standard_resources(&meminfo, mdesc);
 
 #ifdef CONFIG_SMP
        smp_init_cpus();
 #endif
+       reserve_crashkernel();
 
        cpu_init();
        tcm_init();
@@ -729,6 +835,7 @@ void __init setup_arch(char **cmdline_p)
        /*
         * Set up various architecture-specific pointers
         */
+       arch_nr_irqs = mdesc->nr_irqs;
        init_arch_irq = mdesc->init_irq;
        system_timer = mdesc->timer;
        init_machine = mdesc->init_machine;

diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index b8c3d0f689d9560cc33a7e8ec06958ad216e7ef1..40dc74f2b27f3362f8739f5e9898963dd27a221b 100644 (file)
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -429,7 +429,11 @@ static void smp_timer_broadcast(const struct cpumask *mask)
 {
        send_ipi_message(mask, IPI_TIMER);
 }
+#else
+#define smp_timer_broadcast    NULL
+#endif
 
+#ifndef CONFIG_LOCAL_TIMERS
 static void broadcast_timer_set_mode(enum clock_event_mode mode,
        struct clock_event_device *evt)
 {
@@ -444,7 +448,6 @@ static void local_timer_setup(struct clock_event_device *evt)
        evt->rating     = 400;
        evt->mult       = 1;
        evt->set_mode   = broadcast_timer_set_mode;
-       evt->broadcast  = smp_timer_broadcast;
 
        clockevents_register_device(evt);
 }
@@ -456,6 +459,7 @@ void __cpuinit percpu_timer_setup(void)
        struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
 
        evt->cpumask = cpumask_of(cpu);
+       evt->broadcast = smp_timer_broadcast;
 
        local_timer_setup(evt);
 }
@@ -467,10 +471,13 @@ static DEFINE_SPINLOCK(stop_lock);
  */
 static void ipi_cpu_stop(unsigned int cpu)
 {
-       spin_lock(&stop_lock);
-       printk(KERN_CRIT "CPU%u: stopping\n", cpu);
-       dump_stack();
-       spin_unlock(&stop_lock);
+       if (system_state == SYSTEM_BOOTING ||
+           system_state == SYSTEM_RUNNING) {
+               spin_lock(&stop_lock);
+               printk(KERN_CRIT "CPU%u: stopping\n", cpu);
+               dump_stack();
+               spin_unlock(&stop_lock);
+       }
 
        set_cpu_online(cpu, false);
 

diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 7c5f0c024db7e468aba3a185bded3bf3fde7073a..35882fbf37f90063723d3247352a3c05af480f99 100644 (file)
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -132,7 +132,8 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
        twd_calibrate_rate();
 
        clk->name = "local_timer";
-       clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
+       clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
+                       CLOCK_EVT_FEAT_C3STOP;
        clk->rating = 350;
        clk->set_mode = twd_set_mode;
        clk->set_next_event = twd_set_next_event;

diff --git a/arch/arm/kernel/tcm.c b/arch/arm/kernel/tcm.c
index e50303868f1b62dd3853667d4a1445629eb4999c..26685c2f7a49d11b16421f5cad55c3c5109a27ea 100644 (file)
--- a/arch/arm/kernel/tcm.c
+++ b/arch/arm/kernel/tcm.c
@@ -13,38 +13,35 @@
 #include <linux/ioport.h>
 #include <linux/genalloc.h>
 #include <linux/string.h> /* memcpy */
-#include <asm/page.h> /* PAGE_SHIFT */
 #include <asm/cputype.h>
 #include <asm/mach/map.h>
 #include <mach/memory.h>
 #include "tcm.h"
 
-/* Scream and warn about misuse */
-#if !defined(ITCM_OFFSET) || !defined(ITCM_END) || \
-    !defined(DTCM_OFFSET) || !defined(DTCM_END)
-#error "TCM support selected but offsets not defined!"
-#endif
-
 static struct gen_pool *tcm_pool;
 
 /* TCM section definitions from the linker */
 extern char __itcm_start, __sitcm_text, __eitcm_text;
 extern char __dtcm_start, __sdtcm_data, __edtcm_data;
 
+/* These will be increased as we run */
+u32 dtcm_end = DTCM_OFFSET;
+u32 itcm_end = ITCM_OFFSET;
+
 /*
  * TCM memory resources
  */
 static struct resource dtcm_res = {
        .name = "DTCM RAM",
        .start = DTCM_OFFSET,
-       .end = DTCM_END,
+       .end = DTCM_OFFSET,
        .flags = IORESOURCE_MEM
 };
 
 static struct resource itcm_res = {
        .name = "ITCM RAM",
        .start = ITCM_OFFSET,
-       .end = ITCM_END,
+       .end = ITCM_OFFSET,
        .flags = IORESOURCE_MEM
 };
 
@@ -52,8 +49,8 @@ static struct map_desc dtcm_iomap[] __initdata = {
        {
                .virtual        = DTCM_OFFSET,
                .pfn            = __phys_to_pfn(DTCM_OFFSET),
-               .length         = (DTCM_END - DTCM_OFFSET + 1),
-               .type           = MT_UNCACHED
+               .length         = 0,
+               .type           = MT_MEMORY_DTCM
        }
 };
 
@@ -61,8 +58,8 @@ static struct map_desc itcm_iomap[] __initdata = {
        {
                .virtual        = ITCM_OFFSET,
                .pfn            = __phys_to_pfn(ITCM_OFFSET),
-               .length         = (ITCM_END - ITCM_OFFSET + 1),
-               .type           = MT_UNCACHED
+               .length         = 0,
+               .type           = MT_MEMORY_ITCM
        }
 };
 
@@ -93,14 +90,24 @@ void tcm_free(void *addr, size_t len)
 }
 EXPORT_SYMBOL(tcm_free);
 
-
-static void __init setup_tcm_bank(u8 type, u32 offset, u32 expected_size)
+static int __init setup_tcm_bank(u8 type, u8 bank, u8 banks,
+                                 u32 *offset)
 {
        const int tcm_sizes[16] = { 0, -1, -1, 4, 8, 16, 32, 64, 128,
                                    256, 512, 1024, -1, -1, -1, -1 };
        u32 tcm_region;
        int tcm_size;
 
+       /*
+        * If there are more than one TCM bank of this type,
+        * select the TCM bank to operate on in the TCM selection
+        * register.
+        */
+       if (banks > 1)
+               asm("mcr        p15, 0, %0, c9, c2, 0"
+                   : /* No output operands */
+                   : "r" (bank));
+
        /* Read the special TCM region register c9, 0 */
        if (!type)
                asm("mrc        p15, 0, %0, c9, c1, 0"
@@ -111,26 +118,24 @@ static void __init setup_tcm_bank(u8 type, u32 offset, u32 expected_size)
 
        tcm_size = tcm_sizes[(tcm_region >> 2) & 0x0f];
        if (tcm_size < 0) {
-               pr_err("CPU: %sTCM of unknown size!\n",
-                       type ? "I" : "D");
+               pr_err("CPU: %sTCM%d of unknown size\n",
+                      type ? "I" : "D", bank);
+               return -EINVAL;
+       } else if (tcm_size > 32) {
+               pr_err("CPU: %sTCM%d larger than 32k found\n",
+                      type ? "I" : "D", bank);
+               return -EINVAL;
        } else {
-               pr_info("CPU: found %sTCM %dk @ %08x, %senabled\n",
+               pr_info("CPU: found %sTCM%d %dk @ %08x, %senabled\n",
                        type ? "I" : "D",
+                       bank,
                        tcm_size,
                        (tcm_region & 0xfffff000U),
                        (tcm_region & 1) ? "" : "not ");
        }
 
-       if (tcm_size != expected_size) {
-               pr_crit("CPU: %sTCM was detected %dk but expected %dk!\n",
-                      type ? "I" : "D",
-                      tcm_size,
-                      expected_size);
-               /* Adjust to the expected size? what can we do... */
-       }
-
        /* Force move the TCM bank to where we want it, enable */
-       tcm_region = offset | (tcm_region & 0x00000ffeU) | 1;
+       tcm_region = *offset | (tcm_region & 0x00000ffeU) | 1;
 
        if (!type)
                asm("mcr        p15, 0, %0, c9, c1, 0"
@@ -141,10 +146,15 @@ static void __init setup_tcm_bank(u8 type, u32 offset, u32 expected_size)
                    : /* No output operands */
                    : "r" (tcm_region));
 
-       pr_debug("CPU: moved %sTCM %dk to %08x, enabled\n",
-                type ? "I" : "D",
-                tcm_size,
-                (tcm_region & 0xfffff000U));
+       /* Increase offset */
+       *offset += (tcm_size << 10);
+
+       pr_info("CPU: moved %sTCM%d %dk to %08x, enabled\n",
+               type ? "I" : "D",
+               bank,
+               tcm_size,
+               (tcm_region & 0xfffff000U));
+       return 0;
 }
 
 /*
@@ -153,34 +163,52 @@ static void __init setup_tcm_bank(u8 type, u32 offset, u32 expected_size)
 void __init tcm_init(void)
 {
        u32 tcm_status = read_cpuid_tcmstatus();
+       u8 dtcm_banks = (tcm_status >> 16) & 0x03;
+       u8 itcm_banks = (tcm_status & 0x03);
        char *start;
        char *end;
        char *ram;
+       int ret;
+       int i;
 
        /* Setup DTCM if present */
-       if (tcm_status & (1 << 16)) {
-               setup_tcm_bank(0, DTCM_OFFSET,
-                              (DTCM_END - DTCM_OFFSET + 1) >> 10);
+       if (dtcm_banks > 0) {
+               for (i = 0; i < dtcm_banks; i++) {
+                       ret = setup_tcm_bank(0, i, dtcm_banks, &dtcm_end);
+                       if (ret)
+                               return;
+               }
+               dtcm_res.end = dtcm_end - 1;
                request_resource(&iomem_resource, &dtcm_res);
+               dtcm_iomap[0].length = dtcm_end - DTCM_OFFSET;
                iotable_init(dtcm_iomap, 1);
                /* Copy data from RAM to DTCM */
                start = &__sdtcm_data;
                end   = &__edtcm_data;
                ram   = &__dtcm_start;
+               /* This means you compiled more code than fits into DTCM */
+               BUG_ON((end - start) > (dtcm_end - DTCM_OFFSET));
                memcpy(start, ram, (end-start));
                pr_debug("CPU DTCM: copied data from %p - %p\n", start, end);
        }
 
        /* Setup ITCM if present */
-       if (tcm_status & 1) {
-               setup_tcm_bank(1, ITCM_OFFSET,
-                              (ITCM_END - ITCM_OFFSET + 1) >> 10);
+       if (itcm_banks > 0) {
+               for (i = 0; i < itcm_banks; i++) {
+                       ret = setup_tcm_bank(1, i, itcm_banks, &itcm_end);
+                       if (ret)
+                               return;
+               }
+               itcm_res.end = itcm_end - 1;
                request_resource(&iomem_resource, &itcm_res);
+               itcm_iomap[0].length = itcm_end - ITCM_OFFSET;
                iotable_init(itcm_iomap, 1);
                /* Copy code from RAM to ITCM */
                start = &__sitcm_text;
                end   = &__eitcm_text;
                ram   = &__itcm_start;
+               /* This means you compiled more code than fits into ITCM */
+               BUG_ON((end - start) > (itcm_end - ITCM_OFFSET));
                memcpy(start, ram, (end-start));
                pr_debug("CPU ITCM: copied code from %p - %p\n", start, end);
        }
@@ -208,10 +236,10 @@ static int __init setup_tcm_pool(void)
        pr_debug("Setting up TCM memory pool\n");
 
        /* Add the rest of DTCM to the TCM pool */
-       if (tcm_status & (1 << 16)) {
-               if (dtcm_pool_start < DTCM_END) {
+       if (tcm_status & (0x03 << 16)) {
+               if (dtcm_pool_start < dtcm_end) {
                        ret = gen_pool_add(tcm_pool, dtcm_pool_start,
-                                          DTCM_END - dtcm_pool_start + 1, -1);
+                                          dtcm_end - dtcm_pool_start, -1);
                        if (ret) {
                                pr_err("CPU DTCM: could not add DTCM " \
                                       "remainder to pool!\n");
@@ -219,16 +247,16 @@ static int __init setup_tcm_pool(void)
                        }
                        pr_debug("CPU DTCM: Added %08x bytes @ %08x to " \
                                 "the TCM memory pool\n",
-                                DTCM_END - dtcm_pool_start + 1,
+                                dtcm_end - dtcm_pool_start,
                                 dtcm_pool_start);
                }
        }
 
        /* Add the rest of ITCM to the TCM pool */
-       if (tcm_status & 1) {
-               if (itcm_pool_start < ITCM_END) {
+       if (tcm_status & 0x03) {
+               if (itcm_pool_start < itcm_end) {
                        ret = gen_pool_add(tcm_pool, itcm_pool_start,
-                                          ITCM_END - itcm_pool_start + 1, -1);
+                                          itcm_end - itcm_pool_start, -1);
                        if (ret) {
                                pr_err("CPU ITCM: could not add ITCM " \
                                       "remainder to pool!\n");
@@ -236,7 +264,7 @@ static int __init setup_tcm_pool(void)
                        }
                        pr_debug("CPU ITCM: Added %08x bytes @ %08x to " \
                                 "the TCM memory pool\n",
-                                ITCM_END - itcm_pool_start + 1,
+                                itcm_end - itcm_pool_start,
                                 itcm_pool_start);
                }
        }

diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 1621e5327b2a72a6c9197e95615928e749aa5f41..cda78d59aa31b2971ed897b9db78afd6bfb0f36e 100644 (file)
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -30,6 +30,7 @@
 #include <asm/unistd.h>
 #include <asm/traps.h>
 #include <asm/unwind.h>
+#include <asm/tls.h>
 
 #include "ptrace.h"
 #include "signal.h"
@@ -518,17 +519,20 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
 
        case NR(set_tls):
                thread->tp_value = regs->ARM_r0;
-#if defined(CONFIG_HAS_TLS_REG)
-               asm ("mcr p15, 0, %0, c13, c0, 3" : : "r" (regs->ARM_r0) );
-#elif !defined(CONFIG_TLS_REG_EMUL)
-               /*
-                * User space must never try to access this directly.
-                * Expect your app to break eventually if you do so.
-                * The user helper at 0xffff0fe0 must be used instead.
-                * (see entry-armv.S for details)
-                */
-               *((unsigned int *)0xffff0ff0) = regs->ARM_r0;
-#endif
+               if (tls_emu)
+                       return 0;
+               if (has_tls_reg) {
+                       asm ("mcr p15, 0, %0, c13, c0, 3"
+                               : : "r" (regs->ARM_r0));
+               } else {
+                       /*
+                        * User space must never try to access this directly.
+                        * Expect your app to break eventually if you do so.
+                        * The user helper at 0xffff0fe0 must be used instead.
+                        * (see entry-armv.S for details)
+                        */
+                       *((unsigned int *)0xffff0ff0) = regs->ARM_r0;
+               }
                return 0;
 
 #ifdef CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG
@@ -743,6 +747,16 @@ void __init trap_init(void)
        return;
 }
 
+static void __init kuser_get_tls_init(unsigned long vectors)
+{
+       /*
+        * vectors + 0xfe0 = __kuser_get_tls
+        * vectors + 0xfe8 = hardware TLS instruction at 0xffff0fe8
+        */
+       if (tls_emu || has_tls_reg)
+               memcpy((void *)vectors + 0xfe0, (void *)vectors + 0xfe8, 4);
+}
+
 void __init early_trap_init(void)
 {
        unsigned long vectors = CONFIG_VECTORS_BASE;
@@ -760,6 +774,11 @@ void __init early_trap_init(void)
        memcpy((void *)vectors + 0x200, __stubs_start, __stubs_end - __stubs_start);
        memcpy((void *)vectors + 0x1000 - kuser_sz, __kuser_helper_start, kuser_sz);
 
+       /*
+        * Do processor specific fixups for the kuser helpers
+        */
+       kuser_get_tls_init(vectors);
+
        /*
         * Copy signal return handlers into the vector page, and
         * set sigreturn to be a pointer to these.

diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 030ba7219f482bfd9873b196d1a8634d5fc2eacb..59ff42ddf0aed656f3def2c44859f0eec414b1d3 100644 (file)
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -41,7 +41,6 @@ else
 endif
 
 lib-$(CONFIG_ARCH_RPC)         += ecard.o io-acorn.o floppydma.o
-lib-$(CONFIG_ARCH_L7200)       += io-acorn.o
 lib-$(CONFIG_ARCH_SHARK)       += io-shark.o
 
 $(obj)/csumpartialcopy.o:      $(obj)/csumpartialcopygeneric.S

diff --git a/arch/arm/mach-aaec2000/include/mach/memory.h b/arch/arm/mach-aaec2000/include/mach/memory.h
index c00822543d9f78a307c4a7c7f3c576db75c2efb4..4f93c567a35a3acb8969d5ae7951bfc2e8f008e4 100644 (file)
--- a/arch/arm/mach-aaec2000/include/mach/memory.h
+++ b/arch/arm/mach-aaec2000/include/mach/memory.h
@@ -14,14 +14,4 @@
 
 #define PHYS_OFFSET    UL(0xf0000000)
 
-/*
- * The nodes are the followings:
- *
- *   node 0: 0xf000.0000 - 0xf3ff.ffff
- *   node 1: 0xf400.0000 - 0xf7ff.ffff
- *   node 2: 0xf800.0000 - 0xfbff.ffff
- *   node 3: 0xfc00.0000 - 0xffff.ffff
- */
-#define NODE_MEM_SIZE_BITS     26
-
 #endif /* __ASM_ARCH_MEMORY_H */

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 841eaf8f27e221dfa600178e4d20ac0d56ddeaad..939bccd70569846987c6ddb304cd22c7de730bf7 100644 (file)
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -366,6 +366,17 @@ config MACH_STAMP9G20
 
 endif
 
+if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
+comment "AT91SAM9260/AT91SAM9G20 boards"
+
+config MACH_SNAPPER_9260
+        bool "Bluewater Systems Snapper 9260/9G20 module"
+        help
+          Select this if you are using the Bluewater Systems Snapper 9260 or
+          Snapper 9G20 modules.
+          <http://www.bluewatersys.com/>
+endif
+
 # ----------------------------------------------------------
 
 if ARCH_AT91SAM9G45

diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index c1f821e58222b77257e875c3ce5a72ea2be6429d..ca2ac003f41f5666fb8da8c1e23b34ab3e363ea6 100644 (file)
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -66,6 +66,9 @@ obj-$(CONFIG_MACH_CPU9G20)    += board-cpu9krea.o
 obj-$(CONFIG_MACH_STAMP9G20)   += board-stamp9g20.o
 obj-$(CONFIG_MACH_PORTUXG20)   += board-stamp9g20.o
 
+# AT91SAM9260/AT91SAM9G20 board-specific support
+obj-$(CONFIG_MACH_SNAPPER_9260)        += board-snapper9260.o
+
 # AT91SAM9G45 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o
 

diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 85166b7e69a18235969336742526c2961c486d66..753c0d31a3d3f0b407cfe20b68f5ba66189cd1a7 100644 (file)
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -20,6 +20,7 @@
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
 #include <mach/at91_shdwc.h>
+#include <mach/cpu.h>
 
 #include "generic.h"
 #include "clock.h"
@@ -176,6 +177,13 @@ static struct clk mmc1_clk = {
        .type           = CLK_TYPE_PERIPHERAL,
 };
 
+/* Video decoder clock - Only for sam9m10/sam9m11 */
+static struct clk vdec_clk = {
+       .name           = "vdec_clk",
+       .pmc_mask       = 1 << AT91SAM9G45_ID_VDEC,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+
 /* One additional fake clock for ohci */
 static struct clk ohci_clk = {
        .name           = "ohci_clk",
@@ -239,6 +247,9 @@ static void __init at91sam9g45_register_clocks(void)
        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
                clk_register(periph_clocks[i]);
 
+       if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
+               clk_register(&vdec_clk);
+
        clk_register(&pck0);
        clk_register(&pck1);
 }

diff --git a/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c b/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c
index a4102d72cc9b1c8e9d323f432fb5873b2144cc44..c49f5c003ee10d9fbad7a6f076f0e1dc58b0d653 100644 (file)
--- a/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c
+++ b/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c
@@ -26,6 +26,9 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/at73c213.h>
 #include <linux/clk.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/consumer.h>
 
 #include <mach/hardware.h>
 #include <asm/setup.h>
@@ -235,6 +238,46 @@ static struct gpio_led ek_leds[] = {
        }
 };
 
+#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
+static struct regulator_consumer_supply ek_audio_consumer_supplies[] = {
+       REGULATOR_SUPPLY("AVDD", "0-001b"),
+       REGULATOR_SUPPLY("HPVDD", "0-001b"),
+       REGULATOR_SUPPLY("DBVDD", "0-001b"),
+       REGULATOR_SUPPLY("DCVDD", "0-001b"),
+};
+
+static struct regulator_init_data ek_avdd_reg_init_data = {
+       .constraints    = {
+               .name   = "3V3",
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+       },
+       .consumer_supplies = ek_audio_consumer_supplies,
+       .num_consumer_supplies = ARRAY_SIZE(ek_audio_consumer_supplies),
+};
+
+static struct fixed_voltage_config ek_vdd_pdata = {
+       .supply_name    = "board-3V3",
+       .microvolts     = 3300000,
+       .gpio           = -EINVAL,
+       .enabled_at_boot = 0,
+       .init_data      = &ek_avdd_reg_init_data,
+};
+static struct platform_device ek_voltage_regulator = {
+       .name           = "reg-fixed-voltage",
+       .id             = -1,
+       .num_resources  = 0,
+       .dev            = {
+               .platform_data  = &ek_vdd_pdata,
+       },
+};
+static void __init ek_add_regulators(void)
+{
+       platform_device_register(&ek_voltage_regulator);
+}
+#else
+static void __init ek_add_regulators(void) {}
+#endif
+
 static struct i2c_board_info __initdata ek_i2c_devices[] = {
        {
                I2C_BOARD_INFO("24c512", 0x50),
@@ -256,6 +299,8 @@ static void __init ek_board_init(void)
        ek_add_device_nand();
        /* Ethernet */
        at91_add_device_eth(&ek_macb_data);
+       /* Regulators */
+       ek_add_regulators();
        /* MMC */
 #if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
        at91_add_device_mci(0, &ek_mmc_data);

diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index c11fd47aec5d464a9f228f19a9ac79097ebcaf46..6ea9808b8868d53a0c7cefd1926f921eadd82633 100644 (file)
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -27,6 +27,9 @@
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <linux/clk.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/consumer.h>
 
 #include <mach/hardware.h>
 #include <asm/setup.h>
@@ -269,6 +272,46 @@ static void __init ek_add_device_buttons(void)
 static void __init ek_add_device_buttons(void) {}
 #endif
 
+#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
+static struct regulator_consumer_supply ek_audio_consumer_supplies[] = {
+       REGULATOR_SUPPLY("AVDD", "0-001b"),
+       REGULATOR_SUPPLY("HPVDD", "0-001b"),
+       REGULATOR_SUPPLY("DBVDD", "0-001b"),
+       REGULATOR_SUPPLY("DCVDD", "0-001b"),
+};
+
+static struct regulator_init_data ek_avdd_reg_init_data = {
+       .constraints    = {
+               .name   = "3V3",
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+       },
+       .consumer_supplies = ek_audio_consumer_supplies,
+       .num_consumer_supplies = ARRAY_SIZE(ek_audio_consumer_supplies),
+};
+
+static struct fixed_voltage_config ek_vdd_pdata = {
+       .supply_name    = "board-3V3",
+       .microvolts     = 3300000,
+       .gpio           = -EINVAL,
+       .enabled_at_boot = 0,
+       .init_data      = &ek_avdd_reg_init_data,
+};
+static struct platform_device ek_voltage_regulator = {
+       .name           = "reg-fixed-voltage",
+       .id             = -1,
+       .num_resources  = 0,
+       .dev            = {
+               .platform_data  = &ek_vdd_pdata,
+       },
+};
+static void __init ek_add_regulators(void)
+{
+       platform_device_register(&ek_voltage_regulator);
+}
+#else
+static void __init ek_add_regulators(void) {}
+#endif
+
 
 static struct i2c_board_info __initdata ek_i2c_devices[] = {
         {
@@ -294,6 +337,8 @@ static void __init ek_board_init(void)
        ek_add_device_nand();
        /* Ethernet */
        at91_add_device_eth(&ek_macb_data);
+       /* Regulators */
+       ek_add_regulators();
        /* MMC */
        at91_add_device_mmc(0, &ek_mmc_data);
        /* I2C */

diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
new file mode 100644 (file)
index 0000000..2c08ae4
--- /dev/null
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -0,0 +1,189 @@
+/*
+ * linux/arch/arm/mach-at91/board-snapper9260.c
+ *
+ *  Copyright (C) 2010 Bluewater System Ltd
+ *
+ * Author: Andre Renaud <andre@bluewatersys.com>
+ * Author: Ryan Mallon  <ryan@bluewatersys.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/i2c/pca953x.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/hardware.h>
+#include <mach/board.h>
+#include <mach/at91sam9_smc.h>
+
+#include "sam9_smc.h"
+#include "generic.h"
+
+#define SNAPPER9260_IO_EXP_GPIO(x)     (NR_BUILTIN_GPIO + (x))
+
+static void __init snapper9260_map_io(void)
+{
+       at91sam9260_initialize(18432000);
+
+       /* Debug on ttyS0 */
+       at91_register_uart(0, 0, 0);
+       at91_set_serial_console(0);
+
+       at91_register_uart(AT91SAM9260_ID_US0, 1,
+                          ATMEL_UART_CTS | ATMEL_UART_RTS);
+       at91_register_uart(AT91SAM9260_ID_US1, 2,
+                          ATMEL_UART_CTS | ATMEL_UART_RTS);
+       at91_register_uart(AT91SAM9260_ID_US2, 3, 0);
+}
+
+static void __init snapper9260_init_irq(void)
+{
+       at91sam9260_init_interrupts(NULL);
+}
+
+static struct at91_usbh_data __initdata snapper9260_usbh_data = {
+       .ports          = 2,
+};
+
+static struct at91_udc_data __initdata snapper9260_udc_data = {
+       .vbus_pin               = SNAPPER9260_IO_EXP_GPIO(5),
+       .vbus_active_low        = 1,
+       .vbus_polled            = 1,
+};
+
+static struct at91_eth_data snapper9260_macb_data = {
+       .is_rmii        = 1,
+};
+
+static struct mtd_partition __initdata snapper9260_nand_partitions[] = {
+       {
+               .name   = "Preboot",
+               .offset = 0,
+               .size   = SZ_128K,
+       },
+       {
+               .name   = "Bootloader",
+               .offset = MTDPART_OFS_APPEND,
+               .size   = SZ_256K,
+       },
+       {
+               .name   = "Environment",
+               .offset = MTDPART_OFS_APPEND,
+               .size   = SZ_128K,
+       },
+       {
+               .name   = "Kernel",
+               .offset = MTDPART_OFS_APPEND,
+               .size   = SZ_4M,
+       },
+       {
+               .name   = "Filesystem",
+               .offset = MTDPART_OFS_APPEND,
+               .size   = MTDPART_SIZ_FULL,
+       },
+};
+
+static struct mtd_partition * __init
+snapper9260_nand_partition_info(int size, int *num_partitions)
+{
+       *num_partitions = ARRAY_SIZE(snapper9260_nand_partitions);
+       return snapper9260_nand_partitions;
+}
+
+static struct atmel_nand_data __initdata snapper9260_nand_data = {
+       .ale            = 21,
+       .cle            = 22,
+       .rdy_pin        = AT91_PIN_PC13,
+       .partition_info = snapper9260_nand_partition_info,
+       .bus_width_16   = 0,
+};
+
+static struct sam9_smc_config __initdata snapper9260_nand_smc_config = {
+       .ncs_read_setup         = 0,
+       .nrd_setup              = 0,
+       .ncs_write_setup        = 0,
+       .nwe_setup              = 0,
+
+       .ncs_read_pulse         = 5,
+       .nrd_pulse              = 2,
+       .ncs_write_pulse        = 5,
+       .nwe_pulse              = 2,
+
+       .read_cycle             = 7,
+       .write_cycle            = 7,
+
+       .mode                   = (AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+                                  AT91_SMC_EXNWMODE_DISABLE),
+       .tdf_cycles             = 1,
+};
+
+static struct pca953x_platform_data snapper9260_io_expander_data = {
+       .gpio_base              = SNAPPER9260_IO_EXP_GPIO(0),
+};
+
+static struct i2c_board_info __initdata snapper9260_i2c_devices[] = {
+       {
+               /* IO expander */
+               I2C_BOARD_INFO("max7312", 0x28),
+               .platform_data = &snapper9260_io_expander_data,
+       },
+       {
+               /* Audio codec */
+               I2C_BOARD_INFO("tlv320aic23", 0x1a),
+       },
+       {
+               /* RTC */
+               I2C_BOARD_INFO("isl1208", 0x6f),
+       },
+};
+
+static void __init snapper9260_add_device_nand(void)
+{
+       at91_set_A_periph(AT91_PIN_PC14, 0);
+       sam9_smc_configure(3, &snapper9260_nand_smc_config);
+       at91_add_device_nand(&snapper9260_nand_data);
+}
+
+static void __init snapper9260_board_init(void)
+{
+       at91_add_device_i2c(snapper9260_i2c_devices,
+                           ARRAY_SIZE(snapper9260_i2c_devices));
+       at91_add_device_serial();
+       at91_add_device_usbh(&snapper9260_usbh_data);
+       at91_add_device_udc(&snapper9260_udc_data);
+       at91_add_device_eth(&snapper9260_macb_data);
+       at91_add_device_ssc(AT91SAM9260_ID_SSC, (ATMEL_SSC_TF | ATMEL_SSC_TK |
+                                                ATMEL_SSC_TD | ATMEL_SSC_RD));
+       snapper9260_add_device_nand();
+}
+
+MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module")
+       .phys_io        = AT91_BASE_SYS,
+       .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+       .boot_params    = AT91_SDRAM_BASE + 0x100,
+       .timer          = &at91sam926x_timer,
+       .map_io         = snapper9260_map_io,
+       .init_irq       = snapper9260_init_irq,
+       .init_machine   = snapper9260_board_init,
+MACHINE_END
+
+

diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h
index d8c1ededaa75aea4ab8835ade94c2dda544068f7..9c6af97374851a72d2481a0fc4b03ba64781eff8 100644 (file)
--- a/arch/arm/mach-at91/include/mach/at91cap9.h
+++ b/arch/arm/mach-at91/include/mach/at91cap9.h
@@ -84,7 +84,7 @@
  */
 #define AT91_ECC       (0xffffe200 - AT91_BASE_SYS)
 #define AT91_BCRAMC    (0xffffe400 - AT91_BASE_SYS)
-#define AT91_DDRSDRC   (0xffffe600 - AT91_BASE_SYS)
+#define AT91_DDRSDRC0  (0xffffe600 - AT91_BASE_SYS)
 #define AT91_SMC       (0xffffe800 - AT91_BASE_SYS)
 #define AT91_MATRIX    (0xffffea00 - AT91_BASE_SYS)
 #define AT91_CCFG      (0xffffeb10 - AT91_BASE_SYS)

diff --git a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
index 1499b1cbffddbe6c3f0ff3d70617d2314d574ab4..976f4a6c33532e85e6a8053df737cf638c820827 100644 (file)
--- a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
@@ -15,7 +15,7 @@
 #ifndef AT91CAP9_DDRSDR_H
 #define AT91CAP9_DDRSDR_H
 
-#define AT91_DDRSDRC_MR                (AT91_DDRSDRC + 0x00)   /* Mode Register */
+#define AT91_DDRSDRC_MR                0x00    /* Mode Register */
 #define                AT91_DDRSDRC_MODE       (0xf << 0)              /* Command Mode */
 #define                        AT91_DDRSDRC_MODE_NORMAL                0
 #define                        AT91_DDRSDRC_MODE_NOP           1
@@ -25,10 +25,10 @@
 #define                        AT91_DDRSDRC_MODE_EXT_LMR       5
 #define                        AT91_DDRSDRC_MODE_DEEP          6
 
-#define AT91_DDRSDRC_RTR       (AT91_DDRSDRC + 0x04)   /* Refresh Timer Register */
+#define AT91_DDRSDRC_RTR       0x04    /* Refresh Timer Register */
 #define                AT91_DDRSDRC_COUNT      (0xfff << 0)            /* Refresh Timer Counter */
 
-#define AT91_DDRSDRC_CR                (AT91_DDRSDRC + 0x08)   /* Configuration Register */
+#define AT91_DDRSDRC_CR                0x08    /* Configuration Register */
 #define                AT91_DDRSDRC_NC         (3 << 0)                /* Number of Column Bits */
 #define                        AT91_DDRSDRC_NC_SDR8    (0 << 0)
 #define                        AT91_DDRSDRC_NC_SDR9    (1 << 0)
@@ -49,7 +49,7 @@
 #define                AT91_DDRSDRC_DLL        (1 << 7)                /* Reset DLL */
 #define                AT91_DDRSDRC_DICDS      (1 << 8)                /* Output impedance control */
 
-#define AT91_DDRSDRC_T0PR      (AT91_DDRSDRC + 0x0C)   /* Timing 0 Register */
+#define AT91_DDRSDRC_T0PR      0x0C    /* Timing 0 Register */
 #define                AT91_DDRSDRC_TRAS       (0xf <<  0)             /* Active to Precharge delay */
 #define                AT91_DDRSDRC_TRCD       (0xf <<  4)             /* Row to Column delay */
 #define                AT91_DDRSDRC_TWR        (0xf <<  8)             /* Write recovery delay */
@@ -59,13 +59,13 @@
 #define                AT91_DDRSDRC_TWTR       (1   << 24)             /* Internal Write to Read delay */
 #define                AT91_DDRSDRC_TMRD       (0xf << 28)             /* Load mode to active/refresh delay */
 
-#define AT91_DDRSDRC_T1PR      (AT91_DDRSDRC + 0x10)   /* Timing 1 Register */
+#define AT91_DDRSDRC_T1PR      0x10    /* Timing 1 Register */
 #define                AT91_DDRSDRC_TRFC       (0x1f << 0)             /* Row Cycle Delay */
 #define                AT91_DDRSDRC_TXSNR      (0xff << 8)             /* Exit self-refresh to non-read */
 #define                AT91_DDRSDRC_TXSRD      (0xff << 16)            /* Exit self-refresh to read */
 #define                AT91_DDRSDRC_TXP        (0xf  << 24)            /* Exit power-down delay */
 
-#define AT91_DDRSDRC_LPR       (AT91_DDRSDRC + 0x18)   /* Low Power Register */
+#define AT91_DDRSDRC_LPR       0x18    /* Low Power Register */
 #define                AT91_DDRSDRC_LPCB               (3 << 0)        /* Low-power Configurations */
 #define                        AT91_DDRSDRC_LPCB_DISABLE               0
 #define                        AT91_DDRSDRC_LPCB_SELF_REFRESH          1
@@ -80,14 +80,14 @@
 #define                        AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES      (1 << 12)
 #define                        AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES     (2 << 12)
 
-#define AT91_DDRSDRC_MDR       (AT91_DDRSDRC + 0x1C)   /* Memory Device Register */
+#define AT91_DDRSDRC_MDR       0x1C    /* Memory Device Register */
 #define                AT91_DDRSDRC_MD         (3 << 0)                /* Memory Device Type */
 #define                        AT91_DDRSDRC_MD_SDR             0
 #define                        AT91_DDRSDRC_MD_LOW_POWER_SDR   1
 #define                        AT91_DDRSDRC_MD_DDR             2
 #define                        AT91_DDRSDRC_MD_LOW_POWER_DDR   3
 
-#define AT91_DDRSDRC_DLLR      (AT91_DDRSDRC + 0x20)   /* DLL Information Register */
+#define AT91_DDRSDRC_DLLR      0x20    /* DLL Information Register */
 #define                AT91_DDRSDRC_MDINC      (1 << 0)                /* Master Delay increment */
 #define                AT91_DDRSDRC_MDDEC      (1 << 1)                /* Master Delay decrement */
 #define                AT91_DDRSDRC_MDOVF      (1 << 2)                /* Master Delay Overflow */
@@ -98,5 +98,11 @@
 #define                AT91_DDRSDRC_SDVAL      (0xff << 16)            /* Slave Delay value */
 #define                AT91_DDRSDRC_SDCVAL     (0xff << 24)            /* Slave Delay Correction value */
 
+/* Register access macros */
+#define at91_ramc_read(num, reg) \
+       at91_sys_read(AT91_DDRSDRC##num + reg)
+#define at91_ramc_write(num, reg, value) \
+       at91_sys_write(AT91_DDRSDRC##num + reg, value)
+
 
 #endif

diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index 43c396b9b4cb8cc1ceedf44bf24fe62ff225c880..4e79036d3b801849ea8f547e6dd6fdf8b16d894e 100644 (file)
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -84,7 +84,7 @@
  * System Peripherals (offset from AT91_BASE_SYS)
  */
 #define AT91_ECC       (0xffffe800 - AT91_BASE_SYS)
-#define AT91_SDRAMC    (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SDRAMC0   (0xffffea00 - AT91_BASE_SYS)
 #define AT91_SMC       (0xffffec00 - AT91_BASE_SYS)
 #define AT91_MATRIX    (0xffffee00 - AT91_BASE_SYS)
 #define AT91_CCFG      (0xffffef10 - AT91_BASE_SYS)

diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 87de8be17484be6966c7ee02bcf4a94620932e63..2b561851812952fe60e8b44fa1d44641fcdd81bc 100644 (file)
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -68,7 +68,7 @@
 /*
  * System Peripherals (offset from AT91_BASE_SYS)
  */
-#define AT91_SDRAMC    (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SDRAMC0   (0xffffea00 - AT91_BASE_SYS)
 #define AT91_SMC       (0xffffec00 - AT91_BASE_SYS)
 #define AT91_MATRIX    (0xffffee00 - AT91_BASE_SYS)
 #define AT91_AIC       (0xfffff000 - AT91_BASE_SYS)

diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
new file mode 100644 (file)
index 0000000..d27b15b
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -0,0 +1,130 @@
+/*
+ * Header file for the Atmel DDR/SDR SDRAM Controller
+ *
+ * Copyright (C) 2010 Atmel Corporation
+ *     Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef AT91SAM9_DDRSDR_H
+#define AT91SAM9_DDRSDR_H
+
+#define AT91_DDRSDRC_MR                0x00    /* Mode Register */
+#define                AT91_DDRSDRC_MODE       (0x7 << 0)              /* Command Mode */
+#define                        AT91_DDRSDRC_MODE_NORMAL        0
+#define                        AT91_DDRSDRC_MODE_NOP           1
+#define                        AT91_DDRSDRC_MODE_PRECHARGE     2
+#define                        AT91_DDRSDRC_MODE_LMR           3
+#define                        AT91_DDRSDRC_MODE_REFRESH       4
+#define                        AT91_DDRSDRC_MODE_EXT_LMR       5
+#define                        AT91_DDRSDRC_MODE_DEEP          6
+
+#define AT91_DDRSDRC_RTR       0x04    /* Refresh Timer Register */
+#define                AT91_DDRSDRC_COUNT      (0xfff << 0)            /* Refresh Timer Counter */
+
+#define AT91_DDRSDRC_CR                0x08    /* Configuration Register */
+#define                AT91_DDRSDRC_NC         (3 << 0)                /* Number of Column Bits */
+#define                        AT91_DDRSDRC_NC_SDR8    (0 << 0)
+#define                        AT91_DDRSDRC_NC_SDR9    (1 << 0)
+#define                        AT91_DDRSDRC_NC_SDR10   (2 << 0)
+#define                        AT91_DDRSDRC_NC_SDR11   (3 << 0)
+#define                        AT91_DDRSDRC_NC_DDR9    (0 << 0)
+#define                        AT91_DDRSDRC_NC_DDR10   (1 << 0)
+#define                        AT91_DDRSDRC_NC_DDR11   (2 << 0)
+#define                        AT91_DDRSDRC_NC_DDR12   (3 << 0)
+#define                AT91_DDRSDRC_NR         (3 << 2)                /* Number of Row Bits */
+#define                        AT91_DDRSDRC_NR_11      (0 << 2)
+#define                        AT91_DDRSDRC_NR_12      (1 << 2)
+#define                        AT91_DDRSDRC_NR_13      (2 << 2)
+#define                        AT91_DDRSDRC_NR_14      (3 << 2)
+#define                AT91_DDRSDRC_CAS        (7 << 4)                /* CAS Latency */
+#define                        AT91_DDRSDRC_CAS_2      (2 << 4)
+#define                        AT91_DDRSDRC_CAS_3      (3 << 4)
+#define                        AT91_DDRSDRC_CAS_25     (6 << 4)
+#define                AT91_DDRSDRC_RST_DLL    (1 << 7)                /* Reset DLL */
+#define                AT91_DDRSDRC_DICDS      (1 << 8)                /* Output impedance control */
+#define                AT91_DDRSDRC_DIS_DLL    (1 << 9)                /* Disable DLL */
+#define                AT91_DDRSDRC_OCD        (1 << 12)               /* Off-Chip Driver */
+#define                AT91_DDRSDRC_DQMS       (1 << 16)               /* Mask Data is Shared */
+#define                AT91_DDRSDRC_ACTBST     (1 << 18)               /* Active Bank X to Burst Stop Read Access Bank Y */
+
+#define AT91_DDRSDRC_T0PR      0x0C    /* Timing 0 Register */
+#define                AT91_DDRSDRC_TRAS       (0xf <<  0)             /* Active to Precharge delay */
+#define                AT91_DDRSDRC_TRCD       (0xf <<  4)             /* Row to Column delay */
+#define                AT91_DDRSDRC_TWR        (0xf <<  8)             /* Write recovery delay */
+#define                AT91_DDRSDRC_TRC        (0xf << 12)             /* Row cycle delay */
+#define                AT91_DDRSDRC_TRP        (0xf << 16)             /* Row precharge delay */
+#define                AT91_DDRSDRC_TRRD       (0xf << 20)             /* Active BankA to BankB */
+#define                AT91_DDRSDRC_TWTR       (0x7 << 24)             /* Internal Write to Read delay */
+#define                AT91_DDRSDRC_RED_WRRD   (0x1 << 27)             /* Reduce Write to Read Delay */
+#define                AT91_DDRSDRC_TMRD       (0xf << 28)             /* Load mode to active/refresh delay */
+
+#define AT91_DDRSDRC_T1PR      0x10    /* Timing 1 Register */
+#define                AT91_DDRSDRC_TRFC       (0x1f << 0)             /* Row Cycle Delay */
+#define                AT91_DDRSDRC_TXSNR      (0xff << 8)             /* Exit self-refresh to non-read */
+#define                AT91_DDRSDRC_TXSRD      (0xff << 16)            /* Exit self-refresh to read */
+#define                AT91_DDRSDRC_TXP        (0xf  << 24)            /* Exit power-down delay */
+
+#define AT91_DDRSDRC_T2PR      0x14    /* Timing 2 Register */
+#define                AT91_DDRSDRC_TXARD      (0xf  << 0)             /* Exit active power down delay to read command in mode "Fast Exit" */
+#define                AT91_DDRSDRC_TXARDS     (0xf  << 4)             /* Exit active power down delay to read command in mode "Slow Exit" */
+#define                AT91_DDRSDRC_TRPA       (0xf  << 8)             /* Row Precharge All delay */
+#define                AT91_DDRSDRC_TRTP       (0x7  << 12)            /* Read to Precharge delay */
+
+#define AT91_DDRSDRC_LPR       0x1C    /* Low Power Register */
+#define                AT91_DDRSDRC_LPCB       (3 << 0)                /* Low-power Configurations */
+#define                        AT91_DDRSDRC_LPCB_DISABLE               0
+#define                        AT91_DDRSDRC_LPCB_SELF_REFRESH          1
+#define                        AT91_DDRSDRC_LPCB_POWER_DOWN            2
+#define                        AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN       3
+#define                AT91_DDRSDRC_CLKFR      (1 << 2)        /* Clock Frozen */
+#define                AT91_DDRSDRC_PASR       (7 << 4)        /* Partial Array Self Refresh */
+#define                AT91_DDRSDRC_TCSR       (3 << 8)        /* Temperature Compensated Self Refresh */
+#define                AT91_DDRSDRC_DS         (3 << 10)       /* Drive Strength */
+#define                AT91_DDRSDRC_TIMEOUT    (3 << 12)       /* Time to define when Low Power Mode is enabled */
+#define                        AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES       (0 << 12)
+#define                        AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES      (1 << 12)
+#define                        AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES     (2 << 12)
+#define                AT91_DDRSDRC_APDE       (1 << 16)        /* Active power down exit time */
+#define                AT91_DDRSDRC_UPD_MR     (3 << 20)        /* Update load mode register and extended mode register */
+
+#define AT91_DDRSDRC_MDR       0x20    /* Memory Device Register */
+#define                AT91_DDRSDRC_MD         (3 << 0)                /* Memory Device Type */
+#define                        AT91_DDRSDRC_MD_SDR             0
+#define                        AT91_DDRSDRC_MD_LOW_POWER_SDR   1
+#define                        AT91_DDRSDRC_MD_LOW_POWER_DDR   3
+#define                        AT91_DDRSDRC_MD_DDR2            6
+#define                AT91_DDRSDRC_DBW        (1 << 4)                /* Data Bus Width */
+#define                        AT91_DDRSDRC_DBW_32BITS         (0 <<  4)
+#define                        AT91_DDRSDRC_DBW_16BITS         (1 <<  4)
+
+#define AT91_DDRSDRC_DLL       0x24    /* DLL Information Register */
+#define                AT91_DDRSDRC_MDINC      (1 << 0)                /* Master Delay increment */
+#define                AT91_DDRSDRC_MDDEC      (1 << 1)                /* Master Delay decrement */
+#define                AT91_DDRSDRC_MDOVF      (1 << 2)                /* Master Delay Overflow */
+#define                AT91_DDRSDRC_MDVAL      (0xff <<  8)            /* Master Delay value */
+
+#define AT91_DDRSDRC_HS                0x2C    /* High Speed Register */
+#define                AT91_DDRSDRC_DIS_ATCP_RD        (1 << 2)        /* Anticip read access is disabled */
+
+#define AT91_DDRSDRC_DELAY(n)  (0x30 + (0x4 * (n)))    /* Delay I/O Register n */
+
+#define AT91_DDRSDRC_WPMR      0xE4    /* Write Protect Mode Register */
+#define                AT91_DDRSDRC_WP         (1 << 0)                /* Write protect enable */
+#define                AT91_DDRSDRC_WPKEY      (0xffffff << 8)         /* Write protect key */
+#define                AT91_DDRSDRC_KEY        (0x444452 << 8)         /* Write protect key = "DDR" */
+
+#define AT91_DDRSDRC_WPSR      0xE8    /* Write Protect Status Register */
+#define                AT91_DDRSDRC_WPVS       (1 << 0)                /* Write protect violation status */
+#define                AT91_DDRSDRC_WPVSRC     (0xffff << 8)           /* Write protect violation source */
+
+/* Register access macros */
+#define at91_ramc_read(num, reg) \
+       at91_sys_read(AT91_DDRSDRC##num + reg)
+#define at91_ramc_write(num, reg, value) \
+       at91_sys_write(AT91_DDRSDRC##num + reg, value)
+
+#endif

diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
index b7260389f7cac2a51937143c10e55e3e75ee8aa9..100f5a592926356db536780996a7796ff6856e91 100644 (file)
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
@@ -17,7 +17,7 @@
 #define AT91SAM9_SDRAMC_H
 
 /* SDRAM Controller (SDRAMC) registers */
-#define AT91_SDRAMC_MR         (AT91_SDRAMC + 0x00)    /* SDRAM Controller Mode Register */
+#define AT91_SDRAMC_MR         0x00    /* SDRAM Controller Mode Register */
 #define                AT91_SDRAMC_MODE        (0xf << 0)              /* Command Mode */
 #define                        AT91_SDRAMC_MODE_NORMAL         0
 #define                        AT91_SDRAMC_MODE_NOP            1
@@ -27,10 +27,10 @@
 #define                        AT91_SDRAMC_MODE_EXT_LMR        5
 #define                        AT91_SDRAMC_MODE_DEEP           6
 
-#define AT91_SDRAMC_TR         (AT91_SDRAMC + 0x04)    /* SDRAM Controller Refresh Timer Register */
+#define AT91_SDRAMC_TR         0x04    /* SDRAM Controller Refresh Timer Register */
 #define                AT91_SDRAMC_COUNT       (0xfff << 0)            /* Refresh Timer Counter */
 
-#define AT91_SDRAMC_CR         (AT91_SDRAMC + 0x08)    /* SDRAM Controller Configuration Register */
+#define AT91_SDRAMC_CR         0x08    /* SDRAM Controller Configuration Register */
 #define                AT91_SDRAMC_NC          (3 << 0)                /* Number of Column Bits */
 #define                        AT91_SDRAMC_NC_8        (0 << 0)
 #define                        AT91_SDRAMC_NC_9        (1 << 0)
@@ -57,7 +57,7 @@
 #define                AT91_SDRAMC_TRAS        (0xf << 24)             /* Active to Precharge Delay */
 #define                AT91_SDRAMC_TXSR        (0xf << 28)             /* Exit Self Refresh to Active Delay */
 
-#define AT91_SDRAMC_LPR                (AT91_SDRAMC + 0x10)    /* SDRAM Controller Low Power Register */
+#define AT91_SDRAMC_LPR                0x10    /* SDRAM Controller Low Power Register */
 #define                AT91_SDRAMC_LPCB                (3 << 0)        /* Low-power Configurations */
 #define                        AT91_SDRAMC_LPCB_DISABLE                0
 #define                        AT91_SDRAMC_LPCB_SELF_REFRESH           1
@@ -71,16 +71,21 @@
 #define                        AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES       (1 << 12)
 #define                        AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES      (2 << 12)
 
-#define AT91_SDRAMC_IER                (AT91_SDRAMC + 0x14)    /* SDRAM Controller Interrupt Enable Register */
-#define AT91_SDRAMC_IDR                (AT91_SDRAMC + 0x18)    /* SDRAM Controller Interrupt Disable Register */
-#define AT91_SDRAMC_IMR                (AT91_SDRAMC + 0x1C)    /* SDRAM Controller Interrupt Mask Register */
-#define AT91_SDRAMC_ISR                (AT91_SDRAMC + 0x20)    /* SDRAM Controller Interrupt Status Register */
+#define AT91_SDRAMC_IER                0x14    /* SDRAM Controller Interrupt Enable Register */
+#define AT91_SDRAMC_IDR                0x18    /* SDRAM Controller Interrupt Disable Register */
+#define AT91_SDRAMC_IMR                0x1C    /* SDRAM Controller Interrupt Mask Register */
+#define AT91_SDRAMC_ISR                0x20    /* SDRAM Controller Interrupt Status Register */
 #define                AT91_SDRAMC_RES         (1 << 0)                /* Refresh Error Status */
 
-#define AT91_SDRAMC_MDR                (AT91_SDRAMC + 0x24)    /* SDRAM Memory Device Register */
+#define AT91_SDRAMC_MDR                0x24    /* SDRAM Memory Device Register */
 #define                AT91_SDRAMC_MD          (3 << 0)                /* Memory Device Type */
 #define                        AT91_SDRAMC_MD_SDRAM            0
 #define                        AT91_SDRAMC_MD_LOW_POWER_SDRAM  1
 
+/* Register access macros */
+#define at91_ramc_read(num, reg) \
+       at91_sys_read(AT91_SDRAMC##num + reg)
+#define at91_ramc_write(num, reg, value) \
+       at91_sys_write(AT91_SDRAMC##num + reg, value)
 
 #endif

diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index fc2de6c09c86a67c21073e405144ad17d94f8f64..87ba8517ad98291a12749853cfc7379e021c4997 100644 (file)
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -74,7 +74,7 @@
  */
 #define AT91_DMA       (0xffffe600 - AT91_BASE_SYS)
 #define AT91_ECC       (0xffffe800 - AT91_BASE_SYS)
-#define AT91_SDRAMC    (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SDRAMC0   (0xffffea00 - AT91_BASE_SYS)
 #define AT91_SMC       (0xffffec00 - AT91_BASE_SYS)
 #define AT91_MATRIX    (0xffffee00 - AT91_BASE_SYS)
 #define AT91_CCFG      (0xffffef10 - AT91_BASE_SYS)

diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index df2ed848c9f89b0e9f2e0bb3ee6a7c8d0fd631d5..58528aa9c8a86ddea8286cfb9ebdac7e26ed6942 100644 (file)
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -44,6 +44,8 @@
  /* USB Device */
 struct at91_udc_data {
        u8      vbus_pin;               /* high == host powering us */
+       u8      vbus_active_low;        /* vbus polarity */
+       u8      vbus_polled;            /* Use polling, not interrupt */
        u8      pullup_pin;             /* active == D+ pulled up */
        u8      pullup_active_low;      /* true == pullup_pin is active low */
 };

diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index 833659d1200ac057faff56ccd567de4ad718e09b..3bef931d0b1c915b5de540ee860dcf37cf27cba6 100644 (file)
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -52,6 +52,7 @@ static inline unsigned long at91_cpu_fully_identify(void)
 
 #define ARCH_EXID_AT91SAM9M11  0x00000001
 #define ARCH_EXID_AT91SAM9M10  0x00000002
+#define ARCH_EXID_AT91SAM9G46  0x00000003
 #define ARCH_EXID_AT91SAM9G45  0x00000004
 
 static inline unsigned long at91_exid_identify(void)
@@ -128,9 +129,18 @@ static inline unsigned long at91cap9_rev_identify(void)
 #ifdef CONFIG_ARCH_AT91SAM9G45
 #define cpu_is_at91sam9g45()   (at91_cpu_identify() == ARCH_ID_AT91SAM9G45)
 #define cpu_is_at91sam9g45es() (at91_cpu_fully_identify() == ARCH_ID_AT91SAM9G45ES)
+#define cpu_is_at91sam9m10()    (cpu_is_at91sam9g45() && \
+                                (at91_exid_identify() == ARCH_EXID_AT91SAM9M10))
+#define cpu_is_at91sam9m46()    (cpu_is_at91sam9g45() && \
+                                (at91_exid_identify() == ARCH_EXID_AT91SAM9G46))
+#define cpu_is_at91sam9m11()    (cpu_is_at91sam9g45() && \
+                                (at91_exid_identify() == ARCH_EXID_AT91SAM9M11))
 #else
 #define cpu_is_at91sam9g45()   (0)
 #define cpu_is_at91sam9g45es() (0)
+#define cpu_is_at91sam9m10()   (0)
+#define cpu_is_at91sam9g46()   (0)
+#define cpu_is_at91sam9m11()   (0)
 #endif
 
 #ifdef CONFIG_ARCH_AT91CAP9

diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index 04c91e31c9c5be8a7c20ca5a31b6ebef99963f89..bfdd8ab26dc8a2399a379058df2e9a04f41c2888 100644 (file)
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -19,6 +19,7 @@
 #define PIN_BASE               NR_AIC_IRQS
 
 #define MAX_GPIO_BANKS         5
+#define NR_BUILTIN_GPIO                (PIN_BASE + (MAX_GPIO_BANKS * 32))
 
 /* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
 

diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 08322c44df1a98d287c0247321158de4d41bb99c..8c87d0c1b8f8b9b9dc0383bff155798454a6460f 100644 (file)
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -30,14 +30,50 @@ static inline u32 sdram_selfrefresh_enable(void)
 {
        u32 saved_lpr, lpr;
 
-       saved_lpr = at91_sys_read(AT91_DDRSDRC_LPR);
+       saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR);
 
        lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
-       at91_sys_write(AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
+       at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
        return saved_lpr;
 }
 
-#define sdram_selfrefresh_disable(saved_lpr)   at91_sys_write(AT91_DDRSDRC_LPR, saved_lpr)
+#define sdram_selfrefresh_disable(saved_lpr)   at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr)
+
+#elif defined(CONFIG_ARCH_AT91SAM9G45)
+#include <mach/at91sam9_ddrsdr.h>
+
+/* We manage both DDRAM/SDRAM controllers, we need more than one value to
+ * remember.
+ */
+static u32 saved_lpr1;
+
+static inline u32 sdram_selfrefresh_enable(void)
+{
+       /* Those tow values allow us to delay self-refresh activation
+        * to the maximum. */
+       u32 lpr0, lpr1;
+       u32 saved_lpr0;
+
+       saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
+       lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
+       lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
+
+       saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
+       lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
+       lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
+
+       /* self-refresh mode now */
+       at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
+       at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
+
+       return saved_lpr0;
+}
+
+#define sdram_selfrefresh_disable(saved_lpr0)  \
+       do { \
+               at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \
+               at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \
+       } while (0)
 
 #else
 #include <mach/at91sam9_sdramc.h>
@@ -47,7 +83,6 @@ static inline u32 sdram_selfrefresh_enable(void)
  * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
  * handle those cases both here and in the Suspend-To-RAM support.
  */
-#define        AT91_SDRAMC     AT91_SDRAMC0
 #warning Assuming EB1 SDRAM controller is *NOT* used
 #endif
 
@@ -55,13 +90,13 @@ static inline u32 sdram_selfrefresh_enable(void)
 {
        u32 saved_lpr, lpr;
 
-       saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
+       saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
 
        lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
-       at91_sys_write(AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
+       at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
        return saved_lpr;
 }
 
-#define sdram_selfrefresh_disable(saved_lpr)   at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
+#define sdram_selfrefresh_disable(saved_lpr)   at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr)
 
 #endif

diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 9c5b48e68a71343e26f2f17c4856886fc0509373..b6b00a1f612546eb463036214455336381560e37 100644 (file)
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -16,10 +16,12 @@
 #include <mach/hardware.h>
 #include <mach/at91_pmc.h>
 
-#ifdef CONFIG_ARCH_AT91RM9200
+#if defined(CONFIG_ARCH_AT91RM9200)
 #include <mach/at91rm9200_mc.h>
 #elif defined(CONFIG_ARCH_AT91CAP9)
 #include <mach/at91cap9_ddrsdr.h>
+#elif defined(CONFIG_ARCH_AT91SAM9G45)
+#include <mach/at91sam9_ddrsdr.h>
 #else
 #include <mach/at91sam9_sdramc.h>
 #endif
@@ -30,7 +32,6 @@
  * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
  * handle those cases both here and in the Suspend-To-RAM support.
  */
-#define AT91_SDRAMC    AT91_SDRAMC0
 #warning Assuming EB1 SDRAM controller is *NOT* used
 #endif
 
@@ -113,12 +114,14 @@ ENTRY(at91_slow_clock)
        /*
         * Register usage:
         *  R1 = Base address of AT91_PMC
-        *  R2 = Base address of AT91_SDRAMC (or AT91_SYS on AT91RM9200)
+        *  R2 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
         *  R3 = temporary register
         *  R4 = temporary register
+        *  R5 = Base address of second RAM Controller or 0 if not present
         */
        ldr     r1, .at91_va_base_pmc
        ldr     r2, .at91_va_base_sdramc
+       ldr     r5, .at91_va_base_ramc1
 
        /* Drain write buffer */
        mcr     p15, 0, r0, c7, c10, 4
@@ -127,20 +130,33 @@ ENTRY(at91_slow_clock)
        /* Put SDRAM in self-refresh mode */
        mov     r3, #1
        str     r3, [r2, #AT91_SDRAMC_SRR]
-#elif defined(CONFIG_ARCH_AT91CAP9)
-       /* Enable SDRAM self-refresh mode */
-       ldr     r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
-       str     r3, .saved_sam9_lpr
+#elif defined(CONFIG_ARCH_AT91CAP9) \
+       || defined(CONFIG_ARCH_AT91SAM9G45)
 
-       mov     r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
-       str     r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
+       /* prepare for DDRAM self-refresh mode */
+       ldr     r3, [r2, #AT91_DDRSDRC_LPR]
+       str     r3, .saved_sam9_lpr
+       bic     r3, #AT91_DDRSDRC_LPCB
+       orr     r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
+
+       /* figure out if we use the second ram controller */
+       cmp     r5, #0
+       ldrne   r4, [r5, #AT91_DDRSDRC_LPR]
+       strne   r4, .saved_sam9_lpr1
+       bicne   r4, #AT91_DDRSDRC_LPCB
+       orrne   r4, #AT91_DDRSDRC_LPCB_SELF_REFRESH
+
+       /* Enable DDRAM self-refresh mode */
+       str     r3, [r2, #AT91_DDRSDRC_LPR]
+       strne   r4, [r5, #AT91_DDRSDRC_LPR]
 #else
        /* Enable SDRAM self-refresh mode */
-       ldr     r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
+       ldr     r3, [r2, #AT91_SDRAMC_LPR]
        str     r3, .saved_sam9_lpr
 
-       mov     r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
-       str     r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
+       bic     r3, #AT91_SDRAMC_LPCB
+       orr     r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
+       str     r3, [r2, #AT91_SDRAMC_LPR]
 #endif
 
        /* Save Master clock setting */
@@ -247,14 +263,21 @@ ENTRY(at91_slow_clock)
 
 #ifdef CONFIG_ARCH_AT91RM9200
        /* Do nothing - self-refresh is automatically disabled. */
-#elif defined(CONFIG_ARCH_AT91CAP9)
-       /* Restore LPR on AT91CAP9 */
+#elif defined(CONFIG_ARCH_AT91CAP9) \
+       || defined(CONFIG_ARCH_AT91SAM9G45)
+       /* Restore LPR on AT91 with DDRAM */
        ldr     r3, .saved_sam9_lpr
-       str     r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
+       str     r3, [r2, #AT91_DDRSDRC_LPR]
+
+       /* if we use the second ram controller */
+       cmp     r5, #0
+       ldrne   r4, .saved_sam9_lpr1
+       strne   r4, [r5, #AT91_DDRSDRC_LPR]
+
 #else
-       /* Restore LPR on AT91SAM9 */
+       /* Restore LPR on AT91 with SDRAM */
        ldr     r3, .saved_sam9_lpr
-       str     r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
+       str     r3, [r2, #AT91_SDRAMC_LPR]
 #endif
 
        /* Restore registers, and return */
@@ -273,18 +296,29 @@ ENTRY(at91_slow_clock)
 .saved_sam9_lpr:
        .word 0
 
+.saved_sam9_lpr1:
+       .word 0
+
 .at91_va_base_pmc:
        .word AT91_VA_BASE_SYS + AT91_PMC
 
 #ifdef CONFIG_ARCH_AT91RM9200
 .at91_va_base_sdramc:
        .word AT91_VA_BASE_SYS
-#elif defined(CONFIG_ARCH_AT91CAP9)
+#elif defined(CONFIG_ARCH_AT91CAP9) \
+       || defined(CONFIG_ARCH_AT91SAM9G45)
 .at91_va_base_sdramc:
-       .word AT91_VA_BASE_SYS + AT91_DDRSDRC
+       .word AT91_VA_BASE_SYS + AT91_DDRSDRC0
 #else
 .at91_va_base_sdramc:
-       .word AT91_VA_BASE_SYS + AT91_SDRAMC
+       .word AT91_VA_BASE_SYS + AT91_SDRAMC0
+#endif
+
+.at91_va_base_ramc1:
+#if defined(CONFIG_ARCH_AT91SAM9G45)
+       .word AT91_VA_BASE_SYS + AT91_DDRSDRC1
+#else
+       .word 0
 #endif
 
 ENTRY(at91_slow_clock_sz)

diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
index 72e405df0fb07dd4b363153f149742875725f7ad..d3f959e92b2dd2ef15e129a3bd79e52801811efe 100644 (file)
--- a/arch/arm/mach-bcmring/core.c
+++ b/arch/arm/mach-bcmring/core.c
@@ -91,14 +91,23 @@ static struct clk uart_clk = {
        .parent = &pll1_clk,
 };
 
+static struct clk dummy_apb_pclk = {
+       .name = "BUSCLK",
+       .type = CLK_TYPE_PRIMARY,
+       .mode = CLK_MODE_XTAL,
+};
+
 static struct clk_lookup lookups[] = {
-       {                       /* UART0 */
-        .dev_id = "uarta",
-        .clk = &uart_clk,
-        }, {                   /* UART1 */
-            .dev_id = "uartb",
-            .clk = &uart_clk,
-            }
+       {                       /* Bus clock */
+               .con_id = "apb_pclk",
+               .clk = &dummy_apb_pclk,
+       }, {                    /* UART0 */
+               .dev_id = "uarta",
+               .clk = &uart_clk,
+       }, {                    /* UART1 */
+               .dev_id = "uartb",
+               .clk = &uart_clk,
+       }
 };
 
 static struct amba_device *amba_devs[] __initdata = {

diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
index dbaae5f746a1ced107faf56439c7f2bf71bc845c..eb34bd1251d491224f95216ca882070baa5933ce 100644 (file)
--- a/arch/arm/mach-clps711x/Kconfig
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -30,7 +30,6 @@ config ARCH_CLEP7312
 config ARCH_EDB7211
        bool "EDB7211"
        select ISA
-       select ARCH_DISCONTIGMEM_ENABLE
        select ARCH_SPARSEMEM_ENABLE
        select ARCH_SELECT_MEMORY_MODEL
        help

diff --git a/arch/arm/mach-clps711x/clep7312.c b/arch/arm/mach-clps711x/clep7312.c
index 09fb57e452130d0766f4fe3eab0219138572ea13..3c3bf45039ff05f44c122adbc3bb1cceded613ab 100644 (file)
--- a/arch/arm/mach-clps711x/clep7312.c
+++ b/arch/arm/mach-clps711x/clep7312.c
@@ -32,7 +32,6 @@ fixup_clep7312(struct machine_desc *desc, struct tag *tags,
        mi->nr_banks=1;
        mi->bank[0].start = 0xc0000000;
        mi->bank[0].size = 0x01000000;
-       mi->bank[0].node = 0;
 }
 
 

diff --git a/arch/arm/mach-clps711x/edb7211-arch.c b/arch/arm/mach-clps711x/edb7211-arch.c
index dc81cc68595de96edd2f9e2679d1cd855bace03f..4a7a2322979a17c3dcb833bf44122f8af51bba8a 100644 (file)
--- a/arch/arm/mach-clps711x/edb7211-arch.c
+++ b/arch/arm/mach-clps711x/edb7211-arch.c
@@ -18,6 +18,7 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 #include <linux/init.h>
+#include <linux/memblock.h>
 #include <linux/types.h>
 #include <linux/string.h>
 
@@ -29,6 +30,12 @@
 
 extern void edb7211_map_io(void);
 
+/* Reserve screen memory region at the start of main system memory. */
+static void __init edb7211_reserve(void)
+{
+       memblock_reserve(PHYS_OFFSET, 0x00020000);
+}
+
 static void __init
 fixup_edb7211(struct machine_desc *desc, struct tag *tags,
              char **cmdline, struct meminfo *mi)
@@ -43,10 +50,8 @@ fixup_edb7211(struct machine_desc *desc, struct tag *tags,
         */
        mi->bank[0].start = 0xc0000000;
        mi->bank[0].size = 8*1024*1024;
-       mi->bank[0].node = 0;
        mi->bank[1].start = 0xc1000000;
        mi->bank[1].size = 8*1024*1024;
-       mi->bank[1].node = 1;
        mi->nr_banks = 2;
 }
 
@@ -57,6 +62,7 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
        .boot_params    = 0xc0020100,   /* 0xc0000000 - 0xc001ffff can be video RAM */
        .fixup          = fixup_edb7211,
        .map_io         = edb7211_map_io,
+       .reserve        = edb7211_reserve,
        .init_irq       = clps711x_init_irq,
        .timer          = &clps711x_timer,
 MACHINE_END

diff --git a/arch/arm/mach-clps711x/fortunet.c b/arch/arm/mach-clps711x/fortunet.c
index 7430e4049d87b1ca789b372f2641c4088547c31c..a696099aa4f8f22ddd32e836b4bbb124acdc4ea0 100644 (file)
--- a/arch/arm/mach-clps711x/fortunet.c
+++ b/arch/arm/mach-clps711x/fortunet.c
@@ -39,7 +39,6 @@ struct meminfo memmap = {
                {
                        .start  = 0xC0000000,
                        .size   = 0x01000000,
-                       .node   = 0
                },
        },
 };

diff --git a/arch/arm/mach-clps711x/include/mach/memory.h b/arch/arm/mach-clps711x/include/mach/memory.h
index f70d52be48a2a61c88b7276a830b7b3abf17aee5..f45c8e892cb5a0ae9cdf0c9cd2c78c2dfa61bb07 100644 (file)
--- a/arch/arm/mach-clps711x/include/mach/memory.h
+++ b/arch/arm/mach-clps711x/include/mach/memory.h
@@ -20,7 +20,6 @@
 #ifndef __ASM_ARCH_MEMORY_H
 #define __ASM_ARCH_MEMORY_H
 
-
 /*
  * Physical DRAM offset.
  */
@@ -72,7 +71,6 @@
  *     node 2:  0xd0000000 - 0xd7ffffff
  *     node 3:  0xd8000000 - 0xdfffffff
  */
-#define NODE_MEM_SIZE_BITS     24
 #define SECTION_SIZE_BITS      24
 #define MAX_PHYSMEM_BITS       32
 

diff --git a/arch/arm/mach-cns3xxx/Makefile b/arch/arm/mach-cns3xxx/Makefile
index 427507a2d696255449456da00763562056bd731e..11033f1c2e23b82b52d96569fb4932be6a1a11c0 100644 (file)
--- a/arch/arm/mach-cns3xxx/Makefile
+++ b/arch/arm/mach-cns3xxx/Makefile
@@ -1,2 +1,3 @@
-obj-$(CONFIG_ARCH_CNS3XXX)             += core.o pm.o
+obj-$(CONFIG_ARCH_CNS3XXX)             += core.o pm.o devices.o
+obj-$(CONFIG_PCI)                      += pcie.o
 obj-$(CONFIG_MACH_CNS3420VB)           += cns3420vb.o

diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index 2e30c8288740b2a24752cdfe565a7e2bef5e77ca..9df8391fd78ac9ebfbb33425261ff9c631db79b1 100644 (file)
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -32,6 +32,7 @@
 #include <mach/cns3xxx.h>
 #include <mach/irqs.h>
 #include "core.h"
+#include "devices.h"
 
 /*
  * NOR Flash
@@ -117,6 +118,9 @@ static void __init cns3420_init(void)
 {
        platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
 
+       cns3xxx_ahci_init();
+       cns3xxx_sdhci_init();
+
        pm_power_off = cns3xxx_power_off;
 }
 

diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c
new file mode 100644 (file)
index 0000000..50b4d31
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/devices.c
@@ -0,0 +1,111 @@
+/*
+ * CNS3xxx common devices
+ *
+ * Copyright 2008 Cavium Networks
+ *               Scott Shu
+ * Copyright 2010 MontaVista Software, LLC.
+ *               Anton Vorontsov <avorontsov@mvista.com>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/compiler.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <mach/cns3xxx.h>
+#include <mach/irqs.h>
+#include "core.h"
+#include "devices.h"
+
+/*
+ * AHCI
+ */
+static struct resource cns3xxx_ahci_resource[] = {
+       [0] = {
+               .start  = CNS3XXX_SATA2_BASE,
+               .end    = CNS3XXX_SATA2_BASE + CNS3XXX_SATA2_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = IRQ_CNS3XXX_SATA,
+               .end    = IRQ_CNS3XXX_SATA,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device cns3xxx_ahci_pdev = {
+       .name           = "ahci",
+       .id             = 0,
+       .resource       = cns3xxx_ahci_resource,
+       .num_resources  = ARRAY_SIZE(cns3xxx_ahci_resource),
+       .dev            = {
+               .dma_mask               = &cns3xxx_ahci_dmamask,
+               .coherent_dma_mask      = DMA_BIT_MASK(32),
+       },
+};
+
+void __init cns3xxx_ahci_init(void)
+{
+       u32 tmp;
+
+       tmp = __raw_readl(MISC_SATA_POWER_MODE);
+       tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
+       tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
+       __raw_writel(tmp, MISC_SATA_POWER_MODE);
+
+       /* Enable SATA PHY */
+       cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
+       cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
+
+       /* Enable SATA Clock */
+       cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
+
+       /* De-Asscer SATA Reset */
+       cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
+
+       platform_device_register(&cns3xxx_ahci_pdev);
+}
+
+/*
+ * SDHCI
+ */
+static struct resource cns3xxx_sdhci_resources[] = {
+       [0] = {
+               .start = CNS3XXX_SDIO_BASE,
+               .end   = CNS3XXX_SDIO_BASE + SZ_4K - 1,
+               .flags = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start = IRQ_CNS3XXX_SDIO,
+               .end   = IRQ_CNS3XXX_SDIO,
+               .flags = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device cns3xxx_sdhci_pdev = {
+       .name           = "sdhci-cns3xxx",
+       .id             = 0,
+       .num_resources  = ARRAY_SIZE(cns3xxx_sdhci_resources),
+       .resource       = cns3xxx_sdhci_resources,
+};
+
+void __init cns3xxx_sdhci_init(void)
+{
+       u32 __iomem *gpioa = __io(CNS3XXX_MISC_BASE_VIRT + 0x0014);
+       u32 gpioa_pins = __raw_readl(gpioa);
+
+       /* MMC/SD pins share with GPIOA */
+       gpioa_pins |= 0x1fff0004;
+       __raw_writel(gpioa_pins, gpioa);
+
+       cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
+       cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
+
+       platform_device_register(&cns3xxx_sdhci_pdev);
+}

diff --git a/arch/arm/mach-cns3xxx/devices.h b/arch/arm/mach-cns3xxx/devices.h
new file mode 100644 (file)
index 0000000..27e15a1
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/devices.h
@@ -0,0 +1,20 @@
+/*
+ * CNS3xxx common devices
+ *
+ * Copyright 2008 Cavium Networks
+ *               Scott Shu
+ * Copyright 2010 MontaVista Software, LLC.
+ *               Anton Vorontsov <avorontsov@mvista.com>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __CNS3XXX_DEVICES_H_
+#define __CNS3XXX_DEVICES_H_
+
+void __init cns3xxx_ahci_init(void);
+void __init cns3xxx_sdhci_init(void);
+
+#endif /* __CNS3XXX_DEVICES_H_ */

diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
index 8a2f5a21d4ee3ab63843b6311606d55aaa298352..6dbce13771ca49c83c89dde5b4f0b6f734e20c1f 100644 (file)
--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
@@ -247,37 +247,36 @@
  * Misc block
  */
 #define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs))
-#define MISC_MEM_MAP_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_MISC_BASE_VIRT + (offset))))
-
-#define MISC_MEMORY_REMAP_REG                  MISC_MEM_MAP_VALUE(0x00)
-#define MISC_CHIP_CONFIG_REG                   MISC_MEM_MAP_VALUE(0x04)
-#define MISC_DEBUG_PROBE_DATA_REG              MISC_MEM_MAP_VALUE(0x08)
-#define MISC_DEBUG_PROBE_SELECTION_REG         MISC_MEM_MAP_VALUE(0x0C)
-#define MISC_IO_PIN_FUNC_SELECTION_REG         MISC_MEM_MAP_VALUE(0x10)
-#define MISC_GPIOA_PIN_ENABLE_REG              MISC_MEM_MAP_VALUE(0x14)
-#define MISC_GPIOB_PIN_ENABLE_REG              MISC_MEM_MAP_VALUE(0x18)
-#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A      MISC_MEM_MAP_VALUE(0x1C)
-#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B      MISC_MEM_MAP_VALUE(0x20)
-#define MISC_GPIOA_15_0_PULL_CTRL_REG          MISC_MEM_MAP_VALUE(0x24)
-#define MISC_GPIOA_16_31_PULL_CTRL_REG         MISC_MEM_MAP_VALUE(0x28)
-#define MISC_GPIOB_15_0_PULL_CTRL_REG          MISC_MEM_MAP_VALUE(0x2C)
-#define MISC_GPIOB_16_31_PULL_CTRL_REG         MISC_MEM_MAP_VALUE(0x30)
-#define MISC_IO_PULL_CTRL_REG                  MISC_MEM_MAP_VALUE(0x34)
-#define MISC_E_FUSE_31_0_REG                   MISC_MEM_MAP_VALUE(0x40)
-#define MISC_E_FUSE_63_32_REG                  MISC_MEM_MAP_VALUE(0x44)
-#define MISC_E_FUSE_95_64_REG                  MISC_MEM_MAP_VALUE(0x48)
-#define MISC_E_FUSE_127_96_REG                 MISC_MEM_MAP_VALUE(0x4C)
-#define MISC_SOFTWARE_TEST_1_REG               MISC_MEM_MAP_VALUE(0x50)
-#define MISC_SOFTWARE_TEST_2_REG               MISC_MEM_MAP_VALUE(0x54)
-
-#define MISC_SATA_POWER_MODE                   MISC_MEM_MAP_VALUE(0x310)
-
-#define MISC_USB_CFG_REG                       MISC_MEM_MAP_VALUE(0x800)
-#define MISC_USB_STS_REG                       MISC_MEM_MAP_VALUE(0x804)
-#define MISC_USBPHY00_CFG_REG                  MISC_MEM_MAP_VALUE(0x808)
-#define MISC_USBPHY01_CFG_REG                  MISC_MEM_MAP_VALUE(0x80c)
-#define MISC_USBPHY10_CFG_REG                  MISC_MEM_MAP_VALUE(0x810)
-#define MISC_USBPHY11_CFG_REG                  MISC_MEM_MAP_VALUE(0x814)
+
+#define MISC_MEMORY_REMAP_REG                  MISC_MEM_MAP(0x00)
+#define MISC_CHIP_CONFIG_REG                   MISC_MEM_MAP(0x04)
+#define MISC_DEBUG_PROBE_DATA_REG              MISC_MEM_MAP(0x08)
+#define MISC_DEBUG_PROBE_SELECTION_REG         MISC_MEM_MAP(0x0C)
+#define MISC_IO_PIN_FUNC_SELECTION_REG         MISC_MEM_MAP(0x10)
+#define MISC_GPIOA_PIN_ENABLE_REG              MISC_MEM_MAP(0x14)
+#define MISC_GPIOB_PIN_ENABLE_REG              MISC_MEM_MAP(0x18)
+#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A      MISC_MEM_MAP(0x1C)
+#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B      MISC_MEM_MAP(0x20)
+#define MISC_GPIOA_15_0_PULL_CTRL_REG          MISC_MEM_MAP(0x24)
+#define MISC_GPIOA_16_31_PULL_CTRL_REG         MISC_MEM_MAP(0x28)
+#define MISC_GPIOB_15_0_PULL_CTRL_REG          MISC_MEM_MAP(0x2C)
+#define MISC_GPIOB_16_31_PULL_CTRL_REG         MISC_MEM_MAP(0x30)
+#define MISC_IO_PULL_CTRL_REG                  MISC_MEM_MAP(0x34)
+#define MISC_E_FUSE_31_0_REG                   MISC_MEM_MAP(0x40)
+#define MISC_E_FUSE_63_32_REG                  MISC_MEM_MAP(0x44)
+#define MISC_E_FUSE_95_64_REG                  MISC_MEM_MAP(0x48)
+#define MISC_E_FUSE_127_96_REG                 MISC_MEM_MAP(0x4C)
+#define MISC_SOFTWARE_TEST_1_REG               MISC_MEM_MAP(0x50)
+#define MISC_SOFTWARE_TEST_2_REG               MISC_MEM_MAP(0x54)
+
+#define MISC_SATA_POWER_MODE                   MISC_MEM_MAP(0x310)
+
+#define MISC_USB_CFG_REG                       MISC_MEM_MAP(0x800)
+#define MISC_USB_STS_REG                       MISC_MEM_MAP(0x804)
+#define MISC_USBPHY00_CFG_REG                  MISC_MEM_MAP(0x808)
+#define MISC_USBPHY01_CFG_REG                  MISC_MEM_MAP(0x80c)
+#define MISC_USBPHY10_CFG_REG                  MISC_MEM_MAP(0x810)
+#define MISC_USBPHY11_CFG_REG                  MISC_MEM_MAP(0x814)
 
 #define MISC_PCIEPHY_CMCTL(x)                  MISC_MEM_MAP(0x900 + (x) * 0x004)
 #define MISC_PCIEPHY_CTL(x)                    MISC_MEM_MAP(0x940 + (x) * 0x100)
@@ -300,21 +299,21 @@
 /*
  * Power management and clock control
  */
-#define PMU_REG_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_PM_BASE_VIRT + (offset))))
-
-#define PM_CLK_GATE_REG                                        PMU_REG_VALUE(0x000)
-#define PM_SOFT_RST_REG                                        PMU_REG_VALUE(0x004)
-#define PM_HS_CFG_REG                                  PMU_REG_VALUE(0x008)
-#define PM_CACTIVE_STA_REG                             PMU_REG_VALUE(0x00C)
-#define PM_PWR_STA_REG                                 PMU_REG_VALUE(0x010)
-#define PM_CLK_CTRL_REG                                        PMU_REG_VALUE(0x014)
-#define PM_PLL_LCD_I2S_CTRL_REG                                PMU_REG_VALUE(0x018)
-#define PM_PLL_HM_PD_CTRL_REG                          PMU_REG_VALUE(0x01C)
-#define PM_REGULAT_CTRL_REG                            PMU_REG_VALUE(0x020)
-#define PM_WDT_CTRL_REG                                        PMU_REG_VALUE(0x024)
-#define PM_WU_CTRL0_REG                                        PMU_REG_VALUE(0x028)
-#define PM_WU_CTRL1_REG                                        PMU_REG_VALUE(0x02C)
-#define PM_CSR_REG                                     PMU_REG_VALUE(0x030)
+#define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs))
+
+#define PM_CLK_GATE_REG                                        PMU_MEM_MAP(0x000)
+#define PM_SOFT_RST_REG                                        PMU_MEM_MAP(0x004)
+#define PM_HS_CFG_REG                                  PMU_MEM_MAP(0x008)
+#define PM_CACTIVE_STA_REG                             PMU_MEM_MAP(0x00C)
+#define PM_PWR_STA_REG                                 PMU_MEM_MAP(0x010)
+#define PM_CLK_CTRL_REG                                        PMU_MEM_MAP(0x014)
+#define PM_PLL_LCD_I2S_CTRL_REG                                PMU_MEM_MAP(0x018)
+#define PM_PLL_HM_PD_CTRL_REG                          PMU_MEM_MAP(0x01C)
+#define PM_REGULAT_CTRL_REG                            PMU_MEM_MAP(0x020)
+#define PM_WDT_CTRL_REG                                        PMU_MEM_MAP(0x024)
+#define PM_WU_CTRL0_REG                                        PMU_MEM_MAP(0x028)
+#define PM_WU_CTRL1_REG                                        PMU_MEM_MAP(0x02C)
+#define PM_CSR_REG                                     PMU_MEM_MAP(0x030)
 
 /* PM_CLK_GATE_REG */
 #define PM_CLK_GATE_REG_OFFSET_SDIO                    (25)

diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
new file mode 100644 (file)
index 0000000..38088c3
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -0,0 +1,389 @@
+/*
+ * PCI-E support for CNS3xxx
+ *
+ * Copyright 2008 Cavium Networks
+ *               Richard Liu <richard.liu@caviumnetworks.com>
+ * Copyright 2010 MontaVista Software, LLC.
+ *               Anton Vorontsov <avorontsov@mvista.com>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/bug.h>
+#include <linux/pci.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/ptrace.h>
+#include <asm/mach/map.h>
+#include <mach/cns3xxx.h>
+#include "core.h"
+
+enum cns3xxx_access_type {
+       CNS3XXX_HOST_TYPE = 0,
+       CNS3XXX_CFG0_TYPE,
+       CNS3XXX_CFG1_TYPE,
+       CNS3XXX_NUM_ACCESS_TYPES,
+};
+
+struct cns3xxx_pcie {
+       struct map_desc cfg_bases[CNS3XXX_NUM_ACCESS_TYPES];
+       unsigned int irqs[2];
+       struct resource res_io;
+       struct resource res_mem;
+       struct hw_pci hw_pci;
+
+       bool linked;
+};
+
+static struct cns3xxx_pcie cns3xxx_pcie[]; /* forward decl. */
+
+static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata)
+{
+       struct pci_sys_data *root = sysdata;
+
+       return &cns3xxx_pcie[root->domain];
+}
+
+static struct cns3xxx_pcie *pdev_to_cnspci(struct pci_dev *dev)
+{
+       return sysdata_to_cnspci(dev->sysdata);
+}
+
+static struct cns3xxx_pcie *pbus_to_cnspci(struct pci_bus *bus)
+{
+       return sysdata_to_cnspci(bus->sysdata);
+}
+
+static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus,
+                                 unsigned int devfn, int where)
+{
+       struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
+       int busno = bus->number;
+       int slot = PCI_SLOT(devfn);
+       int offset;
+       enum cns3xxx_access_type type;
+       void __iomem *base;
+
+       /* If there is no link, just show the CNS PCI bridge. */
+       if (!cnspci->linked && (busno > 0 || slot > 0))
+               return NULL;
+
+       /*
+        * The CNS PCI bridge doesn't fit into the PCI hierarchy, though
+        * we still want to access it. For this to work, we must place
+        * the first device on the same bus as the CNS PCI bridge.
+        */
+       if (busno == 0) {
+               if (slot > 1)
+                       return NULL;
+               type = slot;
+       } else {
+               type = CNS3XXX_CFG1_TYPE;
+       }
+
+       base = (void __iomem *)cnspci->cfg_bases[type].virtual;
+       offset = ((busno & 0xf) << 20) | (devfn << 12) | (where & 0xffc);
+
+       return base + offset;
+}
+
+static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+                                  int where, int size, u32 *val)
+{
+       u32 v;
+       void __iomem *base;
+       u32 mask = (0x1ull << (size * 8)) - 1;
+       int shift = (where % 4) * 8;
+
+       base = cns3xxx_pci_cfg_base(bus, devfn, where);
+       if (!base) {
+               *val = 0xffffffff;
+               return PCIBIOS_SUCCESSFUL;
+       }
+
+       v = __raw_readl(base);
+
+       if (bus->number == 0 && devfn == 0 &&
+                       (where & 0xffc) == PCI_CLASS_REVISION) {
+               /*
+                * RC's class is 0xb, but Linux PCI driver needs 0x604
+                * for a PCIe bridge. So we must fixup the class code
+                * to 0x604 here.
+                */
+               v &= 0xff;
+               v |= 0x604 << 16;
+       }
+
+       *val = (v >> shift) & mask;
+
+       return PCIBIOS_SUCCESSFUL;
+}
+
+static int cns3xxx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+                                   int where, int size, u32 val)
+{
+       u32 v;
+       void __iomem *base;
+       u32 mask = (0x1ull << (size * 8)) - 1;
+       int shift = (where % 4) * 8;
+
+       base = cns3xxx_pci_cfg_base(bus, devfn, where);
+       if (!base)
+               return PCIBIOS_SUCCESSFUL;
+
+       v = __raw_readl(base);
+
+       v &= ~(mask << shift);
+       v |= (val & mask) << shift;
+
+       __raw_writel(v, base);
+
+       return PCIBIOS_SUCCESSFUL;
+}
+
+static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
+{
+       struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys);
+       struct resource *res_io = &cnspci->res_io;
+       struct resource *res_mem = &cnspci->res_mem;
+       struct resource **sysres = sys->resource;
+
+       BUG_ON(request_resource(&iomem_resource, res_io) ||
+              request_resource(&iomem_resource, res_mem));
+
+       sysres[0] = res_io;
+       sysres[1] = res_mem;
+
+       return 1;
+}
+
+static struct pci_ops cns3xxx_pcie_ops = {
+       .read = cns3xxx_pci_read_config,
+       .write = cns3xxx_pci_write_config,
+};
+
+static struct pci_bus *cns3xxx_pci_scan_bus(int nr, struct pci_sys_data *sys)
+{
+       return pci_scan_bus(sys->busnr, &cns3xxx_pcie_ops, sys);
+}
+
+static int cns3xxx_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+       struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
+       int irq = cnspci->irqs[slot];
+
+       pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
+               pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
+               PCI_FUNC(dev->devfn), slot, pin, irq);
+
+       return irq;
+}
+
+static struct cns3xxx_pcie cns3xxx_pcie[] = {
+       [0] = {
+               .cfg_bases = {
+                       [CNS3XXX_HOST_TYPE] = {
+                               .virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT,
+                               .pfn = __phys_to_pfn(CNS3XXX_PCIE0_HOST_BASE),
+                               .length = SZ_16M,
+                               .type = MT_DEVICE,
+                       },
+                       [CNS3XXX_CFG0_TYPE] = {
+                               .virtual = CNS3XXX_PCIE0_CFG0_BASE_VIRT,
+                               .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG0_BASE),
+                               .length = SZ_16M,
+                               .type = MT_DEVICE,
+                       },
+                       [CNS3XXX_CFG1_TYPE] = {
+                               .virtual = CNS3XXX_PCIE0_CFG1_BASE_VIRT,
+                               .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG1_BASE),
+                               .length = SZ_16M,
+                               .type = MT_DEVICE,
+                       },
+               },
+               .res_io = {
+                       .name = "PCIe0 I/O space",
+                       .start = CNS3XXX_PCIE0_IO_BASE,
+                       .end = CNS3XXX_PCIE0_IO_BASE + SZ_16M - 1,
+                       .flags = IORESOURCE_IO,
+               },
+               .res_mem = {
+                       .name = "PCIe0 non-prefetchable",
+                       .start = CNS3XXX_PCIE0_MEM_BASE,
+                       .end = CNS3XXX_PCIE0_MEM_BASE + SZ_16M - 1,
+                       .flags = IORESOURCE_MEM,
+               },
+               .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
+               .hw_pci = {
+                       .domain = 0,
+                       .swizzle = pci_std_swizzle,
+                       .nr_controllers = 1,
+                       .setup = cns3xxx_pci_setup,
+                       .scan = cns3xxx_pci_scan_bus,
+                       .map_irq = cns3xxx_pcie_map_irq,
+               },
+       },
+       [1] = {
+               .cfg_bases = {
+                       [CNS3XXX_HOST_TYPE] = {
+                               .virtual = CNS3XXX_PCIE1_HOST_BASE_VIRT,
+                               .pfn = __phys_to_pfn(CNS3XXX_PCIE1_HOST_BASE),
+                               .length = SZ_16M,
+                               .type = MT_DEVICE,
+                       },
+                       [CNS3XXX_CFG0_TYPE] = {
+                               .virtual = CNS3XXX_PCIE1_CFG0_BASE_VIRT,
+                               .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG0_BASE),
+                               .length = SZ_16M,
+                               .type = MT_DEVICE,
+                       },
+                       [CNS3XXX_CFG1_TYPE] = {
+                               .virtual = CNS3XXX_PCIE1_CFG1_BASE_VIRT,
+                               .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE),
+                               .length = SZ_16M,
+                               .type = MT_DEVICE,
+                       },
+               },
+               .res_io = {
+                       .name = "PCIe1 I/O space",
+                       .start = CNS3XXX_PCIE1_IO_BASE,
+                       .end = CNS3XXX_PCIE1_IO_BASE + SZ_16M - 1,
+                       .flags = IORESOURCE_IO,
+               },
+               .res_mem = {
+                       .name = "PCIe1 non-prefetchable",
+                       .start = CNS3XXX_PCIE1_MEM_BASE,
+                       .end = CNS3XXX_PCIE1_MEM_BASE + SZ_16M - 1,
+                       .flags = IORESOURCE_MEM,
+               },
+               .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
+               .hw_pci = {
+                       .domain = 1,
+                       .swizzle = pci_std_swizzle,
+                       .nr_controllers = 1,
+                       .setup = cns3xxx_pci_setup,
+                       .scan = cns3xxx_pci_scan_bus,
+                       .map_irq = cns3xxx_pcie_map_irq,
+               },
+       },
+};
+
+static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci)
+{
+       int port = cnspci->hw_pci.domain;
+       u32 reg;
+       unsigned long time;
+
+       reg = __raw_readl(MISC_PCIE_CTRL(port));
+       /*
+        * Enable Application Request to 1, it will exit L1 automatically,
+        * but when chip back, it will use another clock, still can use 0x1.
+        */
+       reg |= 0x3;
+       __raw_writel(reg, MISC_PCIE_CTRL(port));
+
+       pr_info("PCIe: Port[%d] Enable PCIe LTSSM\n", port);
+       pr_info("PCIe: Port[%d] Check data link layer...", port);
+
+       time = jiffies;
+       while (1) {
+               reg = __raw_readl(MISC_PCIE_PM_DEBUG(port));
+               if (reg & 0x1) {
+                       pr_info("Link up.\n");
+                       cnspci->linked = 1;
+                       break;
+               } else if (time_after(jiffies, time + 50)) {
+                       pr_info("Device not found.\n");
+                       break;
+               }
+       }
+}
+
+static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
+{
+       int port = cnspci->hw_pci.domain;
+       struct pci_sys_data sd = {
+               .domain = port,
+       };
+       struct pci_bus bus = {
+               .number = 0,
+               .ops = &cns3xxx_pcie_ops,
+               .sysdata = &sd,
+       };
+       u32 io_base = cnspci->res_io.start >> 16;
+       u32 mem_base = cnspci->res_mem.start >> 16;
+       u32 host_base = cnspci->cfg_bases[CNS3XXX_HOST_TYPE].pfn;
+       u32 cfg0_base = cnspci->cfg_bases[CNS3XXX_CFG0_TYPE].pfn;
+       u32 devfn = 0;
+       u8 tmp8;
+       u16 pos;
+       u16 dc;
+
+       host_base = (__pfn_to_phys(host_base) - 1) >> 16;
+       cfg0_base = (__pfn_to_phys(cfg0_base) - 1) >> 16;
+
+       pci_bus_write_config_byte(&bus, devfn, PCI_PRIMARY_BUS, 0);
+       pci_bus_write_config_byte(&bus, devfn, PCI_SECONDARY_BUS, 1);
+       pci_bus_write_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, 1);
+
+       pci_bus_read_config_byte(&bus, devfn, PCI_PRIMARY_BUS, &tmp8);
+       pci_bus_read_config_byte(&bus, devfn, PCI_SECONDARY_BUS, &tmp8);
+       pci_bus_read_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, &tmp8);
+
+       pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_BASE, mem_base);
+       pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_LIMIT, host_base);
+       pci_bus_write_config_word(&bus, devfn, PCI_IO_BASE_UPPER16, io_base);
+       pci_bus_write_config_word(&bus, devfn, PCI_IO_LIMIT_UPPER16, cfg0_base);
+
+       if (!cnspci->linked)
+               return;
+
+       /* Set Device Max_Read_Request_Size to 128 byte */
+       devfn = PCI_DEVFN(1, 0);
+       pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP);
+       pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
+       dc &= ~(0x3 << 12);     /* Clear Device Control Register [14:12] */
+       pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc);
+       pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
+       if (!(dc & (0x3 << 12)))
+               pr_info("PCIe: Set Device Max_Read_Request_Size to 128 byte\n");
+
+       /* Disable PCIe0 Interrupt Mask INTA to INTD */
+       __raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(port));
+}
+
+static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
+                                     struct pt_regs *regs)
+{
+       if (fsr & (1 << 10))
+               regs->ARM_pc += 4;
+       return 0;
+}
+
+static int __init cns3xxx_pcie_init(void)
+{
+       int i;
+
+       hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS,
+                       "imprecise external abort");
+
+       for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
+               iotable_init(cns3xxx_pcie[i].cfg_bases,
+                            ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
+               cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
+               cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
+               cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
+               cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
+               pci_common_init(&cns3xxx_pcie[i].hw_pci);
+       }
+
+       pci_assign_unassigned_resources();
+
+       return 0;
+}
+device_initcall(cns3xxx_pcie_init);

diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c
index 725e1a4fc23103ecd01df12eea9483d3f81a42f3..38e44706feabf43a69a9a3429f3a6753b51d34a0 100644 (file)
--- a/arch/arm/mach-cns3xxx/pm.c
+++ b/arch/arm/mach-cns3xxx/pm.c
@@ -6,18 +6,25 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/io.h>
 #include <linux/delay.h>
 #include <mach/system.h>
 #include <mach/cns3xxx.h>
 
 void cns3xxx_pwr_clk_en(unsigned int block)
 {
-       PM_CLK_GATE_REG |= (block & PM_CLK_GATE_REG_MASK);
+       u32 reg = __raw_readl(PM_CLK_GATE_REG);
+
+       reg |= (block & PM_CLK_GATE_REG_MASK);
+       __raw_writel(reg, PM_CLK_GATE_REG);
 }
 
 void cns3xxx_pwr_power_up(unsigned int block)
 {
-       PM_PLL_HM_PD_CTRL_REG &= ~(block & CNS3XXX_PWR_PLL_ALL);
+       u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
+
+       reg &= ~(block & CNS3XXX_PWR_PLL_ALL);
+       __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
 
        /* Wait for 300us for the PLL output clock locked. */
        udelay(300);
@@ -25,22 +32,29 @@ void cns3xxx_pwr_power_up(unsigned int block)
 
 void cns3xxx_pwr_power_down(unsigned int block)
 {
+       u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
+
        /* write '1' to power down */
-       PM_PLL_HM_PD_CTRL_REG |= (block & CNS3XXX_PWR_PLL_ALL);
+       reg |= (block & CNS3XXX_PWR_PLL_ALL);
+       __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
 };
 
 static void cns3xxx_pwr_soft_rst_force(unsigned int block)
 {
+       u32 reg = __raw_readl(PM_SOFT_RST_REG);
+
        /*
         * bit 0, 28, 29 => program low to reset,
         * the other else program low and then high
         */
        if (block & 0x30000001) {
-               PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
+               reg &= ~(block & PM_SOFT_RST_REG_MASK);
        } else {
-               PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
-               PM_SOFT_RST_REG |= (block & PM_SOFT_RST_REG_MASK);
+               reg &= ~(block & PM_SOFT_RST_REG_MASK);
+               reg |= (block & PM_SOFT_RST_REG_MASK);
        }
+
+       __raw_writel(reg, PM_SOFT_RST_REG);
 }
 
 void cns3xxx_pwr_soft_rst(unsigned int block)
@@ -73,12 +87,13 @@ void arch_reset(char mode, const char *cmd)
  */
 int cns3xxx_cpu_clock(void)
 {
+       u32 reg = __raw_readl(PM_CLK_CTRL_REG);
        int cpu;
        int cpu_sel;
        int div_sel;
 
-       cpu_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
-       div_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
+       cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
+       div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
 
        cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;
 

diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h
index a91edfb8beeac3109542989c957256436fd5a5c8..22eb97c1c30b48c89e6e2f397f73ee5727f5240a 100644 (file)
--- a/arch/arm/mach-davinci/include/mach/memory.h
+++ b/arch/arm/mach-davinci/include/mach/memory.h
@@ -48,19 +48,16 @@
  * below 128M
  */
 static inline void
-__arch_adjust_zones(int node, unsigned long *size, unsigned long *holes)
+__arch_adjust_zones(unsigned long *size, unsigned long *holes)
 {
        unsigned int sz = (128<<20) >> PAGE_SHIFT;
 
-       if (node != 0)
-               sz = 0;
-
        size[1] = size[0] - sz;
        size[0] = sz;
 }
 
-#define arch_adjust_zones(node, zone_size, holes) \
-        if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(node, zone_size, holes)
+#define arch_adjust_zones(zone_size, holes) \
+        if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(zone_size, holes)
 
 #define ISA_DMA_THRESHOLD      (PHYS_OFFSET + (128<<20) - 1)
 #define MAX_DMA_ADDRESS                (PAGE_OFFSET + (128<<20))

diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 5da2cf402c81d9773ce979ead618381e0efcd3e2..f7a12586a1f5eaf9c1b0316b6efc2b914a63fa30 100644 (file)
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -752,6 +752,67 @@ void __init dove_xor1_init(void)
        platform_device_register(&dove_xor11_channel);
 }
 
+/*****************************************************************************
+ * SDIO
+ ****************************************************************************/
+static u64 sdio_dmamask = DMA_BIT_MASK(32);
+
+static struct resource dove_sdio0_resources[] = {
+       {
+               .start  = DOVE_SDIO0_PHYS_BASE,
+               .end    = DOVE_SDIO0_PHYS_BASE + 0xff,
+               .flags  = IORESOURCE_MEM,
+       }, {
+               .start  = IRQ_DOVE_SDIO0,
+               .end    = IRQ_DOVE_SDIO0,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device dove_sdio0 = {
+       .name           = "sdhci-mv",
+       .id             = 0,
+       .dev            = {
+               .dma_mask               = &sdio_dmamask,
+               .coherent_dma_mask      = DMA_BIT_MASK(32),
+       },
+       .resource       = dove_sdio0_resources,
+       .num_resources  = ARRAY_SIZE(dove_sdio0_resources),
+};
+
+void __init dove_sdio0_init(void)
+{
+       platform_device_register(&dove_sdio0);
+}
+
+static struct resource dove_sdio1_resources[] = {
+       {
+               .start  = DOVE_SDIO1_PHYS_BASE,
+               .end    = DOVE_SDIO1_PHYS_BASE + 0xff,
+               .flags  = IORESOURCE_MEM,
+       }, {
+               .start  = IRQ_DOVE_SDIO1,
+               .end    = IRQ_DOVE_SDIO1,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device dove_sdio1 = {
+       .name           = "sdhci-mv",
+       .id             = 1,
+       .dev            = {
+               .dma_mask               = &sdio_dmamask,
+               .coherent_dma_mask      = DMA_BIT_MASK(32),
+       },
+       .resource       = dove_sdio1_resources,
+       .num_resources  = ARRAY_SIZE(dove_sdio1_resources),
+};
+
+void __init dove_sdio1_init(void)
+{
+       platform_device_register(&dove_sdio1);
+}
+
 void __init dove_init(void)
 {
        int tclk;

diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index b29e8937de4fd0acf9148bb0880dcc1c1ccafc94..a51517c3fe7654b629f4772ae2ef16cc63280f5f 100644 (file)
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -36,5 +36,7 @@ void dove_uart3_init(void);
 void dove_spi0_init(void);
 void dove_spi1_init(void);
 void dove_i2c_init(void);
+void dove_sdio0_init(void);
+void dove_sdio1_init(void);
 
 #endif

diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c
index f2971b7452242132a7ddc07552af66a5c330c911..bef70460fbc669353907355d3b9ca04f0a8308f3 100644 (file)
--- a/arch/arm/mach-dove/dove-db-setup.c
+++ b/arch/arm/mach-dove/dove-db-setup.c
@@ -82,6 +82,8 @@ static void __init dove_db_init(void)
        dove_ehci0_init();
        dove_ehci1_init();
        dove_sata_init(&dove_db_sata_data);
+       dove_sdio0_init();
+       dove_sdio1_init();
        dove_spi0_init();
        dove_spi1_init();
        dove_uart0_init();

diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
index 3a1a855bfdcace3e35591a50ede18edb6f2a1ec3..f744f676783f3024c0d18be2bff733432b260d9c 100644 (file)
--- a/arch/arm/mach-ep93xx/adssphere.c
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -13,7 +13,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
 
 #include <mach/hardware.h>
 
@@ -21,26 +20,6 @@
 #include <asm/mach/arch.h>
 
 
-static struct physmap_flash_data adssphere_flash_data = {
-       .width          = 4,
-};
-
-static struct resource adssphere_flash_resource = {
-       .start          = EP93XX_CS6_PHYS_BASE,
-       .end            = EP93XX_CS6_PHYS_BASE + SZ_32M - 1,
-       .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device adssphere_flash = {
-       .name           = "physmap-flash",
-       .id             = 0,
-       .dev            = {
-               .platform_data  = &adssphere_flash_data,
-       },
-       .num_resources  = 1,
-       .resource       = &adssphere_flash_resource,
-};
-
 static struct ep93xx_eth_data __initdata adssphere_eth_data = {
        .phy_id         = 1,
 };
@@ -48,8 +27,7 @@ static struct ep93xx_eth_data __initdata adssphere_eth_data = {
 static void __init adssphere_init_machine(void)
 {
        ep93xx_init_devices();
-       platform_device_register(&adssphere_flash);
-
+       ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M);
        ep93xx_register_eth(&adssphere_eth_data, 1);
 }
 

diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index e29bdef9b2e201ea345c4139487e4895dffad94d..7f3039761d91aecf0c0c46c84424f5ad4c1bf743 100644 (file)
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -185,7 +185,7 @@ static struct clk_lookup clocks[] = {
        INIT_CK(NULL,                   "pll1",         &clk_pll1),
        INIT_CK(NULL,                   "fclk",         &clk_f),
        INIT_CK(NULL,                   "hclk",         &clk_h),
-       INIT_CK(NULL,                   "pclk",         &clk_p),
+       INIT_CK(NULL,                   "apb_pclk",     &clk_p),
        INIT_CK(NULL,                   "pll2",         &clk_pll2),
        INIT_CK("ep93xx-ohci",          NULL,           &clk_usb_host),
        INIT_CK("ep93xx-keypad",        NULL,           &clk_keypad),

diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 9092677f63eb739a529d137b5b1be891b11f53da..8e37a045188cbcf4bc334d521186b8d4a2871d5d 100644 (file)
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -29,6 +29,7 @@
 #include <linux/termios.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/serial.h>
+#include <linux/mtd/physmap.h>
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
 #include <linux/spi/spi.h>
@@ -215,8 +216,8 @@ void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
        spin_lock_irqsave(&syscon_swlock, flags);
 
        val = __raw_readl(EP93XX_SYSCON_DEVCFG);
-       val |= set_bits;
        val &= ~clear_bits;
+       val |= set_bits;
        __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
        __raw_writel(val, EP93XX_SYSCON_DEVCFG);
 
@@ -347,6 +348,43 @@ static struct platform_device ep93xx_ohci_device = {
 };
 
 
+/*************************************************************************
+ * EP93xx physmap'ed flash
+ *************************************************************************/
+static struct physmap_flash_data ep93xx_flash_data;
+
+static struct resource ep93xx_flash_resource = {
+       .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device ep93xx_flash = {
+       .name           = "physmap-flash",
+       .id             = 0,
+       .dev            = {
+               .platform_data  = &ep93xx_flash_data,
+       },
+       .num_resources  = 1,
+       .resource       = &ep93xx_flash_resource,
+};
+
+/**
+ * ep93xx_register_flash() - Register the external flash device.
+ * @width:     bank width in octets
+ * @start:     resource start address
+ * @size:      resource size
+ */
+void __init ep93xx_register_flash(unsigned int width,
+                                 resource_size_t start, resource_size_t size)
+{
+       ep93xx_flash_data.width         = width;
+
+       ep93xx_flash_resource.start     = start;
+       ep93xx_flash_resource.end       = start + size - 1;
+
+       platform_device_register(&ep93xx_flash);
+}
+
+
 /*************************************************************************
  * EP93xx ethernet peripheral handling
  *************************************************************************/
@@ -620,6 +658,11 @@ static struct platform_device ep93xx_fb_device = {
        .resource               = ep93xx_fb_resource,
 };
 
+static struct platform_device ep93xx_bl_device = {
+       .name           = "ep93xx-bl",
+       .id             = -1,
+};
+
 /**
  * ep93xx_register_fb - Register the framebuffer platform device.
  * @data:      platform specific framebuffer configuration (__initdata)
@@ -628,6 +671,7 @@ void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data)
 {
        ep93xxfb_data = *data;
        platform_device_register(&ep93xx_fb_device);
+       platform_device_register(&ep93xx_bl_device);
 }
 
 

diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index 3884182cd3623e8799b00323115d097f1894e4e9..c2ce9034ba87f5b856cb6e1cae89fb69060b8ffe 100644 (file)
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -27,7 +27,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
 #include <linux/gpio.h>
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
@@ -38,39 +37,13 @@
 #include <asm/mach/arch.h>
 
 
-static struct physmap_flash_data edb93xx_flash_data;
-
-static struct resource edb93xx_flash_resource = {
-       .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device edb93xx_flash = {
-       .name           = "physmap-flash",
-       .id             = 0,
-       .dev            = {
-               .platform_data  = &edb93xx_flash_data,
-       },
-       .num_resources  = 1,
-       .resource       = &edb93xx_flash_resource,
-};
-
-static void __init __edb93xx_register_flash(unsigned int width,
-                       resource_size_t start, resource_size_t size)
-{
-       edb93xx_flash_data.width        = width;
-       edb93xx_flash_resource.start    = start;
-       edb93xx_flash_resource.end      = start + size - 1;
-
-       platform_device_register(&edb93xx_flash);
-}
-
 static void __init edb93xx_register_flash(void)
 {
        if (machine_is_edb9307() || machine_is_edb9312() ||
            machine_is_edb9315()) {
-               __edb93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M);
+               ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M);
        } else {
-               __edb93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M);
+               ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M);
        }
 }
 

diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c
index a809618e9f059043b706bf25e57ffcf070dd3ff4..d97168c0ba336fa22179328b9dc72316807c13bb 100644 (file)
--- a/arch/arm/mach-ep93xx/gesbc9312.c
+++ b/arch/arm/mach-ep93xx/gesbc9312.c
@@ -13,7 +13,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
 
 #include <mach/hardware.h>
 
@@ -21,26 +20,6 @@
 #include <asm/mach/arch.h>
 
 
-static struct physmap_flash_data gesbc9312_flash_data = {
-       .width          = 4,
-};
-
-static struct resource gesbc9312_flash_resource = {
-       .start          = EP93XX_CS6_PHYS_BASE,
-       .end            = EP93XX_CS6_PHYS_BASE + SZ_8M - 1,
-       .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device gesbc9312_flash = {
-       .name           = "physmap-flash",
-       .id             = 0,
-       .dev            = {
-               .platform_data  = &gesbc9312_flash_data,
-       },
-       .num_resources  = 1,
-       .resource       = &gesbc9312_flash_resource,
-};
-
 static struct ep93xx_eth_data __initdata gesbc9312_eth_data = {
        .phy_id         = 1,
 };
@@ -48,8 +27,7 @@ static struct ep93xx_eth_data __initdata gesbc9312_eth_data = {
 static void __init gesbc9312_init_machine(void)
 {
        ep93xx_init_devices();
-       platform_device_register(&gesbc9312_flash);
-
+       ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_8M);
        ep93xx_register_eth(&gesbc9312_eth_data, 0);
 }
 

diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index 9a4413dd44bb6e1cd2ac6cbc291cfd87b7220d6f..a6c09176334ce1a7028705feeddfc38ddadf235e 100644 (file)
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -43,6 +43,9 @@ static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
 
 unsigned int ep93xx_chip_revision(void);
 
+void ep93xx_register_flash(unsigned int width,
+                          resource_size_t start, resource_size_t size);
+
 void ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr);
 void ep93xx_register_i2c(struct i2c_gpio_platform_data *data,
                         struct i2c_board_info *devices, int num);

diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c
index 1cc911b4efa659dbfbc7e35aee6f80236e81e800..2ba776320a8282e978d989eea0377d6511dc3ab7 100644 (file)
--- a/arch/arm/mach-ep93xx/micro9.c
+++ b/arch/arm/mach-ep93xx/micro9.c
@@ -14,7 +14,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
 #include <linux/io.h>
 
 #include <mach/hardware.h>
@@ -31,31 +30,6 @@
  * Micro9-Lite uses a separate MTD map driver for flash support
  * Micro9-Slim has up to 64MB of either 32-bit or 16-bit flash on CS1
  *************************************************************************/
-static struct physmap_flash_data micro9_flash_data;
-
-static struct resource micro9_flash_resource = {
-       .start          = EP93XX_CS1_PHYS_BASE,
-       .end            = EP93XX_CS1_PHYS_BASE + SZ_64M - 1,
-       .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device micro9_flash = {
-       .name           = "physmap-flash",
-       .id             = 0,
-       .dev            = {
-               .platform_data  = &micro9_flash_data,
-       },
-       .num_resources  = 1,
-       .resource       = &micro9_flash_resource,
-};
-
-static void __init __micro9_register_flash(unsigned int width)
-{
-       micro9_flash_data.width = width;
-
-       platform_device_register(&micro9_flash);
-}
-
 static unsigned int __init micro9_detect_bootwidth(void)
 {
        u32 v;
@@ -70,10 +44,17 @@ static unsigned int __init micro9_detect_bootwidth(void)
 
 static void __init micro9_register_flash(void)
 {
+       unsigned int width;
+
        if (machine_is_micro9())
-               __micro9_register_flash(4);
+               width = 4;
        else if (machine_is_micro9m() || machine_is_micro9s())
-               __micro9_register_flash(micro9_detect_bootwidth());
+               width = micro9_detect_bootwidth();
+       else
+               width = 0;
+
+       if (width)
+               ep93xx_register_flash(width, EP93XX_CS1_PHYS_BASE, SZ_64M);
 }
 
 

diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
index 388aec95f60e39fb304ac48c655c413f33129c45..5dded5884133f89e27898567a61163c583fa8f3d 100644 (file)
--- a/arch/arm/mach-ep93xx/simone.c
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -18,7 +18,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
 #include <linux/gpio.h>
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
@@ -29,26 +28,6 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-static struct physmap_flash_data simone_flash_data = {
-       .width          = 2,
-};
-
-static struct resource simone_flash_resource = {
-       .start          = EP93XX_CS6_PHYS_BASE,
-       .end            = EP93XX_CS6_PHYS_BASE + SZ_8M - 1,
-       .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device simone_flash = {
-       .name           = "physmap-flash",
-       .id             = 0,
-       .num_resources  = 1,
-       .resource       = &simone_flash_resource,
-       .dev = {
-               .platform_data  = &simone_flash_data,
-       },
-};
-
 static struct ep93xx_eth_data __initdata simone_eth_data = {
        .phy_id         = 1,
 };
@@ -77,8 +56,7 @@ static struct i2c_board_info __initdata simone_i2c_board_info[] = {
 static void __init simone_init_machine(void)
 {
        ep93xx_init_devices();
-
-       platform_device_register(&simone_flash);
+       ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_8M);
        ep93xx_register_eth(&simone_eth_data, 1);
        ep93xx_register_fb(&simone_fb_info);
        ep93xx_register_i2c(&simone_i2c_gpio_data, simone_i2c_board_info,

diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index ae7319e588c7e59ca570173d47d1e95a0fe06d0f..93aeab8af705e8dd3dde989b1658e81e6ed60062 100644 (file)
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -17,7 +17,6 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/m48t86.h>
-#include <linux/mtd/physmap.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 
@@ -173,31 +172,13 @@ static struct platform_device ts72xx_nand_flash = {
 };
 
 
-/*************************************************************************
- * NOR flash (TS-7200 only)
- *************************************************************************/
-static struct physmap_flash_data ts72xx_nor_data = {
-       .width          = 2,
-};
-
-static struct resource ts72xx_nor_resource = {
-       .start          = EP93XX_CS6_PHYS_BASE,
-       .end            = EP93XX_CS6_PHYS_BASE + SZ_16M - 1,
-       .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device ts72xx_nor_flash = {
-       .name                   = "physmap-flash",
-       .id                     = 0,
-       .dev.platform_data      = &ts72xx_nor_data,
-       .resource               = &ts72xx_nor_resource,
-       .num_resources          = 1,
-};
-
 static void __init ts72xx_register_flash(void)
 {
+       /*
+        * TS7200 has NOR flash all other TS72xx board have NAND flash.
+        */
        if (board_is_ts7200()) {
-               platform_device_register(&ts72xx_nor_flash);
+               ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M);
        } else {
                resource_size_t start;
 

diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-imx/Kconfig
similarity index 57%
rename from arch/arm/mach-mx2/Kconfig
rename to arch/arm/mach-imx/Kconfig
index 742fd4e6dcb928486d299eec335f95b7cba6a431..c5c0369bb481dff32f4bbb8c214f4859a16787ac 100644 (file)
--- a/arch/arm/mach-mx2/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,42 +1,103 @@
+config IMX_HAVE_DMA_V1
+       bool
+
+if ARCH_MX1
+
+config SOC_IMX1
+       select CPU_ARM920T
+       select IMX_HAVE_DMA_V1
+       select IMX_HAVE_IOMUX_V1
+       bool
+
+comment "MX1 platforms:"
+config MACH_MXLADS
+       bool
+
+config ARCH_MX1ADS
+       bool "MX1ADS platform"
+       select MACH_MXLADS
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_IMX_UART
+       help
+         Say Y here if you are using Motorola MX1ADS/MXLADS boards
+
+config MACH_SCB9328
+       bool "Synertronixx scb9328"
+       select IMX_HAVE_PLATFORM_IMX_UART
+       help
+         Say Y here if you are using a Synertronixx scb9328 board
+
+endif
+
 if ARCH_MX2
 
+config SOC_IMX21
+       select CPU_ARM926T
+       select ARCH_MXC_AUDMUX_V1
+       select IMX_HAVE_DMA_V1
+       select IMX_HAVE_IOMUX_V1
+       bool
+
+config SOC_IMX27
+       select CPU_ARM926T
+       select ARCH_MXC_AUDMUX_V1
+       select IMX_HAVE_DMA_V1
+       select IMX_HAVE_IOMUX_V1
+       bool
+
 choice
        prompt "CPUs:"
        default MACH_MX21
 
 config MACH_MX21
        bool "i.MX21 support"
-       select ARCH_MXC_AUDMUX_V1
+       select SOC_IMX21
        help
          This enables support for Freescale's MX2 based i.MX21 processor.
 
 config MACH_MX27
        bool "i.MX27 support"
-       select ARCH_MXC_AUDMUX_V1
+       select SOC_IMX27
        help
          This enables support for Freescale's MX2 based i.MX27 processor.
 
 endchoice
 
-comment "MX2 platforms:"
+endif
+
+if MACH_MX21
+
+comment "MX21 platforms:"
 
 config MACH_MX21ADS
        bool "MX21ADS platform"
-       depends on MACH_MX21
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_MXC_NAND
        help
          Include support for MX21ADS platform. This includes specific
          configurations for the board and its peripherals.
 
+endif
+
+if MACH_MX27
+
+comment "MX27 platforms:"
+
 config MACH_MX27ADS
        bool "MX27ADS platform"
-       depends on MACH_MX27
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_MXC_NAND
        help
          Include support for MX27ADS platform. This includes specific
          configurations for the board and its peripherals.
 
 config MACH_PCM038
        bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
-       depends on MACH_MX27
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_MXC_NAND
+       select IMX_HAVE_PLATFORM_SPI_IMX
        select MXC_ULPI if USB_ULPI
        help
          Include support for phyCORE-i.MX27 (aka pcm038) platform. This
@@ -58,7 +119,9 @@ endchoice
 
 config MACH_CPUIMX27
        bool "Eukrea CPUIMX27 module"
-       depends on MACH_MX27
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_MXC_NAND
        help
          Include support for Eukrea CPUIMX27 platform. This includes
          specific configurations for the module and its peripherals.
@@ -67,9 +130,16 @@ config MACH_EUKREA_CPUIMX27_USESDHC2
        bool "CPUIMX27 integrates SDHC2 module"
        depends on MACH_CPUIMX27
        help
-         This adds support for the internal SDHC2 used on CPUIMX27 used
+         This adds support for the internal SDHC2 used on CPUIMX27
          for wifi or eMMC.
 
+config MACH_EUKREA_CPUIMX27_USEUART4
+       bool "CPUIMX27 integrates UART4 module"
+       depends on MACH_CPUIMX27
+       help
+         This adds support for the internal UART4 used on CPUIMX27
+         for bluetooth.
+
 choice
        prompt "Baseboard"
        depends on MACH_CPUIMX27
@@ -78,6 +148,8 @@ choice
 config MACH_EUKREA_MBIMX27_BASEBOARD
        prompt "Eukrea MBIMX27 development board"
        bool
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_SPI_IMX
        help
          This adds board specific devices that can be found on Eukrea's
          MBIMX27 evaluation board.
@@ -86,21 +158,24 @@ endchoice
 
 config MACH_MX27_3DS
        bool "MX27PDK platform"
-       depends on MACH_MX27
+       select IMX_HAVE_PLATFORM_IMX_UART
        help
          Include support for MX27PDK platform. This includes specific
          configurations for the board and its peripherals.
 
 config MACH_IMX27LITE
        bool "LogicPD MX27 LITEKIT platform"
-       depends on MACH_MX27
+       select IMX_HAVE_PLATFORM_IMX_UART
        help
          Include support for MX27 LITEKIT platform. This includes specific
          configurations for the board and its peripherals.
 
 config MACH_PCA100
        bool "Phytec phyCARD-s (pca100)"
-       depends on MACH_MX27
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_MXC_NAND
+       select IMX_HAVE_PLATFORM_SPI_IMX
        select MXC_ULPI if USB_ULPI
        help
          Include support for phyCARD-s (aka pca100) platform. This
@@ -108,7 +183,9 @@ config MACH_PCA100
 
 config MACH_MXT_TD60
        bool "Maxtrack i-MXT TD60"
-       depends on MACH_MX27
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_MXC_NAND
        help
          Include support for i-MXT (aka td60) platform. This
          includes specific configurations for the module and its peripherals.

diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-imx/Makefile
similarity index 55%
rename from arch/arm/mach-mx2/Makefile
rename to arch/arm/mach-imx/Makefile
index e3254faac8289655f2997afe2f0d24d1fff8cfbb..46a9fdfbbd157101e22fbd19e1edb6d2c2d893af 100644 (file)
--- a/arch/arm/mach-mx2/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -4,14 +4,24 @@
 
 # Object file lists.
 
-obj-y  :=  devices.o serial.o
+obj-y  :=  devices.o
 
-obj-$(CONFIG_MACH_MX21) += clock_imx21.o mm-imx21.o
+obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
 
-obj-$(CONFIG_MACH_MX27) += cpu_imx27.o
-obj-$(CONFIG_MACH_MX27) += clock_imx27.o mm-imx27.o
+obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
+obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
+
+obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o
+obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o
+
+# Support for CMOS sensor interface
+obj-$(CONFIG_MX1_VIDEO)        += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
+
+obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
+obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
 
 obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
+
 obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
 obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
 obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o

diff --git a/arch/arm/mach-mx2/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
similarity index 67%
rename from arch/arm/mach-mx2/Makefile.boot
rename to arch/arm/mach-imx/Makefile.boot
index e867398a8fdbb5304493c40104635e1e40a3f778..7988a85cf07db0453ec39715c38a70067a2ef1d0 100644 (file)
--- a/arch/arm/mach-mx2/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -1,3 +1,7 @@
+zreladdr-$(CONFIG_ARCH_MX1)    := 0x08008000
+params_phys-$(CONFIG_ARCH_MX1) := 0x08000100
+initrd_phys-$(CONFIG_ARCH_MX1) := 0x08800000
+
 zreladdr-$(CONFIG_MACH_MX21)   := 0xC0008000
 params_phys-$(CONFIG_MACH_MX21)        := 0xC0000100
 initrd_phys-$(CONFIG_MACH_MX21)        := 0xC0800000

diff --git a/arch/arm/mach-mx1/clock.c b/arch/arm/mach-imx/clock-imx1.c
similarity index 90%
rename from arch/arm/mach-mx1/clock.c
rename to arch/arm/mach-imx/clock-imx1.c
index 6cf2d4a7511dc441561c80fe80ca432cf886d3b5..c05096c38301038292e9b9f6e0bb10990c31433e 100644 (file)
--- a/arch/arm/mach-mx1/clock.c
+++ b/arch/arm/mach-imx/clock-imx1.c
@@ -2,18 +2,17 @@
  *  Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
  *
  * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
  */
 
 #include <linux/kernel.h>
@@ -29,7 +28,41 @@
 #include <mach/clock.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include "crm_regs.h"
+
+#define IO_ADDR_CCM(off)       (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
+
+/* CCM register addresses */
+#define CCM_CSCR       IO_ADDR_CCM(0x0)
+#define CCM_MPCTL0     IO_ADDR_CCM(0x4)
+#define CCM_SPCTL0     IO_ADDR_CCM(0xc)
+#define CCM_PCDR       IO_ADDR_CCM(0x20)
+
+#define CCM_CSCR_CLKO_OFFSET   29
+#define CCM_CSCR_CLKO_MASK     (0x7 << 29)
+#define CCM_CSCR_USB_OFFSET    26
+#define CCM_CSCR_USB_MASK      (0x7 << 26)
+#define CCM_CSCR_OSC_EN_SHIFT  17
+#define CCM_CSCR_SYSTEM_SEL    (1 << 16)
+#define CCM_CSCR_BCLK_OFFSET   10
+#define CCM_CSCR_BCLK_MASK     (0xf << 10)
+#define CCM_CSCR_PRESC         (1 << 15)
+
+#define CCM_PCDR_PCLK3_OFFSET  16
+#define CCM_PCDR_PCLK3_MASK    (0x7f << 16)
+#define CCM_PCDR_PCLK2_OFFSET  4
+#define CCM_PCDR_PCLK2_MASK    (0xf << 4)
+#define CCM_PCDR_PCLK1_OFFSET  0
+#define CCM_PCDR_PCLK1_MASK    0xf
+
+#define IO_ADDR_SCM(off)       (MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off)))
+
+/* SCM register addresses */
+#define SCM_GCCR       IO_ADDR_SCM(0xc)
+
+#define SCM_GCCR_DMA_CLK_EN_OFFSET     3
+#define SCM_GCCR_CSI_CLK_EN_OFFSET     2
+#define SCM_GCCR_MMA_CLK_EN_OFFSET     1
+#define SCM_GCCR_USBD_CLK_EN_OFFSET    0
 
 static int _clk_enable(struct clk *clk)
 {
@@ -596,7 +629,8 @@ int __init mx1_clocks_init(unsigned long fref)
        clk_enable(&hclk);
        clk_enable(&fclk);
 
-       mxc_timer_init(&gpt_clk, IO_ADDRESS(TIM1_BASE_ADDR), TIM1_INT);
+       mxc_timer_init(&gpt_clk, MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR),
+                       MX1_TIM1_INT);
 
        return 0;
 }

diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-imx/clock-imx21.c
similarity index 100%
rename from arch/arm/mach-mx2/clock_imx21.c
rename to arch/arm/mach-imx/clock-imx21.c

diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-imx/clock-imx27.c
similarity index 99%
rename from arch/arm/mach-mx2/clock_imx27.c
rename to arch/arm/mach-imx/clock-imx27.c
index 0f0823c8b1707e9d8f86bbc77fb0320aa25395b8..5a1aa15c8a16140f17e75ea451b5441c9c413d10 100644 (file)
--- a/arch/arm/mach-mx2/clock_imx27.c
+++ b/arch/arm/mach-imx/clock-imx27.c
@@ -644,7 +644,7 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
        _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
        _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
-       _REGISTER_CLOCK(NULL, "csi", csi_clk)
+       _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
        _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk)
        _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1)
        _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk)

diff --git a/arch/arm/mach-mx2/cpu_imx27.c b/arch/arm/mach-imx/cpu-imx27.c
similarity index 100%
rename from arch/arm/mach-mx2/cpu_imx27.c
rename to arch/arm/mach-imx/cpu-imx27.c

diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h
new file mode 100644 (file)
index 0000000..a8d94f0
--- /dev/null
+++ b/arch/arm/mach-imx/devices-imx1.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx1.h>
+#include <mach/devices-common.h>
+
+#define imx1_add_i2c_imx(pdata)                \
+       imx_add_imx_i2c(0, MX1_I2C_BASE_ADDR, SZ_4K, MX1_INT_I2C, pdata)
+
+#define imx1_add_imx_uart0(pdata)      \
+       imx_add_imx_uart_3irq(0, MX1_UART1_BASE_ADDR, 0xd0, MX1_INT_UART1RX, MX1_INT_UART1TX, MX1_INT_UART1RTS, pdata)
+#define imx1_add_imx_uart1(pdata)      \
+       imx_add_imx_uart_3irq(0, MX1_UART2_BASE_ADDR, 0xd0, MX1_INT_UART2RX, MX1_INT_UART2TX, MX1_INT_UART2RTS, pdata)

diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h
new file mode 100644 (file)
index 0000000..42788e9
--- /dev/null
+++ b/arch/arm/mach-imx/devices-imx21.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx21.h>
+#include <mach/devices-common.h>
+
+#define imx21_add_i2c_imx(pdata)       \
+       imx_add_imx_i2c(0, MX2x_I2C_BASE_ADDR, SZ_4K, MX2x_INT_I2C, pdata)
+
+#define imx21_add_imx_uart0(pdata)     \
+       imx_add_imx_uart_1irq(0, MX21_UART1_BASE_ADDR, SZ_4K, MX21_INT_UART1, pdata)
+#define imx21_add_imx_uart1(pdata)     \
+       imx_add_imx_uart_1irq(1, MX21_UART2_BASE_ADDR, SZ_4K, MX21_INT_UART2, pdata)
+#define imx21_add_imx_uart2(pdata)     \
+       imx_add_imx_uart_1irq(2, MX21_UART3_BASE_ADDR, SZ_4K, MX21_INT_UART3, pdata)
+#define imx21_add_imx_uart3(pdata)     \
+       imx_add_imx_uart_1irq(3, MX21_UART4_BASE_ADDR, SZ_4K, MX21_INT_UART4, pdata)
+
+#define imx21_add_mxc_nand(pdata)      \
+       imx_add_mxc_nand_v1(MX21_NFC_BASE_ADDR, MX21_INT_NANDFC, pdata)
+
+#define imx21_add_spi_imx0(pdata)      \
+       imx_add_spi_imx(0, MX21_CSPI1_BASE_ADDR, SZ_4K, MX21_INT_CSPI1, pdata)
+#define imx21_add_spi_imx1(pdata)      \
+       imx_add_spi_imx(1, MX21_CSPI2_BASE_ADDR, SZ_4K, MX21_INT_CSPI2, pdata)

diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
new file mode 100644 (file)
index 0000000..65e7bb7
--- /dev/null
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx27.h>
+#include <mach/devices-common.h>
+
+#define imx27_add_i2c_imx0(pdata)      \
+       imx_add_imx_i2c(0, MX27_I2C1_BASE_ADDR, SZ_4K, MX27_INT_I2C1, pdata)
+#define imx27_add_i2c_imx1(pdata)      \
+       imx_add_imx_i2c(1, MX27_I2C2_BASE_ADDR, SZ_4K, MX27_INT_I2C2, pdata)
+
+#define imx27_add_imx_uart0(pdata)     \
+       imx_add_imx_uart_1irq(0, MX27_UART1_BASE_ADDR, SZ_4K, MX27_INT_UART1, pdata)
+#define imx27_add_imx_uart1(pdata)     \
+       imx_add_imx_uart_1irq(1, MX27_UART2_BASE_ADDR, SZ_4K, MX27_INT_UART2, pdata)
+#define imx27_add_imx_uart2(pdata)     \
+       imx_add_imx_uart_1irq(2, MX27_UART3_BASE_ADDR, SZ_4K, MX27_INT_UART3, pdata)
+#define imx27_add_imx_uart3(pdata)     \
+       imx_add_imx_uart_1irq(3, MX27_UART4_BASE_ADDR, SZ_4K, MX27_INT_UART4, pdata)
+#define imx27_add_imx_uart4(pdata)     \
+       imx_add_imx_uart_1irq(4, MX27_UART5_BASE_ADDR, SZ_4K, MX27_INT_UART5, pdata)
+#define imx27_add_imx_uart5(pdata)     \
+       imx_add_imx_uart_1irq(5, MX27_UART6_BASE_ADDR, SZ_4K, MX27_INT_UART6, pdata)
+
+#define imx27_add_mxc_nand(pdata)      \
+       imx_add_mxc_nand_v1(MX27_NFC_BASE_ADDR, MX27_INT_NANDFC, pdata)
+
+#define imx27_add_spi_imx0(pdata)      \
+       imx_add_spi_imx(0, MX27_CSPI1_BASE_ADDR, SZ_4K, MX27_INT_CSPI1, pdata)
+#define imx27_add_spi_imx1(pdata)      \
+       imx_add_spi_imx(1, MX27_CSPI2_BASE_ADDR, SZ_4K, MX27_INT_CSPI2, pdata)
+#define imx27_add_spi_imx2(pdata)      \
+       imx_add_spi_imx(2, MX27_CSPI3_BASE_ADDR, SZ_4K, MX27_INT_CSPI3, pdata)

diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-imx/devices.c
similarity index 67%
rename from arch/arm/mach-mx2/devices.c
rename to arch/arm/mach-imx/devices.c
index a0aeb8a4adc19ef419a0a045ad3b882131597106..9c271a752b84da4e0380bf9fed2c86a5658a9640 100644 (file)
--- a/arch/arm/mach-mx2/devices.c
+++ b/arch/arm/mach-imx/devices.c
@@ -11,6 +11,9 @@
  *
  * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
+ * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -32,6 +35,7 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/dma-mapping.h>
+#include <linux/serial.h>
 
 #include <mach/irqs.h>
 #include <mach/hardware.h>
@@ -40,38 +44,179 @@
 
 #include "devices.h"
 
-/*
- * SPI master controller
- *
- * - i.MX1: 2 channel (slighly different register setting)
- * - i.MX21: 2 channel
- * - i.MX27: 3 channel
- */
-#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq)                                        \
-       static struct resource mxc_spi_resources ## n[] = {                     \
-               {                                                               \
-                       .start = baseaddr,                                      \
-                       .end = baseaddr + SZ_4K - 1,                            \
-                       .flags = IORESOURCE_MEM,                                \
-               }, {                                                            \
-                       .start = irq,                                           \
-                       .end = irq,                                             \
-                       .flags = IORESOURCE_IRQ,                                \
-               },                                                              \
-       };                                                                      \
-                                                                               \
-       struct platform_device mxc_spi_device ## n = {                          \
-               .name = "spi_imx",                                              \
-               .id = n,                                                        \
-               .num_resources = ARRAY_SIZE(mxc_spi_resources ## n),            \
-               .resource = mxc_spi_resources ## n,                             \
+#if defined(CONFIG_ARCH_MX1)
+static struct resource imx1_camera_resources[] = {
+       {
+               .start  = 0x00224000,
+               .end    = 0x00224010,
+               .flags  = IORESOURCE_MEM,
+       }, {
+               .start  = MX1_CSI_INT,
+               .end    = MX1_CSI_INT,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static u64 imx1_camera_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device imx1_camera_device = {
+       .name           = "mx1-camera",
+       .id             = 0, /* This is used to put cameras on this interface */
+       .dev            = {
+               .dma_mask = &imx1_camera_dmamask,
+               .coherent_dma_mask = DMA_BIT_MASK(32),
+       },
+       .resource       = imx1_camera_resources,
+       .num_resources  = ARRAY_SIZE(imx1_camera_resources),
+};
+
+static struct resource imx_rtc_resources[] = {
+       {
+               .start  = 0x00204000,
+               .end    = 0x00204024,
+               .flags  = IORESOURCE_MEM,
+       }, {
+               .start  = MX1_RTC_INT,
+               .end    = MX1_RTC_INT,
+               .flags  = IORESOURCE_IRQ,
+       }, {
+               .start  = MX1_RTC_SAMINT,
+               .end    = MX1_RTC_SAMINT,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+struct platform_device imx_rtc_device = {
+       .name           = "rtc-imx",
+       .id             = 0,
+       .resource       = imx_rtc_resources,
+       .num_resources  = ARRAY_SIZE(imx_rtc_resources),
+};
+
+static struct resource imx_wdt_resources[] = {
+       {
+               .start  = 0x00201000,
+               .end    = 0x00201008,
+               .flags  = IORESOURCE_MEM,
+       }, {
+               .start  = MX1_WDT_INT,
+               .end    = MX1_WDT_INT,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+struct platform_device imx_wdt_device = {
+       .name           = "imx-wdt",
+       .id             = 0,
+       .resource       = imx_wdt_resources,
+       .num_resources  = ARRAY_SIZE(imx_wdt_resources),
+};
+
+static struct resource imx_usb_resources[] = {
+       {
+               .start  = 0x00212000,
+               .end    = 0x00212148,
+               .flags  = IORESOURCE_MEM,
+       }, {
+               .start  = MX1_USBD_INT0,
+               .end    = MX1_USBD_INT0,
+               .flags  = IORESOURCE_IRQ,
+       }, {
+               .start  = MX1_USBD_INT1,
+               .end    = MX1_USBD_INT1,
+               .flags  = IORESOURCE_IRQ,
+       }, {
+               .start  = MX1_USBD_INT2,
+               .end    = MX1_USBD_INT2,
+               .flags  = IORESOURCE_IRQ,
+       }, {
+               .start  = MX1_USBD_INT3,
+               .end    = MX1_USBD_INT3,
+               .flags  = IORESOURCE_IRQ,
+       }, {
+               .start  = MX1_USBD_INT4,
+               .end    = MX1_USBD_INT4,
+               .flags  = IORESOURCE_IRQ,
+       }, {
+               .start  = MX1_USBD_INT5,
+               .end    = MX1_USBD_INT5,
+               .flags  = IORESOURCE_IRQ,
+       }, {
+               .start  = MX1_USBD_INT6,
+               .end    = MX1_USBD_INT6,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+struct platform_device imx_usb_device = {
+       .name           = "imx_udc",
+       .id             = 0,
+       .num_resources  = ARRAY_SIZE(imx_usb_resources),
+       .resource       = imx_usb_resources,
+};
+
+/* GPIO port description */
+static struct mxc_gpio_port imx_gpio_ports[] = {
+       {
+               .chip.label = "gpio-0",
+               .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
+               .irq = MX1_GPIO_INT_PORTA,
+               .virtual_irq_start = MXC_GPIO_IRQ_START,
+       }, {
+               .chip.label = "gpio-1",
+               .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100),
+               .irq = MX1_GPIO_INT_PORTB,
+               .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
+       }, {
+               .chip.label = "gpio-2",
+               .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200),
+               .irq = MX1_GPIO_INT_PORTC,
+               .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
+       }, {
+               .chip.label = "gpio-3",
+               .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300),
+               .irq = MX1_GPIO_INT_PORTD,
+               .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
        }
+};
+
+int __init imx1_register_gpios(void)
+{
+       return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
+}
+#endif
 
-DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
-DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
+#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
 
 #ifdef CONFIG_MACH_MX27
-DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
+static struct resource mx27_camera_resources[] = {
+       {
+              .start = MX27_CSI_BASE_ADDR,
+              .end = MX27_CSI_BASE_ADDR + 0x1f,
+              .flags = IORESOURCE_MEM,
+       }, {
+              .start = MX27_EMMA_PRP_BASE_ADDR,
+              .end = MX27_EMMA_PRP_BASE_ADDR + 0x1f,
+              .flags = IORESOURCE_MEM,
+       }, {
+              .start = MX27_INT_CSI,
+              .end = MX27_INT_CSI,
+              .flags = IORESOURCE_IRQ,
+       },{
+              .start = MX27_INT_EMMAPRP,
+              .end = MX27_INT_EMMAPRP,
+              .flags = IORESOURCE_IRQ,
+       },
+};
+struct platform_device mx27_camera_device = {
+       .name = "mx2-camera",
+       .id = 0,
+       .num_resources = ARRAY_SIZE(mx27_camera_resources),
+       .resource = mx27_camera_resources,
+       .dev = {
+               .coherent_dma_mask = 0xffffffff,
+       },
+};
 #endif
 
 /*
@@ -140,34 +285,6 @@ struct platform_device mxc_w1_master_device = {
        .resource = mxc_w1_master_resources,
 };
 
-#define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq)                     \
-       static struct resource pfx ## _nand_resources[] = {             \
-               {                                                       \
-                       .start = baseaddr,                              \
-                       .end = baseaddr + SZ_4K - 1,                    \
-                       .flags = IORESOURCE_MEM,                        \
-               }, {                                                    \
-                       .start = irq,                                   \
-                       .end = irq,                                     \
-                       .flags = IORESOURCE_IRQ,                        \
-               },                                                      \
-       };                                                              \
-                                                                       \
-       struct platform_device pfx ## _nand_device = {                  \
-               .name = "mxc_nand",                                     \
-               .id = 0,                                                \
-               .num_resources = ARRAY_SIZE(pfx ## _nand_resources),    \
-               .resource = pfx ## _nand_resources,                     \
-       }
-
-#ifdef CONFIG_MACH_MX21
-DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC);
-#endif
-
-#ifdef CONFIG_MACH_MX27
-DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC);
-#endif
-
 /*
  * lcdc:
  * - i.MX1: the basic controller
@@ -218,32 +335,6 @@ struct platform_device mxc_fec_device = {
 };
 #endif
 
-#define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq)                                \
-       static struct resource mxc_i2c_resources ## n[] = {             \
-               {                                                       \
-                       .start = baseaddr,                              \
-                       .end = baseaddr + SZ_4K - 1,                    \
-                       .flags = IORESOURCE_MEM,                        \
-               }, {                                                    \
-                       .start = irq,                                   \
-                       .end = irq,                                     \
-                       .flags = IORESOURCE_IRQ,                        \
-               }                                                       \
-       };                                                              \
-                                                                       \
-       struct platform_device mxc_i2c_device ## n = {                  \
-               .name = "imx-i2c",                                      \
-               .id = n,                                                \
-               .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n),    \
-               .resource = mxc_i2c_resources ## n,                     \
-       }
-
-DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);
-
-#ifdef CONFIG_MACH_MX27
-DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
-#endif
-
 static struct resource mxc_pwm_resources[] = {
        {
                .start = MX2x_PWM_BASE_ADDR,
@@ -454,26 +545,21 @@ DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
 
 #ifdef CONFIG_MACH_MX21
 DEFINE_MXC_GPIO_PORTS(MX21, imx21);
+
+int __init imx21_register_gpios(void)
+{
+       return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
+}
 #endif
 
 #ifdef CONFIG_MACH_MX27
 DEFINE_MXC_GPIO_PORTS(MX27, imx27);
-#endif
 
-int __init mxc_register_gpios(void)
+int __init imx27_register_gpios(void)
 {
-#ifdef CONFIG_MACH_MX21
-       if (cpu_is_mx21())
-               return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
-       else
-#endif
-#ifdef CONFIG_MACH_MX27
-       if (cpu_is_mx27())
-               return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
-       else
-#endif
-               return 0;
+       return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
 }
+#endif
 
 #ifdef CONFIG_MACH_MX21
 static struct resource mx21_usbhc_resources[] = {
@@ -501,3 +587,23 @@ struct platform_device mx21_usbhc_device = {
 };
 #endif
 
+static struct resource imx_kpp_resources[] = {
+       {
+               .start  = MX2x_KPP_BASE_ADDR,
+               .end    = MX2x_KPP_BASE_ADDR + 0xf,
+               .flags  = IORESOURCE_MEM
+       }, {
+               .start  = MX2x_INT_KPP,
+               .end    = MX2x_INT_KPP,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+struct platform_device imx_kpp_device = {
+       .name = "imx-keypad",
+       .id = -1,
+       .num_resources = ARRAY_SIZE(imx_kpp_resources),
+       .resource = imx_kpp_resources,
+};
+
+#endif

diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-imx/devices.h
similarity index 54%
rename from arch/arm/mach-mx2/devices.h
rename to arch/arm/mach-imx/devices.h
index 84ed51380174ebd6cadaef60f19245ede9df7782..efd4527506a5e661da74c95e9d756c0674ca3d33 100644 (file)
--- a/arch/arm/mach-mx2/devices.h
+++ b/arch/arm/mach-imx/devices.h
@@ -1,3 +1,11 @@
+#ifdef CONFIG_ARCH_MX1
+extern struct platform_device imx1_camera_device;
+extern struct platform_device imx_rtc_device;
+extern struct platform_device imx_wdt_device;
+extern struct platform_device imx_usb_device;
+#endif
+
+#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
 extern struct platform_device mxc_gpt1;
 extern struct platform_device mxc_gpt2;
 #ifdef CONFIG_MACH_MX27
@@ -6,37 +14,19 @@ extern struct platform_device mxc_gpt4;
 extern struct platform_device mxc_gpt5;
 #endif
 extern struct platform_device mxc_wdt;
-extern struct platform_device mxc_uart_device0;
-extern struct platform_device mxc_uart_device1;
-extern struct platform_device mxc_uart_device2;
-extern struct platform_device mxc_uart_device3;
-extern struct platform_device mxc_uart_device4;
-extern struct platform_device mxc_uart_device5;
 extern struct platform_device mxc_w1_master_device;
-#ifdef CONFIG_MACH_MX21
-extern struct platform_device imx21_nand_device;
-#endif
-#ifdef CONFIG_MACH_MX27
-extern struct platform_device imx27_nand_device;
-#endif
 extern struct platform_device mxc_fb_device;
 extern struct platform_device mxc_fec_device;
 extern struct platform_device mxc_pwm_device;
-extern struct platform_device mxc_i2c_device0;
-#ifdef CONFIG_MACH_MX27
-extern struct platform_device mxc_i2c_device1;
-#endif
 extern struct platform_device mxc_sdhc_device0;
 extern struct platform_device mxc_sdhc_device1;
 extern struct platform_device mxc_otg_udc_device;
+extern struct platform_device mx27_camera_device;
 extern struct platform_device mxc_otg_host;
 extern struct platform_device mxc_usbh1;
 extern struct platform_device mxc_usbh2;
-extern struct platform_device mxc_spi_device0;
-extern struct platform_device mxc_spi_device1;
-#ifdef CONFIG_MACH_MX27
-extern struct platform_device mxc_spi_device2;
-#endif
 extern struct platform_device mx21_usbhc_device;
 extern struct platform_device imx_ssi_device0;
 extern struct platform_device imx_ssi_device1;
+extern struct platform_device imx_kpp_device;
+#endif

diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/mach-imx/dma-v1.c
similarity index 99%
rename from arch/arm/plat-mxc/dma-mx1-mx2.c
rename to arch/arm/mach-imx/dma-v1.c
index e16014b0d13c817fe56e66fcb71a588ee0abf72e..fd1d9197d06ef66f9b5e5a3d95d3a825510f47a5 100644 (file)
--- a/arch/arm/plat-mxc/dma-mx1-mx2.c
+++ b/arch/arm/mach-imx/dma-v1.c
@@ -1,5 +1,5 @@
 /*
- *  linux/arch/arm/plat-mxc/dma-mx1-mx2.c
+ *  linux/arch/arm/plat-mxc/dma-v1.c
  *
  *  i.MX DMA registration and IRQ dispatching
  *
@@ -34,7 +34,7 @@
 #include <asm/system.h>
 #include <asm/irq.h>
 #include <mach/hardware.h>
-#include <mach/dma-mx1-mx2.h>
+#include <mach/dma-v1.h>
 
 #define DMA_DCR     0x00               /* Control Register */
 #define DMA_DISR    0x04               /* Interrupt status Register */

diff --git a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
similarity index 52%
rename from arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
rename to arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index f3b169d5245fcdf7f751c896ad693073bba31087..4edc5f43920109011d6e8f8fd64234e3fe3cb992 100644 (file)
--- a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2009 Eric Benard - eric@eukrea.com
+ * Copyright (C) 2009-2010 Eric Benard - eric@eukrea.com
  *
  * Based on pcm970-baseboard.c which is :
  * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
@@ -24,6 +24,9 @@
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
+#include <linux/backlight.h>
+#include <video/platform_lcd.h>
+#include <linux/input/matrix_keypad.h>
 
 #include <asm/mach/arch.h>
 
@@ -32,8 +35,11 @@
 #include <mach/imxfb.h>
 #include <mach/hardware.h>
 #include <mach/mmc.h>
-#include <mach/imx-uart.h>
+#include <mach/spi.h>
+#include <mach/ssi.h>
+#include <mach/audmux.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 static int eukrea_mbimx27_pins[] = {
@@ -48,10 +54,12 @@ static int eukrea_mbimx27_pins[] = {
        PE10_PF_UART3_CTS,
        PE11_PF_UART3_RTS,
        /* UART4 */
+#if !defined(MACH_EUKREA_CPUIMX27_USEUART4)
        PB26_AF_UART4_RTS,
        PB28_AF_UART4_TXD,
        PB29_AF_UART4_CTS,
        PB31_AF_UART4_RXD,
+#endif
        /* SDHC1*/
        PE18_PF_SD1_D0,
        PE19_PF_SD1_D1,
@@ -84,10 +92,29 @@ static int eukrea_mbimx27_pins[] = {
        PA30_PF_CONTRAST,
        PA31_PF_OE_ACD,
        /* SPI1 */
-       PD28_PF_CSPI1_SS0,
        PD29_PF_CSPI1_SCLK,
        PD30_PF_CSPI1_MISO,
        PD31_PF_CSPI1_MOSI,
+       /* SSI4 */
+#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \
+       || defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE)
+       PC16_PF_SSI4_FS,
+       PC17_PF_SSI4_RXD | GPIO_PUEN,
+       PC18_PF_SSI4_TXD | GPIO_PUEN,
+       PC19_PF_SSI4_CLK,
+#endif
+};
+
+static const uint32_t eukrea_mbimx27_keymap[] = {
+       KEY(0, 0, KEY_UP),
+       KEY(0, 1, KEY_DOWN),
+       KEY(1, 0, KEY_RIGHT),
+       KEY(1, 1, KEY_LEFT),
+};
+
+static struct matrix_keymap_data eukrea_mbimx27_keymap_data = {
+       .keymap         = eukrea_mbimx27_keymap,
+       .keymap_size    = ARRAY_SIZE(eukrea_mbimx27_keymap),
 };
 
 static struct gpio_led gpio_leds[] = {
@@ -103,12 +130,6 @@ static struct gpio_led gpio_leds[] = {
                .active_low             = 1,
                .gpio                   = GPIO_PORTF | 19,
        },
-       {
-               .name                   = "backlight",
-               .default_trigger        = "backlight",
-               .active_low             = 0,
-               .gpio                   = GPIO_PORTE | 5,
-       },
 };
 
 static struct gpio_led_platform_data gpio_led_info = {
@@ -127,7 +148,7 @@ static struct platform_device leds_gpio = {
 static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
        {
                .mode = {
-                       .name           = "CMO-QGVA",
+                       .name           = "CMO-QVGA",
                        .refresh        = 60,
                        .xres           = 320,
                        .yres           = 240,
@@ -141,6 +162,38 @@ static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
                },
                .pcr            = 0xFAD08B80,
                .bpp            = 16,
+       }, {
+               .mode = {
+                       .name           = "DVI-VGA",
+                       .refresh        = 60,
+                       .xres           = 640,
+                       .yres           = 480,
+                       .pixclock       = 32000,
+                       .hsync_len      = 1,
+                       .left_margin    = 35,
+                       .right_margin   = 0,
+                       .vsync_len      = 1,
+                       .upper_margin   = 7,
+                       .lower_margin   = 0,
+               },
+               .pcr            = 0xFA208B80,
+               .bpp            = 16,
+       }, {
+               .mode = {
+                       .name           = "DVI-SVGA",
+                       .refresh        = 60,
+                       .xres           = 800,
+                       .yres           = 600,
+                       .pixclock       = 25000,
+                       .hsync_len      = 1,
+                       .left_margin    = 35,
+                       .right_margin   = 0,
+                       .vsync_len      = 1,
+                       .upper_margin   = 7,
+                       .lower_margin   = 0,
+               },
+               .pcr            = 0xFA208B80,
+               .bpp            = 16,
        },
 };
 
@@ -153,16 +206,52 @@ static struct imx_fb_platform_data eukrea_mbimx27_fb_data = {
        .dmacr          = 0x00040060,
 };
 
-static struct imxuart_platform_data uart_pdata[] = {
-       {
-               .flags = IMXUART_HAVE_RTSCTS,
-       },
-       {
-               .flags = IMXUART_HAVE_RTSCTS,
+static void eukrea_mbimx27_bl_set_intensity(int intensity)
+{
+       if (intensity)
+               gpio_direction_output(GPIO_PORTE | 5, 1);
+       else
+               gpio_direction_output(GPIO_PORTE | 5, 0);
+}
+
+static struct generic_bl_info eukrea_mbimx27_bl_info = {
+       .name                   = "eukrea_mbimx27-bl",
+       .max_intensity          = 0xff,
+       .default_intensity      = 0xff,
+       .set_bl_intensity       = eukrea_mbimx27_bl_set_intensity,
+};
+
+static struct platform_device eukrea_mbimx27_bl_dev = {
+       .name                   = "generic-bl",
+       .id                     = 1,
+       .dev = {
+               .platform_data  = &eukrea_mbimx27_bl_info,
        },
 };
 
-#if defined(CONFIG_TOUCHSCREEN_ADS7846)
+static void eukrea_mbimx27_lcd_power_set(struct plat_lcd_data *pd,
+                                  unsigned int power)
+{
+       if (power)
+               gpio_direction_output(GPIO_PORTA | 25, 1);
+       else
+               gpio_direction_output(GPIO_PORTA | 25, 0);
+}
+
+static struct plat_lcd_data eukrea_mbimx27_lcd_power_data = {
+       .set_power              = eukrea_mbimx27_lcd_power_set,
+};
+
+static struct platform_device eukrea_mbimx27_lcd_powerdev = {
+       .name                   = "platform-lcd",
+       .dev.platform_data      = &eukrea_mbimx27_lcd_power_data,
+};
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+       .flags = IMXUART_HAVE_RTSCTS,
+};
+
+#if defined(CONFIG_TOUCHSCREEN_ADS7846) \
        || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
 
 #define ADS7846_PENDOWN (GPIO_PORTD | 25)
@@ -173,7 +262,6 @@ static void ads7846_dev_init(void)
                printk(KERN_ERR "can't get ads746 pen down GPIO\n");
                return;
        }
-
        gpio_direction_input(ADS7846_PENDOWN);
 }
 
@@ -186,7 +274,9 @@ static struct ads7846_platform_data ads7846_config __initdata = {
        .get_pendown_state      = ads7846_get_pendown_state,
        .keep_vref_on           = 1,
 };
+#endif
 
+#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
 static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = {
        [0] = {
                .modalias       = "ads7846",
@@ -201,16 +291,30 @@ static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = {
 
 static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28};
 
-static struct spi_imx_master eukrea_mbimx27_spi_0_data = {
+static const struct spi_imx_master eukrea_mbimx27_spi0_data __initconst = {
        .chipselect     = eukrea_mbimx27_spi_cs,
        .num_chipselect = ARRAY_SIZE(eukrea_mbimx27_spi_cs),
 };
 #endif
 
+static struct i2c_board_info eukrea_mbimx27_i2c_devices[] = {
+       {
+               I2C_BOARD_INFO("tlv320aic23", 0x1a),
+       },
+};
+
 static struct platform_device *platform_devices[] __initdata = {
        &leds_gpio,
 };
 
+static struct imxmmc_platform_data sdhc_pdata = {
+       .dat3_card_detect = 1,
+};
+
+struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata = {
+       .flags = IMX_SSI_DMA | IMX_SSI_USE_I2S_SLAVE,
+};
+
 /*
  * system init for baseboard usage. Will be called by cpuimx27 init.
  *
@@ -222,21 +326,52 @@ void __init eukrea_mbimx27_baseboard_init(void)
        mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins,
                ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27");
 
-       mxc_register_device(&mxc_uart_device1, &uart_pdata[0]);
-       mxc_register_device(&mxc_uart_device2, &uart_pdata[1]);
+#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \
+       || defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE)
+       /* SSI unit master I2S codec connected to SSI_PINS_4*/
+       mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
+                       MXC_AUDMUX_V1_PCR_SYN |
+                       MXC_AUDMUX_V1_PCR_TFSDIR |
+                       MXC_AUDMUX_V1_PCR_TCLKDIR |
+                       MXC_AUDMUX_V1_PCR_RFSDIR |
+                       MXC_AUDMUX_V1_PCR_RCLKDIR |
+                       MXC_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
+                       MXC_AUDMUX_V1_PCR_RFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
+                       MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4)
+       );
+       mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR3_SSI_PINS_4,
+                       MXC_AUDMUX_V1_PCR_SYN |
+                       MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0)
+       );
+#endif
+
+       imx27_add_imx_uart1(&uart_pdata);
+       imx27_add_imx_uart2(&uart_pdata);
+#if !defined(MACH_EUKREA_CPUIMX27_USEUART4)
+       imx27_add_imx_uart3(&uart_pdata);
+#endif
 
        mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data);
-       mxc_register_device(&mxc_sdhc_device0, NULL);
+       mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata);
 
-#if defined(CONFIG_TOUCHSCREEN_ADS7846)
+       i2c_register_board_info(0, eukrea_mbimx27_i2c_devices,
+                               ARRAY_SIZE(eukrea_mbimx27_i2c_devices));
+
+       mxc_register_device(&imx_ssi_device0, &eukrea_mbimx27_ssi_pdata);
+
+#if defined(CONFIG_TOUCHSCREEN_ADS7846) \
        || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-       /* SPI and ADS7846 Touchscreen controler init */
-       mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
+       /* ADS7846 Touchscreen controller init */
        mxc_gpio_mode(GPIO_PORTD | 25 | GPIO_GPIO | GPIO_IN);
-       mxc_register_device(&mxc_spi_device0, &eukrea_mbimx27_spi_0_data);
+       ads7846_dev_init();
+#endif
+
+#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
+       /* SPI_CS0 init */
+       mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
+       imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data);
        spi_register_board_info(eukrea_mbimx27_spi_board_info,
                        ARRAY_SIZE(eukrea_mbimx27_spi_board_info));
-       ads7846_dev_init();
 #endif
 
        /* Leds configuration */
@@ -244,6 +379,14 @@ void __init eukrea_mbimx27_baseboard_init(void)
        mxc_gpio_mode(GPIO_PORTF | 19 | GPIO_GPIO | GPIO_OUT);
        /* Backlight */
        mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT);
+       gpio_request(GPIO_PORTE | 5, "backlight");
+       platform_device_register(&eukrea_mbimx27_bl_dev);
+       /* LCD Reset */
+       mxc_gpio_mode(GPIO_PORTA | 25 | GPIO_GPIO | GPIO_OUT);
+       gpio_request(GPIO_PORTA | 25, "lcd_enable");
+       platform_device_register(&eukrea_mbimx27_lcd_powerdev);
+
+       mxc_register_device(&imx_kpp_device, &eukrea_mbimx27_keymap_data);
 
        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }

diff --git a/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h b/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h
new file mode 100644 (file)
index 0000000..df5f522
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h
@@ -0,0 +1,10 @@
+#ifndef __MACH_DMA_MX1_MX2_H__
+#define __MACH_DMA_MX1_MX2_H__
+/*
+ * Don't use this header in new code, it will go away when all users are
+ * converted to mach/dma-v1.h
+ */
+
+#include <mach/dma-v1.h>
+
+#endif /* ifndef __MACH_DMA_MX1_MX2_H__ */

diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/mach-imx/include/mach/dma-v1.h
similarity index 93%
rename from arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
rename to arch/arm/mach-imx/include/mach/dma-v1.h
index 7c4870bd5a2144e39697501ce4b85e42e1e36459..287431cc13e59d32f4e592d6e1d58eb247c378b2 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
+++ b/arch/arm/mach-imx/include/mach/dma-v1.h
@@ -1,5 +1,5 @@
 /*
- *  linux/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
+ *  linux/arch/arm/mach-imx/include/mach/dma-v1.h
  *
  *  i.MX DMA registration and IRQ dispatching
  *
@@ -22,8 +22,10 @@
  * MA 02110-1301, USA.
  */
 
-#ifndef __ASM_ARCH_MXC_DMA_H
-#define __ASM_ARCH_MXC_DMA_H
+#ifndef __MACH_DMA_V1_H__
+#define __MACH_DMA_V1_H__
+
+#define imx_has_dma_v1()       (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
 
 #define IMX_DMA_CHANNELS  16
 
@@ -102,4 +104,4 @@ enum imx_dma_prio {
 
 int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
 
-#endif /* _ASM_ARCH_MXC_DMA_H */
+#endif /* __MACH_DMA_V1_H__ */

diff --git a/arch/arm/mach-mx2/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
similarity index 66%
rename from arch/arm/mach-mx2/mach-cpuimx27.c
rename to arch/arm/mach-imx/mach-cpuimx27.c
index 1f616dcaabc9bbf1089438c29e81bc57d0140dea..575ff1ae85a738f84cf48720d19e850b96caa0e5 100644 (file)
--- a/arch/arm/mach-mx2/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -26,20 +26,24 @@
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <linux/fsl_devices.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 
-#include <mach/board-eukrea_cpuimx27.h>
+#include <mach/eukrea-baseboards.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/i2c.h>
 #include <mach/iomux-mx27.h>
-#include <mach/imx-uart.h>
 #include <mach/mxc_nand.h>
+#include <mach/mxc_ehci.h>
+#include <mach/ulpi.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 static int eukrea_cpuimx27_pins[] = {
@@ -49,10 +53,12 @@ static int eukrea_cpuimx27_pins[] = {
        PE14_PF_UART1_CTS,
        PE15_PF_UART1_RTS,
        /* UART4 */
+#if defined(MACH_EUKREA_CPUIMX27_USEUART4)
        PB26_AF_UART4_RTS,
        PB28_AF_UART4_TXD,
        PB29_AF_UART4_CTS,
        PB31_AF_UART4_RXD,
+#endif
        /* FEC */
        PD0_AIN_FEC_TXD0,
        PD1_AIN_FEC_TXD1,
@@ -76,19 +82,47 @@ static int eukrea_cpuimx27_pins[] = {
        PD17_PF_I2C_DATA,
        PD18_PF_I2C_CLK,
        /* SDHC2 */
+#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
        PB4_PF_SD2_D0,
        PB5_PF_SD2_D1,
        PB6_PF_SD2_D2,
        PB7_PF_SD2_D3,
        PB8_PF_SD2_CMD,
        PB9_PF_SD2_CLK,
+#endif
 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
        /* Quad UART's IRQ */
-       GPIO_PORTD | 22 | GPIO_GPIO | GPIO_IN,
-       GPIO_PORTD | 23 | GPIO_GPIO | GPIO_IN,
-       GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN,
-       GPIO_PORTD | 30 | GPIO_GPIO | GPIO_IN,
+       GPIO_PORTB | 22 | GPIO_GPIO | GPIO_IN,
+       GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN,
+       GPIO_PORTB | 27 | GPIO_GPIO | GPIO_IN,
+       GPIO_PORTB | 30 | GPIO_GPIO | GPIO_IN,
 #endif
+       /* OTG */
+       PC7_PF_USBOTG_DATA5,
+       PC8_PF_USBOTG_DATA6,
+       PC9_PF_USBOTG_DATA0,
+       PC10_PF_USBOTG_DATA2,
+       PC11_PF_USBOTG_DATA1,
+       PC12_PF_USBOTG_DATA4,
+       PC13_PF_USBOTG_DATA3,
+       PE0_PF_USBOTG_NXT,
+       PE1_PF_USBOTG_STP,
+       PE2_PF_USBOTG_DIR,
+       PE24_PF_USBOTG_CLK,
+       PE25_PF_USBOTG_DATA7,
+       /* USBH2 */
+       PA0_PF_USBH2_CLK,
+       PA1_PF_USBH2_DIR,
+       PA2_PF_USBH2_DATA7,
+       PA3_PF_USBH2_NXT,
+       PA4_PF_USBH2_STP,
+       PD19_AF_USBH2_DATA4,
+       PD20_AF_USBH2_DATA3,
+       PD21_AF_USBH2_DATA6,
+       PD22_AF_USBH2_DATA0,
+       PD23_AF_USBH2_DATA2,
+       PD24_AF_USBH2_DATA1,
+       PD26_AF_USBH2_DATA5,
 };
 
 static struct physmap_flash_data eukrea_cpuimx27_flash_data = {
@@ -111,15 +145,12 @@ static struct platform_device eukrea_cpuimx27_nor_mtd_device = {
        .resource = &eukrea_cpuimx27_flash_resource,
 };
 
-static struct imxuart_platform_data uart_pdata[] = {
-       {
-               .flags = IMXUART_HAVE_RTSCTS,
-       }, {
-               .flags = IMXUART_HAVE_RTSCTS,
-       },
+static const struct imxuart_platform_data uart_pdata __initconst = {
+       .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static struct mxc_nand_platform_data eukrea_cpuimx27_nand_board_info = {
+static const struct mxc_nand_platform_data
+cpuimx27_nand_board_info __initconst = {
        .width = 1,
        .hw_ecc = 1,
 };
@@ -127,9 +158,11 @@ static struct mxc_nand_platform_data eukrea_cpuimx27_nand_board_info = {
 static struct platform_device *platform_devices[] __initdata = {
        &eukrea_cpuimx27_nor_mtd_device,
        &mxc_fec_device,
+       &mxc_wdt,
+       &mxc_w1_master_device,
 };
 
-static struct imxi2c_platform_data eukrea_cpuimx27_i2c_1_data = {
+static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = {
        .bitrate = 100000,
 };
 
@@ -182,34 +215,83 @@ static struct platform_device serial_device = {
 };
 #endif
 
+#if defined(CONFIG_USB_ULPI)
+static struct mxc_usbh_platform_data otg_pdata = {
+       .portsc = MXC_EHCI_MODE_ULPI,
+       .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
+};
+
+static struct mxc_usbh_platform_data usbh2_pdata = {
+       .portsc = MXC_EHCI_MODE_ULPI,
+       .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
+};
+#endif
+
+static struct fsl_usb2_platform_data otg_device_pdata = {
+       .operating_mode = FSL_USB2_DR_DEVICE,
+       .phy_mode       = FSL_USB2_PHY_ULPI,
+};
+
+static int otg_mode_host;
+
+static int __init eukrea_cpuimx27_otg_mode(char *options)
+{
+       if (!strcmp(options, "host"))
+               otg_mode_host = 1;
+       else if (!strcmp(options, "device"))
+               otg_mode_host = 0;
+       else
+               pr_info("otg_mode neither \"host\" nor \"device\". "
+                       "Defaulting to device\n");
+       return 0;
+}
+__setup("otg_mode=", eukrea_cpuimx27_otg_mode);
+
 static void __init eukrea_cpuimx27_init(void)
 {
        mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins,
                ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27");
 
-       mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
+       imx27_add_imx_uart0(&uart_pdata);
 
-       mxc_register_device(&imx27_nand_device,
-                       &eukrea_cpuimx27_nand_board_info);
+       imx27_add_mxc_nand(&cpuimx27_nand_board_info);
 
        i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
                                ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
 
-       mxc_register_device(&mxc_i2c_device0, &eukrea_cpuimx27_i2c_1_data);
+       imx27_add_i2c_imx1(&cpuimx27_i2c1_data);
 
        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 
 #if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
        /* SDHC2 can be used for Wifi */
        mxc_register_device(&mxc_sdhc_device1, NULL);
+#endif
+#if defined(MACH_EUKREA_CPUIMX27_USEUART4)
        /* in which case UART4 is also used for Bluetooth */
-       mxc_register_device(&mxc_uart_device3, &uart_pdata[1]);
+       imx27_add_imx_uart3(&uart_pdata);
 #endif
 
 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
        platform_device_register(&serial_device);
 #endif
 
+#if defined(CONFIG_USB_ULPI)
+       if (otg_mode_host) {
+               otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                               USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+
+               mxc_register_device(&mxc_otg_host, &otg_pdata);
+       }
+
+       usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                               USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+
+       mxc_register_device(&mxc_usbh2, &usbh2_pdata);
+#endif
+       if (!otg_mode_host)
+               mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
+
 #ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
        eukrea_mbimx27_baseboard_init();
 #endif

diff --git a/arch/arm/mach-mx2/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
similarity index 86%
rename from arch/arm/mach-mx2/mach-imx27lite.c
rename to arch/arm/mach-imx/mach-imx27lite.c
index b5710bf18b9684d7f65682e52060aa16b4f48b1b..22a2b5d912136590addc1fcd05f32d905b1af8d0 100644 (file)
--- a/arch/arm/mach-mx2/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/platform_device.h>
@@ -26,10 +22,9 @@
 #include <asm/mach/map.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx27.h>
-#include <mach/board-mx27lite.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 static unsigned int mx27lite_pins[] = {
@@ -59,7 +54,7 @@ static unsigned int mx27lite_pins[] = {
        PF23_AIN_FEC_TX_EN,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -71,7 +66,7 @@ static void __init mx27lite_init(void)
 {
        mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins),
                "imx27lite");
-       mxc_register_device(&mxc_uart_device0, &uart_pdata);
+       imx27_add_imx_uart0(&uart_pdata);
        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }
 

diff --git a/arch/arm/mach-mx1/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
similarity index 81%
rename from arch/arm/mach-mx1/mach-mx1ads.c
rename to arch/arm/mach-imx/mach-mx1ads.c
index 51f3cfd83db2ee4615d68824797db1b755a61fb1..77a760cfadc0260dba05324318e00e3d5605defd 100644 (file)
--- a/arch/arm/mach-mx1/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -26,10 +26,10 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/i2c.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx1.h>
 #include <mach/irqs.h>
 
+#include "devices-imx1.h"
 #include "devices.h"
 
 static int mx1ads_pins[] = {
@@ -58,12 +58,12 @@ static int mx1ads_pins[] = {
  * UARTs platform data
  */
 
-static struct imxuart_platform_data uart_pdata[] = {
-       {
-               .flags = IMXUART_HAVE_RTSCTS,
-       }, {
-               .flags = IMXUART_HAVE_RTSCTS,
-       },
+static const struct imxuart_platform_data uart0_pdata __initconst = {
+       .flags = IMXUART_HAVE_RTSCTS,
+};
+       
+static const struct imxuart_platform_data uart1_pdata __initconst = {
+       .flags = IMXUART_HAVE_RTSCTS,
 };
 
 /*
@@ -75,8 +75,8 @@ static struct physmap_flash_data mx1ads_flash_data = {
 };
 
 static struct resource flash_resource = {
-       .start  = IMX_CS0_PHYS,
-       .end    = IMX_CS0_PHYS + SZ_32M - 1,
+       .start  = MX1_CS0_PHYS,
+       .end    = MX1_CS0_PHYS + SZ_32M - 1,
        .flags  = IORESOURCE_MEM,
 };
 
@@ -98,7 +98,7 @@ static struct pcf857x_platform_data pcf857x_data[] = {
        }
 };
 
-static struct imxi2c_platform_data mx1ads_i2c_data = {
+static const struct imxi2c_platform_data mx1ads_i2c_data __initconst = {
        .bitrate = 100000,
 };
 
@@ -121,8 +121,8 @@ static void __init mx1ads_init(void)
                ARRAY_SIZE(mx1ads_pins), "mx1ads");
 
        /* UART */
-       mxc_register_device(&imx_uart1_device, &uart_pdata[0]);
-       mxc_register_device(&imx_uart2_device, &uart_pdata[1]);
+       imx1_add_imx_uart0(&uart0_pdata);
+       imx1_add_imx_uart1(&uart1_pdata);
 
        /* Physmap flash */
        mxc_register_device(&flash_device, &mx1ads_flash_data);
@@ -131,7 +131,7 @@ static void __init mx1ads_init(void)
        i2c_register_board_info(0, mx1ads_i2c_devices,
                                ARRAY_SIZE(mx1ads_i2c_devices));
 
-       mxc_register_device(&imx_i2c_device, &mx1ads_i2c_data);
+       imx1_add_i2c_imx(&mx1ads_i2c_data);
 }
 
 static void __init mx1ads_timer_init(void)
@@ -145,8 +145,8 @@ struct sys_timer mx1ads_timer = {
 
 MACHINE_START(MX1ADS, "Freescale MX1ADS")
        /* Maintainer: Sascha Hauer, Pengutronix */
-       .phys_io        = IMX_IO_PHYS,
-       .io_pg_offst    = (IMX_IO_BASE >> 18) & 0xfffc,
+       .phys_io        = MX1_IO_BASE_ADDR,
+       .io_pg_offst    = (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc,
        .boot_params    = MX1_PHYS_OFFSET + 0x100,
        .map_io         = mx1_map_io,
        .init_irq       = mx1_init_irq,
@@ -155,8 +155,8 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS")
 MACHINE_END
 
 MACHINE_START(MXLADS, "Freescale MXLADS")
-       .phys_io        = IMX_IO_PHYS,
-       .io_pg_offst    = (IMX_IO_BASE >> 18) & 0xfffc,
+       .phys_io        = MX1_IO_BASE_ADDR,
+       .io_pg_offst    = (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc,
        .boot_params    = MX1_PHYS_OFFSET + 0x100,
        .map_io         = mx1_map_io,
        .init_irq       = mx1_init_irq,

diff --git a/arch/arm/mach-mx2/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
similarity index 77%
rename from arch/arm/mach-mx2/mach-mx21ads.c
rename to arch/arm/mach-imx/mach-mx21ads.c
index 113e58d7cb4025962f0eebd85ac3fbc5b63dc398..96d7f8189f3253a0feb79d0278c51abbc3e4e5bf 100644 (file)
--- a/arch/arm/mach-mx2/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/platform_device.h>
@@ -28,15 +24,49 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <mach/imx-uart.h>
 #include <mach/imxfb.h>
 #include <mach/iomux-mx21.h>
 #include <mach/mxc_nand.h>
 #include <mach/mmc.h>
-#include <mach/board-mx21ads.h>
 
+#include "devices-imx21.h"
 #include "devices.h"
 
+/*
+ * Memory-mapped I/O on MX21ADS base board
+ */
+#define MX21ADS_MMIO_BASE_ADDR   0xf5000000
+#define MX21ADS_MMIO_SIZE        SZ_16M
+
+#define MX21ADS_REG_ADDR(offset)    (void __force __iomem *) \
+               (MX21ADS_MMIO_BASE_ADDR + (offset))
+
+#define MX21ADS_CS8900A_IRQ         IRQ_GPIOE(11)
+#define MX21ADS_CS8900A_IOBASE_REG  MX21ADS_REG_ADDR(0x000000)
+#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
+#define MX21ADS_VERSION_REG         MX21ADS_REG_ADDR(0x400000)
+#define MX21ADS_IO_REG              MX21ADS_REG_ADDR(0x800000)
+
+/* MX21ADS_IO_REG bit definitions */
+#define MX21ADS_IO_SD_WP        0x0001 /* read */
+#define MX21ADS_IO_TP6          0x0001 /* write */
+#define MX21ADS_IO_SW_SEL       0x0002 /* read */
+#define MX21ADS_IO_TP7          0x0002 /* write */
+#define MX21ADS_IO_RESET_E_UART 0x0004
+#define MX21ADS_IO_RESET_BASE   0x0008
+#define MX21ADS_IO_CSI_CTL2     0x0010
+#define MX21ADS_IO_CSI_CTL1     0x0020
+#define MX21ADS_IO_CSI_CTL0     0x0040
+#define MX21ADS_IO_UART1_EN     0x0080
+#define MX21ADS_IO_UART4_EN     0x0100
+#define MX21ADS_IO_LCDON        0x0200
+#define MX21ADS_IO_IRDA_EN      0x0400
+#define MX21ADS_IO_IRDA_FIR_SEL 0x0800
+#define MX21ADS_IO_IRDA_MD0_B   0x1000
+#define MX21ADS_IO_IRDA_MD1     0x2000
+#define MX21ADS_IO_LED4_ON      0x4000
+#define MX21ADS_IO_LED3_ON      0x8000
+
 static unsigned int mx21ads_pins[] = {
 
        /* CS8900A */
@@ -133,14 +163,13 @@ static struct platform_device mx21ads_nor_mtd_device = {
        .resource = &mx21ads_flash_resource,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata_rts __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static struct imxuart_platform_data uart_norts_pdata = {
+static const struct imxuart_platform_data uart_pdata_norts __initconst = {
 };
 
-
 static int mx21ads_fb_init(struct platform_device *pdev)
 {
        u16 tmp;
@@ -227,7 +256,8 @@ static struct imxmmc_platform_data mx21ads_sdhc_pdata = {
        .exit = mx21ads_sdhc_exit,
 };
 
-static struct mxc_nand_platform_data mx21ads_nand_board_info = {
+static const struct mxc_nand_platform_data
+mx21ads_nand_board_info __initconst = {
        .width = 1,
        .hw_ecc = 1,
 };
@@ -263,12 +293,12 @@ static void __init mx21ads_board_init(void)
        mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins),
                        "mx21ads");
 
-       mxc_register_device(&mxc_uart_device0, &uart_pdata);
-       mxc_register_device(&mxc_uart_device2, &uart_norts_pdata);
-       mxc_register_device(&mxc_uart_device3, &uart_pdata);
+       imx21_add_imx_uart0(&uart_pdata_rts);
+       imx21_add_imx_uart2(&uart_pdata_norts);
+       imx21_add_imx_uart3(&uart_pdata_rts);
        mxc_register_device(&mxc_fb_device, &mx21ads_fb_data);
        mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata);
-       mxc_register_device(&imx21_nand_device, &mx21ads_nand_board_info);
+       imx21_add_mxc_nand(&mx21ads_nand_board_info);
 
        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }

diff --git a/arch/arm/mach-mx2/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
similarity index 74%
rename from arch/arm/mach-mx2/mach-mx27_3ds.c
rename to arch/arm/mach-imx/mach-mx27_3ds.c
index b2f4e0db3fb3eeea439f25627bdc043dec6b5c76..e66ffaa1c26c26dbd4ba2b7d7b75c2455b06f5a1 100644 (file)
--- a/arch/arm/mach-mx2/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -12,23 +12,25 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * This machine is known as:
+ *  - i.MX27 3-Stack Development System
+ *  - i.MX27 Platform Development Kit (i.MX27 PDK)
  */
 
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
+#include <linux/input/matrix_keypad.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx27.h>
-#include <mach/board-mx27pdk.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 static unsigned int mx27pdk_pins[] = {
@@ -58,7 +60,7 @@ static unsigned int mx27pdk_pins[] = {
        PF23_AIN_FEC_TX_EN,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -66,12 +68,34 @@ static struct platform_device *platform_devices[] __initdata = {
        &mxc_fec_device,
 };
 
+/*
+ * Matrix keyboard
+ */
+
+static const uint32_t mx27_3ds_keymap[] = {
+       KEY(0, 0, KEY_UP),
+       KEY(0, 1, KEY_DOWN),
+       KEY(1, 0, KEY_RIGHT),
+       KEY(1, 1, KEY_LEFT),
+       KEY(1, 2, KEY_ENTER),
+       KEY(2, 0, KEY_F6),
+       KEY(2, 1, KEY_F8),
+       KEY(2, 2, KEY_F9),
+       KEY(2, 3, KEY_F10),
+};
+
+static struct matrix_keymap_data mx27_3ds_keymap_data = {
+       .keymap         = mx27_3ds_keymap,
+       .keymap_size    = ARRAY_SIZE(mx27_3ds_keymap),
+};
+
 static void __init mx27pdk_init(void)
 {
        mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
                "mx27pdk");
-       mxc_register_device(&mxc_uart_device0, &uart_pdata);
+       imx27_add_imx_uart0(&uart_pdata);
        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+       mxc_register_device(&imx_kpp_device, &mx27_3ds_keymap_data);
 }
 
 static void __init mx27pdk_timer_init(void)

diff --git a/arch/arm/mach-mx2/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
similarity index 82%
rename from arch/arm/mach-mx2/mach-mx27ads.c
rename to arch/arm/mach-imx/mach-mx27ads.c
index 6ce323669e58f3efea4f10951b7cff0a38355f07..9c77da98a10eec59060e016088a63516a343aff2 100644 (file)
--- a/arch/arm/mach-mx2/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/platform_device.h>
@@ -32,16 +28,44 @@
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 #include <mach/gpio.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx27.h>
-#include <mach/board-mx27ads.h>
 #include <mach/mxc_nand.h>
-#include <mach/i2c.h>
 #include <mach/imxfb.h>
 #include <mach/mmc.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
+/*
+ * Base address of PBC controller, CS4
+ */
+#define PBC_BASE_ADDRESS        0xf4300000
+#define PBC_REG_ADDR(offset)    (void __force __iomem *) \
+               (PBC_BASE_ADDRESS + (offset))
+
+/* When the PBC address connection is fixed in h/w, defined as 1 */
+#define PBC_ADDR_SH             0
+
+/* Offsets for the PBC Controller register */
+/*
+ * PBC Board version register offset
+ */
+#define PBC_VERSION_REG         PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 1 set address.
+ */
+#define PBC_BCTRL1_SET_REG      PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 1 clear address.
+ */
+#define PBC_BCTRL1_CLEAR_REG    PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
+
+/* PBC Board Control Register 1 bit definitions */
+#define PBC_BCTRL1_LCDON        0x0800 /* Enable the LCD */
+
+/* to determine the correct external crystal reference */
+#define CKIH_27MHZ_BIT_SET      (1 << 3)
+
 static unsigned int mx27ads_pins[] = {
        /* UART0 */
        PE12_PF_UART1_TXD,
@@ -141,7 +165,8 @@ static unsigned int mx27ads_pins[] = {
        PB9_PF_SD2_CLK,
 };
 
-static struct mxc_nand_platform_data mx27ads_nand_board_info = {
+static const struct mxc_nand_platform_data
+mx27ads_nand_board_info __initconst = {
        .width = 1,
        .hw_ecc = 1,
 };
@@ -168,7 +193,7 @@ static struct platform_device mx27ads_nor_mtd_device = {
        .resource = &mx27ads_flash_resource,
 };
 
-static struct imxi2c_platform_data mx27ads_i2c_data = {
+static const struct imxi2c_platform_data mx27ads_i2c1_data __initconst = {
        .bitrate = 100000,
 };
 
@@ -263,20 +288,8 @@ static struct platform_device *platform_devices[] __initdata = {
        &mxc_w1_master_device,
 };
 
-static struct imxuart_platform_data uart_pdata[] = {
-       {
-               .flags = IMXUART_HAVE_RTSCTS,
-       }, {
-               .flags = IMXUART_HAVE_RTSCTS,
-       }, {
-               .flags = IMXUART_HAVE_RTSCTS,
-       }, {
-               .flags = IMXUART_HAVE_RTSCTS,
-       }, {
-               .flags = IMXUART_HAVE_RTSCTS,
-       }, {
-               .flags = IMXUART_HAVE_RTSCTS,
-       },
+static const struct imxuart_platform_data uart_pdata __initconst = {
+       .flags = IMXUART_HAVE_RTSCTS,
 };
 
 static void __init mx27ads_board_init(void)
@@ -284,18 +297,18 @@ static void __init mx27ads_board_init(void)
        mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
                        "mx27ads");
 
-       mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
-       mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
-       mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
-       mxc_register_device(&mxc_uart_device3, &uart_pdata[3]);
-       mxc_register_device(&mxc_uart_device4, &uart_pdata[4]);
-       mxc_register_device(&mxc_uart_device5, &uart_pdata[5]);
-       mxc_register_device(&imx27_nand_device, &mx27ads_nand_board_info);
+       imx27_add_imx_uart0(&uart_pdata);
+       imx27_add_imx_uart1(&uart_pdata);
+       imx27_add_imx_uart2(&uart_pdata);
+       imx27_add_imx_uart3(&uart_pdata);
+       imx27_add_imx_uart4(&uart_pdata);
+       imx27_add_imx_uart5(&uart_pdata);
+       imx27_add_mxc_nand(&mx27ads_nand_board_info);
 
        /* only the i2c master 1 is used on this CPU card */
        i2c_register_board_info(1, mx27ads_i2c_devices,
                                ARRAY_SIZE(mx27ads_i2c_devices));
-       mxc_register_device(&mxc_i2c_device1, &mx27ads_i2c_data);
+       imx27_add_i2c_imx1(&mx27ads_i2c1_data);
        mxc_register_device(&mxc_fb_device, &mx27ads_fb_data);
        mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
        mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata);
@@ -342,4 +355,3 @@ MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
        .init_machine   = mx27ads_board_init,
        .timer          = &mx27ads_timer,
 MACHINE_END
-

diff --git a/arch/arm/mach-mx2/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
similarity index 86%
rename from arch/arm/mach-mx2/mach-mxt_td60.c
rename to arch/arm/mach-imx/mach-mxt_td60.c
index bc3855992677d34a4cd6ed9064c089d85e568022..a3a1e452d4c5a15bef12ced37d70d275fabd2fad 100644 (file)
--- a/arch/arm/mach-mx2/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/platform_device.h>
@@ -32,14 +28,13 @@
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 #include <linux/gpio.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx27.h>
 #include <mach/mxc_nand.h>
-#include <mach/i2c.h>
 #include <linux/i2c/pca953x.h>
 #include <mach/imxfb.h>
 #include <mach/mmc.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 static unsigned int mxt_td60_pins[] __initdata = {
@@ -128,12 +123,13 @@ static unsigned int mxt_td60_pins[] __initdata = {
        PB9_PF_SD2_CLK,
 };
 
-static struct mxc_nand_platform_data mxt_td60_nand_board_info = {
+static const struct mxc_nand_platform_data
+mxt_td60_nand_board_info __initconst = {
        .width = 1,
        .hw_ecc = 1,
 };
 
-static struct imxi2c_platform_data mxt_td60_i2c_data = {
+static const struct imxi2c_platform_data mxt_td60_i2c0_data __initconst = {
        .bitrate = 100000,
 };
 
@@ -173,7 +169,7 @@ static struct i2c_board_info mxt_td60_i2c_devices[] = {
        },
 };
 
-static struct imxi2c_platform_data mxt_td60_i2c2_data = {
+static const struct imxi2c_platform_data mxt_td60_i2c1_data __initconst = {
        .bitrate = 100000,
 };
 
@@ -239,14 +235,8 @@ static struct platform_device *platform_devices[] __initdata = {
        &mxc_fec_device,
 };
 
-static struct imxuart_platform_data uart_pdata[] = {
-       {
-               .flags = IMXUART_HAVE_RTSCTS,
-       }, {
-               .flags = IMXUART_HAVE_RTSCTS,
-       }, {
-               .flags = IMXUART_HAVE_RTSCTS,
-       },
+static const struct imxuart_platform_data uart_pdata __initconst = {
+       .flags = IMXUART_HAVE_RTSCTS,
 };
 
 static void __init mxt_td60_board_init(void)
@@ -254,10 +244,10 @@ static void __init mxt_td60_board_init(void)
        mxc_gpio_setup_multiple_pins(mxt_td60_pins, ARRAY_SIZE(mxt_td60_pins),
                        "MXT_TD60");
 
-       mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
-       mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
-       mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
-       mxc_register_device(&imx27_nand_device, &mxt_td60_nand_board_info);
+       imx27_add_imx_uart0(&uart_pdata);
+       imx27_add_imx_uart1(&uart_pdata);
+       imx27_add_imx_uart2(&uart_pdata);
+       imx27_add_mxc_nand(&mxt_td60_nand_board_info);
 
        i2c_register_board_info(0, mxt_td60_i2c_devices,
                                ARRAY_SIZE(mxt_td60_i2c_devices));
@@ -265,8 +255,8 @@ static void __init mxt_td60_board_init(void)
        i2c_register_board_info(1, mxt_td60_i2c2_devices,
                                ARRAY_SIZE(mxt_td60_i2c2_devices));
 
-       mxc_register_device(&mxc_i2c_device0, &mxt_td60_i2c_data);
-       mxc_register_device(&mxc_i2c_device1, &mxt_td60_i2c2_data);
+       imx27_add_i2c_imx0(&mxt_td60_i2c0_data);
+       imx27_add_i2c_imx1(&mxt_td60_i2c1_data);
        mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data);
        mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
 

diff --git a/arch/arm/mach-mx2/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
similarity index 80%
rename from arch/arm/mach-mx2/mach-pca100.c
rename to arch/arm/mach-imx/mach-pca100.c
index a87422ed4ff5a1ea9bd4f07605092bc646842ca9..6c92deaf468f6677559655fe366fba8aad97006c 100644 (file)
--- a/arch/arm/mach-mx2/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -36,12 +36,7 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx27.h>
-#include <mach/i2c.h>
 #include <asm/mach/time.h>
-#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
-#include <mach/spi.h>
-#endif
-#include <mach/imx-uart.h>
 #include <mach/audmux.h>
 #include <mach/ssi.h>
 #include <mach/mxc_nand.h>
@@ -49,11 +44,16 @@
 #include <mach/mmc.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
+#include <mach/imxfb.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 #define OTG_PHY_CS_GPIO (GPIO_PORTB + 23)
 #define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24)
+#define SPI1_SS0 (GPIO_PORTD + 28)
+#define SPI1_SS1 (GPIO_PORTD + 27)
+#define SD2_CD (GPIO_PORTC + 29)
 
 static int pca100_pins[] = {
        /* UART1 */
@@ -68,6 +68,7 @@ static int pca100_pins[] = {
        PB7_PF_SD2_D3,
        PB8_PF_SD2_CMD,
        PB9_PF_SD2_CLK,
+       SD2_CD | GPIO_GPIO | GPIO_IN,
        /* FEC */
        PD0_AIN_FEC_TXD0,
        PD1_AIN_FEC_TXD1,
@@ -131,13 +132,42 @@ static int pca100_pins[] = {
        PD23_AF_USBH2_DATA2,
        PD24_AF_USBH2_DATA1,
        PD26_AF_USBH2_DATA5,
+       /* display */
+       PA5_PF_LSCLK,
+       PA6_PF_LD0,
+       PA7_PF_LD1,
+       PA8_PF_LD2,
+       PA9_PF_LD3,
+       PA10_PF_LD4,
+       PA11_PF_LD5,
+       PA12_PF_LD6,
+       PA13_PF_LD7,
+       PA14_PF_LD8,
+       PA15_PF_LD9,
+       PA16_PF_LD10,
+       PA17_PF_LD11,
+       PA18_PF_LD12,
+       PA19_PF_LD13,
+       PA20_PF_LD14,
+       PA21_PF_LD15,
+       PA22_PF_LD16,
+       PA23_PF_LD17,
+       PA26_PF_PS,
+       PA28_PF_HSYNC,
+       PA29_PF_VSYNC,
+       PA31_PF_OE_ACD,
+       /* free GPIO */
+       GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN, /* GPIO0_IRQ */
+       GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN, /* GPIO1_IRQ */
+       GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN, /* GPIO2_IRQ */
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static struct mxc_nand_platform_data pca100_nand_board_info = {
+static const struct mxc_nand_platform_data
+pca100_nand_board_info __initconst = {
        .width = 1,
        .hw_ecc = 1,
 };
@@ -148,7 +178,7 @@ static struct platform_device *platform_devices[] __initdata = {
        &mxc_wdt,
 };
 
-static struct imxi2c_platform_data pca100_i2c_1_data = {
+static const struct imxi2c_platform_data pca100_i2c1_data __initconst = {
        .bitrate = 100000,
 };
 
@@ -189,9 +219,9 @@ static struct spi_board_info pca100_spi_board_info[] __initdata = {
        },
 };
 
-static int pca100_spi_cs[] = {GPIO_PORTD + 28, GPIO_PORTD + 27};
+static int pca100_spi_cs[] = {SPI1_SS0, SPI1_SS1};
 
-static struct spi_imx_master pca100_spi_0_data = {
+static const struct spi_imx_master pca100_spi0_data __initconst = {
        .chipselect     = pca100_spi_cs,
        .num_chipselect = ARRAY_SIZE(pca100_spi_cs),
 };
@@ -253,6 +283,7 @@ static struct imxmmc_platform_data sdhc_pdata = {
        .exit = pca100_sdhc2_exit,
 };
 
+#if defined(CONFIG_USB_ULPI)
 static int otg_phy_init(struct platform_device *pdev)
 {
        gpio_set_value(OTG_PHY_CS_GPIO, 0);
@@ -276,6 +307,7 @@ static struct mxc_usbh_platform_data usbh2_pdata = {
        .portsc = MXC_EHCI_MODE_ULPI,
        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
+#endif
 
 static struct fsl_usb2_platform_data otg_device_pdata = {
        .operating_mode = FSL_USB2_DR_DEVICE,
@@ -297,6 +329,45 @@ static int __init pca100_otg_mode(char *options)
 }
 __setup("otg_mode=", pca100_otg_mode);
 
+/* framebuffer info */
+static struct imx_fb_videomode pca100_fb_modes[] = {
+       {
+               .mode = {
+                       .name           = "EMERGING-ETV570G0DHU",
+                       .refresh        = 60,
+                       .xres           = 640,
+                       .yres           = 480,
+                       .pixclock       = 39722, /* in ps (25.175 MHz) */
+                       .hsync_len      = 30,
+                       .left_margin    = 114,
+                       .right_margin   = 16,
+                       .vsync_len      = 3,
+                       .upper_margin   = 32,
+                       .lower_margin   = 0,
+               },
+               /*
+                * TFT
+                * Pixel pol active high
+                * HSYNC active low
+                * VSYNC active low
+                * use HSYNC for ACD count
+                * line clock disable while idle
+                * always enable line clock even if no data
+                */
+               .pcr = 0xf0c08080,
+               .bpp = 16,
+       },
+};
+
+static struct imx_fb_platform_data pca100_fb_data = {
+       .mode = pca100_fb_modes,
+       .num_modes = ARRAY_SIZE(pca100_fb_modes),
+
+       .pwmr           = 0x00A903FF,
+       .lscr1          = 0x00120300,
+       .dmacr          = 0x00020010,
+};
+
 static void __init pca100_init(void)
 {
        int ret;
@@ -320,33 +391,24 @@ static void __init pca100_init(void)
 
        mxc_register_device(&imx_ssi_device0, &pca100_ssi_pdata);
 
-       mxc_register_device(&mxc_uart_device0, &uart_pdata);
+       imx27_add_imx_uart0(&uart_pdata);
 
-       mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN);
        mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
 
-       mxc_register_device(&imx27_nand_device, &pca100_nand_board_info);
+       imx27_add_mxc_nand(&pca100_nand_board_info);
 
        /* only the i2c master 1 is used on this CPU card */
        i2c_register_board_info(1, pca100_i2c_devices,
                                ARRAY_SIZE(pca100_i2c_devices));
 
-       mxc_register_device(&mxc_i2c_device1, &pca100_i2c_1_data);
-
-       mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
-       mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_OUT);
-
-       /* GPIO0_IRQ */
-       mxc_gpio_mode(GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN);
-       /* GPIO1_IRQ */
-       mxc_gpio_mode(GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN);
-       /* GPIO2_IRQ */
-       mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN);
+       imx27_add_i2c_imx1(&pca100_i2c1_data);
 
 #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
+       mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN);
+       mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN);
        spi_register_board_info(pca100_spi_board_info,
                                ARRAY_SIZE(pca100_spi_board_info));
-       mxc_register_device(&mxc_spi_device0, &pca100_spi_0_data);
+       imx27_add_spi_imx0(&pca100_spi_0_data);
 #endif
 
        gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs");
@@ -372,6 +434,8 @@ static void __init pca100_init(void)
                mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
        }
 
+       mxc_register_device(&mxc_fb_device, &pca100_fb_data);
+
        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }
 

diff --git a/arch/arm/mach-mx2/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
similarity index 91%
rename from arch/arm/mach-mx2/mach-pcm038.c
rename to arch/arm/mach-imx/mach-pcm038.c
index 36c89431679a93edd5e66118ce9eb9b5838b9045..9212e8f37001d050418b505bdb7c8874b94cd9f0 100644 (file)
--- a/arch/arm/mach-mx2/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -35,14 +35,12 @@
 #include <mach/board-pcm038.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/i2c.h>
 #include <mach/iomux-mx27.h>
-#include <mach/imx-uart.h>
 #include <mach/mxc_nand.h>
-#include <mach/spi.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 static int pcm038_pins[] = {
@@ -162,17 +160,12 @@ static struct platform_device pcm038_nor_mtd_device = {
        .resource = &pcm038_flash_resource,
 };
 
-static struct imxuart_platform_data uart_pdata[] = {
-       {
-               .flags = IMXUART_HAVE_RTSCTS,
-       }, {
-               .flags = IMXUART_HAVE_RTSCTS,
-       }, {
-               .flags = IMXUART_HAVE_RTSCTS,
-       },
+static const struct imxuart_platform_data uart_pdata __initconst = {
+       .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static struct mxc_nand_platform_data pcm038_nand_board_info = {
+static const struct mxc_nand_platform_data
+pcm038_nand_board_info __initconst = {
        .width = 1,
        .hw_ecc = 1,
 };
@@ -192,7 +185,7 @@ static void __init pcm038_init_sram(void)
        mx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00);
 }
 
-static struct imxi2c_platform_data pcm038_i2c_1_data = {
+static const struct imxi2c_platform_data pcm038_i2c1_data __initconst = {
        .bitrate = 100000,
 };
 
@@ -215,7 +208,7 @@ static struct i2c_board_info pcm038_i2c_devices[] = {
 
 static int pcm038_spi_cs[] = {GPIO_PORTD + 28};
 
-static struct spi_imx_master pcm038_spi_0_data = {
+static const struct spi_imx_master pcm038_spi0_data __initconst = {
        .chipselect = pcm038_spi_cs,
        .num_chipselect = ARRAY_SIZE(pcm038_spi_cs),
 };
@@ -305,18 +298,18 @@ static void __init pcm038_init(void)
 
        pcm038_init_sram();
 
-       mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
-       mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
-       mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
+       imx27_add_imx_uart0(&uart_pdata);
+       imx27_add_imx_uart1(&uart_pdata);
+       imx27_add_imx_uart2(&uart_pdata);
 
        mxc_gpio_mode(PE16_AF_OWIRE);
-       mxc_register_device(&imx27_nand_device, &pcm038_nand_board_info);
+       imx27_add_mxc_nand(&pcm038_nand_board_info);
 
        /* only the i2c master 1 is used on this CPU card */
        i2c_register_board_info(1, pcm038_i2c_devices,
                                ARRAY_SIZE(pcm038_i2c_devices));
 
-       mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data);
+       imx27_add_i2c_imx1(&pcm038_i2c1_data);
 
        /* PE18 for user-LED D40 */
        mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT);
@@ -326,7 +319,7 @@ static void __init pcm038_init(void)
        /* MC13783 IRQ */
        mxc_gpio_mode(GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN);
 
-       mxc_register_device(&mxc_spi_device0, &pcm038_spi_0_data);
+       imx27_add_spi_imx0(&pcm038_spi0_data);
        spi_register_board_info(pcm038_spi_board_info,
                                ARRAY_SIZE(pcm038_spi_board_info));
 

diff --git a/arch/arm/mach-mx1/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
similarity index 89%
rename from arch/arm/mach-mx1/mach-scb9328.c
rename to arch/arm/mach-imx/mach-scb9328.c
index 7587a7a12460242d9f4b25b2233efef6dc5bab65..88bf0d1e26e6ebb3400e07db4f545e3f86c97b9b 100644 (file)
--- a/arch/arm/mach-mx1/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -22,17 +22,17 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx1.h>
 
+#include "devices-imx1.h"
 #include "devices.h"
 
 /*
  * This scb9328 has a 32MiB flash
  */
 static struct resource flash_resource = {
-       .start  = IMX_CS0_PHYS,
-       .end    = IMX_CS0_PHYS + (32 * 1024 * 1024) - 1,
+       .start  = MX1_CS0_PHYS,
+       .end    = MX1_CS0_PHYS + (32 * 1024 * 1024) - 1,
        .flags  = IORESOURCE_MEM,
 };
 
@@ -70,13 +70,13 @@ static struct dm9000_plat_data dm9000_platdata = {
 static struct resource dm9000x_resources[] = {
        {
                .name   = "address area",
-               .start  = IMX_CS5_PHYS,
-               .end    = IMX_CS5_PHYS + 1,
+               .start  = MX1_CS5_PHYS,
+               .end    = MX1_CS5_PHYS + 1,
                .flags  = IORESOURCE_MEM,       /* address access */
        }, {
                .name   = "data area",
-               .start  = IMX_CS5_PHYS + 4,
-               .end    = IMX_CS5_PHYS + 5,
+               .start  = MX1_CS5_PHYS + 4,
+               .end    = MX1_CS5_PHYS + 5,
                .flags  = IORESOURCE_MEM,       /* data access */
        }, {
                .start  = IRQ_GPIOC(3),
@@ -108,14 +108,13 @@ static int uart1_mxc_init(struct platform_device *pdev)
                        ARRAY_SIZE(mxc_uart1_pins), "UART1");
 }
 
-static int uart1_mxc_exit(struct platform_device *pdev)
+static void uart1_mxc_exit(struct platform_device *pdev)
 {
        mxc_gpio_release_multiple_pins(mxc_uart1_pins,
                        ARRAY_SIZE(mxc_uart1_pins));
-       return 0;
 }
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
        .init = uart1_mxc_init,
        .exit = uart1_mxc_exit,
        .flags = IMXUART_HAVE_RTSCTS,
@@ -131,7 +130,7 @@ static struct platform_device *devices[] __initdata = {
  */
 static void __init scb9328_init(void)
 {
-       mxc_register_device(&imx_uart1_device, &uart_pdata);
+       imx1_add_imx_uart0(&uart_pdata);
 
        printk(KERN_INFO"Scb9328: Adding devices\n");
        platform_add_devices(devices, ARRAY_SIZE(devices));

diff --git a/arch/arm/mach-mx1/generic.c b/arch/arm/mach-imx/mm-imx1.c
similarity index 68%
rename from arch/arm/mach-mx1/generic.c
rename to arch/arm/mach-imx/mm-imx1.c
index 7f9fc1034c0884b186e2ccb7ec6bc5348598d50a..9be92b96dc8961d02efe8a019ac95a46d1647295 100644 (file)
--- a/arch/arm/mach-mx1/generic.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -3,7 +3,7 @@
  *  Created: april 20th, 2004
  *  Copyright: Synertronixx GmbH
  *
- *  Common code for i.MX machines
+ *  Common code for i.MX1 machines
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,11 +14,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -31,23 +26,25 @@
 
 static struct map_desc imx_io_desc[] __initdata = {
        {
-               .virtual        = IMX_IO_BASE,
-               .pfn            = __phys_to_pfn(IMX_IO_PHYS),
-               .length         = IMX_IO_SIZE,
-               .type           = MT_DEVICE
+               .virtual = MX1_IO_BASE_ADDR_VIRT,
+               .pfn = __phys_to_pfn(MX1_IO_BASE_ADDR),
+               .length = MX1_IO_SIZE,
+               .type = MT_DEVICE
        }
 };
 
 void __init mx1_map_io(void)
 {
        mxc_set_cpu_type(MXC_CPU_MX1);
-       mxc_arch_reset_init(IO_ADDRESS(WDT_BASE_ADDR));
+       mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
 
        iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
 }
 
+int imx1_register_gpios(void);
+
 void __init mx1_init_irq(void)
 {
-       mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
+       mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR));
+       imx1_register_gpios();
 }
-

diff --git a/arch/arm/mach-mx2/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
similarity index 95%
rename from arch/arm/mach-mx2/mm-imx21.c
rename to arch/arm/mach-imx/mm-imx21.c
index 64134314d012a43b43f80d2690abaad92f5cee0b..12faeeaa0a9706ce4ea2eb0c774abff437dc9901 100644 (file)
--- a/arch/arm/mach-mx2/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -1,5 +1,5 @@
 /*
- * arch/arm/mach-mx2/mm-imx21.c
+ * arch/arm/mach-imx/mm-imx21.c
  *
  * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
  *
@@ -77,7 +77,10 @@ void __init mx21_map_io(void)
        iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc));
 }
 
+int imx21_register_gpios(void);
+
 void __init mx21_init_irq(void)
 {
        mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR));
+       imx21_register_gpios();
 }

diff --git a/arch/arm/mach-mx2/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
similarity index 95%
rename from arch/arm/mach-mx2/mm-imx27.c
rename to arch/arm/mach-imx/mm-imx27.c
index 3366ed44cfd5a60b283d2266bd083ffe664047e0..a24622957ff2dc3eeed0f1e949d4a12fc35a9e30 100644 (file)
--- a/arch/arm/mach-mx2/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -1,5 +1,5 @@
 /*
- * arch/arm/mach-mx2/mm-imx27.c
+ * arch/arm/mach-imx/mm-imx27.c
  *
  * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
  *
@@ -77,7 +77,10 @@ void __init mx27_map_io(void)
        iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc));
 }
 
+int imx27_register_gpios(void);
+
 void __init mx27_init_irq(void)
 {
        mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR));
+       imx27_register_gpios();
 }

diff --git a/arch/arm/mach-mx1/ksym_mx1.c b/arch/arm/mach-imx/mx1-camera-fiq-ksym.c
similarity index 100%
rename from arch/arm/mach-mx1/ksym_mx1.c
rename to arch/arm/mach-imx/mx1-camera-fiq-ksym.c

diff --git a/arch/arm/mach-mx1/mx1_camera_fiq.S b/arch/arm/mach-imx/mx1-camera-fiq.S
similarity index 100%
rename from arch/arm/mach-mx1/mx1_camera_fiq.S
rename to arch/arm/mach-imx/mx1-camera-fiq.S

diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c
similarity index 100%
rename from arch/arm/mach-mx2/pcm970-baseboard.c
rename to arch/arm/mach-imx/pcm970-baseboard.c

diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c
new file mode 100644 (file)
index 0000000..afc17ce
--- /dev/null
+++ b/arch/arm/mach-imx/pm-imx27.c
@@ -0,0 +1,46 @@
+/*
+ * i.MX27 Power Management Routines
+ *
+ * Based on Freescale's BSP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License.
+ */
+
+#include <linux/kernel.h>
+#include <linux/suspend.h>
+#include <linux/io.h>
+#include <mach/system.h>
+#include <mach/mx27.h>
+
+static int mx27_suspend_enter(suspend_state_t state)
+{
+       u32 cscr;
+       switch (state) {
+       case PM_SUSPEND_MEM:
+               /* Clear MPEN and SPEN to disable MPLL/SPLL */
+               cscr = __raw_readl(MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
+               cscr &= 0xFFFFFFFC;
+               __raw_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
+               /* Executes WFI */
+               arch_idle();
+               break;
+
+       default:
+               return -EINVAL;
+       }
+       return 0;
+}
+
+static struct platform_suspend_ops mx27_suspend_ops = {
+       .enter = mx27_suspend_enter,
+       .valid = suspend_valid_only_mem,
+};
+
+static int __init mx27_pm_init(void)
+{
+       suspend_set_ops(&mx27_suspend_ops);
+       return 0;
+}
+
+device_initcall(mx27_pm_init);

diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h
new file mode 100644 (file)
index 0000000..5f96e15
--- /dev/null
+++ b/arch/arm/mach-integrator/common.h
@@ -0,0 +1 @@
+void integrator_reserve(void);

diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index b02cfc06e0aeeff452a2c3813523fccd53f1edf2..8f4fb6d638f7ea66717a5afb5d962ef0d88723a3 100644 (file)
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -14,6 +14,7 @@
 #include <linux/spinlock.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/memblock.h>
 #include <linux/sched.h>
 #include <linux/smp.h>
 #include <linux/termios.h>
@@ -30,6 +31,7 @@
 #include <asm/system.h>
 #include <asm/leds.h>
 #include <asm/mach/time.h>
+#include <asm/pgtable.h>
 
 static struct amba_pl010_data integrator_uart_data;
 
@@ -119,8 +121,13 @@ static struct clk uartclk = {
        .rate   = 14745600,
 };
 
+static struct clk dummy_apb_pclk;
+
 static struct clk_lookup lookups[] = {
-       {       /* UART0 */
+       {       /* Bus clock */
+               .con_id         = "apb_pclk",
+               .clk            = &dummy_apb_pclk,
+       }, {    /* UART0 */
                .dev_id         = "mb:16",
                .clk            = &uartclk,
        }, {    /* UART1 */
@@ -215,3 +222,13 @@ void cm_control(u32 mask, u32 set)
 }
 
 EXPORT_SYMBOL(cm_control);
+
+/*
+ * We need to stop things allocating the low memory; ideally we need a
+ * better implementation of GFP_DMA which does not assume that DMA-able
+ * memory starts at zero.
+ */
+void __init integrator_reserve(void)
+{
+       memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
+}

diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 227cf4d05088ec85bf870e1423b7044d0758d133..6ab5a03ab9d8b0a7f45311595b0ee1fa16474ef3 100644 (file)
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -48,6 +48,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 
+#include "common.h"
+
 /* 
  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  * is the (PA >> 12).
@@ -502,6 +504,7 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator")
        .io_pg_offst    = ((0xf1600000) >> 18) & 0xfffc,
        .boot_params    = 0x00000100,
        .map_io         = ap_map_io,
+       .reserve        = integrator_reserve,
        .init_irq       = ap_init_irq,
        .timer          = &ap_timer,
        .init_machine   = ap_init,

diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index cde57b2b83b57a36288382ef5b57a39ae895d802..05db40e3c4f75a7fcf661718269cdcf330d7f9cc 100644 (file)
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -43,6 +43,8 @@
 
 #include <plat/timer-sp.h>
 
+#include "common.h"
+
 #define INTCP_PA_FLASH_BASE            0x24000000
 #define INTCP_FLASH_SIZE               SZ_32M
 
@@ -601,6 +603,7 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
        .io_pg_offst    = ((0xf1600000) >> 18) & 0xfffc,
        .boot_params    = 0x00000100,
        .map_io         = intcp_map_io,
+       .reserve        = integrator_reserve,
        .init_irq       = intcp_init_irq,
        .timer          = &cp_timer,
        .init_machine   = intcp_init,

diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index 9cef0590d5aa3d4af92e62d41601b7057f94e0b3..6467d99fa2ee4a0c674d9071dad669cb5caa7b32 100644 (file)
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -505,10 +505,10 @@ void __init pci_v3_preinit(void)
        /*
         * Hook in our fault handler for PCI errors
         */
-       hook_fault_code(4, v3_pci_fault, SIGBUS, "external abort on linefetch");
-       hook_fault_code(6, v3_pci_fault, SIGBUS, "external abort on linefetch");
-       hook_fault_code(8, v3_pci_fault, SIGBUS, "external abort on non-linefetch");
-       hook_fault_code(10, v3_pci_fault, SIGBUS, "external abort on non-linefetch");
+       hook_fault_code(4, v3_pci_fault, SIGBUS, 0, "external abort on linefetch");
+       hook_fault_code(6, v3_pci_fault, SIGBUS, 0, "external abort on linefetch");
+       hook_fault_code(8, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
+       hook_fault_code(10, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
 
        spin_lock_irqsave(&v3_lock, flags);
 

diff --git a/arch/arm/mach-iop13xx/include/mach/memory.h b/arch/arm/mach-iop13xx/include/mach/memory.h
index 25b1da9a5035469fcf4355e80082f3dd7af586c8..7415e4338651e7c84e2e3a587092a1c1859cda1d 100644 (file)
--- a/arch/arm/mach-iop13xx/include/mach/memory.h
+++ b/arch/arm/mach-iop13xx/include/mach/memory.h
@@ -69,6 +69,4 @@ static inline unsigned long __lbus_to_virt(dma_addr_t x)
 #endif /* CONFIG_ARCH_IOP13XX */
 #endif /* !ASSEMBLY */
 
-#define PFN_TO_NID(addr)       (0)
-
 #endif

diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index 6d5a90813d31b6b96532b3b1a5cdb555e972ec41..773ea0c95b9f6fc91d8c9c57f3a3bd0f714b306d 100644 (file)
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -987,7 +987,7 @@ void __init iop13xx_pci_init(void)
                iop13xx_atux_setup();
        }
 
-       hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS,
+       hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS, 0,
                        "imprecise external abort");
 }
 

diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c
index 90771cad06f86f7fe3238021ce8ae39ce90cadc2..f797c5f538b094e2d600c78b85d70d70ff25d295 100644 (file)
--- a/arch/arm/mach-ixp2000/pci.c
+++ b/arch/arm/mach-ixp2000/pci.c
@@ -209,7 +209,7 @@ ixp2000_pci_preinit(void)
                        "the needed workaround has not been configured in");
 #endif
 
-       hook_fault_code(16+6, ixp2000_pci_abort_handler, SIGBUS,
+       hook_fault_code(16+6, ixp2000_pci_abort_handler, SIGBUS, 0,
                                "PCI config cycle to non-existent device");
 }
 

diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c
index 4b0e598a91c91f4573d927a8016d91aab0154f7d..563819a83292db81f72b147986b98b573868149f 100644 (file)
--- a/arch/arm/mach-ixp23xx/pci.c
+++ b/arch/arm/mach-ixp23xx/pci.c
@@ -229,7 +229,7 @@ void __init ixp23xx_pci_preinit(void)
 {
        ixp23xx_pci_common_init();
 
-       hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS,
+       hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS, 0,
                        "PCI config cycle to non-existent device");
 
        *IXP23XX_PCI_ADDR_EXT = 0x0000e000;

diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index e3181534c7f9dba7fe1cc8f6e4185aae21c8c87b..61cd4d64b98596c7507dcaf67d069dbe22508e50 100644 (file)
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -348,7 +348,7 @@ int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
  * This is really ugly and we need a better way of specifying
  * DMA-capable regions of memory.
  */
-void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size,
+void __init ixp4xx_adjust_zones(unsigned long *zone_size,
        unsigned long *zhole_size)
 {
        unsigned int sz = SZ_64M >> PAGE_SHIFT;
@@ -356,7 +356,7 @@ void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size,
        /*
         * Only adjust if > 64M on current system
         */
-       if (node || (zone_size[0] <= sz))
+       if (zone_size[0] <= sz)
                return;
 
        zone_size[1] = zone_size[0] - sz;
@@ -382,7 +382,8 @@ void __init ixp4xx_pci_preinit(void)
 
 
        /* hook in our fault handler for PCI errors */
-       hook_fault_code(16+6, abort_handler, SIGBUS, "imprecise external abort");
+       hook_fault_code(16+6, abort_handler, SIGBUS, 0,
+                       "imprecise external abort");
 
        pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n");
 

diff --git a/arch/arm/mach-ixp4xx/include/mach/memory.h b/arch/arm/mach-ixp4xx/include/mach/memory.h
index 98f5e5e2098001398d45930d2fb5d33b3452f0ea..0136eaa29224a538cfdd65179dd59432fa7b1488 100644 (file)
--- a/arch/arm/mach-ixp4xx/include/mach/memory.h
+++ b/arch/arm/mach-ixp4xx/include/mach/memory.h
@@ -16,10 +16,10 @@
 
 #if !defined(__ASSEMBLY__) && defined(CONFIG_PCI)
 
-void ixp4xx_adjust_zones(int node, unsigned long *size, unsigned long *holes);
+void ixp4xx_adjust_zones(unsigned long *size, unsigned long *holes);
 
-#define arch_adjust_zones(node, size, holes) \
-       ixp4xx_adjust_zones(node, size, holes)
+#define arch_adjust_zones(size, holes) \
+       ixp4xx_adjust_zones(size, holes)
 
 #define ISA_DMA_THRESHOLD (SZ_64M - 1)
 #define MAX_DMA_ADDRESS                (PAGE_OFFSET + SZ_64M)

diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 29b2163b1fe3b3cff4ce40e9c23b112c360e1a56..cc25501b57fa8edf270752e0a719f2564965f44a 100644 (file)
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -75,6 +75,13 @@ config MACH_OPENRD_CLIENT
          Say 'Y' here if you want your kernel to support the
          Marvell OpenRD Client Board.
 
+config MACH_OPENRD_ULTIMATE
+       bool "Marvell OpenRD Ultimate Board"
+       select MACH_OPENRD
+       help
+         Say 'Y' here if you want your kernel to support the
+         Marvell OpenRD Ultimate Board.
+
 config MACH_NETSPACE_V2
        bool "LaCie Network Space v2 NAS Board"
        help
@@ -87,6 +94,12 @@ config MACH_INETSPACE_V2
          Say 'Y' here if you want your kernel to support the
          LaCie Internet Space v2 NAS.
 
+config MACH_NETSPACE_MAX_V2
+       bool "LaCie Network Space Max v2 NAS Board"
+       help
+         Say 'Y' here if you want your kernel to support the
+         LaCie Network Space Max v2 NAS.
+
 config MACH_NET2BIG_V2
        bool "LaCie 2Big Network v2 NAS Board"
        help
@@ -99,6 +112,12 @@ config MACH_NET5BIG_V2
          Say 'Y' here if you want your kernel to support the
          LaCie 5Big Network v2 NAS.
 
+config MACH_T5325
+       bool "HP t5325 Thin Client"
+       help
+         Say 'Y' here if you want your kernel to support the
+         HP t5325 Thin Client.
+
 endmenu
 
 endif

diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index c0cd5d362002c325cee09cc8a8c8a59cfaaebf26..295d7baa6ae11150956e004330259859ef3c4ec6 100644 (file)
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -12,7 +12,9 @@ obj-$(CONFIG_MACH_TS41X)              += ts41x-setup.o tsx1x-common.o
 obj-$(CONFIG_MACH_OPENRD)              += openrd-setup.o
 obj-$(CONFIG_MACH_NETSPACE_V2)         += netspace_v2-setup.o
 obj-$(CONFIG_MACH_INETSPACE_V2)                += netspace_v2-setup.o
+obj-$(CONFIG_MACH_NETSPACE_MAX_V2)     += netspace_v2-setup.o
 obj-$(CONFIG_MACH_NET2BIG_V2)          += netxbig_v2-setup.o
 obj-$(CONFIG_MACH_NET5BIG_V2)          += netxbig_v2-setup.o
+obj-$(CONFIG_MACH_T5325)               += t5325-setup.o
 
 obj-$(CONFIG_CPU_IDLE)                 += cpuidle.o

diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index 2e69168fc699881d9928964c266eb7c866c00ee2..8d03bcef5182c8a9696159c8c220da833ee2cbd6 100644 (file)
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -31,6 +31,8 @@
 #define ATTR_DEV_CS0           0x3e
 #define ATTR_PCIE_IO           0xe0
 #define ATTR_PCIE_MEM          0xe8
+#define ATTR_PCIE1_IO          0xd0
+#define ATTR_PCIE1_MEM         0xd8
 #define ATTR_SRAM              0x01
 
 /*
@@ -106,17 +108,21 @@ void __init kirkwood_setup_cpu_mbus(void)
                      TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
        setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
                      TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);
+       setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
+                     TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE);
+       setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
+                     TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE);
 
        /*
         * Setup window for NAND controller.
         */
-       setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
+       setup_cpu_win(4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
                      TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
 
        /*
         * Setup window for SRAM.
         */
-       setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
+       setup_cpu_win(5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
                      TARGET_SRAM, ATTR_SRAM, -1);
 
        /*

diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 6072eaa5e66acf81f080d72374fbfd1dfbe7382c..9dd67c7b44590dafa63dcb11204998fe8c3d3ad3 100644 (file)
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -43,6 +43,11 @@ static struct map_desc kirkwood_io_desc[] __initdata = {
                .pfn            = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
                .length         = KIRKWOOD_PCIE_IO_SIZE,
                .type           = MT_DEVICE,
+       }, {
+               .virtual        = KIRKWOOD_PCIE1_IO_VIRT_BASE,
+               .pfn            = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
+               .length         = KIRKWOOD_PCIE1_IO_SIZE,
+               .type           = MT_DEVICE,
        }, {
                .virtual        = KIRKWOOD_REGS_VIRT_BASE,
                .pfn            = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
@@ -402,7 +407,7 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
        u32 dev, rev;
 
        kirkwood_pcie_id(&dev, &rev);
-       if (rev == 0)  /* catch all Kirkwood Z0's */
+       if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */
                mvsdio_data->clock = 100000000;
        else
                mvsdio_data->clock = 200000000;
@@ -847,8 +852,10 @@ int __init kirkwood_find_tclk(void)
        u32 dev, rev;
 
        kirkwood_pcie_id(&dev, &rev);
-       if (dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 ||
-                                       rev == MV88F6281_REV_A1))
+
+       if ((dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 ||
+                                       rev == MV88F6281_REV_A1)) ||
+           (dev == MV88F6282_DEV_ID))
                return 200000000;
 
        return 166666667;
@@ -891,13 +898,22 @@ static char * __init kirkwood_id(void)
                        return "MV88F6192-Z0";
                else if (rev == MV88F6192_REV_A0)
                        return "MV88F6192-A0";
+               else if (rev == MV88F6192_REV_A1)
+                       return "MV88F6192-A1";
                else
                        return "MV88F6192-Rev-Unsupported";
        } else if (dev == MV88F6180_DEV_ID) {
                if (rev == MV88F6180_REV_A0)
                        return "MV88F6180-Rev-A0";
+               else if (rev == MV88F6180_REV_A1)
+                       return "MV88F6180-Rev-A1";
                else
                        return "MV88F6180-Rev-Unsupported";
+       } else if (dev == MV88F6282_DEV_ID) {
+               if (rev == MV88F6282_REV_A0)
+                       return "MV88F6282-Rev-A0";
+               else
+                       return "MV88F6282-Rev-Unsupported";
        } else {
                return "Device-Unknown";
        }
@@ -949,12 +965,14 @@ void __init kirkwood_init(void)
 static int __init kirkwood_clock_gate(void)
 {
        unsigned int curr = readl(CLOCK_GATING_CTRL);
+       u32 dev, rev;
 
+       kirkwood_pcie_id(&dev, &rev);
        printk(KERN_DEBUG "Gating clock of unused units\n");
        printk(KERN_DEBUG "before: 0x%08x\n", curr);
 
        /* Make sure those units are accessible */
-       writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0, CLOCK_GATING_CTRL);
+       writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);
 
        /* For SATA: first shutdown the phy */
        if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
@@ -979,6 +997,18 @@ static int __init kirkwood_clock_gate(void)
                writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
        }
 
+       /* For PCIe 1: first shutdown the phy */
+       if (dev == MV88F6282_DEV_ID) {
+               if (!(kirkwood_clk_ctrl & CGC_PEX1)) {
+                       writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
+                       while (1)
+                               if (readl(PCIE1_STATUS) & 0x1)
+                                       break;
+                       writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
+               }
+       } else  /* keep this bit set for devices that don't have PCIe1 */
+               kirkwood_clk_ctrl |= CGC_PEX1;
+
        /* Now gate clock the required units */
        writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
        printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));

diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 05e8a8a5692e8150535973105b1f50bed60bcfea..5b2c1c18d641670eed6600753cc1691cb18d7efd 100644 (file)
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -18,6 +18,9 @@ struct mvsdio_platform_data;
 struct mtd_partition;
 struct mtd_info;
 
+#define KW_PCIE0       (1 << 0)
+#define KW_PCIE1       (1 << 1)
+
 /*
  * Basic Kirkwood init functions used early by machine-setup.
  */
@@ -34,7 +37,7 @@ void kirkwood_ehci_init(void);
 void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);
 void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data);
 void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq);
-void kirkwood_pcie_init(void);
+void kirkwood_pcie_init(unsigned int portmask);
 void kirkwood_sata_init(struct mv_sata_platform_data *sata_data);
 void kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data);
 void kirkwood_spi_init(void);

diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index 39bdf4bcace959322cc966d613cc976007dbe020..16f6691e7c685cc6af9266b56bcd0af1265a60ef 100644 (file)
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -51,6 +51,14 @@ static struct mvsdio_platform_data db88f6281_mvsdio_data = {
 };
 
 static unsigned int db88f6281_mpp_config[] __initdata = {
+       MPP0_NF_IO2,
+       MPP1_NF_IO3,
+       MPP2_NF_IO4,
+       MPP3_NF_IO5,
+       MPP4_NF_IO6,
+       MPP5_NF_IO7,
+       MPP18_NF_IO0,
+       MPP19_NF_IO1,
        MPP37_GPIO,
        MPP38_GPIO,
        0
@@ -74,9 +82,15 @@ static void __init db88f6281_init(void)
 
 static int __init db88f6281_pci_init(void)
 {
-       if (machine_is_db88f6281_bp())
-               kirkwood_pcie_init();
+       if (machine_is_db88f6281_bp()) {
+               u32 dev, rev;
 
+               kirkwood_pcie_id(&dev, &rev);
+               if (dev == MV88F6282_DEV_ID)
+                       kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0);
+               else
+                       kirkwood_pcie_init(KW_PCIE0);
+       }
        return 0;
 }
 subsys_initcall(db88f6281_pci_init);

diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index 418f5017c50e1d916468ebc99e5b958a706d98f6..aff0e1327e38f8f360fa25dc5291722a2c7df9fe 100644 (file)
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -59,8 +59,9 @@
 #define CGC_SATA1              (1 << 15)
 #define CGC_XOR1               (1 << 16)
 #define CGC_CRYPTO             (1 << 17)
+#define CGC_PEX1               (1 << 18)
 #define CGC_GE1                        (1 << 19)
 #define CGC_TDM                        (1 << 20)
-#define CGC_RESERVED           ((1 << 18) | (0x6 << 21))
+#define CGC_RESERVED           (0x6 << 21)
 
 #endif

diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h
index f00a0a45a67e5356bf08d722a4c5bda29b4a57ce..9da2eb59180b2128af2d14bed71091d2bd574b1d 100644 (file)
--- a/arch/arm/mach-kirkwood/include/mach/irqs.h
+++ b/arch/arm/mach-kirkwood/include/mach/irqs.h
@@ -23,6 +23,7 @@
 #define IRQ_KIRKWOOD_XOR_10    7
 #define IRQ_KIRKWOOD_XOR_11    8
 #define IRQ_KIRKWOOD_PCIE      9
+#define IRQ_KIRKWOOD_PCIE1     10
 #define IRQ_KIRKWOOD_GE00_SUM  11
 #define IRQ_KIRKWOOD_GE01_SUM  15
 #define IRQ_KIRKWOOD_USB       19

diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index a15cf0ee22bd802c7aaefb4a04b067540eabcd1b..d141af4c274422a542634b33581f9488385def59 100644 (file)
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -16,36 +16,48 @@
  * Marvell Kirkwood address maps.
  *
  * phys
- * e0000000    PCIe Memory space
+ * e0000000    PCIe #0 Memory space
+ * e8000000    PCIe #1 Memory space
  * f1000000    on-chip peripheral registers
- * f2000000    PCIe I/O space
- * f3000000    NAND controller address window
- * f4000000    Security Accelerator SRAM
+ * f2000000    PCIe #0 I/O space
+ * f3000000    PCIe #1 I/O space
+ * f4000000    NAND controller address window
+ * f5000000    Security Accelerator SRAM
  *
  * virt                phys            size
- * fee00000    f1000000        1M      on-chip peripheral registers
- * fef00000    f2000000        1M      PCIe I/O space
+ * fed00000    f1000000        1M      on-chip peripheral registers
+ * fee00000    f2000000        1M      PCIe #0 I/O space
+ * fef00000    f3000000        1M      PCIe #1 I/O space
  */
 
-#define KIRKWOOD_SRAM_PHYS_BASE                0xf4000000
+#define KIRKWOOD_SRAM_PHYS_BASE                0xf5000000
 #define KIRKWOOD_SRAM_SIZE             SZ_2K
 
-#define KIRKWOOD_NAND_MEM_PHYS_BASE    0xf3000000
+#define KIRKWOOD_NAND_MEM_PHYS_BASE    0xf4000000
 #define KIRKWOOD_NAND_MEM_SIZE         SZ_1K
 
+#define KIRKWOOD_PCIE1_IO_PHYS_BASE    0xf3000000
+#define KIRKWOOD_PCIE1_IO_VIRT_BASE    0xfef00000
+#define KIRKWOOD_PCIE1_IO_BUS_BASE     0x00000000
+#define KIRKWOOD_PCIE1_IO_SIZE         SZ_1M
+
 #define KIRKWOOD_PCIE_IO_PHYS_BASE     0xf2000000
-#define KIRKWOOD_PCIE_IO_VIRT_BASE     0xfef00000
+#define KIRKWOOD_PCIE_IO_VIRT_BASE     0xfee00000
 #define KIRKWOOD_PCIE_IO_BUS_BASE      0x00000000
 #define KIRKWOOD_PCIE_IO_SIZE          SZ_1M
 
 #define KIRKWOOD_REGS_PHYS_BASE                0xf1000000
-#define KIRKWOOD_REGS_VIRT_BASE                0xfee00000
+#define KIRKWOOD_REGS_VIRT_BASE                0xfed00000
 #define KIRKWOOD_REGS_SIZE             SZ_1M
 
 #define KIRKWOOD_PCIE_MEM_PHYS_BASE    0xe0000000
 #define KIRKWOOD_PCIE_MEM_BUS_BASE     0xe0000000
 #define KIRKWOOD_PCIE_MEM_SIZE         SZ_128M
 
+#define KIRKWOOD_PCIE1_MEM_PHYS_BASE   0xe8000000
+#define KIRKWOOD_PCIE1_MEM_BUS_BASE    0xe8000000
+#define KIRKWOOD_PCIE1_MEM_SIZE                SZ_128M
+
 /*
  * Register Map
  */
@@ -72,6 +84,9 @@
 #define PCIE_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
 #define PCIE_LINK_CTRL         (PCIE_VIRT_BASE | 0x70)
 #define PCIE_STATUS            (PCIE_VIRT_BASE | 0x1a04)
+#define PCIE1_VIRT_BASE                (KIRKWOOD_REGS_VIRT_BASE | 0x44000)
+#define PCIE1_LINK_CTRL                (PCIE1_VIRT_BASE | 0x70)
+#define PCIE1_STATUS           (PCIE1_VIRT_BASE | 0x1a04)
 
 #define USB_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
 
@@ -107,8 +122,12 @@
 #define MV88F6192_DEV_ID       0x6192
 #define MV88F6192_REV_Z0       0
 #define MV88F6192_REV_A0       2
+#define MV88F6192_REV_A1       3
 
 #define MV88F6180_DEV_ID       0x6180
 #define MV88F6180_REV_A0       2
+#define MV88F6180_REV_A1       3
 
+#define MV88F6282_DEV_ID       0x6282
+#define MV88F6282_REV_A0       0
 #endif

diff --git a/arch/arm/mach-kirkwood/include/mach/leds-ns2.h b/arch/arm/mach-kirkwood/include/mach/leds-ns2.h
new file mode 100644 (file)
index 0000000..e21272e
--- /dev/null
+++ b/arch/arm/mach-kirkwood/include/mach/leds-ns2.h
@@ -0,0 +1,26 @@
+/*
+ * arch/arm/mach-kirkwood/include/mach/leds-ns2.h
+ *
+ * Platform data structure for Network Space v2 LED driver
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_LEDS_NS2_H
+#define __MACH_LEDS_NS2_H
+
+struct ns2_led {
+       const char      *name;
+       const char      *default_trigger;
+       unsigned        cmd;
+       unsigned        slow;
+};
+
+struct ns2_led_platform_data {
+       int             num_leds;
+       struct ns2_led  *leds;
+};
+
+#endif /* __MACH_LEDS_NS2_H */

diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index a5900f64e38c112e7fb195ea2cdca7281cc64af7..065187d177c6299f12543c3198c23c7cbd8f2476 100644 (file)
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -23,7 +23,8 @@ static unsigned int __init kirkwood_variant(void)
 
        kirkwood_pcie_id(&dev, &rev);
 
-       if (dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0)
+       if ((dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) ||
+           (dev == MV88F6282_DEV_ID))
                return MPP_F6281_MASK;
        if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0)
                return MPP_F6192_MASK;

diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h
index bc74278ed311c2bef402d6e16d808111669ed96e..9b0a94d85c3ee6b4e2238c0db2e65117f63f44eb 100644 (file)
--- a/arch/arm/mach-kirkwood/mpp.h
+++ b/arch/arm/mach-kirkwood/mpp.h
@@ -11,7 +11,7 @@
 #ifndef __KIRKWOOD_MPP_H
 #define __KIRKWOOD_MPP_H
 
-#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \
+#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281, _F6282) ( \
        /* MPP number */                ((_num) & 0xff) | \
        /* MPP select value */          (((_sel) & 0xf) << 8) | \
        /* may be input signal */       ((!!(_in)) << 12) | \
@@ -19,282 +19,332 @@
        /* available on F6180 */        ((!!(_F6180)) << 14) | \
        /* available on F6190 */        ((!!(_F6190)) << 15) | \
        /* available on F6192 */        ((!!(_F6192)) << 16) | \
-       /* available on F6281 */        ((!!(_F6281)) << 17))
+       /* available on F6281 */        ((!!(_F6281)) << 17) | \
+       /* available on F6282 */        ((!!(_F6282)) << 18))
 
 #define MPP_NUM(x)     ((x) & 0xff)
 #define MPP_SEL(x)     (((x) >> 8) & 0xf)
 
-                               /*   num sel  i  o  6180 6190 6192 6281 */
-
-#define MPP_INPUT_MASK         MPP(  0, 0x0, 1, 0, 0,   0,   0,   0    )
-#define MPP_OUTPUT_MASK                MPP(  0, 0x0, 0, 1, 0,   0,   0,   0    )
-
-#define MPP_F6180_MASK         MPP(  0, 0x0, 0, 0, 1,   0,   0,   0    )
-#define MPP_F6190_MASK         MPP(  0, 0x0, 0, 0, 0,   1,   0,   0    )
-#define MPP_F6192_MASK         MPP(  0, 0x0, 0, 0, 0,   0,   1,   0    )
-#define MPP_F6281_MASK         MPP(  0, 0x0, 0, 0, 0,   0,   0,   1    )
-
-#define MPP0_GPIO              MPP(  0, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP0_NF_IO2            MPP(  0, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP0_SPI_SCn           MPP(  0, 0x2, 0, 1, 1,   1,   1,   1    )
-
-#define MPP1_GPO               MPP(  1, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP1_NF_IO3            MPP(  1, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP1_SPI_MOSI          MPP(  1, 0x2, 0, 1, 1,   1,   1,   1    )
-
-#define MPP2_GPO               MPP(  2, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP2_NF_IO4            MPP(  2, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP2_SPI_SCK           MPP(  2, 0x2, 0, 1, 1,   1,   1,   1    )
-
-#define MPP3_GPO               MPP(  3, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP3_NF_IO5            MPP(  3, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP3_SPI_MISO          MPP(  3, 0x2, 1, 0, 1,   1,   1,   1    )
-
-#define MPP4_GPIO              MPP(  4, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP4_NF_IO6            MPP(  4, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP4_UART0_RXD         MPP(  4, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP4_SATA1_ACTn                MPP(  4, 0x5, 0, 1, 0,   0,   1,   1    )
-#define MPP4_PTP_CLK           MPP(  4, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP5_GPO               MPP(  5, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP5_NF_IO7            MPP(  5, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP5_UART0_TXD         MPP(  5, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP5_PTP_TRIG_GEN      MPP(  5, 0x4, 0, 1, 1,   1,   1,   1    )
-#define MPP5_SATA0_ACTn                MPP(  5, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP6_SYSRST_OUTn       MPP(  6, 0x1, 0, 1, 1,   1,   1,   1    )
-#define MPP6_SPI_MOSI          MPP(  6, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP6_PTP_TRIG_GEN      MPP(  6, 0x3, 0, 1, 1,   1,   1,   1    )
-
-#define MPP7_GPO               MPP(  7, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP7_PEX_RST_OUTn      MPP(  7, 0x1, 0, 1, 1,   1,   1,   1    )
-#define MPP7_SPI_SCn           MPP(  7, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP7_PTP_TRIG_GEN      MPP(  7, 0x3, 0, 1, 1,   1,   1,   1    )
-
-#define MPP8_GPIO              MPP(  8, 0x0, 1, 1, 1,    1,  1,   1    )
-#define MPP8_TW_SDA            MPP(  8, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP8_UART0_RTS         MPP(  8, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP8_UART1_RTS         MPP(  8, 0x3, 0, 1, 1,   1,   1,   1    )
-#define MPP8_MII0_RXERR                MPP(  8, 0x4, 1, 0, 0,   1,   1,   1    )
-#define MPP8_SATA1_PRESENTn    MPP(  8, 0x5, 0, 1, 0,   0,   1,   1    )
-#define MPP8_PTP_CLK           MPP(  8, 0xc, 1, 0, 1,   1,   1,   1    )
-#define MPP8_MII0_COL          MPP(  8, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP9_GPIO              MPP(  9, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP9_TW_SCK            MPP(  9, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP9_UART0_CTS         MPP(  9, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP9_UART1_CTS         MPP(  9, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP9_SATA0_PRESENTn    MPP(  9, 0x5, 0, 1, 0,   1,   1,   1    )
-#define MPP9_PTP_EVENT_REQ     MPP(  9, 0xc, 1, 0, 1,   1,   1,   1    )
-#define MPP9_MII0_CRS          MPP(  9, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP10_GPO              MPP( 10, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP10_SPI_SCK          MPP( 10, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP10_UART0_TXD                MPP( 10, 0X3, 0, 1, 1,   1,   1,   1    )
-#define MPP10_SATA1_ACTn       MPP( 10, 0x5, 0, 1, 0,   0,   1,   1    )
-#define MPP10_PTP_TRIG_GEN     MPP( 10, 0xc, 0, 1, 1,   1,   1,   1    )
-
-#define MPP11_GPIO             MPP( 11, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP11_SPI_MISO         MPP( 11, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP11_UART0_RXD                MPP( 11, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP11_PTP_EVENT_REQ    MPP( 11, 0x4, 1, 0, 1,   1,   1,   1    )
-#define MPP11_PTP_TRIG_GEN     MPP( 11, 0xc, 0, 1, 1,   1,   1,   1    )
-#define MPP11_PTP_CLK          MPP( 11, 0xd, 1, 0, 1,   1,   1,   1    )
-#define MPP11_SATA0_ACTn       MPP( 11, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP12_GPO              MPP( 12, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP12_SD_CLK           MPP( 12, 0x1, 0, 1, 1,   1,   1,   1    )
-
-#define MPP13_GPIO             MPP( 13, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP13_SD_CMD           MPP( 13, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP13_UART1_TXD                MPP( 13, 0x3, 0, 1, 1,   1,   1,   1    )
-
-#define MPP14_GPIO             MPP( 14, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP14_SD_D0            MPP( 14, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP14_UART1_RXD                MPP( 14, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP14_SATA1_PRESENTn   MPP( 14, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP14_MII0_COL         MPP( 14, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP15_GPIO             MPP( 15, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP15_SD_D1            MPP( 15, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP15_UART0_RTS                MPP( 15, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP15_UART1_TXD                MPP( 15, 0x3, 0, 1, 1,   1,   1,   1    )
-#define MPP15_SATA0_ACTn       MPP( 15, 0x4, 0, 1, 0,   1,   1,   1    )
-
-#define MPP16_GPIO             MPP( 16, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP16_SD_D2            MPP( 16, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP16_UART0_CTS                MPP( 16, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP16_UART1_RXD                MPP( 16, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP16_SATA1_ACTn       MPP( 16, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP16_MII0_CRS         MPP( 16, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP17_GPIO             MPP( 17, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP17_SD_D3            MPP( 17, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP17_SATA0_PRESENTn   MPP( 17, 0x4, 0, 1, 0,   1,   1,   1    )
-
-#define MPP18_GPO              MPP( 18, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP18_NF_IO0           MPP( 18, 0x1, 1, 1, 1,   1,   1,   1    )
-
-#define MPP19_GPO              MPP( 19, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP19_NF_IO1           MPP( 19, 0x1, 1, 1, 1,   1,   1,   1    )
-
-#define MPP20_GPIO             MPP( 20, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP20_TSMP0            MPP( 20, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP20_TDM_CH0_TX_QL    MPP( 20, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP20_GE1_0            MPP( 20, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP20_AUDIO_SPDIFI     MPP( 20, 0x4, 1, 0, 0,   0,   1,   1    )
-#define MPP20_SATA1_ACTn       MPP( 20, 0x5, 0, 1, 0,   0,   1,   1    )
-
-#define MPP21_GPIO             MPP( 21, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP21_TSMP1            MPP( 21, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP21_TDM_CH0_RX_QL    MPP( 21, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP21_GE1_1            MPP( 21, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP21_AUDIO_SPDIFO     MPP( 21, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP21_SATA0_ACTn       MPP( 21, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP22_GPIO             MPP( 22, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP22_TSMP2            MPP( 22, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP22_TDM_CH2_TX_QL    MPP( 22, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP22_GE1_2            MPP( 22, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP22_AUDIO_SPDIFRMKCLK        MPP( 22, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP22_SATA1_PRESENTn   MPP( 22, 0x5, 0, 1, 0,   0,   1,   1    )
-
-#define MPP23_GPIO             MPP( 23, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP23_TSMP3            MPP( 23, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP23_TDM_CH2_RX_QL    MPP( 23, 0x2, 1, 0, 0,   0,   1,   1    )
-#define MPP23_GE1_3            MPP( 23, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP23_AUDIO_I2SBCLK    MPP( 23, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP23_SATA0_PRESENTn   MPP( 23, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP24_GPIO             MPP( 24, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP24_TSMP4            MPP( 24, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP24_TDM_SPI_CS0      DEV( 24, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP24_GE1_4            MPP( 24, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP24_AUDIO_I2SDO      MPP( 24, 0x4, 0, 1, 0,   0,   1,   1    )
-
-#define MPP25_GPIO             MPP( 25, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP25_TSMP5            MPP( 25, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP25_TDM_SPI_SCK      MPP( 25, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP25_GE1_5            MPP( 25, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP25_AUDIO_I2SLRCLK   MPP( 25, 0x4, 0, 1, 0,   0,   1,   1    )
-
-#define MPP26_GPIO             MPP( 26, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP26_TSMP6            MPP( 26, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP26_TDM_SPI_MISO     MPP( 26, 0x2, 1, 0, 0,   0,   1,   1    )
-#define MPP26_GE1_6            MPP( 26, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP26_AUDIO_I2SMCLK    MPP( 26, 0x4, 0, 1, 0,   0,   1,   1    )
-
-#define MPP27_GPIO             MPP( 27, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP27_TSMP7            MPP( 27, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP27_TDM_SPI_MOSI     MPP( 27, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP27_GE1_7            MPP( 27, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP27_AUDIO_I2SDI      MPP( 27, 0x4, 1, 0, 0,   0,   1,   1    )
-
-#define MPP28_GPIO             MPP( 28, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP28_TSMP8            MPP( 28, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP28_TDM_CODEC_INTn   MPP( 28, 0x2, 0, 0, 0,   0,   1,   1    )
-#define MPP28_GE1_8            MPP( 28, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP28_AUDIO_EXTCLK     MPP( 28, 0x4, 1, 0, 0,   0,   1,   1    )
-
-#define MPP29_GPIO             MPP( 29, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP29_TSMP9            MPP( 29, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP29_TDM_CODEC_RSTn   MPP( 29, 0x2, 0, 0, 0,   0,   1,   1    )
-#define MPP29_GE1_9            MPP( 29, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP30_GPIO             MPP( 30, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP30_TSMP10           MPP( 30, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP30_TDM_PCLK         MPP( 30, 0x2, 1, 1, 0,   0,   1,   1    )
-#define MPP30_GE1_10           MPP( 30, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP31_GPIO             MPP( 31, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP31_TSMP11           MPP( 31, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP31_TDM_FS           MPP( 31, 0x2, 1, 1, 0,   0,   1,   1    )
-#define MPP31_GE1_11           MPP( 31, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP32_GPIO             MPP( 32, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP32_TSMP12           MPP( 32, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP32_TDM_DRX          MPP( 32, 0x2, 1, 0, 0,   0,   1,   1    )
-#define MPP32_GE1_12           MPP( 32, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP33_GPIO             MPP( 33, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP33_TDM_DTX          MPP( 33, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP33_GE1_13           MPP( 33, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP34_GPIO             MPP( 34, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP34_TDM_SPI_CS1      MPP( 34, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP34_GE1_14           MPP( 34, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP35_GPIO             MPP( 35, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP35_TDM_CH0_TX_QL    MPP( 35, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP35_GE1_15           MPP( 35, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP35_SATA0_ACTn       MPP( 35, 0x5, 0, 1, 0,   1,   1,   1    )
-#define MPP35_MII0_RXERR       MPP( 35, 0xc, 1, 0, 1,   1,   1,   1    )
-
-#define MPP36_GPIO             MPP( 36, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP36_TSMP0            MPP( 36, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP36_TDM_SPI_CS1      MPP( 36, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP36_AUDIO_SPDIFI     MPP( 36, 0x4, 1, 0, 1,   0,   0,   1    )
-
-#define MPP37_GPIO             MPP( 37, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP37_TSMP1            MPP( 37, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP37_TDM_CH2_TX_QL    MPP( 37, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP37_AUDIO_SPDIFO     MPP( 37, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP38_GPIO             MPP( 38, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP38_TSMP2            MPP( 38, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP38_TDM_CH2_RX_QL    MPP( 38, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP38_AUDIO_SPDIFRMLCLK        MPP( 38, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP39_GPIO             MPP( 39, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP39_TSMP3            MPP( 39, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP39_TDM_SPI_CS0      MPP( 39, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP39_AUDIO_I2SBCLK    MPP( 39, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP40_GPIO             MPP( 40, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP40_TSMP4            MPP( 40, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP40_TDM_SPI_SCK      MPP( 40, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP40_AUDIO_I2SDO      MPP( 40, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP41_GPIO             MPP( 41, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP41_TSMP5            MPP( 41, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP41_TDM_SPI_MISO     MPP( 41, 0x2, 1, 0, 0,   0,   0,   1    )
-#define MPP41_AUDIO_I2SLRC     MPP( 41, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP42_GPIO             MPP( 42, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP42_TSMP6            MPP( 42, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP42_TDM_SPI_MOSI     MPP( 42, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP42_AUDIO_I2SMCLK    MPP( 42, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP43_GPIO             MPP( 43, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP43_TSMP7            MPP( 43, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP43_TDM_CODEC_INTn   MPP( 43, 0x2, 0, 0, 0,   0,   0,   1    )
-#define MPP43_AUDIO_I2SDI      MPP( 43, 0x4, 1, 0, 1,   0,   0,   1    )
-
-#define MPP44_GPIO             MPP( 44, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP44_TSMP8            MPP( 44, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP44_TDM_CODEC_RSTn   MPP( 44, 0x2, 0, 0, 0,   0,   0,   1    )
-#define MPP44_AUDIO_EXTCLK     MPP( 44, 0x4, 1, 0, 1,   0,   0,   1    )
-
-#define MPP45_GPIO             MPP( 45, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP45_TSMP9            MPP( 45, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP45_TDM_PCLK         MPP( 45, 0x2, 1, 1, 0,   0,   0,   1    )
-
-#define MPP46_GPIO             MPP( 46, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP46_TSMP10           MPP( 46, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP46_TDM_FS           MPP( 46, 0x2, 1, 1, 0,   0,   0,   1    )
-
-#define MPP47_GPIO             MPP( 47, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP47_TSMP11           MPP( 47, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP47_TDM_DRX          MPP( 47, 0x2, 1, 0, 0,   0,   0,   1    )
-
-#define MPP48_GPIO             MPP( 48, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP48_TSMP12           MPP( 48, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP48_TDM_DTX          MPP( 48, 0x2, 0, 1, 0,   0,   0,   1    )
-
-#define MPP49_GPIO             MPP( 49, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP49_TSMP9            MPP( 49, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP49_TDM_CH0_RX_QL    MPP( 49, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP49_PTP_CLK          MPP( 49, 0x5, 1, 0, 0,   0,   0,   1    )
+                               /*   num sel  i  o  6180 6190 6192 6281 6282 */
+
+#define MPP_INPUT_MASK         MPP(  0, 0x0, 1, 0, 0,   0,   0,   0,   0 )
+#define MPP_OUTPUT_MASK                MPP(  0, 0x0, 0, 1, 0,   0,   0,   0,   0 )
+
+#define MPP_F6180_MASK         MPP(  0, 0x0, 0, 0, 1,   0,   0,   0,   0 )
+#define MPP_F6190_MASK         MPP(  0, 0x0, 0, 0, 0,   1,   0,   0,   0 )
+#define MPP_F6192_MASK         MPP(  0, 0x0, 0, 0, 0,   0,   1,   0,   0 )
+#define MPP_F6281_MASK         MPP(  0, 0x0, 0, 0, 0,   0,   0,   1,   0 )
+#define MPP_F6282_MASK         MPP(  0, 0x0, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP0_GPIO              MPP(  0, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP0_NF_IO2            MPP(  0, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP0_SPI_SCn           MPP(  0, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+
+#define MPP1_GPO               MPP(  1, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP1_NF_IO3            MPP(  1, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP1_SPI_MOSI          MPP(  1, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+
+#define MPP2_GPO               MPP(  2, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP2_NF_IO4            MPP(  2, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP2_SPI_SCK           MPP(  2, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+
+#define MPP3_GPO               MPP(  3, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP3_NF_IO5            MPP(  3, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP3_SPI_MISO          MPP(  3, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP4_GPIO              MPP(  4, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP4_NF_IO6            MPP(  4, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP4_UART0_RXD         MPP(  4, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP4_SATA1_ACTn                MPP(  4, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP4_LCD_VGA_HSYNC     MPP(  4, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+#define MPP4_PTP_CLK           MPP(  4, 0xd, 1, 0, 1,   1,   1,   1,   0 )
+
+#define MPP5_GPO               MPP(  5, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP5_NF_IO7            MPP(  5, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP5_UART0_TXD         MPP(  5, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP5_PTP_TRIG_GEN      MPP(  5, 0x4, 0, 1, 1,   1,   1,   1,   0 )
+#define MPP5_SATA0_ACTn                MPP(  5, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP5_LCD_VGA_VSYNC     MPP(  5, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP6_SYSRST_OUTn       MPP(  6, 0x1, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP6_SPI_MOSI          MPP(  6, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP6_PTP_TRIG_GEN      MPP(  6, 0x3, 0, 1, 1,   1,   1,   1,   0 )
+
+#define MPP7_GPO               MPP(  7, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP7_PEX_RST_OUTn      MPP(  7, 0x1, 0, 1, 1,   1,   1,   1,   0 )
+#define MPP7_SPI_SCn           MPP(  7, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP7_PTP_TRIG_GEN      MPP(  7, 0x3, 0, 1, 1,   1,   1,   1,   0 )
+#define MPP7_LCD_PWM           MPP(  7, 0xb, 0, 1, 0,   0,   0,   0,   1 )
+
+#define MPP8_GPIO              MPP(  8, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP8_TW0_SDA           MPP(  8, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP8_UART0_RTS         MPP(  8, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP8_UART1_RTS         MPP(  8, 0x3, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP8_MII0_RXERR                MPP(  8, 0x4, 1, 0, 0,   1,   1,   1,   1 )
+#define MPP8_SATA1_PRESENTn    MPP(  8, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP8_PTP_CLK           MPP(  8, 0xc, 1, 0, 1,   1,   1,   1,   0 )
+#define MPP8_MII0_COL          MPP(  8, 0xd, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP9_GPIO              MPP(  9, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP9_TW0_SCK           MPP(  9, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP9_UART0_CTS         MPP(  9, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP9_UART1_CTS         MPP(  9, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP9_SATA0_PRESENTn    MPP(  9, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP9_PTP_EVENT_REQ     MPP(  9, 0xc, 1, 0, 1,   1,   1,   1,   0 )
+#define MPP9_MII0_CRS          MPP(  9, 0xd, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP10_GPO              MPP( 10, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP10_SPI_SCK          MPP( 10, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP10_UART0_TXD                MPP( 10, 0X3, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP10_SATA1_ACTn       MPP( 10, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP10_PTP_TRIG_GEN     MPP( 10, 0xc, 0, 1, 1,   1,   1,   1,   0 )
+
+#define MPP11_GPIO             MPP( 11, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP11_SPI_MISO         MPP( 11, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP11_UART0_RXD                MPP( 11, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP11_PTP_EVENT_REQ    MPP( 11, 0x4, 1, 0, 1,   1,   1,   1,   0 )
+#define MPP11_PTP_TRIG_GEN     MPP( 11, 0xc, 0, 1, 1,   1,   1,   1,   0 )
+#define MPP11_PTP_CLK          MPP( 11, 0xd, 1, 0, 1,   1,   1,   1,   0 )
+#define MPP11_SATA0_ACTn       MPP( 11, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+
+#define MPP12_GPO              MPP( 12, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP12_SD_CLK           MPP( 12, 0x1, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP12_AU_SPDIF0                MPP( 12, 0xa, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP12_SPI_MOSI         MPP( 12, 0xb, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP12_TW1_SDA          MPP( 12, 0xd, 1, 0, 0,   0,   0,   0,   1 )
+
+#define MPP13_GPIO             MPP( 13, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP13_SD_CMD           MPP( 13, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP13_UART1_TXD                MPP( 13, 0x3, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP13_AU_SPDIFRMCLK    MPP( 13, 0xa, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP13_LCDPWM           MPP( 13, 0xb, 0, 1, 0,   0,   0,   0,   1 )
+
+#define MPP14_GPIO             MPP( 14, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP14_SD_D0            MPP( 14, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP14_UART1_RXD                MPP( 14, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP14_SATA1_PRESENTn   MPP( 14, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP14_AU_SPDIFI                MPP( 14, 0xa, 1, 0, 0,   0,   0,   0,   1 )
+#define MPP14_AU_I2SDI         MPP( 14, 0xb, 1, 0, 0,   0,   0,   0,   1 )
+#define MPP14_MII0_COL         MPP( 14, 0xd, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP15_GPIO             MPP( 15, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP15_SD_D1            MPP( 15, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP15_UART0_RTS                MPP( 15, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP15_UART1_TXD                MPP( 15, 0x3, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP15_SATA0_ACTn       MPP( 15, 0x4, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP15_SPI_CSn          MPP( 15, 0xb, 0, 1, 0,   0,   0,   0,   1 )
+
+#define MPP16_GPIO             MPP( 16, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP16_SD_D2            MPP( 16, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP16_UART0_CTS                MPP( 16, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP16_UART1_RXD                MPP( 16, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP16_SATA1_ACTn       MPP( 16, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP16_LCD_EXT_REF_CLK  MPP( 16, 0xb, 1, 0, 0,   0,   0,   0,   1 )
+#define MPP16_MII0_CRS         MPP( 16, 0xd, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP17_GPIO             MPP( 17, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP17_SD_D3            MPP( 17, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP17_SATA0_PRESENTn   MPP( 17, 0x4, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP17_SATA1_ACTn       MPP( 17, 0xa, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP17_TW1_SCK          MPP( 17, 0xd, 1, 1, 0,   0,   0,   0,   1 )
+
+#define MPP18_GPO              MPP( 18, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP18_NF_IO0           MPP( 18, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP18_PEX0_CLKREQ      MPP( 18, 0x2, 0, 1, 0,   0,   0,   0,   1 )
+
+#define MPP19_GPO              MPP( 19, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP19_NF_IO1           MPP( 19, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+
+#define MPP20_GPIO             MPP( 20, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP20_TSMP0            MPP( 20, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP20_TDM_CH0_TX_QL    MPP( 20, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP20_GE1_TXD0         MPP( 20, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP20_AU_SPDIFI                MPP( 20, 0x4, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP20_SATA1_ACTn       MPP( 20, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP20_LCD_D0           MPP( 20, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP21_GPIO             MPP( 21, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP21_TSMP1            MPP( 21, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP21_TDM_CH0_RX_QL    MPP( 21, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP21_GE1_TXD1         MPP( 21, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP21_AU_SPDIFO                MPP( 21, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP21_SATA0_ACTn       MPP( 21, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP21_LCD_D1           MPP( 21, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP22_GPIO             MPP( 22, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP22_TSMP2            MPP( 22, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP22_TDM_CH2_TX_QL    MPP( 22, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP22_GE1_TXD2         MPP( 22, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP22_AU_SPDIFRMKCLK   MPP( 22, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP22_SATA1_PRESENTn   MPP( 22, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP22_LCD_D2           MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP23_GPIO             MPP( 23, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP23_TSMP3            MPP( 23, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP23_TDM_CH2_RX_QL    MPP( 23, 0x2, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP23_GE1_TXD3         MPP( 23, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP23_AU_I2SBCLK       MPP( 23, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP23_SATA0_PRESENTn   MPP( 23, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP23_LCD_D3           MPP( 23, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP24_GPIO             MPP( 24, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP24_TSMP4            MPP( 24, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP24_TDM_SPI_CS0      MPP( 24, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP24_GE1_RXD0         MPP( 24, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP24_AU_I2SDO         MPP( 24, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP24_LCD_D4           MPP( 24, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP25_GPIO             MPP( 25, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP25_TSMP5            MPP( 25, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP25_TDM_SPI_SCK      MPP( 25, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP25_GE1_RXD1         MPP( 25, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP25_AU_I2SLRCLK      MPP( 25, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP25_LCD_D5           MPP( 25, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP26_GPIO             MPP( 26, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP26_TSMP6            MPP( 26, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP26_TDM_SPI_MISO     MPP( 26, 0x2, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP26_GE1_RXD2         MPP( 26, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP26_AU_I2SMCLK       MPP( 26, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP26_LCD_D6           MPP( 26, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP27_GPIO             MPP( 27, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP27_TSMP7            MPP( 27, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP27_TDM_SPI_MOSI     MPP( 27, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP27_GE1_RXD3         MPP( 27, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP27_AU_I2SDI         MPP( 27, 0x4, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP27_LCD_D7           MPP( 27, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP28_GPIO             MPP( 28, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP28_TSMP8            MPP( 28, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP28_TDM_CODEC_INTn   MPP( 28, 0x2, 0, 0, 0,   0,   1,   1,   1 )
+#define MPP28_GE1_COL          MPP( 28, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP28_AU_EXTCLK                MPP( 28, 0x4, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP28_LCD_D8           MPP( 28, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP29_GPIO             MPP( 29, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP29_TSMP9            MPP( 29, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP29_TDM_CODEC_RSTn   MPP( 29, 0x2, 0, 0, 0,   0,   1,   1,   1 )
+#define MPP29_GE1_TCLK         MPP( 29, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP29_LCD_D9           MPP( 29, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP30_GPIO             MPP( 30, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP30_TSMP10           MPP( 30, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP30_TDM_PCLK         MPP( 30, 0x2, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP30_GE1_RXCTL                MPP( 30, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP30_LCD_D10          MPP( 30, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP31_GPIO             MPP( 31, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP31_TSMP11           MPP( 31, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP31_TDM_FS           MPP( 31, 0x2, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP31_GE1_RXCLK                MPP( 31, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP31_LCD_D11          MPP( 31, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP32_GPIO             MPP( 32, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP32_TSMP12           MPP( 32, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP32_TDM_DRX          MPP( 32, 0x2, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP32_GE1_TCLKOUT      MPP( 32, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP32_LCD_D12          MPP( 32, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP33_GPO              MPP( 33, 0x0, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP33_TDM_DTX          MPP( 33, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP33_GE1_TXCTL                MPP( 33, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP33_LCD_D13          MPP( 33, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP34_GPIO             MPP( 34, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP34_TDM_SPI_CS1      MPP( 34, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP34_GE1_TXEN         MPP( 34, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP34_SATA1_ACTn       MPP( 34, 0x5, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP34_LCD_D14          MPP( 34, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP35_GPIO             MPP( 35, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP35_TDM_CH0_TX_QL    MPP( 35, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP35_GE1_RXERR                MPP( 35, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP35_SATA0_ACTn       MPP( 35, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP35_LCD_D15          MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+#define MPP35_MII0_RXERR       MPP( 35, 0xc, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP36_GPIO             MPP( 36, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP36_TSMP0            MPP( 36, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP36_TDM_SPI_CS1      MPP( 36, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP36_AU_SPDIFI                MPP( 36, 0x4, 1, 0, 1,   0,   0,   1,   1 )
+#define MPP36_TW1_SDA          MPP( 36, 0xb, 1, 1, 0,   0,   0,   0,   1 )
+
+#define MPP37_GPIO             MPP( 37, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP37_TSMP1            MPP( 37, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP37_TDM_CH2_TX_QL    MPP( 37, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP37_AU_SPDIFO                MPP( 37, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP37_TW1_SCK          MPP( 37, 0xb, 1, 1, 0,   0,   0,   0,   1 )
+
+#define MPP38_GPIO             MPP( 38, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP38_TSMP2            MPP( 38, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP38_TDM_CH2_RX_QL    MPP( 38, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP38_AU_SPDIFRMLCLK   MPP( 38, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP38_LCD_D18          MPP( 38, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP39_GPIO             MPP( 39, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP39_TSMP3            MPP( 39, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP39_TDM_SPI_CS0      MPP( 39, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP39_AU_I2SBCLK       MPP( 39, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP39_LCD_D19          MPP( 39, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP40_GPIO             MPP( 40, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP40_TSMP4            MPP( 40, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP40_TDM_SPI_SCK      MPP( 40, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP40_AU_I2SDO         MPP( 40, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP40_LCD_D20          MPP( 40, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP41_GPIO             MPP( 41, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP41_TSMP5            MPP( 41, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP41_TDM_SPI_MISO     MPP( 41, 0x2, 1, 0, 0,   0,   0,   1,   1 )
+#define MPP41_AU_I2SLRCLK      MPP( 41, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP41_LCD_D21          MPP( 41, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP42_GPIO             MPP( 42, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP42_TSMP6            MPP( 42, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP42_TDM_SPI_MOSI     MPP( 42, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP42_AU_I2SMCLK       MPP( 42, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP42_LCD_D22          MPP( 42, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP43_GPIO             MPP( 43, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP43_TSMP7            MPP( 43, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP43_TDM_CODEC_INTn   MPP( 43, 0x2, 0, 0, 0,   0,   0,   1,   1 )
+#define MPP43_AU_I2SDI         MPP( 43, 0x4, 1, 0, 1,   0,   0,   1,   1 )
+#define MPP43_LCD_D23          MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP44_GPIO             MPP( 44, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP44_TSMP8            MPP( 44, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP44_TDM_CODEC_RSTn   MPP( 44, 0x2, 0, 0, 0,   0,   0,   1,   1 )
+#define MPP44_AU_EXTCLK                MPP( 44, 0x4, 1, 0, 1,   0,   0,   1,   1 )
+#define MPP44_LCD_CLK          MPP( 44, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP45_GPIO             MPP( 45, 0x0, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP45_TSMP9            MPP( 45, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP45_TDM_PCLK         MPP( 45, 0x2, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP245_LCD_E           MPP( 45, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP46_GPIO             MPP( 46, 0x0, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP46_TSMP10           MPP( 46, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP46_TDM_FS           MPP( 46, 0x2, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP46_LCD_HSYNC                MPP( 46, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP47_GPIO             MPP( 47, 0x0, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP47_TSMP11           MPP( 47, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP47_TDM_DRX          MPP( 47, 0x2, 1, 0, 0,   0,   0,   1,   1 )
+#define MPP47_LCD_VSYNC                MPP( 47, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP48_GPIO             MPP( 48, 0x0, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP48_TSMP12           MPP( 48, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP48_TDM_DTX          MPP( 48, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP48_LCD_D16          MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP49_GPIO             MPP( 49, 0x0, 1, 1, 0,   0,   0,   1,   0 )
+#define MPP49_GPO              MPP( 49, 0x0, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP49_TSMP9            MPP( 49, 0x1, 1, 1, 0,   0,   0,   1,   0 )
+#define MPP49_TDM_CH0_RX_QL    MPP( 49, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP49_PTP_CLK          MPP( 49, 0x5, 1, 0, 0,   0,   0,   1,   0 )
+#define MPP49_PEX0_CLKREQ      MPP( 49, 0xa, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP49_LCD_D17          MPP( 49, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 
 #define MPP_MAX                        49
 

diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
index 5e6f711b1c6753713b8819078ec0bc053566f200..c6b92b42eb4e5a627fcceb74b61078bc8e589f4a 100644 (file)
--- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
@@ -155,7 +155,7 @@ static void __init mv88f6281gtw_ge_init(void)
 static int __init mv88f6281gtw_ge_pci_init(void)
 {
        if (machine_is_mv88f6281gtw_ge())
-               kirkwood_pcie_init();
+               kirkwood_pcie_init(KW_PCIE0);
 
        return 0;
 }

diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
index 3ae158d72681f13a2a6f9e0246c08e3a3f618d3a..d26bf324738bde48e5be8b5c5cf13978a9f03730 100644 (file)
--- a/arch/arm/mach-kirkwood/netspace_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -39,6 +39,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/kirkwood.h>
+#include <mach/leds-ns2.h>
 #include <plat/time.h>
 #include "common.h"
 #include "mpp.h"
@@ -126,6 +127,18 @@ static void __init netspace_v2_sata_power_init(void)
        }
        if (err)
                pr_err("netspace_v2: failed to setup SATA0 power\n");
+
+       if (machine_is_netspace_max_v2()) {
+               err = gpio_request(NETSPACE_V2_GPIO_SATA1_POWER, "SATA1 power");
+               if (err == 0) {
+                       err = gpio_direction_output(
+                                       NETSPACE_V2_GPIO_SATA1_POWER, 1);
+                       if (err)
+                               gpio_free(NETSPACE_V2_GPIO_SATA1_POWER);
+               }
+               if (err)
+                       pr_err("netspace_v2: failed to setup SATA1 power\n");
+       }
 }
 
 /*****************************************************************************
@@ -160,36 +173,12 @@ static struct platform_device netspace_v2_gpio_buttons = {
  * GPIO LEDs
  ****************************************************************************/
 
-/*
- * The blue front LED is wired to a CPLD and can blink in relation with the
- * SATA activity.
- *
- * The following array detail the different LED registers and the combination
- * of their possible values:
- *
- *  cmd_led   |  slow_led  | /SATA active | LED state
- *            |            |              |
- *     1      |     0      |      x       |  off
- *     -      |     1      |      x       |  on
- *     0      |     0      |      1       |  on
- *     0      |     0      |      0       |  blink (rate 300ms)
- */
-
 #define NETSPACE_V2_GPIO_RED_LED       12
-#define NETSPACE_V2_GPIO_BLUE_LED_SLOW 29
-#define NETSPACE_V2_GPIO_BLUE_LED_CMD  30
-
 
 static struct gpio_led netspace_v2_gpio_led_pins[] = {
        {
-               .name                   = "ns_v2:blue:sata",
-               .default_trigger        = "default-on",
-               .gpio                   = NETSPACE_V2_GPIO_BLUE_LED_CMD,
-               .active_low             = 1,
-       },
-       {
-               .name                   = "ns_v2:red:fail",
-               .gpio                   = NETSPACE_V2_GPIO_RED_LED,
+               .name   = "ns_v2:red:fail",
+               .gpio   = NETSPACE_V2_GPIO_RED_LED,
        },
 };
 
@@ -206,22 +195,33 @@ static struct platform_device netspace_v2_gpio_leds = {
        },
 };
 
-static void __init netspace_v2_gpio_leds_init(void)
-{
-       int err;
+/*****************************************************************************
+ * Dual-GPIO CPLD LEDs
+ ****************************************************************************/
 
-       /* Configure register slow_led to allow SATA activity LED blinking */
-       err = gpio_request(NETSPACE_V2_GPIO_BLUE_LED_SLOW, "blue LED slow");
-       if (err == 0) {
-               err = gpio_direction_output(NETSPACE_V2_GPIO_BLUE_LED_SLOW, 0);
-               if (err)
-                       gpio_free(NETSPACE_V2_GPIO_BLUE_LED_SLOW);
-       }
-       if (err)
-               pr_err("netspace_v2: failed to configure blue LED slow GPIO\n");
+#define NETSPACE_V2_GPIO_BLUE_LED_SLOW 29
+#define NETSPACE_V2_GPIO_BLUE_LED_CMD  30
 
-       platform_device_register(&netspace_v2_gpio_leds);
-}
+static struct ns2_led netspace_v2_led_pins[] = {
+       {
+               .name   = "ns_v2:blue:sata",
+               .cmd    = NETSPACE_V2_GPIO_BLUE_LED_CMD,
+               .slow   = NETSPACE_V2_GPIO_BLUE_LED_SLOW,
+       },
+};
+
+static struct ns2_led_platform_data netspace_v2_leds_data = {
+       .num_leds       = ARRAY_SIZE(netspace_v2_led_pins),
+       .leds           = netspace_v2_led_pins,
+};
+
+static struct platform_device netspace_v2_leds = {
+       .name           = "leds-ns2",
+       .id             = -1,
+       .dev            = {
+               .platform_data  = &netspace_v2_leds_data,
+       },
+};
 
 /*****************************************************************************
  * Timer
@@ -249,17 +249,21 @@ static unsigned int netspace_v2_mpp_config[] __initdata = {
        MPP4_NF_IO6,
        MPP5_NF_IO7,
        MPP6_SYSRST_OUTn,
-       MPP8_TW_SDA,
-       MPP9_TW_SCK,
+       MPP7_GPO,               /* Fan speed (bit 1) */
+       MPP8_TW0_SDA,
+       MPP9_TW0_SCK,
        MPP10_UART0_TXD,
        MPP11_UART0_RXD,
        MPP12_GPO,              /* Red led */
        MPP14_GPIO,             /* USB fuse */
        MPP16_GPIO,             /* SATA 0 power */
+       MPP17_GPIO,             /* SATA 1 power */
        MPP18_NF_IO0,
        MPP19_NF_IO1,
        MPP20_SATA1_ACTn,
        MPP21_SATA0_ACTn,
+       MPP22_GPIO,             /* Fan speed (bit 0) */
+       MPP23_GPIO,             /* Fan power */
        MPP24_GPIO,             /* USB mode select */
        MPP25_GPIO,             /* Fan rotation fail */
        MPP26_GPIO,             /* USB device vbus */
@@ -268,6 +272,7 @@ static unsigned int netspace_v2_mpp_config[] __initdata = {
        MPP30_GPIO,             /* Blue led (command register) */
        MPP31_GPIO,             /* Board power off */
        MPP32_GPIO,             /* Power button (0 = Released, 1 = Pushed) */
+       MPP33_GPO,              /* Fan speed (bit 2) */
        0
 };
 
@@ -299,7 +304,8 @@ static void __init netspace_v2_init(void)
        i2c_register_board_info(0, netspace_v2_i2c_info,
                                ARRAY_SIZE(netspace_v2_i2c_info));
 
-       netspace_v2_gpio_leds_init();
+       platform_device_register(&netspace_v2_leds);
+       platform_device_register(&netspace_v2_gpio_leds);
        platform_device_register(&netspace_v2_gpio_buttons);
 
        if (gpio_request(NETSPACE_V2_GPIO_POWER_OFF, "power-off") == 0 &&
@@ -332,3 +338,15 @@ MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2")
        .timer          = &netspace_v2_timer,
 MACHINE_END
 #endif
+
+#ifdef CONFIG_MACH_NETSPACE_MAX_V2
+MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2")
+       .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+       .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+       .boot_params    = 0x00000100,
+       .init_machine   = netspace_v2_init,
+       .map_io         = kirkwood_map_io,
+       .init_irq       = kirkwood_init_irq,
+       .timer          = &netspace_v2_timer,
+MACHINE_END
+#endif

diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
index 8a2bb0228e4f1d73b26b266d5e9c07bae49049ef..2bd14c5079de7c0e7379439523aed3422173f383 100644 (file)
--- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
@@ -270,8 +270,8 @@ static unsigned int net2big_v2_mpp_config[] __initdata = {
        MPP3_SPI_MISO,
        MPP6_SYSRST_OUTn,
        MPP7_GPO,               /* Request power-off */
-       MPP8_TW_SDA,
-       MPP9_TW_SCK,
+       MPP8_TW0_SDA,
+       MPP9_TW0_SCK,
        MPP10_UART0_TXD,
        MPP11_UART0_RXD,
        MPP13_GPIO,             /* Rear power switch (on|auto) */
@@ -306,8 +306,8 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
        MPP3_SPI_MISO,
        MPP6_SYSRST_OUTn,
        MPP7_GPO,               /* Request power-off */
-       MPP8_TW_SDA,
-       MPP9_TW_SCK,
+       MPP8_TW0_SDA,
+       MPP9_TW0_SCK,
        MPP10_UART0_TXD,
        MPP11_UART0_RXD,
        MPP13_GPIO,             /* Rear power switch (on|auto) */
@@ -315,20 +315,20 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
        MPP15_GPIO,             /* Rear power switch (auto|off) */
        MPP16_GPIO,             /* SATA HDD1 power */
        MPP17_GPIO,             /* SATA HDD2 power */
-       MPP20_GE1_0,
-       MPP21_GE1_1,
-       MPP22_GE1_2,
-       MPP23_GE1_3,
-       MPP24_GE1_4,
-       MPP25_GE1_5,
-       MPP26_GE1_6,
-       MPP27_GE1_7,
+       MPP20_GE1_TXD0,
+       MPP21_GE1_TXD1,
+       MPP22_GE1_TXD2,
+       MPP23_GE1_TXD3,
+       MPP24_GE1_RXD0,
+       MPP25_GE1_RXD1,
+       MPP26_GE1_RXD2,
+       MPP27_GE1_RXD3,
        MPP28_GPIO,             /* USB enable host vbus */
        MPP29_GPIO,             /* CPLD extension ALE */
-       MPP30_GE1_10,
-       MPP31_GE1_11,
-       MPP32_GE1_12,
-       MPP33_GE1_13,
+       MPP30_GE1_RXCTL,
+       MPP31_GE1_RXCLK,
+       MPP32_GE1_TCLKOUT,
+       MPP33_GE1_TXCTL,
        MPP34_GPIO,             /* Rear Push button */
        MPP35_GPIO,             /* Inhibit switch power-off */
        MPP36_GPIO,             /* SATA HDD1 presence */

diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index ad3f1ec3379689556296ef1ccf3b425c07f8007a..fd64cd2b4e0ad0cd8780ef33f25f5821407d49c8 100644 (file)
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-kirkwood/openrd-setup.c
  *
- * Marvell OpenRD (Base|Client) Board Setup
+ * Marvell OpenRD (Base|Client|Ultimate) Board Setup
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2.  This program is licensed "as is" without any
@@ -73,9 +73,15 @@ static void __init openrd_init(void)
 
        kirkwood_ehci_init();
 
+       if (machine_is_openrd_ultimate()) {
+               openrd_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
+               openrd_ge01_data.phy_addr = MV643XX_ETH_PHY_ADDR(1);
+       }
+
        kirkwood_ge00_init(&openrd_ge00_data);
-       if (machine_is_openrd_client())
+       if (!machine_is_openrd_base())
                kirkwood_ge01_init(&openrd_ge01_data);
+
        kirkwood_sata_init(&openrd_sata_data);
        kirkwood_sdio_init(&openrd_mvsdio_data);
 
@@ -84,8 +90,10 @@ static void __init openrd_init(void)
 
 static int __init openrd_pci_init(void)
 {
-       if (machine_is_openrd_base() || machine_is_openrd_client())
-               kirkwood_pcie_init();
+       if (machine_is_openrd_base() ||
+           machine_is_openrd_client() ||
+           machine_is_openrd_ultimate())
+               kirkwood_pcie_init(KW_PCIE0);
 
        return 0;
 }
@@ -116,3 +124,16 @@ MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board")
        .timer          = &kirkwood_timer,
 MACHINE_END
 #endif
+
+#ifdef CONFIG_MACH_OPENRD_ULTIMATE
+MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board")
+       /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */
+       .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+       .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+       .boot_params    = 0x00000100,
+       .init_machine   = openrd_init,
+       .map_io         = kirkwood_map_io,
+       .init_irq       = kirkwood_init_irq,
+       .timer          = &kirkwood_timer,
+MACHINE_END
+#endif

diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index dee1eff50d3933d2252a2f66aed2f1d7456d69c3..55e7f00836b7cdba68a9662729119e977904a2dd 100644 (file)
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -18,29 +18,43 @@
 #include <mach/bridge-regs.h>
 #include "common.h"
 
+void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
+{
+       *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
+       *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
+}
 
-#define PCIE_BASE      ((void __iomem *)PCIE_VIRT_BASE)
+struct pcie_port {
+       u8                      root_bus_nr;
+       void __iomem            *base;
+       spinlock_t              conf_lock;
+       int                     irq;
+       struct resource         res[2];
+};
 
-void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
+static int pcie_port_map[2];
+static int num_pcie_ports;
+
+static inline struct pcie_port *bus_to_port(struct pci_bus *bus)
 {
-       *dev = orion_pcie_dev_id(PCIE_BASE);
-       *rev = orion_pcie_rev(PCIE_BASE);
+       struct pci_sys_data *sys = bus->sysdata;
+       return sys->private_data;
 }
 
-static int pcie_valid_config(int bus, int dev)
+static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
 {
        /*
         * Don't go out when trying to access --
         * 1. nonexisting device on local bus
         * 2. where there's no device connected (no link)
         */
-       if (bus == 0 && dev == 0)
+       if (bus == pp->root_bus_nr && dev == 0)
                return 1;
 
-       if (!orion_pcie_link_up(PCIE_BASE))
+       if (!orion_pcie_link_up(pp->base))
                return 0;
 
-       if (bus == 0 && dev != 1)
+       if (bus == pp->root_bus_nr && dev != 1)
                return 0;
 
        return 1;
@@ -52,22 +66,22 @@ static int pcie_valid_config(int bus, int dev)
  * and then reading the PCIE_CONF_DATA register. Need to make sure these
  * transactions are atomic.
  */
-static DEFINE_SPINLOCK(kirkwood_pcie_lock);
 
 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
                        int size, u32 *val)
 {
+       struct pcie_port *pp = bus_to_port(bus);
        unsigned long flags;
        int ret;
 
-       if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
+       if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
                *val = 0xffffffff;
                return PCIBIOS_DEVICE_NOT_FOUND;
        }
 
-       spin_lock_irqsave(&kirkwood_pcie_lock, flags);
-       ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
-       spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
+       spin_lock_irqsave(&pp->conf_lock, flags);
+       ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
+       spin_unlock_irqrestore(&pp->conf_lock, flags);
 
        return ret;
 }
@@ -75,15 +89,16 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
                        int where, int size, u32 val)
 {
+       struct pcie_port *pp = bus_to_port(bus);
        unsigned long flags;
        int ret;
 
-       if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
+       if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
                return PCIBIOS_DEVICE_NOT_FOUND;
 
-       spin_lock_irqsave(&kirkwood_pcie_lock, flags);
-       ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
-       spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
+       spin_lock_irqsave(&pp->conf_lock, flags);
+       ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
+       spin_unlock_irqrestore(&pp->conf_lock, flags);
 
        return ret;
 }
@@ -93,50 +108,98 @@ static struct pci_ops pcie_ops = {
        .write = pcie_wr_conf,
 };
 
-
-static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
+static void __init pcie0_ioresources_init(struct pcie_port *pp)
 {
-       struct resource *res;
-       extern unsigned int kirkwood_clk_ctrl;
+       pp->base = (void __iomem *)PCIE_VIRT_BASE;
+       pp->irq = IRQ_KIRKWOOD_PCIE;
 
        /*
-        * Generic PCIe unit setup.
+        * IORESOURCE_IO
         */
-       orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info);
+       pp->res[0].name = "PCIe 0 I/O Space";
+       pp->res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
+       pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
+       pp->res[0].flags = IORESOURCE_IO;
 
        /*
-        * Request resources.
+        * IORESOURCE_MEM
         */
-       res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
-       if (!res)
-               panic("pcie_setup unable to alloc resources");
+       pp->res[1].name = "PCIe 0 MEM";
+       pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
+       pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
+       pp->res[1].flags = IORESOURCE_MEM;
+}
+
+static void __init pcie1_ioresources_init(struct pcie_port *pp)
+{
+       pp->base = (void __iomem *)PCIE1_VIRT_BASE;
+       pp->irq = IRQ_KIRKWOOD_PCIE1;
 
        /*
         * IORESOURCE_IO
         */
-       res[0].name = "PCIe I/O Space";
-       res[0].flags = IORESOURCE_IO;
-       res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
-       res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
-       if (request_resource(&ioport_resource, &res[0]))
-               panic("Request PCIe IO resource failed\n");
-       sys->resource[0] = &res[0];
+       pp->res[0].name = "PCIe 1 I/O Space";
+       pp->res[0].start = KIRKWOOD_PCIE1_IO_PHYS_BASE;
+       pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
+       pp->res[0].flags = IORESOURCE_IO;
 
        /*
         * IORESOURCE_MEM
         */
-       res[1].name = "PCIe Memory Space";
-       res[1].flags = IORESOURCE_MEM;
-       res[1].start = KIRKWOOD_PCIE_MEM_BUS_BASE;
-       res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
-       if (request_resource(&iomem_resource, &res[1]))
-               panic("Request PCIe Memory resource failed\n");
-       sys->resource[1] = &res[1];
+       pp->res[1].name = "PCIe 1 MEM";
+       pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
+       pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
+       pp->res[1].flags = IORESOURCE_MEM;
+}
+
+static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
+{
+       extern unsigned int kirkwood_clk_ctrl;
+       struct pcie_port *pp;
+       int index;
 
+       if (nr >= num_pcie_ports)
+               return 0;
+
+       index = pcie_port_map[nr];
+       printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
+
+       pp = kzalloc(sizeof(*pp), GFP_KERNEL);
+       if (!pp)
+               panic("PCIe: failed to allocate pcie_port data");
+       sys->private_data = pp;
+       pp->root_bus_nr = sys->busnr;
+       spin_lock_init(&pp->conf_lock);
+
+       switch (index) {
+       case 0:
+               kirkwood_clk_ctrl |= CGC_PEX0;
+               pcie0_ioresources_init(pp);
+               break;
+       case 1:
+               kirkwood_clk_ctrl |= CGC_PEX1;
+               pcie1_ioresources_init(pp);
+               break;
+       default:
+               panic("PCIe setup: invalid controller %d", index);
+       }
+
+       if (request_resource(&ioport_resource, &pp->res[0]))
+               panic("Request PCIe%d IO resource failed\n", index);
+       if (request_resource(&iomem_resource, &pp->res[1]))
+               panic("Request PCIe%d Memory resource failed\n", index);
+
+       sys->resource[0] = &pp->res[0];
+       sys->resource[1] = &pp->res[1];
        sys->resource[2] = NULL;
        sys->io_offset = 0;
 
-       kirkwood_clk_ctrl |= CGC_PEX0;
+       /*
+        * Generic PCIe unit setup.
+        */
+       orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
+
+       orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info);
 
        return 1;
 }
@@ -163,7 +226,7 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 {
        struct pci_bus *bus;
 
-       if (nr == 0) {
+       if (nr < num_pcie_ports) {
                bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
        } else {
                bus = NULL;
@@ -175,18 +238,37 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 
 static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
-       return IRQ_KIRKWOOD_PCIE;
+       struct pcie_port *pp = bus_to_port(dev->bus);
+
+       return pp->irq;
 }
 
 static struct hw_pci kirkwood_pci __initdata = {
-       .nr_controllers = 1,
        .swizzle        = pci_std_swizzle,
        .setup          = kirkwood_pcie_setup,
        .scan           = kirkwood_pcie_scan_bus,
        .map_irq        = kirkwood_pcie_map_irq,
 };
 
-void __init kirkwood_pcie_init(void)
+static void __init add_pcie_port(int index, unsigned long base)
 {
+       printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
+
+       if (orion_pcie_link_up((void __iomem *)base)) {
+               printk(KERN_INFO "link up\n");
+               pcie_port_map[num_pcie_ports++] = index;
+       } else
+               printk(KERN_INFO "link down, ignoring\n");
+}
+
+void __init kirkwood_pcie_init(unsigned int portmask)
+{
+       if (portmask & KW_PCIE0)
+               add_pcie_port(0, PCIE_VIRT_BASE);
+
+       if (portmask & KW_PCIE1)
+               add_pcie_port(1, PCIE1_VIRT_BASE);
+
+       kirkwood_pci.nr_controllers = num_pcie_ports;
        pci_common_init(&kirkwood_pci);
 }

diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index 3bf6304158f64354b410461c87d9ec0778ba26cf..c34718c2cfe511373df10338e28c399a092c7744 100644 (file)
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -71,7 +71,7 @@ static void __init rd88f6192_init(void)
 static int __init rd88f6192_pci_init(void)
 {
        if (machine_is_rd88f6192_nas())
-               kirkwood_pcie_init();
+               kirkwood_pcie_init(KW_PCIE0);
 
        return 0;
 }

diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index 31708ddbc83e13d5d97b31bdbaf3c13eeb735c1a..3d1477135e12d8fb0edacb8067304a18f04bc111 100644 (file)
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -107,7 +107,7 @@ static void __init rd88f6281_init(void)
 static int __init rd88f6281_pci_init(void)
 {
        if (machine_is_rd88f6281())
-               kirkwood_pcie_init();
+               kirkwood_pcie_init(KW_PCIE0);
 
        return 0;
 }

diff --git a/arch/arm/mach-kirkwood/t5325-setup.c b/arch/arm/mach-kirkwood/t5325-setup.c
new file mode 100644 (file)
index 0000000..d01bf89
--- /dev/null
+++ b/arch/arm/mach-kirkwood/t5325-setup.c
@@ -0,0 +1,194 @@
+/*
+ *
+ * HP t5325 Thin Client setup
+ *
+ * Copyright (C) 2010  Martin Michlmayr <tbm@cyrius.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/orion_spi.h>
+#include <linux/i2c.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/ata_platform.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include "common.h"
+#include "mpp.h"
+
+struct mtd_partition hp_t5325_partitions[] = {
+       {
+               .name           = "u-boot env",
+               .size           = SZ_64K,
+               .offset         = SZ_512K + SZ_256K,
+       },
+       {
+               .name           = "permanent u-boot env",
+               .size           = SZ_64K,
+               .offset         = MTDPART_OFS_APPEND,
+               .mask_flags     = MTD_WRITEABLE,
+       },
+       {
+               .name           = "HP env",
+               .size           = SZ_64K,
+               .offset         = MTDPART_OFS_APPEND,
+       },
+       {
+               .name           = "u-boot",
+               .size           = SZ_512K,
+               .offset         = 0,
+               .mask_flags     = MTD_WRITEABLE,
+       },
+       {
+               .name           = "SSD firmware",
+               .size           = SZ_256K,
+               .offset         = SZ_512K,
+       },
+};
+
+const struct flash_platform_data hp_t5325_flash = {
+       .type           = "mx25l8005",
+       .name           = "spi_flash",
+       .parts          = hp_t5325_partitions,
+       .nr_parts       = ARRAY_SIZE(hp_t5325_partitions),
+};
+
+struct spi_board_info __initdata hp_t5325_spi_slave_info[] = {
+       {
+               .modalias       = "m25p80",
+               .platform_data  = &hp_t5325_flash,
+               .irq            = -1,
+       },
+};
+
+static struct mv643xx_eth_platform_data hp_t5325_ge00_data = {
+       .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+
+static struct mv_sata_platform_data hp_t5325_sata_data = {
+       .n_ports        = 2,
+};
+
+static struct gpio_keys_button hp_t5325_buttons[] = {
+       {
+               .code           = KEY_POWER,
+               .gpio           = 45,
+               .desc           = "Power",
+               .active_low     = 1,
+       },
+};
+
+static struct gpio_keys_platform_data hp_t5325_button_data = {
+       .buttons        = hp_t5325_buttons,
+       .nbuttons       = ARRAY_SIZE(hp_t5325_buttons),
+};
+
+static struct platform_device hp_t5325_button_device = {
+       .name           = "gpio-keys",
+       .id             = -1,
+       .num_resources  = 0,
+       .dev            = {
+               .platform_data  = &hp_t5325_button_data,
+       }
+};
+
+static unsigned int hp_t5325_mpp_config[] __initdata = {
+       MPP0_NF_IO2,
+       MPP1_SPI_MOSI,
+       MPP2_SPI_SCK,
+       MPP3_SPI_MISO,
+       MPP4_NF_IO6,
+       MPP5_NF_IO7,
+       MPP6_SYSRST_OUTn,
+       MPP7_SPI_SCn,
+       MPP8_TW0_SDA,
+       MPP9_TW0_SCK,
+       MPP10_UART0_TXD,
+       MPP11_UART0_RXD,
+       MPP12_SD_CLK,
+       MPP13_GPIO,
+       MPP14_GPIO,
+       MPP15_GPIO,
+       MPP16_GPIO,
+       MPP17_GPIO,
+       MPP18_NF_IO0,
+       MPP19_NF_IO1,
+       MPP20_GPIO,
+       MPP21_GPIO,
+       MPP22_GPIO,
+       MPP23_GPIO,
+       MPP32_GPIO,
+       MPP33_GE1_TXCTL,
+       MPP39_AU_I2SBCLK,
+       MPP40_AU_I2SDO,
+       MPP41_AU_I2SLRCLK,
+       MPP42_AU_I2SMCLK,
+       MPP45_GPIO,             /* Power button */
+       MPP48_GPIO,             /* Board power off */
+       0
+};
+
+#define HP_T5325_GPIO_POWER_OFF                48
+
+static void hp_t5325_power_off(void)
+{
+       gpio_set_value(HP_T5325_GPIO_POWER_OFF, 1);
+}
+
+static void __init hp_t5325_init(void)
+{
+       /*
+        * Basic setup. Needs to be called early.
+        */
+       kirkwood_init();
+       kirkwood_mpp_conf(hp_t5325_mpp_config);
+
+       kirkwood_uart0_init();
+       spi_register_board_info(hp_t5325_spi_slave_info,
+                               ARRAY_SIZE(hp_t5325_spi_slave_info));
+       kirkwood_spi_init();
+       kirkwood_i2c_init();
+       kirkwood_ge00_init(&hp_t5325_ge00_data);
+       kirkwood_sata_init(&hp_t5325_sata_data);
+       kirkwood_ehci_init();
+       platform_device_register(&hp_t5325_button_device);
+
+       if (gpio_request(HP_T5325_GPIO_POWER_OFF, "power-off") == 0 &&
+           gpio_direction_output(HP_T5325_GPIO_POWER_OFF, 0) == 0)
+               pm_power_off = hp_t5325_power_off;
+       else
+               pr_err("t5325: failed to configure power-off GPIO\n");
+}
+
+static int __init hp_t5325_pci_init(void)
+{
+       if (machine_is_t5325())
+               kirkwood_pcie_init(KW_PCIE0);
+
+       return 0;
+}
+subsys_initcall(hp_t5325_pci_init);
+
+MACHINE_START(T5325, "HP t5325 Thin Client")
+       /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
+       .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+       .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+       .boot_params    = 0x00000100,
+       .init_machine   = hp_t5325_init,
+       .map_io         = kirkwood_map_io,
+       .init_irq       = kirkwood_init_irq,
+       .timer          = &kirkwood_timer,
+MACHINE_END

diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index 2830f0fe80e09d0b37c14a9589972a012cc733b2..a5bd7fde04a9429068f856070225cf816b96bb56 100644 (file)
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -74,8 +74,8 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = {
        MPP3_SPI_MISO,
        MPP4_SATA1_ACTn,
        MPP5_SATA0_ACTn,
-       MPP8_TW_SDA,
-       MPP9_TW_SCK,
+       MPP8_TW0_SDA,
+       MPP9_TW0_SCK,
        MPP10_UART0_TXD,
        MPP11_UART0_RXD,
        MPP13_UART1_TXD,        /* PIC controller */
@@ -83,6 +83,7 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = {
        MPP15_GPIO,             /* USB Copy button */
        MPP16_GPIO,             /* Reset button */
        MPP36_GPIO,             /* RAM: 0: 256 MB, 1: 512 MB */
+       MPP44_GPIO,             /* Board ID: 0: TS-11x, 1: TS-21x */
        0
 };
 
@@ -110,10 +111,10 @@ static void __init qnap_ts219_init(void)
 
 static int __init ts219_pci_init(void)
 {
-   if (machine_is_ts219())
-           kirkwood_pcie_init();
+       if (machine_is_ts219())
+               kirkwood_pcie_init(KW_PCIE0);
 
-   return 0;
+       return 0;
 }
 subsys_initcall(ts219_pci_init);
 

diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index de49c2d9e74b0b262072721630aeac92f6a57e7a..2e14afef07a2ace0708e144b98bf4ef1f2a446b1 100644 (file)
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -2,7 +2,7 @@
  *
  * QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS Board Setup
  *
- * Copyright (C) 2009  Martin Michlmayr <tbm@cyrius.com>
+ * Copyright (C) 2009-2010  Martin Michlmayr <tbm@cyrius.com>
  * Copyright (C) 2008  Byron Bradley <byron.bbradley@gmail.com>
  *
  * This program is free software; you can redistribute it and/or
@@ -17,6 +17,7 @@
 #include <linux/i2c.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/ata_platform.h>
+#include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <asm/mach-types.h>
@@ -26,6 +27,8 @@
 #include "mpp.h"
 #include "tsx1x-common.h"
 
+#define QNAP_TS41X_JUMPER_JP1  45
+
 static struct i2c_board_info __initdata qnap_ts41x_i2c_rtc = {
        I2C_BOARD_INFO("s35390a", 0x30),
 };
@@ -78,31 +81,31 @@ static unsigned int qnap_ts41x_mpp_config[] __initdata = {
        MPP3_SPI_MISO,
        MPP6_SYSRST_OUTn,
        MPP7_PEX_RST_OUTn,
-       MPP8_TW_SDA,
-       MPP9_TW_SCK,
+       MPP8_TW0_SDA,
+       MPP9_TW0_SCK,
        MPP10_UART0_TXD,
        MPP11_UART0_RXD,
        MPP13_UART1_TXD,        /* PIC controller */
        MPP14_UART1_RXD,        /* PIC controller */
        MPP15_SATA0_ACTn,
        MPP16_SATA1_ACTn,
-       MPP20_GE1_0,
-       MPP21_GE1_1,
-       MPP22_GE1_2,
-       MPP23_GE1_3,
-       MPP24_GE1_4,
-       MPP25_GE1_5,
-       MPP26_GE1_6,
-       MPP27_GE1_7,
-       MPP30_GE1_10,
-       MPP31_GE1_11,
-       MPP32_GE1_12,
-       MPP33_GE1_13,
+       MPP20_GE1_TXD0,
+       MPP21_GE1_TXD1,
+       MPP22_GE1_TXD2,
+       MPP23_GE1_TXD3,
+       MPP24_GE1_RXD0,
+       MPP25_GE1_RXD1,
+       MPP26_GE1_RXD2,
+       MPP27_GE1_RXD3,
+       MPP30_GE1_RXCTL,
+       MPP31_GE1_RXCLK,
+       MPP32_GE1_TCLKOUT,
+       MPP33_GE1_TXCTL,
        MPP36_GPIO,             /* RAM: 0: 256 MB, 1: 512 MB */
        MPP37_GPIO,             /* Reset button */
        MPP43_GPIO,             /* USB Copy button */
        MPP44_GPIO,             /* Board ID: 0: TS-419U, 1: TS-419 */
-       MPP45_GPIO,             /* JP1: 0: console, 1: LCD */
+       MPP45_GPIO,             /* JP1: 0: LCD, 1: serial console */
        MPP46_GPIO,             /* External SATA HDD1 error indicator */
        MPP47_GPIO,             /* External SATA HDD2 error indicator */
        MPP48_GPIO,             /* External SATA HDD3 error indicator */
@@ -131,12 +134,14 @@ static void __init qnap_ts41x_init(void)
 
        pm_power_off = qnap_tsx1x_power_off;
 
+       if (gpio_request(QNAP_TS41X_JUMPER_JP1, "JP1") == 0)
+               gpio_export(QNAP_TS41X_JUMPER_JP1, 0);
 }
 
 static int __init ts41x_pci_init(void)
 {
        if (machine_is_ts41x())
-               kirkwood_pcie_init();
+               kirkwood_pcie_init(KW_PCIE0);
 
    return 0;
 }

diff --git a/arch/arm/mach-ks8695/pci.c b/arch/arm/mach-ks8695/pci.c
index 78499667eb7b3241c3a5c1dfbbc69df4840a3991..5fcd082a17f9bff9b0d8a0818b199ebffd5833d2 100644 (file)
--- a/arch/arm/mach-ks8695/pci.c
+++ b/arch/arm/mach-ks8695/pci.c
@@ -268,8 +268,8 @@ static void __init ks8695_pci_preinit(void)
        __raw_writel(0, KS8695_PCI_VA + KS8695_PIOBAC);
 
        /* hook in fault handlers */
-       hook_fault_code(8, ks8695_pci_fault, SIGBUS, "external abort on non-linefetch");
-       hook_fault_code(10, ks8695_pci_fault, SIGBUS, "external abort on non-linefetch");
+       hook_fault_code(8, ks8695_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
+       hook_fault_code(10, ks8695_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
 }
 
 static void ks8695_show_pciregs(void)

diff --git a/arch/arm/mach-l7200/Makefile b/arch/arm/mach-l7200/Makefile
deleted file mode 100644 (file)
index 4bd8ebd..0000000
--- a/arch/arm/mach-l7200/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-# Object file lists.
-
-obj-y                  := core.o
-obj-m                  :=
-obj-n                  :=
-obj-                   :=
-

diff --git a/arch/arm/mach-l7200/Makefile.boot b/arch/arm/mach-l7200/Makefile.boot
deleted file mode 100644 (file)
index 6c72ecb..0000000
--- a/arch/arm/mach-l7200/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
-   zreladdr-y  := 0xf0008000
-

diff --git a/arch/arm/mach-l7200/core.c b/arch/arm/mach-l7200/core.c
deleted file mode 100644 (file)
index 50d2324..0000000
--- a/arch/arm/mach-l7200/core.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- *  linux/arch/arm/mm/mm-lusl7200.c
- *
- *  Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
- *
- *  Extra MM routines for L7200 architecture
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/device.h>
-
-#include <asm/types.h>
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <asm/page.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-/*
- * IRQ base register
- */
-#define        IRQ_BASE        (IO_BASE_2 + 0x1000)
-
-/* 
- * Normal IRQ registers
- */
-#define IRQ_STATUS     (*(volatile unsigned long *) (IRQ_BASE + 0x000))
-#define IRQ_RAWSTATUS  (*(volatile unsigned long *) (IRQ_BASE + 0x004))
-#define IRQ_ENABLE     (*(volatile unsigned long *) (IRQ_BASE + 0x008))
-#define IRQ_ENABLECLEAR        (*(volatile unsigned long *) (IRQ_BASE + 0x00c))
-#define IRQ_SOFT       (*(volatile unsigned long *) (IRQ_BASE + 0x010))
-#define IRQ_SOURCESEL  (*(volatile unsigned long *) (IRQ_BASE + 0x018))
-
-/* 
- * Fast IRQ registers
- */
-#define FIQ_STATUS     (*(volatile unsigned long *) (IRQ_BASE + 0x100))
-#define FIQ_RAWSTATUS  (*(volatile unsigned long *) (IRQ_BASE + 0x104))
-#define FIQ_ENABLE     (*(volatile unsigned long *) (IRQ_BASE + 0x108))
-#define FIQ_ENABLECLEAR        (*(volatile unsigned long *) (IRQ_BASE + 0x10c))
-#define FIQ_SOFT       (*(volatile unsigned long *) (IRQ_BASE + 0x110))
-#define FIQ_SOURCESEL  (*(volatile unsigned long *) (IRQ_BASE + 0x118))
-
-static void l7200_mask_irq(unsigned int irq)
-{
-       IRQ_ENABLECLEAR = 1 << irq;
-}
-
-static void l7200_unmask_irq(unsigned int irq)
-{
-       IRQ_ENABLE = 1 << irq;
-}
-
-static struct irq_chip l7200_irq_chip = {
-       .ack            = l7200_mask_irq,
-       .mask           = l7200_mask_irq,
-       .unmask         = l7200_unmask_irq
-};
- 
-static void __init l7200_init_irq(void)
-{
-       int irq;
-
-       IRQ_ENABLECLEAR = 0xffffffff;   /* clear all interrupt enables */
-       FIQ_ENABLECLEAR = 0xffffffff;   /* clear all fast interrupt enables */
-
-       for (irq = 0; irq < NR_IRQS; irq++) {
-               set_irq_chip(irq, &l7200_irq_chip);
-               set_irq_flags(irq, IRQF_VALID);
-               set_irq_handler(irq, handle_level_irq);
-       }
-
-       init_FIQ();
-}
-
-static struct map_desc l7200_io_desc[] __initdata = {
-       { IO_BASE,      IO_START,       IO_SIZE,        MT_DEVICE },
-       { IO_BASE_2,    IO_START_2,     IO_SIZE_2,      MT_DEVICE },
-       { AUX_BASE,     AUX_START,      AUX_SIZE,       MT_DEVICE },
-       { FLASH1_BASE,  FLASH1_START,   FLASH1_SIZE,    MT_DEVICE },
-       { FLASH2_BASE,  FLASH2_START,   FLASH2_SIZE,    MT_DEVICE }
-};
-
-static void __init l7200_map_io(void)
-{
-       iotable_init(l7200_io_desc, ARRAY_SIZE(l7200_io_desc));
-}
-
-MACHINE_START(L7200, "LinkUp Systems L7200")
-       /* Maintainer: Steve Hill / Scott McConnell */
-       .phys_io        = 0x80040000,
-       .io_pg_offst    = ((0xd0000000) >> 18) & 0xfffc,
-       .map_io         = l7200_map_io,
-       .init_irq       = l7200_init_irq,
-MACHINE_END
-

diff --git a/arch/arm/mach-l7200/include/mach/aux_reg.h b/arch/arm/mach-l7200/include/mach/aux_reg.h
deleted file mode 100644 (file)
index 4671558..0000000
--- a/arch/arm/mach-l7200/include/mach/aux_reg.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/aux_reg.h
- *
- * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *   08-02-2000        SJH     Created file
- */
-#ifndef _ASM_ARCH_AUXREG_H
-#define _ASM_ARCH_AUXREG_H
-
-#include <mach/hardware.h>
-
-#define l7200aux_reg   *((volatile unsigned int *) (AUX_BASE))
-
-/*
- * Auxillary register values
- */
-#define AUX_CLEAR              0x00000000
-#define AUX_DIAG_LED_ON                0x00000002
-#define AUX_RTS_UART1          0x00000004
-#define AUX_DTR_UART1          0x00000008
-#define AUX_KBD_COLUMN_12_HIGH 0x00000010
-#define AUX_KBD_COLUMN_12_OFF  0x00000020
-#define AUX_KBD_COLUMN_13_HIGH 0x00000040
-#define AUX_KBD_COLUMN_13_OFF  0x00000080
-
-#endif

diff --git a/arch/arm/mach-l7200/include/mach/debug-macro.S b/arch/arm/mach-l7200/include/mach/debug-macro.S
deleted file mode 100644 (file)
index b69ed34..0000000
--- a/arch/arm/mach-l7200/include/mach/debug-macro.S
+++ /dev/null
@@ -1,40 +0,0 @@
-/* arch/arm/mach-l7200/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-               .equ    io_virt, IO_BASE
-               .equ    io_phys, IO_START
-
-               .macro  addruart, rx, tmp
-               mrc     p15, 0, \rx, c1, c0
-               tst     \rx, #1                 @ MMU enabled?
-               moveq   \rx, #io_phys           @ physical base address
-               movne   \rx, #io_virt           @ virtual address
-               add     \rx, \rx, #0x00044000   @ UART1
-@              add     \rx, \rx, #0x00045000   @ UART2
-               .endm
-
-               .macro  senduart,rd,rx
-               str     \rd, [\rx, #0x0]        @ UARTDR
-               .endm
-
-               .macro  waituart,rd,rx
-1001:          ldr     \rd, [\rx, #0x18]       @ UARTFLG
-               tst     \rd, #1 << 5            @ UARTFLGUTXFF - 1 when full
-               bne     1001b
-               .endm
-
-               .macro  busyuart,rd,rx
-1001:          ldr     \rd, [\rx, #0x18]       @ UARTFLG
-               tst     \rd, #1 << 3            @ UARTFLGUBUSY - 1 when busy
-               bne     1001b
-               .endm

diff --git a/arch/arm/mach-l7200/include/mach/entry-macro.S b/arch/arm/mach-l7200/include/mach/entry-macro.S
deleted file mode 100644 (file)
index 1726d91..0000000
--- a/arch/arm/mach-l7200/include/mach/entry-macro.S
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for L7200-based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <mach/hardware.h>
-
-               .equ    irq_base_addr,  IO_BASE_2
-
-               .macro  disable_fiq
-               .endm
-
-               .macro  get_irqnr_preamble, base, tmp
-               .endm
-
-               .macro  arch_ret_to_user, tmp1, tmp2
-               .endm
-
-               .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-               mov     \irqstat, #irq_base_addr                @ Virt addr IRQ regs
-               add     \irqstat, \irqstat, #0x00001000         @ Status reg
-               ldr     \irqstat, [\irqstat, #0]                @ get interrupts
-               mov     \irqnr, #0
-1001:          tst     \irqstat, #1
-               addeq   \irqnr, \irqnr, #1
-               moveq   \irqstat, \irqstat, lsr #1
-               tsteq   \irqnr, #32
-               beq     1001b
-               teq     \irqnr, #32
-               .endm
-

diff --git a/arch/arm/mach-l7200/include/mach/gp_timers.h b/arch/arm/mach-l7200/include/mach/gp_timers.h
deleted file mode 100644 (file)
index 2b7086a..0000000
--- a/arch/arm/mach-l7200/include/mach/gp_timers.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/gp_timers.h
- *
- * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *   07-28-2000        SJH     Created file
- *   08-02-2000        SJH     Used structure for registers
- */
-#ifndef _ASM_ARCH_GPTIMERS_H
-#define _ASM_ARCH_GPTIMERS_H
-
-#include <mach/hardware.h>
-
-/*
- * Layout of L7200 general purpose timer registers
- */
-struct GPT_Regs {
-       unsigned int TIMERLOAD;
-       unsigned int TIMERVALUE;
-       unsigned int TIMERCONTROL;
-       unsigned int TIMERCLEAR;
-};
-
-#define GPT_BASE               (IO_BASE_2 + 0x3000)
-#define l7200_timer1_regs      ((volatile struct GPT_Regs *) (GPT_BASE))
-#define l7200_timer2_regs      ((volatile struct GPT_Regs *) (GPT_BASE + 0x20))
-
-/*
- * General register values
- */
-#define        GPT_PRESCALE_1          0x00000000
-#define        GPT_PRESCALE_16         0x00000004
-#define        GPT_PRESCALE_256        0x00000008
-#define GPT_MODE_FREERUN       0x00000000
-#define GPT_MODE_PERIODIC      0x00000040
-#define GPT_ENABLE             0x00000080
-#define GPT_BZTOG              0x00000100
-#define GPT_BZMOD              0x00000200
-#define GPT_LOAD_MASK          0x0000ffff
-
-#endif

diff --git a/arch/arm/mach-l7200/include/mach/gpio.h b/arch/arm/mach-l7200/include/mach/gpio.h
deleted file mode 100644 (file)
index c7b0a5d..0000000
--- a/arch/arm/mach-l7200/include/mach/gpio.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/****************************************************************************/
-/*
- *      arch/arm/mach-l7200/include/mach/gpio.h
- *
- *      Registers and  helper functions for the L7200 Link-Up Systems
- *      GPIO.
- *
- *      (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License. See the file COPYING in the main directory of this archive for
- *  more details.
- */
-
-/****************************************************************************/
-
-#define GPIO_OFF   0x00005000  /* Offset from IO_START to the GPIO reg's. */
-
-/* IO_START and IO_BASE are defined in hardware.h */
-
-#define GPIO_START (IO_START_2 + GPIO_OFF) /* Physical addr of the GPIO reg. */
-#define GPIO_BASE  (IO_BASE_2  + GPIO_OFF) /* Virtual addr of the GPIO reg. */
-
-/* Offsets from the start of the GPIO for all the registers. */
-#define PADR_OFF     0x000
-#define PADDR_OFF    0x004
-#define PASBSR_OFF   0x008
-#define PAEENR_OFF   0x00c
-#define PAESNR_OFF   0x010
-#define PAESTR_OFF   0x014
-#define PAIMR_OFF    0x018
-#define PAINT_OFF    0x01c
-
-#define PBDR_OFF     0x020
-#define PBDDR_OFF    0x024
-#define PBSBSR_OFF   0x028
-#define PBIMR_OFF    0x038
-#define PBINT_OFF    0x03c
-
-#define PCDR_OFF     0x040
-#define PCDDR_OFF    0x044
-#define PCSBSR_OFF   0x048
-#define PCIMR_OFF    0x058
-#define PCINT_OFF    0x05c
-
-#define PDDR_OFF     0x060
-#define PDDDR_OFF    0x064
-#define PDSBSR_OFF   0x068
-#define PDEENR_OFF   0x06c
-#define PDESNR_OFF   0x070
-#define PDESTR_OFF   0x074
-#define PDIMR_OFF    0x078
-#define PDINT_OFF    0x07c
-
-#define PEDR_OFF     0x080
-#define PEDDR_OFF    0x084
-#define PESBSR_OFF   0x088
-#define PEEENR_OFF   0x08c
-#define PEESNR_OFF   0x090
-#define PEESTR_OFF   0x094
-#define PEIMR_OFF    0x098
-#define PEINT_OFF    0x09c
-
-/* Define the GPIO registers for use by device drivers and the kernel. */
-#define PADR   (*(volatile unsigned long *)(GPIO_BASE+PADR_OFF))
-#define PADDR  (*(volatile unsigned long *)(GPIO_BASE+PADDR_OFF))
-#define PASBSR (*(volatile unsigned long *)(GPIO_BASE+PASBSR_OFF))
-#define PAEENR (*(volatile unsigned long *)(GPIO_BASE+PAEENR_OFF))
-#define PAESNR (*(volatile unsigned long *)(GPIO_BASE+PAESNR_OFF))
-#define PAESTR (*(volatile unsigned long *)(GPIO_BASE+PAESTR_OFF))
-#define PAIMR  (*(volatile unsigned long *)(GPIO_BASE+PAIMR_OFF))
-#define PAINT  (*(volatile unsigned long *)(GPIO_BASE+PAINT_OFF))
-
-#define PBDR   (*(volatile unsigned long *)(GPIO_BASE+PBDR_OFF))
-#define PBDDR  (*(volatile unsigned long *)(GPIO_BASE+PBDDR_OFF))
-#define PBSBSR (*(volatile unsigned long *)(GPIO_BASE+PBSBSR_OFF))
-#define PBIMR  (*(volatile unsigned long *)(GPIO_BASE+PBIMR_OFF))
-#define PBINT  (*(volatile unsigned long *)(GPIO_BASE+PBINT_OFF))
-
-#define PCDR   (*(volatile unsigned long *)(GPIO_BASE+PCDR_OFF))
-#define PCDDR  (*(volatile unsigned long *)(GPIO_BASE+PCDDR_OFF))
-#define PCSBSR (*(volatile unsigned long *)(GPIO_BASE+PCSBSR_OFF))
-#define PCIMR  (*(volatile unsigned long *)(GPIO_BASE+PCIMR_OFF))
-#define PCINT  (*(volatile unsigned long *)(GPIO_BASE+PCINT_OFF))
-
-#define PDDR   (*(volatile unsigned long *)(GPIO_BASE+PDDR_OFF))
-#define PDDDR  (*(volatile unsigned long *)(GPIO_BASE+PDDDR_OFF))
-#define PDSBSR (*(volatile unsigned long *)(GPIO_BASE+PDSBSR_OFF))
-#define PDEENR (*(volatile unsigned long *)(GPIO_BASE+PDEENR_OFF))
-#define PDESNR (*(volatile unsigned long *)(GPIO_BASE+PDESNR_OFF))
-#define PDESTR (*(volatile unsigned long *)(GPIO_BASE+PDESTR_OFF))
-#define PDIMR  (*(volatile unsigned long *)(GPIO_BASE+PDIMR_OFF))
-#define PDINT  (*(volatile unsigned long *)(GPIO_BASE+PDINT_OFF))
-
-#define PEDR   (*(volatile unsigned long *)(GPIO_BASE+PEDR_OFF))
-#define PEDDR  (*(volatile unsigned long *)(GPIO_BASE+PEDDR_OFF))
-#define PESBSR (*(volatile unsigned long *)(GPIO_BASE+PESBSR_OFF))
-#define PEEENR (*(volatile unsigned long *)(GPIO_BASE+PEEENR_OFF))
-#define PEESNR (*(volatile unsigned long *)(GPIO_BASE+PEESNR_OFF))
-#define PEESTR (*(volatile unsigned long *)(GPIO_BASE+PEESTR_OFF))
-#define PEIMR  (*(volatile unsigned long *)(GPIO_BASE+PEIMR_OFF))
-#define PEINT  (*(volatile unsigned long *)(GPIO_BASE+PEINT_OFF))
-
-#define VEE_EN         0x02
-#define BACKLIGHT_EN   0x04

diff --git a/arch/arm/mach-l7200/include/mach/hardware.h b/arch/arm/mach-l7200/include/mach/hardware.h
deleted file mode 100644 (file)
index c31909c..0000000
--- a/arch/arm/mach-l7200/include/mach/hardware.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/hardware.h
- *
- * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
- *                    Steve Hill (sjhill@cotw.com)
- *
- * This file contains the hardware definitions for the 
- * LinkUp Systems L7200 SOC development board.
- *
- * Changelog:
- *   02-01-2000         RS     Created L7200 version, derived from rpc code
- *   03-21-2000        SJH     Cleaned up file
- *   04-21-2000         RS     Changed mapping of I/O in virtual space
- *   04-25-2000        SJH     Removed unused symbols and such
- *   05-05-2000        SJH     Complete rewrite
- *   07-31-2000        SJH     Added undocumented debug auxillary port to
- *                     get at last two columns for keyboard driver
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-/* Hardware addresses of major areas.
- *  *_START is the physical address
- *  *_SIZE  is the size of the region
- *  *_BASE  is the virtual address
- */
-#define RAM_START              0xf0000000
-#define RAM_SIZE               0x02000000
-#define RAM_BASE               0xc0000000
-
-#define IO_START               0x80000000      /* I/O */
-#define IO_SIZE                        0x01000000
-#define IO_BASE                        0xd0000000
-
-#define IO_START_2             0x90000000      /* I/O */
-#define IO_SIZE_2              0x01000000
-#define IO_BASE_2              0xd1000000
-
-#define AUX_START              0x1a000000      /* AUX PORT */
-#define AUX_SIZE               0x01000000
-#define AUX_BASE               0xd2000000
-
-#define FLASH1_START           0x00000000      /* FLASH BANK 1 */
-#define FLASH1_SIZE            0x01000000
-#define FLASH1_BASE            0xd3000000
-
-#define FLASH2_START           0x10000000      /* FLASH BANK 2 */
-#define FLASH2_SIZE            0x01000000
-#define FLASH2_BASE            0xd4000000
-
-#define ISA_START              0x20000000      /* ISA */
-#define ISA_SIZE               0x20000000
-#define ISA_BASE               0xe0000000
-
-#define PCIO_BASE              IO_BASE
-
-#endif

diff --git a/arch/arm/mach-l7200/include/mach/io.h b/arch/arm/mach-l7200/include/mach/io.h
deleted file mode 100644 (file)
index a770a89..0000000
--- a/arch/arm/mach-l7200/include/mach/io.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/io.h
- *
- * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *  03-21-2000 SJH     Created from arch/arm/mach-nexuspci/include/mach/io.h
- *  08-31-2000 SJH     Added in IO functions necessary for new drivers
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * There are not real ISA nor PCI buses, so we fake it.
- */
-#define __io(a)                __typesafe_io(a)
-#define __mem_pci(a)   (a)
-
-#endif

diff --git a/arch/arm/mach-l7200/include/mach/irqs.h b/arch/arm/mach-l7200/include/mach/irqs.h
deleted file mode 100644 (file)
index 7edffd7..0000000
--- a/arch/arm/mach-l7200/include/mach/irqs.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/irqs.h
- *
- * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
- *                    Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *   01-02-2000 RS     Create l7200 version
- *   03-28-2000 SJH    Removed unused interrupt
- *   07-28-2000 SJH    Added pseudo-keyboard interrupt
- */
-
-/*
- * NOTE: The second timer (Timer 2) is used as the keyboard
- *       interrupt when the keyboard driver is enabled.
- */
-
-#define NR_IRQS          32
-
-#define IRQ_STWDOG        0   /* Watchdog timer */
-#define IRQ_PROG          1   /* Programmable interrupt */
-#define IRQ_DEBUG_RX      2   /* Comm Rx debug */
-#define IRQ_DEBUG_TX      3   /* Comm Tx debug */
-#define IRQ_GCTC1         4   /* Timer 1 */
-#define IRQ_GCTC2         5   /* Timer 2 / Keyboard */
-#define IRQ_DMA           6   /* DMA controller */
-#define IRQ_CLCD          7   /* Color LCD controller */
-#define IRQ_SM_RX         8   /* Smart card */
-#define IRQ_SM_TX         9   /* Smart cart */
-#define IRQ_SM_RST       10   /* Smart card */
-#define IRQ_SIB          11   /* Serial Interface Bus */
-#define IRQ_MMC          12   /* MultiMediaCard */
-#define IRQ_SSP1         13   /* Synchronous Serial Port 1 */
-#define IRQ_SSP2         14   /* Synchronous Serial Port 1 */
-#define IRQ_SPI          15   /* SPI slave */
-#define IRQ_UART_1       16   /* UART 1 */
-#define IRQ_UART_2       17   /* UART 2 */
-#define IRQ_IRDA         18   /* IRDA */
-#define IRQ_RTC_TICK     19   /* Real Time Clock tick */
-#define IRQ_RTC_ALARM    20   /* Real Time Clock alarm */
-#define IRQ_GPIO         21   /* General Purpose IO */
-#define IRQ_GPIO_DMA     22   /* General Purpose IO, DMA */
-#define IRQ_M2M          23   /* Memory to memory DMA  */
-#define IRQ_RESERVED     24   /* RESERVED, don't use */
-#define IRQ_INTF         25   /* External active low interrupt */
-#define IRQ_INT0         26   /* External active low interrupt */
-#define IRQ_INT1         27   /* External active low interrupt */
-#define IRQ_INT2         28   /* External active low interrupt */
-#define IRQ_UCB1200      29   /* Interrupt generated by UCB1200*/
-#define IRQ_BAT_LO       30   /* Low batery or external power */
-#define IRQ_MEDIA_CHG    31   /* Media change interrupt */
-
-/*
- * This is the offset of the FIQ "IRQ" numbers
- */
-#define FIQ_START      64

diff --git a/arch/arm/mach-l7200/include/mach/memory.h b/arch/arm/mach-l7200/include/mach/memory.h
deleted file mode 100644 (file)
index 9fb40ed..0000000
--- a/arch/arm/mach-l7200/include/mach/memory.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/memory.h
- *
- * Copyright (c) 2000 Steve Hill (sjhill@cotw.com)
- * Copyright (c) 2000 Rob Scott (rscott@mtrob.fdns.net)
- *
- * Changelog:
- *  03-13-2000 SJH     Created
- *  04-13-2000  RS      Changed bus macros for new addr
- *  05-03-2000  SJH     Removed bus macros and fixed virt_to_phys macro
- */
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/*
- * Physical DRAM offset on the L7200 SDB.
- */
-#define PHYS_OFFSET     UL(0xf0000000)
-
-/*
- * Cache flushing area - ROM
- */
-#define FLUSH_BASE_PHYS                0x40000000
-#define FLUSH_BASE             0xdf000000
-
-#endif

diff --git a/arch/arm/mach-l7200/include/mach/pmpcon.h b/arch/arm/mach-l7200/include/mach/pmpcon.h
deleted file mode 100644 (file)
index 3959871..0000000
--- a/arch/arm/mach-l7200/include/mach/pmpcon.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/****************************************************************************/
-/*
- *  arch/arm/mach-l7200/include/mach/pmpcon.h
- *
- *   Registers and  helper functions for the L7200 Link-Up Systems
- *   DC/DC converter register.
- *
- *   (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License. See the file COPYING in the main directory of this archive for
- *  more details.
- */
-
-/****************************************************************************/
-
-#define PMPCON_OFF 0x00006000  /* Offset from IO_START_2. */
-
-/* IO_START_2 and IO_BASE_2 are defined in hardware.h */
-
-#define PMPCON_START (IO_START_2 + PMPCON_OFF)  /* Physical address of reg. */
-#define PMPCON_BASE  (IO_BASE_2  + PMPCON_OFF)  /* Virtual address of reg. */
-
-
-#define PMPCON (*(volatile unsigned int *)(PMPCON_BASE))
-
-#define PWM2_50CYCLE 0x800
-#define CONTRAST     0x9
-
-#define PWM1H (CONTRAST)
-#define PWM1L (CONTRAST << 4)
-
-#define PMPCON_VALUE  (PWM2_50CYCLE | PWM1L | PWM1H) 
-       
-/* PMPCON = 0x811;   // too light and fuzzy
- * PMPCON = 0x844;   
- * PMPCON = 0x866;   // better color poor depth
- * PMPCON = 0x888;   // Darker but better depth 
- * PMPCON = 0x899;   // Darker even better depth
- * PMPCON = 0x8aa;   // too dark even better depth
- * PMPCON = 0X8cc;   // Way too dark
- */
-
-/* As CONTRAST value increases the greater the depth perception and
- * the darker the colors.
- */

diff --git a/arch/arm/mach-l7200/include/mach/pmu.h b/arch/arm/mach-l7200/include/mach/pmu.h
deleted file mode 100644 (file)
index a2da7ae..0000000
--- a/arch/arm/mach-l7200/include/mach/pmu.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/****************************************************************************/
-/*
- *  arch/arm/mach-l7200/include/mach/pmu.h
- *
- *   Registers and  helper functions for the L7200 Link-Up Systems
- *   Power Management Unit (PMU).
- *
- *   (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License. See the file COPYING in the main directory of this archive for
- *  more details.
- */
-
-/****************************************************************************/
-
-#define PMU_OFF   0x00050000  /* Offset from IO_START to the PMU registers. */
-
-/* IO_START and IO_BASE are defined in hardware.h */
-
-#define PMU_START (IO_START + PMU_OFF)  /* Physical addr. of the PMU reg. */
-#define PMU_BASE  (IO_BASE  + PMU_OFF)  /* Virtual addr. of the PMU reg. */
-
-
-/* Define the PMU registers for use by device drivers and the kernel. */
-
-typedef struct {
-     unsigned int CURRENT;  /* Current configuration register */
-     unsigned int NEXT;     /* Next configuration register */
-     unsigned int reserved;
-     unsigned int RUN;      /* Run configuration register */
-     unsigned int COMM;     /* Configuration command register */
-     unsigned int SDRAM;    /* SDRAM configuration bypass register */
-} pmu_interface;
-
-#define PMU ((volatile pmu_interface *)(PMU_BASE))
-
-
-/* Macro's for reading the common register fields. */
-
-#define GET_TRANSOP(reg)  ((reg >> 25) & 0x03) /* Bits 26-25 */
-#define GET_OSCEN(reg)    ((reg >> 16) & 0x01)
-#define GET_OSCMUX(reg)   ((reg >> 15) & 0x01)
-#define GET_PLLMUL(reg)   ((reg >>  9) & 0x3f) /* Bits 14-9 */
-#define GET_PLLEN(reg)    ((reg >>  8) & 0x01)
-#define GET_PLLMUX(reg)   ((reg >>  7) & 0x01)
-#define GET_BCLK_DIV(reg) ((reg >>  3) & 0x03) /* Bits 4-3 */
-#define GET_SDRB_SEL(reg) ((reg >>  2) & 0x01)
-#define GET_SDRF_SEL(reg) ((reg >>  1) & 0x01)
-#define GET_FASTBUS(reg)  (reg & 0x1)
-
-/* CFG_NEXT register */
-
-#define CFG_NEXT_CLOCKRECOVERY ((PMU->NEXT >> 18) & 0x7f)   /* Bits 24-18 */
-#define CFG_NEXT_INTRET        ((PMU->NEXT >> 17) & 0x01)
-#define CFG_NEXT_SDR_STOP      ((PMU->NEXT >>  6) & 0x01)
-#define CFG_NEXT_SYSCLKEN      ((PMU->NEXT >>  5) & 0x01)
-
-/* Useful field values that can be used to construct the
- * CFG_NEXT and CFG_RUN registers.
- */
-
-#define TRANSOP_NOP      0<<25  /* NOCHANGE_NOSTALL */
-#define NOCHANGE_STALL   1<<25
-#define CHANGE_NOSTALL   2<<25
-#define CHANGE_STALL     3<<25
-
-#define INTRET           1<<17
-#define OSCEN            1<<16
-#define OSCMUX           1<<15
-
-/* PLL frequencies */
-
-#define PLLMUL_0         0<<9         /*  3.6864 MHz */
-#define PLLMUL_1         1<<9         /*  ?????? MHz */
-#define PLLMUL_5         5<<9         /*  18.432 MHz */
-#define PLLMUL_10       10<<9         /*  36.864 MHz */
-#define PLLMUL_18       18<<9         /*  ?????? MHz */
-#define PLLMUL_20       20<<9         /*  73.728 MHz */
-#define PLLMUL_32       32<<9         /*  ?????? MHz */
-#define PLLMUL_35       35<<9         /* 129.024 MHz */
-#define PLLMUL_36       36<<9         /*  ?????? MHz */
-#define PLLMUL_39       39<<9         /*  ?????? MHz */
-#define PLLMUL_40       40<<9         /* 147.456 MHz */
-
-/* Clock recovery times */
-
-#define CRCLOCK_1        1<<18
-#define CRCLOCK_2        2<<18
-#define CRCLOCK_4        4<<18
-#define CRCLOCK_8        8<<18
-#define CRCLOCK_16      16<<18
-#define CRCLOCK_32      32<<18
-#define CRCLOCK_63      63<<18
-#define CRCLOCK_127    127<<18
-
-#define PLLEN            1<<8
-#define PLLMUX           1<<7
-#define SDR_STOP         1<<6
-#define SYSCLKEN         1<<5
-
-#define BCLK_DIV_4       2<<3
-#define BCLK_DIV_2       1<<3
-#define BCLK_DIV_1       0<<3
-
-#define SDRB_SEL         1<<2
-#define SDRF_SEL         1<<1
-#define FASTBUS          1<<0
-
-
-/* CFG_SDRAM */
-
-#define SDRREFFQ         1<<0  /* Only if SDRSTOPRQ is not set. */
-#define SDRREFACK        1<<1  /* Read-only */
-#define SDRSTOPRQ        1<<2  /* Only if SDRREFFQ is not set. */
-#define SDRSTOPACK       1<<3  /* Read-only */
-#define PICEN            1<<4  /* Enable Co-procesor */
-#define PICTEST          1<<5
-
-#define GET_SDRREFFQ    ((PMU->SDRAM >> 0) & 0x01)
-#define GET_SDRREFACK   ((PMU->SDRAM >> 1) & 0x01) /* Read-only */
-#define GET_SDRSTOPRQ   ((PMU->SDRAM >> 2) & 0x01)
-#define GET_SDRSTOPACK  ((PMU->SDRAM >> 3) & 0x01) /* Read-only */
-#define GET_PICEN       ((PMU->SDRAM >> 4) & 0x01)
-#define GET_PICTEST     ((PMU->SDRAM >> 5) & 0x01)

diff --git a/arch/arm/mach-l7200/include/mach/serial.h b/arch/arm/mach-l7200/include/mach/serial.h
deleted file mode 100644 (file)
index adc05e5..0000000
--- a/arch/arm/mach-l7200/include/mach/serial.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/serial.h
- *
- * Copyright (c) 2000 Rob Scott (rscott@mtrob.fdns.net)
- *                    Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *  03-20-2000  SJH     Created
- *  03-26-2000  SJH     Added flags for serial ports
- *  03-27-2000  SJH     Corrected BASE_BAUD value
- *  04-14-2000  RS      Made register addr dependent on IO_BASE
- *  05-03-2000  SJH     Complete rewrite
- *  05-09-2000 SJH     Stripped out architecture specific serial stuff
- *                      and placed it in a separate file
- *  07-28-2000 SJH     Moved base baud rate variable
- */
-#ifndef __ASM_ARCH_SERIAL_H
-#define __ASM_ARCH_SERIAL_H
-
-/*
- * This assumes you have a 3.6864 MHz clock for your UART.
- */
-#define BASE_BAUD      3686400
-
-/*
- * Standard COM flags
- */
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
-
-#define STD_SERIAL_PORT_DEFNS          \
-       /* MAGIC UART CLK   PORT       IRQ     FLAGS */                 \
-       { 0, BASE_BAUD, UART1_BASE, IRQ_UART_1, STD_COM_FLAGS },  /* ttyLU0 */ \
-       { 0, BASE_BAUD, UART2_BASE, IRQ_UART_2, STD_COM_FLAGS },  /* ttyLU1 */ \
-
-#define EXTRA_SERIAL_PORT_DEFNS
-
-#endif

diff --git a/arch/arm/mach-l7200/include/mach/serial_l7200.h b/arch/arm/mach-l7200/include/mach/serial_l7200.h
deleted file mode 100644 (file)
index 645f1c5..0000000
--- a/arch/arm/mach-l7200/include/mach/serial_l7200.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/serial_l7200.h
- *
- * Copyright (c) 2000 Steven Hill (sjhill@cotw.com)
- *
- * Changelog:
- *  05-09-2000 SJH     Created
- */
-#ifndef __ASM_ARCH_SERIAL_L7200_H
-#define __ASM_ARCH_SERIAL_L7200_H
-
-#include <mach/memory.h>
-
-/*
- * This assumes you have a 3.6864 MHz clock for your UART.
- */
-#define BASE_BAUD 3686400
-
-/*
- * UART base register addresses
- */
-#define UART1_BASE     (IO_BASE + 0x00044000)
-#define UART2_BASE     (IO_BASE + 0x00045000)
-
-/*
- * UART register offsets
- */
-#define UARTDR                 0x00    /* Tx/Rx data */
-#define RXSTAT                 0x04    /* Rx status */
-#define H_UBRLCR               0x08    /* mode register high */
-#define M_UBRLCR               0x0C    /* mode reg mid (MSB of baud)*/
-#define L_UBRLCR               0x10    /* mode reg low (LSB of baud)*/
-#define UARTCON                        0x14    /* control register */
-#define UARTFLG                        0x18    /* flag register */
-#define UARTINTSTAT            0x1C    /* FIFO IRQ status register */
-#define UARTINTMASK            0x20    /* FIFO IRQ mask register */
-
-/*
- * UART baud rate register values
- */
-#define BR_110                 0x827
-#define BR_1200                        0x06e
-#define BR_2400                        0x05f
-#define BR_4800                        0x02f
-#define BR_9600                        0x017
-#define BR_14400               0x00f
-#define BR_19200               0x00b
-#define BR_38400               0x005
-#define BR_57600               0x003
-#define BR_76800               0x002
-#define BR_115200              0x001
-
-/*
- * Receiver status register (RXSTAT) mask values
- */
-#define RXSTAT_NO_ERR          0x00    /* No error */
-#define RXSTAT_FRM_ERR         0x01    /* Framing error */
-#define RXSTAT_PAR_ERR         0x02    /* Parity error */
-#define RXSTAT_OVR_ERR         0x04    /* Overrun error */
-
-/*
- * High byte of UART bit rate and line control register (H_UBRLCR) values
- */
-#define UBRLCR_BRK             0x01    /* generate break on tx */
-#define UBRLCR_PEN             0x02    /* enable parity */
-#define UBRLCR_PDIS            0x00    /* disable parity */
-#define UBRLCR_EVEN            0x04    /* 1= even parity,0 = odd parity */
-#define UBRLCR_STP2            0x08    /* transmit 2 stop bits */
-#define UBRLCR_FIFO            0x10    /* enable FIFO */
-#define UBRLCR_LEN5            0x60    /* word length5 */
-#define UBRLCR_LEN6            0x40    /* word length6 */
-#define UBRLCR_LEN7            0x20    /* word length7 */
-#define UBRLCR_LEN8            0x00    /* word length8 */
-
-/*
- * UART control register (UARTCON) values
- */
-#define UARTCON_UARTEN         0x01    /* Enable UART */
-#define UARTCON_DMAONERR       0x08    /* Mask RxDmaRq when errors occur */
-
-/*
- * UART flag register (UARTFLG) mask values
- */
-#define UARTFLG_UTXFF          0x20    /* Transmit FIFO full */
-#define UARTFLG_URXFE          0x10    /* Receiver FIFO empty */
-#define UARTFLG_UBUSY          0x08    /* Transmitter busy */
-#define UARTFLG_DCD            0x04    /* Data carrier detect */
-#define UARTFLG_DSR            0x02    /* Data set ready */
-#define UARTFLG_CTS            0x01    /* Clear to send */
-
-/*
- * UART interrupt status/clear registers (UARTINTSTAT/CLR) values
- */
-#define UART_TXINT             0x01    /* TX interrupt */
-#define UART_RXINT             0x02    /* RX interrupt */
-#define UART_RXERRINT          0x04    /* RX error interrupt */
-#define UART_MSINT             0x08    /* Modem Status interrupt */
-#define UART_UDINT             0x10    /* UART Disabled interrupt */
-#define UART_ALLIRQS           0x1f    /* All interrupts */
-
-#endif

diff --git a/arch/arm/mach-l7200/include/mach/sib.h b/arch/arm/mach-l7200/include/mach/sib.h
deleted file mode 100644 (file)
index 9657287..0000000
--- a/arch/arm/mach-l7200/include/mach/sib.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/****************************************************************************/
-/*
- *  arch/arm/mach-l7200/include/mach/sib.h
- *
- *  Registers and helper functions for the Serial Interface Bus.
- *
- *  (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License. See the file COPYING in the main directory of this archive for
- *  more details.
- */
-
-/****************************************************************************/
-
-#define SIB_OFF   0x00040000  /* Offset from IO_START to the SIB reg's. */
-
-/* IO_START and IO_BASE are defined in hardware.h */
-
-#define SIB_START (IO_START + SIB_OFF) /* Physical addr of the SIB reg. */
-#define SIB_BASE  (IO_BASE  + SIB_OFF) /* Virtual addr of the SIB reg.  */
-
-/* Offsets from the start of the SIB for all the registers. */
-
-/* Define the SIB registers for use by device drivers and the kernel. */
-
-typedef struct
-{
-     unsigned int MCCR;    /* SIB Control Register           Offset: 0x00 */
-     unsigned int RES1;    /* Reserved                       Offset: 0x04 */
-     unsigned int MCDR0;   /* SIB Data Register 0            Offset: 0x08 */
-     unsigned int MCDR1;   /* SIB Data Register 1            Offset: 0x0c */
-     unsigned int MCDR2;   /* SIB Data Register 2 (UCB1x00)  Offset: 0x10 */
-     unsigned int RES2;    /* Reserved                       Offset: 0x14 */
-     unsigned int MCSR;    /* SIB Status Register            Offset: 0x18 */
-} SIB_Interface;
-
-#define SIB ((volatile SIB_Interface *) (SIB_BASE))
-
-/* MCCR */
-
-#define INTERNAL_FREQ   9216000  /* Hertz */
-#define AUDIO_FREQ         5000  /* Hertz */
-#define TELECOM_FREQ       5000  /* Hertz */
-
-#define AUDIO_DIVIDE    (INTERNAL_FREQ / (32 * AUDIO_FREQ))
-#define TELECOM_DIVIDE  (INTERNAL_FREQ / (32 * TELECOM_FREQ))
-
-#define MCCR_ASD57      AUDIO_DIVIDE
-#define MCCR_TSD57      (TELECOM_DIVIDE << 8)
-#define MCCR_MCE        (1 << 16)             /* SIB enable */
-#define MCCR_ECS        (1 << 17)             /* External Clock Select */
-#define MCCR_ADM        (1 << 18)             /* A/D Data Sampling */
-#define MCCR_PMC        (1 << 26)             /* PIN Multiplexer Control */
-
-
-#define GET_ASD ((SIB->MCCR >>  0) & 0x3f) /* Audio Sample Rate Div. */
-#define GET_TSD ((SIB->MCCR >>  8) & 0x3f) /* Telcom Sample Rate Div. */
-#define GET_MCE ((SIB->MCCR >> 16) & 0x01) /* SIB Enable */
-#define GET_ECS ((SIB->MCCR >> 17) & 0x01) /* External Clock Select */
-#define GET_ADM ((SIB->MCCR >> 18) & 0x01) /* A/D Data Sampling Mode */
-#define GET_TTM ((SIB->MCCR >> 19) & 0x01) /* Telco Trans. FIFO I mask */ 
-#define GET_TRM ((SIB->MCCR >> 20) & 0x01) /* Telco Recv. FIFO I mask */
-#define GET_ATM ((SIB->MCCR >> 21) & 0x01) /* Audio Trans. FIFO I mask */ 
-#define GET_ARM ((SIB->MCCR >> 22) & 0x01) /* Audio Recv. FIFO I mask */
-#define GET_LBM ((SIB->MCCR >> 23) & 0x01) /* Loop Back Mode */
-#define GET_ECP ((SIB->MCCR >> 24) & 0x03) /* Extern. Clck Prescale sel */
-#define GET_PMC ((SIB->MCCR >> 26) & 0x01) /* PIN Multiplexer Control */
-#define GET_ERI ((SIB->MCCR >> 27) & 0x01) /* External Read Interrupt */
-#define GET_EWI ((SIB->MCCR >> 28) & 0x01) /* External Write Interrupt */
-
-/* MCDR0 */
-
-#define AUDIO_RECV     ((SIB->MCDR0 >> 4) & 0xfff)
-#define AUDIO_WRITE(v) ((SIB->MCDR0 = (v & 0xfff) << 4))
-
-/* MCDR1 */
-
-#define TELECOM_RECV     ((SIB->MCDR1 >> 2) & 032fff)
-#define TELECOM_WRITE(v) ((SIB->MCDR1 = (v & 0x3fff) << 2))
-
-
-/* MCSR */
-
-#define MCSR_ATU (1 << 4)  /* Audio Transmit FIFO Underrun */
-#define MCSR_ARO (1 << 5)  /* Audio Receive  FIFO Underrun */
-#define MCSR_TTU (1 << 6)  /* TELECOM Transmit FIFO Underrun */
-#define MCSR_TRO (1 << 7)  /* TELECOM Receive  FIFO Underrun */
-
-#define MCSR_CLEAR_UNDERUN_BITS (MCSR_ATU | MCSR_ARO | MCSR_TTU | MCSR_TRO)
-
-
-#define GET_ATS ((SIB->MCSR >>  0) & 0x01) /* Audio Transmit FIFO Service Req*/
-#define GET_ARS ((SIB->MCSR >>  1) & 0x01) /* Audio Recv FIFO Service Request*/
-#define GET_TTS ((SIB->MCSR >>  2) & 0x01) /* TELECOM Transmit FIFO  Flag */
-#define GET_TRS ((SIB->MCSR >>  3) & 0x01) /* TELECOM Recv FIFO Service Req. */
-#define GET_ATU ((SIB->MCSR >>  4) & 0x01) /* Audio Transmit FIFO Underrun */
-#define GET_ARO ((SIB->MCSR >>  5) & 0x01) /* Audio Receive  FIFO Underrun */
-#define GET_TTU ((SIB->MCSR >>  6) & 0x01) /* TELECOM Transmit FIFO Underrun */
-#define GET_TRO ((SIB->MCSR >>  7) & 0x01) /* TELECOM Receive  FIFO Underrun */
-#define GET_ANF ((SIB->MCSR >>  8) & 0x01) /* Audio Transmit FIFO not full */
-#define GET_ANE ((SIB->MCSR >>  9) & 0x01) /* Audio Receive FIFO not empty */
-#define GET_TNF ((SIB->MCSR >> 10) & 0x01) /* Telecom Transmit FIFO not full */
-#define GET_TNE ((SIB->MCSR >> 11) & 0x01) /* Telecom Receive FIFO not empty */
-#define GET_CWC ((SIB->MCSR >> 12) & 0x01) /* Codec Write Complete */
-#define GET_CRC ((SIB->MCSR >> 13) & 0x01) /* Codec Read Complete */
-#define GET_ACE ((SIB->MCSR >> 14) & 0x01) /* Audio Codec Enabled */
-#define GET_TCE ((SIB->MCSR >> 15) & 0x01) /* Telecom Codec Enabled */
-
-/* MCDR2 */
-
-#define MCDR2_rW               (1 << 16)
-
-#define WRITE_MCDR2(reg, data) (SIB->MCDR2 =((reg<<17)|MCDR2_rW|(data&0xffff)))
-#define MCDR2_WRITE_COMPLETE   GET_CWC
-
-#define INITIATE_MCDR2_READ(reg) (SIB->MCDR2 = (reg << 17))
-#define MCDR2_READ_COMPLETE      GET_CRC
-#define MCDR2_READ               (SIB->MCDR2 & 0xffff)

diff --git a/arch/arm/mach-l7200/include/mach/sys-clock.h b/arch/arm/mach-l7200/include/mach/sys-clock.h
deleted file mode 100644 (file)
index e9729a3..0000000
--- a/arch/arm/mach-l7200/include/mach/sys-clock.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/****************************************************************************/
-/*
- *  arch/arm/mach-l7200/include/mach/sys-clock.h
- *
- *   Registers and  helper functions for the L7200 Link-Up Systems
- *   System clocks.
- *
- *   (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License. See the file COPYING in the main directory of this archive for
- *  more details.
- */
-
-/****************************************************************************/
-
-#define SYS_CLOCK_OFF   0x00050030  /* Offset from IO_START. */
-
-/* IO_START and IO_BASE are defined in hardware.h */
-
-#define SYS_CLOCK_START (IO_START + SYS_CLOCK_OFF)  /* Physical address */
-#define SYS_CLOCK_BASE  (IO_BASE  + SYS_CLOCK_OFF)  /* Virtual address  */
-
-/* Define the interface to the SYS_CLOCK */
-
-typedef struct
-{
-     unsigned int ENABLE;
-     unsigned int ESYNC;
-     unsigned int SELECT;
-} sys_clock_interface;
-
-#define SYS_CLOCK   ((volatile sys_clock_interface *)(SYS_CLOCK_BASE))
-
-//#define CLOCK_EN    (*(volatile unsigned long *)(PMU_BASE+CLOCK_EN_OFF))
-//#define CLOCK_ESYNC (*(volatile unsigned long *)(PMU_BASE+CLOCK_ESYNC_OFF))
-//#define CLOCK_SEL   (*(volatile unsigned long *)(PMU_BASE+CLOCK_SEL_OFF))
-
-/* SYS_CLOCK -> ENABLE */
-
-#define SYN_EN          1<<0
-#define B18M_EN         1<<1
-#define CLK3M6_EN       1<<2
-#define BUART_EN        1<<3
-#define CLK18MU_EN      1<<4
-#define FIR_EN          1<<5
-#define MIRN_EN         1<<6
-#define UARTM_EN        1<<7
-#define SIBADC_EN       1<<8
-#define ALTD_EN         1<<9
-#define CLCLK_EN        1<<10
-
-/* SYS_CLOCK -> SELECT */
-
-#define CLK18M_DIV      1<<0
-#define MIR_SEL         1<<1
-#define SSP_SEL         1<<4
-#define MM_DIV          1<<5
-#define MM_SEL          1<<6
-#define ADC_SEL_2       0<<7
-#define ADC_SEL_4       1<<7
-#define ADC_SEL_8       3<<7
-#define ADC_SEL_16      7<<7
-#define ADC_SEL_32      0x0f<<7
-#define ADC_SEL_64      0x1f<<7
-#define ADC_SEL_128     0x3f<<7
-#define ALTD_SEL        1<<13

diff --git a/arch/arm/mach-l7200/include/mach/system.h b/arch/arm/mach-l7200/include/mach/system.h
deleted file mode 100644 (file)
index e0dd3b6..0000000
--- a/arch/arm/mach-l7200/include/mach/system.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/system.h
- *
- * Copyright (c) 2000 Steve Hill (sjhill@cotw.com)
- *
- * Changelog
- *  03-21-2000  SJH    Created
- *  04-26-2000  SJH    Fixed functions
- *  05-03-2000  SJH    Removed usage of obsolete 'iomd.h'
- *  05-31-2000  SJH    Properly implemented 'arch_idle'
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <mach/hardware.h>
-
-static inline void arch_idle(void)
-{
-       *(unsigned long *)(IO_BASE + 0x50004) = 1;      /* idle mode */
-}
-
-static inline void arch_reset(char mode, const char *cmd)
-{
-       if (mode == 's') {
-               cpu_reset(0);
-       }
-}
-
-#endif

diff --git a/arch/arm/mach-l7200/include/mach/time.h b/arch/arm/mach-l7200/include/mach/time.h
deleted file mode 100644 (file)
index 061771c..0000000
--- a/arch/arm/mach-l7200/include/mach/time.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/time.h
- *
- * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
- *                    Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *   01-02-2000        RS      Created l7200 version, derived from rpc code
- *   05-03-2000        SJH     Complete rewrite
- */
-#ifndef _ASM_ARCH_TIME_H
-#define _ASM_ARCH_TIME_H
-
-#include <mach/irqs.h>
-
-/*
- * RTC base register address
- */
-#define RTC_BASE       (IO_BASE_2 + 0x2000)
-
-/*
- * RTC registers
- */
-#define RTC_RTCDR      (*(volatile unsigned char *) (RTC_BASE + 0x000))
-#define RTC_RTCMR      (*(volatile unsigned char *) (RTC_BASE + 0x004))
-#define RTC_RTCS       (*(volatile unsigned char *) (RTC_BASE + 0x008))
-#define RTC_RTCC       (*(volatile unsigned char *) (RTC_BASE + 0x008))
-#define RTC_RTCDV      (*(volatile unsigned char *) (RTC_BASE + 0x00c))
-#define RTC_RTCCR      (*(volatile unsigned char *) (RTC_BASE + 0x010))
-
-/*
- * RTCCR register values
- */
-#define RTC_RATE_32    0x00      /* 32 Hz tick */
-#define RTC_RATE_64    0x10      /* 64 Hz tick */
-#define RTC_RATE_128   0x20      /* 128 Hz tick */
-#define RTC_RATE_256   0x30      /* 256 Hz tick */
-#define RTC_EN_ALARM   0x01      /* Enable alarm */
-#define RTC_EN_TIC     0x04      /* Enable counter */
-#define RTC_EN_STWDOG  0x08      /* Enable watchdog */
-
-/*
- * Handler for RTC timer interrupt
- */
-static irqreturn_t
-timer_interrupt(int irq, void *dev_id)
-{
-       struct pt_regs *regs = get_irq_regs();
-       do_timer(1);
-#ifndef CONFIG_SMP
-       update_process_times(user_mode(regs));
-#endif
-       do_profile(regs);
-       RTC_RTCC = 0;                           /* Clear interrupt */
-
-       return IRQ_HANDLED;
-}
-
-/*
- * Set up RTC timer interrupt, and return the current time in seconds.
- */
-void __init time_init(void)
-{
-       RTC_RTCC = 0;                           /* Clear interrupt */
-
-       timer_irq.handler = timer_interrupt;
-
-       setup_irq(IRQ_RTC_TICK, &timer_irq);
-
-       RTC_RTCCR = RTC_RATE_128 | RTC_EN_TIC;  /* Set rate and enable timer */
-}
-
-#endif

diff --git a/arch/arm/mach-l7200/include/mach/timex.h b/arch/arm/mach-l7200/include/mach/timex.h
deleted file mode 100644 (file)
index ffc96a6..0000000
--- a/arch/arm/mach-l7200/include/mach/timex.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/timex.h
- *
- * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
- *                    Steve Hill (sjhill@cotw.com)
- *
- * 04-21-2000  RS Created file
- * 05-03-2000 SJH Tick rate was wrong
- *
- */
-
-/*
- * On the ARM720T, clock ticks are set to 128 Hz.
- *
- * NOTE: The actual RTC value is set in 'time.h' which
- *       must be changed when choosing a different tick
- *       rate. The value of HZ in 'param.h' must also
- *       be changed to match below.
- */
-#define CLOCK_TICK_RATE                128

diff --git a/arch/arm/mach-l7200/include/mach/uncompress.h b/arch/arm/mach-l7200/include/mach/uncompress.h
deleted file mode 100644 (file)
index 591c962..0000000
--- a/arch/arm/mach-l7200/include/mach/uncompress.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/uncompress.h
- *
- * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *  05-01-2000 SJH     Created
- *  05-13-2000 SJH     Filled in function bodies
- *  07-26-2000 SJH     Removed hard coded baud rate
- */
-
-#include <mach/hardware.h>
-
-#define IO_UART  IO_START + 0x00044000
-
-#define __raw_writeb(v,p)      (*(volatile unsigned char *)(p) = (v))
-#define __raw_readb(p)         (*(volatile unsigned char *)(p))
-
-static inline void putc(int c)
-{
-       while(__raw_readb(IO_UART + 0x18) & 0x20 ||
-             __raw_readb(IO_UART + 0x18) & 0x08)
-               barrier();
-
-       __raw_writeb(c, IO_UART + 0x00);
-}
-
-static inline void flush(void)
-{
-}
-
-static __inline__ void arch_decomp_setup(void)
-{
-       __raw_writeb(0x00, IO_UART + 0x08);     /* Set HSB */
-       __raw_writeb(0x00, IO_UART + 0x20);     /* Disable IRQs */
-       __raw_writeb(0x01, IO_UART + 0x14);     /* Enable UART */
-}
-
-#define arch_decomp_wdog()

diff --git a/arch/arm/mach-l7200/include/mach/vmalloc.h b/arch/arm/mach-l7200/include/mach/vmalloc.h
deleted file mode 100644 (file)
index 85f0abb..0000000
--- a/arch/arm/mach-l7200/include/mach/vmalloc.h
+++ /dev/null
@@ -1,4 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/vmalloc.h
- */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)

diff --git a/arch/arm/mach-lh7a40x/include/mach/memory.h b/arch/arm/mach-lh7a40x/include/mach/memory.h
index 189d20e543e75f41b52a39f4f009e30ed87ed2d5..edb8f5faf5d5032c9047d4c743a66e1230dbe0e8 100644 (file)
--- a/arch/arm/mach-lh7a40x/include/mach/memory.h
+++ b/arch/arm/mach-lh7a40x/include/mach/memory.h
@@ -19,50 +19,6 @@
  */
 #define PHYS_OFFSET    UL(0xc0000000)
 
-#ifdef CONFIG_DISCONTIGMEM
-
-/*
- * Given a kernel address, find the home node of the underlying memory.
- */
-
-# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE
-#  define KVADDR_TO_NID(addr) \
-  (  ((((unsigned long) (addr) - PAGE_OFFSET) >> 24) &  1)\
-   | ((((unsigned long) (addr) - PAGE_OFFSET) >> 25) & ~1))
-# else  /* 2 banks per node */
-#  define KVADDR_TO_NID(addr) \
-      (((unsigned long) (addr) - PAGE_OFFSET) >> 26)
-# endif
-
-/*
- * Given a page frame number, convert it to a node id.
- */
-
-# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE
-#  define PFN_TO_NID(pfn) \
-  (((((pfn) - PHYS_PFN_OFFSET) >> (24 - PAGE_SHIFT)) &  1)\
- | ((((pfn) - PHYS_PFN_OFFSET) >> (25 - PAGE_SHIFT)) & ~1))
-# else  /* 2 banks per node */
-#  define PFN_TO_NID(pfn) \
-    (((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT))
-#endif
-
-/*
- * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
- * and returns the index corresponding to the appropriate page in the
- * node's mem_map.
- */
-
-# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE
-#  define LOCAL_MAP_NR(addr) \
-       (((unsigned long)(addr) & 0x003fffff) >> PAGE_SHIFT)
-# else  /* 2 banks per node */
-#  define LOCAL_MAP_NR(addr) \
-       (((unsigned long)(addr) & 0x01ffffff) >> PAGE_SHIFT)
-# endif
-
-#endif
-
 /*
  * Sparsemem version of the above
  */

diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig
new file mode 100644 (file)
index 0000000..fde6635
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/Kconfig
@@ -0,0 +1,33 @@
+if ARCH_LPC32XX
+
+menu "Individual UART enable selections"
+
+config ARCH_LPC32XX_UART3_SELECT
+       bool "Add support for standard UART3"
+       help
+        Adds support for standard UART 3 when the 8250 serial support
+        is enabled.
+
+config ARCH_LPC32XX_UART4_SELECT
+       bool "Add support for standard UART4"
+       help
+        Adds support for standard UART 4 when the 8250 serial support
+        is enabled.
+
+config ARCH_LPC32XX_UART5_SELECT
+       bool "Add support for standard UART5"
+       default y
+       help
+        Adds support for standard UART 5 when the 8250 serial support
+        is enabled.
+
+config ARCH_LPC32XX_UART6_SELECT
+       bool "Add support for standard UART6"
+       help
+        Adds support for standard UART 6 when the 8250 serial support
+        is enabled.
+
+endmenu
+
+endif
+

diff --git a/arch/arm/mach-lpc32xx/Makefile b/arch/arm/mach-lpc32xx/Makefile
new file mode 100644 (file)
index 0000000..a5fc5d0
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for the linux kernel.
+#
+
+obj-y  := timer.o irq.o common.o serial.o clock.o
+obj-y  += gpiolib.o pm.o suspend.o
+obj-y  += phy3250.o
+

diff --git a/arch/arm/mach-lpc32xx/Makefile.boot b/arch/arm/mach-lpc32xx/Makefile.boot
new file mode 100644 (file)
index 0000000..b796b41
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/Makefile.boot
@@ -0,0 +1,4 @@
+   zreladdr-y  := 0x80008000
+params_phys-y  := 0x80000100
+initrd_phys-y  := 0x82000000
+

diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
new file mode 100644 (file)
index 0000000..32d6379
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -0,0 +1,1137 @@
+/*
+ * arch/arm/mach-lpc32xx/clock.c
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * LPC32xx clock management driver overview
+ *
+ * The LPC32XX contains a number of high level system clocks that can be
+ * generated from different sources. These system clocks are used to
+ * generate the CPU and bus rates and the individual peripheral clocks in
+ * the system. When Linux is started by the boot loader, the system
+ * clocks are already running. Stopping a system clock during normal
+ * Linux operation should never be attempted, as peripherals that require
+ * those clocks will quit working (ie, DRAM).
+ *
+ * The LPC32xx high level clock tree looks as follows. Clocks marked with
+ * an asterisk are always on and cannot be disabled. Clocks marked with
+ * an ampersand can only be disabled in CPU suspend mode. Clocks marked
+ * with a caret are always on if it is the selected clock for the SYSCLK
+ * source. The clock that isn't used for SYSCLK can be enabled and
+ * disabled normally.
+ *                               32KHz oscillator*
+ *                               /      |      \
+ *                             RTC*   PLL397^ TOUCH
+ *                                     /
+ *               Main oscillator^     /
+ *                   |        \      /
+ *                   |         SYSCLK&
+ *                   |            \
+ *                   |             \
+ *                USB_PLL       HCLK_PLL&
+ *                   |           |    |
+ *            USB host/device  PCLK&  |
+ *                               |    |
+ *                             Peripherals
+ *
+ * The CPU and chip bus rates are derived from the HCLK PLL, which can
+ * generate various clock rates up to 266MHz and beyond. The internal bus
+ * rates (PCLK and HCLK) are generated from dividers based on the HCLK
+ * PLL rate. HCLK can be a ratio of 1:1, 1:2, or 1:4 or HCLK PLL rate,
+ * while PCLK can be 1:1 to 1:32 of HCLK PLL rate. Most peripherals high
+ * level clocks are based on either HCLK or PCLK, but have their own
+ * dividers as part of the IP itself. Because of this, the system clock
+ * rates should not be changed.
+ *
+ * The HCLK PLL is clocked from SYSCLK, which can be derived from the
+ * main oscillator or PLL397. PLL397 generates a rate that is 397 times
+ * the 32KHz oscillator rate. The main oscillator runs at the selected
+ * oscillator/crystal rate on the mosc_in pin of the LPC32xx. This rate
+ * is normally 13MHz, but depends on the selection of external crystals
+ * or oscillators. If USB operation is required, the main oscillator must
+ * be used in the system.
+ *
+ * Switching SYSCLK between sources during normal Linux operation is not
+ * supported. SYSCLK is preset in the bootloader. Because of the
+ * complexities of clock management during clock frequency changes,
+ * there are some limitations to the clock driver explained below:
+ * - The PLL397 and main oscillator can be enabled and disabled by the
+ *   clk_enable() and clk_disable() functions unless SYSCLK is based
+ *   on that clock. This allows the other oscillator that isn't driving
+ *   the HCLK PLL to be used as another system clock that can be routed
+ *   to an external pin.
+ * - The muxed SYSCLK input and HCLK_PLL rate cannot be changed with
+ *   this driver.
+ * - HCLK and PCLK rates cannot be changed as part of this driver.
+ * - Most peripherals have their own dividers are part of the peripheral
+ *   block. Changing SYSCLK, HCLK PLL, HCLK, or PCLK sources or rates
+ *   will also impact the individual peripheral rates.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/clcd.h>
+
+#include <mach/hardware.h>
+#include <asm/clkdev.h>
+#include <mach/clkdev.h>
+#include <mach/platform.h>
+#include "clock.h"
+#include "common.h"
+
+static struct clk clk_armpll;
+static struct clk clk_usbpll;
+static DEFINE_MUTEX(clkm_lock);
+
+/*
+ * Post divider values for PLLs based on selected register value
+ */
+static const u32 pll_postdivs[4] = {1, 2, 4, 8};
+
+static unsigned long local_return_parent_rate(struct clk *clk)
+{
+       /*
+        * If a clock has a rate of 0, then it inherits it's parent
+        * clock rate
+        */
+       while (clk->rate == 0)
+               clk = clk->parent;
+
+       return clk->rate;
+}
+
+/* 32KHz clock has a fixed rate and is not stoppable */
+static struct clk osc_32KHz = {
+       .rate           = LPC32XX_CLOCK_OSC_FREQ,
+       .get_rate       = local_return_parent_rate,
+};
+
+static int local_pll397_enable(struct clk *clk, int enable)
+{
+       u32 reg;
+       unsigned long timeout = 1 + msecs_to_jiffies(10);
+
+       reg = __raw_readl(LPC32XX_CLKPWR_PLL397_CTRL);
+
+       if (enable == 0) {
+               reg |= LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
+               __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
+       } else {
+               /* Enable PLL397 */
+               reg &= ~LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
+               __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
+
+               /* Wait for PLL397 lock */
+               while (((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
+                       LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0) &&
+                       (timeout > jiffies))
+                       cpu_relax();
+
+               if ((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
+                       LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0)
+                       return -ENODEV;
+       }
+
+       return 0;
+}
+
+static int local_oscmain_enable(struct clk *clk, int enable)
+{
+       u32 reg;
+       unsigned long timeout = 1 + msecs_to_jiffies(10);
+
+       reg = __raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL);
+
+       if (enable == 0) {
+               reg |= LPC32XX_CLKPWR_MOSC_DISABLE;
+               __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
+       } else {
+               /* Enable main oscillator */
+               reg &= ~LPC32XX_CLKPWR_MOSC_DISABLE;
+               __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
+
+               /* Wait for main oscillator to start */
+               while (((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
+                       LPC32XX_CLKPWR_MOSC_DISABLE) != 0) &&
+                       (timeout > jiffies))
+                       cpu_relax();
+
+               if ((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
+                       LPC32XX_CLKPWR_MOSC_DISABLE) != 0)
+                       return -ENODEV;
+       }
+
+       return 0;
+}
+
+static struct clk osc_pll397 = {
+       .parent         = &osc_32KHz,
+       .enable         = local_pll397_enable,
+       .rate           = LPC32XX_CLOCK_OSC_FREQ * 397,
+       .get_rate       = local_return_parent_rate,
+};
+
+static struct clk osc_main = {
+       .enable         = local_oscmain_enable,
+       .rate           = LPC32XX_MAIN_OSC_FREQ,
+       .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_sys;
+
+/*
+ * Convert a PLL register value to a PLL output frequency
+ */
+u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval)
+{
+       struct clk_pll_setup pllcfg;
+
+       pllcfg.cco_bypass_b15 = 0;
+       pllcfg.direct_output_b14 = 0;
+       pllcfg.fdbk_div_ctrl_b13 = 0;
+       if ((regval & LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS) != 0)
+               pllcfg.cco_bypass_b15 = 1;
+       if ((regval & LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS) != 0)
+               pllcfg.direct_output_b14 = 1;
+       if ((regval & LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK) != 0)
+               pllcfg.fdbk_div_ctrl_b13 = 1;
+       pllcfg.pll_m = 1 + ((regval >> 1) & 0xFF);
+       pllcfg.pll_n = 1 + ((regval >> 9) & 0x3);
+       pllcfg.pll_p = pll_postdivs[((regval >> 11) & 0x3)];
+
+       return clk_check_pll_setup(inputclk, &pllcfg);
+}
+
+/*
+ * Setup the HCLK PLL with a PLL structure
+ */
+static u32 local_clk_pll_setup(struct clk_pll_setup *PllSetup)
+{
+       u32 tv, tmp = 0;
+
+       if (PllSetup->analog_on != 0)
+               tmp |= LPC32XX_CLKPWR_HCLKPLL_POWER_UP;
+       if (PllSetup->cco_bypass_b15 != 0)
+               tmp |= LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS;
+       if (PllSetup->direct_output_b14 != 0)
+               tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS;
+       if (PllSetup->fdbk_div_ctrl_b13 != 0)
+               tmp |= LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK;
+
+       tv = ffs(PllSetup->pll_p) - 1;
+       if ((!is_power_of_2(PllSetup->pll_p)) || (tv > 3))
+               return 0;
+
+       tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(tv);
+       tmp |= LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(PllSetup->pll_n - 1);
+       tmp |= LPC32XX_CLKPWR_HCLKPLL_PLLM(PllSetup->pll_m - 1);
+
+       return tmp;
+}
+
+/*
+ * Update the ARM core PLL frequency rate variable from the actual PLL setting
+ */
+static void local_update_armpll_rate(void)
+{
+       u32 clkin, pllreg;
+
+       clkin = clk_armpll.parent->rate;
+       pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
+
+       clk_armpll.rate = clk_get_pllrate_from_reg(clkin, pllreg);
+}
+
+/*
+ * Find a PLL configuration for the selected input frequency
+ */
+static u32 local_clk_find_pll_cfg(u32 pllin_freq, u32 target_freq,
+       struct clk_pll_setup *pllsetup)
+{
+       u32 ifreq, freqtol, m, n, p, fclkout;
+
+       /* Determine frequency tolerance limits */
+       freqtol = target_freq / 250;
+       ifreq = pllin_freq;
+
+       /* Is direct bypass mode possible? */
+       if (abs(pllin_freq - target_freq) <= freqtol) {
+               pllsetup->analog_on = 0;
+               pllsetup->cco_bypass_b15 = 1;
+               pllsetup->direct_output_b14 = 1;
+               pllsetup->fdbk_div_ctrl_b13 = 1;
+               pllsetup->pll_p = pll_postdivs[0];
+               pllsetup->pll_n = 1;
+               pllsetup->pll_m = 1;
+               return clk_check_pll_setup(ifreq, pllsetup);
+       } else if (target_freq <= ifreq) {
+               pllsetup->analog_on = 0;
+               pllsetup->cco_bypass_b15 = 1;
+               pllsetup->direct_output_b14 = 0;
+               pllsetup->fdbk_div_ctrl_b13 = 1;
+               pllsetup->pll_n = 1;
+               pllsetup->pll_m = 1;
+               for (p = 0; p <= 3; p++) {
+                       pllsetup->pll_p = pll_postdivs[p];
+                       fclkout = clk_check_pll_setup(ifreq, pllsetup);
+                       if (abs(target_freq - fclkout) <= freqtol)
+                               return fclkout;
+               }
+       }
+
+       /* Is direct mode possible? */
+       pllsetup->analog_on = 1;
+       pllsetup->cco_bypass_b15 = 0;
+       pllsetup->direct_output_b14 = 1;
+       pllsetup->fdbk_div_ctrl_b13 = 0;
+       pllsetup->pll_p = pll_postdivs[0];
+       for (m = 1; m <= 256; m++) {
+               for (n = 1; n <= 4; n++) {
+                       /* Compute output frequency for this value */
+                       pllsetup->pll_n = n;
+                       pllsetup->pll_m = m;
+                       fclkout = clk_check_pll_setup(ifreq,
+                               pllsetup);
+                       if (abs(target_freq - fclkout) <=
+                               freqtol)
+                               return fclkout;
+               }
+       }
+
+       /* Is integer mode possible? */
+       pllsetup->analog_on = 1;
+       pllsetup->cco_bypass_b15 = 0;
+       pllsetup->direct_output_b14 = 0;
+       pllsetup->fdbk_div_ctrl_b13 = 1;
+       for (m = 1; m <= 256; m++) {
+               for (n = 1; n <= 4; n++) {
+                       for (p = 0; p < 4; p++) {
+                               /* Compute output frequency */
+                               pllsetup->pll_p = pll_postdivs[p];
+                               pllsetup->pll_n = n;
+                               pllsetup->pll_m = m;
+                               fclkout = clk_check_pll_setup(
+                                       ifreq, pllsetup);
+                               if (abs(target_freq - fclkout) <= freqtol)
+                                       return fclkout;
+                       }
+               }
+       }
+
+       /* Try non-integer mode */
+       pllsetup->analog_on = 1;
+       pllsetup->cco_bypass_b15 = 0;
+       pllsetup->direct_output_b14 = 0;
+       pllsetup->fdbk_div_ctrl_b13 = 0;
+       for (m = 1; m <= 256; m++) {
+               for (n = 1; n <= 4; n++) {
+                       for (p = 0; p < 4; p++) {
+                               /* Compute output frequency */
+                               pllsetup->pll_p = pll_postdivs[p];
+                               pllsetup->pll_n = n;
+                               pllsetup->pll_m = m;
+                               fclkout = clk_check_pll_setup(
+                                       ifreq, pllsetup);
+                               if (abs(target_freq - fclkout) <= freqtol)
+                                       return fclkout;
+                       }
+               }
+       }
+
+       return 0;
+}
+
+static struct clk clk_armpll = {
+       .parent         = &clk_sys,
+       .get_rate       = local_return_parent_rate,
+};
+
+/*
+ * Setup the USB PLL with a PLL structure
+ */
+static u32 local_clk_usbpll_setup(struct clk_pll_setup *pHCLKPllSetup)
+{
+       u32 reg, tmp = local_clk_pll_setup(pHCLKPllSetup);
+
+       reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL) & ~0x1FFFF;
+       reg |= tmp;
+       __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
+
+       return clk_check_pll_setup(clk_usbpll.parent->rate,
+               pHCLKPllSetup);
+}
+
+static int local_usbpll_enable(struct clk *clk, int enable)
+{
+       u32 reg;
+       int ret = -ENODEV;
+       unsigned long timeout = 1 + msecs_to_jiffies(10);
+
+       reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
+
+       if (enable == 0) {
+               reg &= ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN1 |
+                       LPC32XX_CLKPWR_USBCTRL_CLK_EN2);
+               __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
+       } else if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP) {
+               reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
+               __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
+
+               /* Wait for PLL lock */
+               while ((timeout > jiffies) & (ret == -ENODEV)) {
+                       reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
+                       if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS)
+                               ret = 0;
+               }
+
+               if (ret == 0) {
+                       reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2;
+                       __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
+               }
+       }
+
+       return ret;
+}
+
+static unsigned long local_usbpll_round_rate(struct clk *clk,
+       unsigned long rate)
+{
+       u32 clkin, usbdiv;
+       struct clk_pll_setup pllsetup;
+
+       /*
+        * Unlike other clocks, this clock has a KHz input rate, so bump
+        * it up to work with the PLL function
+        */
+       rate = rate * 1000;
+
+       clkin = clk->parent->rate;
+       usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
+               LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
+       clkin = clkin / usbdiv;
+
+       /* Try to find a good rate setup */
+       if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
+               return 0;
+
+       return clk_check_pll_setup(clkin, &pllsetup);
+}
+
+static int local_usbpll_set_rate(struct clk *clk, unsigned long rate)
+{
+       u32 clkin, reg, usbdiv;
+       struct clk_pll_setup pllsetup;
+
+       /*
+        * Unlike other clocks, this clock has a KHz input rate, so bump
+        * it up to work with the PLL function
+        */
+       rate = rate * 1000;
+
+       clkin = clk->get_rate(clk);
+       usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
+               LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
+       clkin = clkin / usbdiv;
+
+       /* Try to find a good rate setup */
+       if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
+               return -EINVAL;
+
+       local_usbpll_enable(clk, 0);
+
+       reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
+       reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
+       __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
+
+       pllsetup.analog_on = 1;
+       local_clk_usbpll_setup(&pllsetup);
+
+       clk->rate = clk_check_pll_setup(clkin, &pllsetup);
+
+       reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
+       reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2;
+       __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
+
+       return 0;
+}
+
+static struct clk clk_usbpll = {
+       .parent         = &osc_main,
+       .set_rate       = local_usbpll_set_rate,
+       .enable         = local_usbpll_enable,
+       .rate           = 48000, /* In KHz */
+       .get_rate       = local_return_parent_rate,
+       .round_rate     = local_usbpll_round_rate,
+};
+
+static u32 clk_get_hclk_div(void)
+{
+       static const u32 hclkdivs[4] = {1, 2, 4, 4};
+       return hclkdivs[LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(
+               __raw_readl(LPC32XX_CLKPWR_HCLK_DIV))];
+}
+
+static struct clk clk_hclk = {
+       .parent         = &clk_armpll,
+       .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_pclk = {
+       .parent         = &clk_armpll,
+       .get_rate       = local_return_parent_rate,
+};
+
+static int local_onoff_enable(struct clk *clk, int enable)
+{
+       u32 tmp;
+
+       tmp = __raw_readl(clk->enable_reg);
+
+       if (enable == 0)
+               tmp &= ~clk->enable_mask;
+       else
+               tmp |= clk->enable_mask;
+
+       __raw_writel(tmp, clk->enable_reg);
+
+       return 0;
+}
+
+/* Peripheral clock sources */
+static struct clk clk_timer0 = {
+       .parent         = &clk_pclk,
+       .enable         = local_onoff_enable,
+       .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
+       .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN,
+       .get_rate       = local_return_parent_rate,
+};
+static struct clk clk_timer1 = {
+       .parent         = &clk_pclk,
+       .enable         = local_onoff_enable,
+       .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
+       .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
+       .get_rate       = local_return_parent_rate,
+};
+static struct clk clk_timer2 = {
+       .parent         = &clk_pclk,
+       .enable         = local_onoff_enable,
+       .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
+       .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN,
+       .get_rate       = local_return_parent_rate,
+};
+static struct clk clk_timer3 = {
+       .parent         = &clk_pclk,
+       .enable         = local_onoff_enable,
+       .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
+       .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN,
+       .get_rate       = local_return_parent_rate,
+};
+static struct clk clk_wdt = {
+       .parent         = &clk_pclk,
+       .enable         = local_onoff_enable,
+       .enable_reg     = LPC32XX_CLKPWR_TIMER_CLK_CTRL,
+       .enable_mask    = LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
+       .get_rate       = local_return_parent_rate,
+};
+static struct clk clk_vfp9 = {
+       .parent         = &clk_pclk,
+       .enable         = local_onoff_enable,
+       .enable_reg     = LPC32XX_CLKPWR_DEBUG_CTRL,
+       .enable_mask    = LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT,
+       .get_rate       = local_return_parent_rate,
+};
+static struct clk clk_dma = {
+       .parent         = &clk_hclk,
+       .enable         = local_onoff_enable,
+       .enable_reg     = LPC32XX_CLKPWR_DMA_CLK_CTRL,
+       .enable_mask    = LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN,
+       .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_uart3 = {
+       .parent         = &clk_pclk,
+       .enable         = local_onoff_enable,
+       .enable_reg     = LPC32XX_CLKPWR_UART_CLK_CTRL,
+       .enable_mask    = LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN,
+       .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_uart4 = {
+       .parent         = &clk_pclk,
+       .enable         = local_onoff_enable,
+       .enable_reg     = LPC32XX_CLKPWR_UART_CLK_CTRL,
+       .enable_mask    = LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN,
+       .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_uart5 = {
+       .parent         = &clk_pclk,
+       .enable         = local_onoff_enable,
+       .enable_reg     = LPC32XX_CLKPWR_UART_CLK_CTRL,
+       .enable_mask    = LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN,
+       .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_uart6 = {
+       .parent         = &clk_pclk,
+       .enable         = local_onoff_enable,
+       .enable_reg     = LPC32XX_CLKPWR_UART_CLK_CTRL,
+       .enable_mask    = LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN,
+       .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_i2c0 = {
+       .parent         = &clk_hclk,
+       .enable         = local_onoff_enable,
+       .enable_reg     = LPC32XX_CLKPWR_I2C_CLK_CTRL,
+       .enable_mask    = LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN,
+       .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_i2c1 = {
+       .parent         = &clk_hclk,
+       .enable         = local_onoff_enable,
+       .enable_reg     = LPC32XX_CLKPWR_I2C_CLK_CTRL,
+       .enable_mask    = LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN,
+       .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_i2c2 = {
+       .parent         = &clk_pclk,
+       .enable         = local_onoff_enable,
+       .enable_reg     = io_p2v(LPC32XX_USB_BASE + 0xFF4),
+       .enable_mask    = 0x4,
+       .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_ssp0 = {
+       .parent         = &clk_hclk,
+       .enable         = local_onoff_enable,
+       .enable_reg     = LPC32XX_CLKPWR_SSP_CLK_CTRL,
+       .enable_mask    = LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN,
+       .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_ssp1 = {
+       .parent         = &clk_hclk,
+       .enable         = local_onoff_enable,
+       .enable_reg     = LPC32XX_CLKPWR_SSP_CLK_CTRL,
+       .enable_mask    = LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN,
+       .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_kscan = {
+       .parent         = &osc_32KHz,
+       .enable         = local_onoff_enable,
+       .enable_reg     = LPC32XX_CLKPWR_KEY_CLK_CTRL,
+       .enable_mask    = LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN,
+       .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_nand = {
+       .parent         = &clk_hclk,
+       .enable         = local_onoff_enable,
+       .enable_reg     = LPC32XX_CLKPWR_NAND_CLK_CTRL,
+       .enable_mask    = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN,
+       .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_i2s0 = {
+       .parent         = &clk_hclk,
+       .enable         = local_onoff_enable,
+       .enable_reg     = LPC32XX_CLKPWR_I2S_CLK_CTRL,
+       .enable_mask    = LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN,
+       .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_i2s1 = {
+       .parent         = &clk_hclk,
+       .enable         = local_onoff_enable,
+       .enable_reg     = LPC32XX_CLKPWR_I2S_CLK_CTRL,
+       .enable_mask    = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN,
+       .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_net = {
+       .parent         = &clk_hclk,
+       .enable         = local_onoff_enable,
+       .enable_reg     = LPC32XX_CLKPWR_MACCLK_CTRL,
+       .enable_mask    = (LPC32XX_CLKPWR_MACCTRL_DMACLK_EN |
+               LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN |
+               LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN),
+       .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_rtc = {
+       .parent         = &osc_32KHz,
+       .rate           = 1, /* 1 Hz */
+       .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_usbd = {
+       .parent         = &clk_usbpll,
+       .enable         = local_onoff_enable,
+       .enable_reg     = LPC32XX_CLKPWR_USB_CTRL,
+       .enable_mask    = LPC32XX_CLKPWR_USBCTRL_HCLK_EN,
+       .get_rate       = local_return_parent_rate,
+};
+
+static int tsc_onoff_enable(struct clk *clk, int enable)
+{
+       u32 tmp;
+
+       /* Make sure 32KHz clock is the selected clock */
+       tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
+       tmp &= ~LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL;
+       __raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
+
+       if (enable == 0)
+               __raw_writel(0, clk->enable_reg);
+       else
+               __raw_writel(clk->enable_mask, clk->enable_reg);
+
+       return 0;
+}
+
+static struct clk clk_tsc = {
+       .parent         = &osc_32KHz,
+       .enable         = tsc_onoff_enable,
+       .enable_reg     = LPC32XX_CLKPWR_ADC_CLK_CTRL,
+       .enable_mask    = LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN,
+       .get_rate       = local_return_parent_rate,
+};
+
+static int mmc_onoff_enable(struct clk *clk, int enable)
+{
+       u32 tmp;
+
+       tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
+               ~LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
+
+       /* If rate is 0, disable clock */
+       if (enable != 0)
+               tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
+
+       __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
+
+       return 0;
+}
+
+static unsigned long mmc_get_rate(struct clk *clk)
+{
+       u32 div, rate, oldclk;
+
+       /* The MMC clock must be on when accessing an MMC register */
+       oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
+       __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
+               LPC32XX_CLKPWR_MS_CTRL);
+       div = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
+       __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
+
+       /* Get the parent clock rate */
+       rate = clk->parent->get_rate(clk->parent);
+
+       /* Get the MMC controller clock divider value */
+       div = div & LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
+
+       if (!div)
+               div = 1;
+
+       return rate / div;
+}
+
+static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate)
+{
+       unsigned long div, prate;
+
+       /* Get the parent clock rate */
+       prate = clk->parent->get_rate(clk->parent);
+
+       if (rate >= prate)
+               return prate;
+
+       div = prate / rate;
+       if (div > 0xf)
+               div = 0xf;
+
+       return prate / div;
+}
+
+static int mmc_set_rate(struct clk *clk, unsigned long rate)
+{
+       u32 oldclk, tmp;
+       unsigned long prate, div, crate = mmc_round_rate(clk, rate);
+
+       prate = clk->parent->get_rate(clk->parent);
+
+       div = prate / crate;
+
+       /* The MMC clock must be on when accessing an MMC register */
+       oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
+       __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
+               LPC32XX_CLKPWR_MS_CTRL);
+       tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
+               ~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
+       tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div);
+       __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
+
+       __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
+
+       return 0;
+}
+
+static struct clk clk_mmc = {
+       .parent         = &clk_armpll,
+       .set_rate       = mmc_set_rate,
+       .get_rate       = mmc_get_rate,
+       .round_rate     = mmc_round_rate,
+       .enable         = mmc_onoff_enable,
+       .enable_reg     = LPC32XX_CLKPWR_MS_CTRL,
+       .enable_mask    = LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
+};
+
+static unsigned long clcd_get_rate(struct clk *clk)
+{
+       u32 tmp, div, rate, oldclk;
+
+       /* The LCD clock must be on when accessing an LCD register */
+       oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
+       __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
+               LPC32XX_CLKPWR_LCDCLK_CTRL);
+       tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
+       __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
+
+       rate = clk->parent->get_rate(clk->parent);
+
+       /* Only supports internal clocking */
+       if (tmp & TIM2_BCD)
+               return rate;
+
+       div = (tmp & 0x1F) | ((tmp & 0xF8) >> 22);
+       tmp = rate / (2 + div);
+
+       return tmp;
+}
+
+static int clcd_set_rate(struct clk *clk, unsigned long rate)
+{
+       u32 tmp, prate, div, oldclk;
+
+       /* The LCD clock must be on when accessing an LCD register */
+       oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
+       __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
+               LPC32XX_CLKPWR_LCDCLK_CTRL);
+
+       tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2)) | TIM2_BCD;
+       prate = clk->parent->get_rate(clk->parent);
+
+       if (rate < prate) {
+               /* Find closest divider */
+               div = prate / rate;
+               if (div >= 2) {
+                       div -= 2;
+                       tmp &= ~TIM2_BCD;
+               }
+
+               tmp &= ~(0xF800001F);
+               tmp |= (div & 0x1F);
+               tmp |= (((div >> 5) & 0x1F) << 27);
+       }
+
+       __raw_writel(tmp, io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
+       __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
+
+       return 0;
+}
+
+static unsigned long clcd_round_rate(struct clk *clk, unsigned long rate)
+{
+       u32 prate, div;
+
+       prate = clk->parent->get_rate(clk->parent);
+
+       if (rate >= prate)
+               rate = prate;
+       else {
+               div = prate / rate;
+               if (div > 0x3ff)
+                       div = 0x3ff;
+
+               rate = prate / div;
+       }
+
+       return rate;
+}
+
+static struct clk clk_lcd = {
+       .parent         = &clk_hclk,
+       .set_rate       = clcd_set_rate,
+       .get_rate       = clcd_get_rate,
+       .round_rate     = clcd_round_rate,
+       .enable         = local_onoff_enable,
+       .enable_reg     = LPC32XX_CLKPWR_LCDCLK_CTRL,
+       .enable_mask    = LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
+};
+
+static inline void clk_lock(void)
+{
+       mutex_lock(&clkm_lock);
+}
+
+static inline void clk_unlock(void)
+{
+       mutex_unlock(&clkm_lock);
+}
+
+static void local_clk_disable(struct clk *clk)
+{
+       WARN_ON(clk->usecount == 0);
+
+       /* Don't attempt to disable clock if it has no users */
+       if (clk->usecount > 0) {
+               clk->usecount--;
+
+               /* Only disable clock when it has no more users */
+               if ((clk->usecount == 0) && (clk->enable))
+                       clk->enable(clk, 0);
+
+               /* Check parent clocks, they may need to be disabled too */
+               if (clk->parent)
+                       local_clk_disable(clk->parent);
+       }
+}
+
+static int local_clk_enable(struct clk *clk)
+{
+       int ret = 0;
+
+       /* Enable parent clocks first and update use counts */
+       if (clk->parent)
+               ret = local_clk_enable(clk->parent);
+
+       if (!ret) {
+               /* Only enable clock if it's currently disabled */
+               if ((clk->usecount == 0) && (clk->enable))
+                       ret = clk->enable(clk, 1);
+
+               if (!ret)
+                       clk->usecount++;
+               else if (clk->parent)
+                       local_clk_disable(clk->parent);
+       }
+
+       return ret;
+}
+
+/*
+ * clk_enable - inform the system when the clock source should be running.
+ */
+int clk_enable(struct clk *clk)
+{
+       int ret;
+
+       clk_lock();
+       ret = local_clk_enable(clk);
+       clk_unlock();
+
+       return ret;
+}
+EXPORT_SYMBOL(clk_enable);
+
+/*
+ * clk_disable - inform the system when the clock source is no longer required
+ */
+void clk_disable(struct clk *clk)
+{
+       clk_lock();
+       local_clk_disable(clk);
+       clk_unlock();
+}
+EXPORT_SYMBOL(clk_disable);
+
+/*
+ * clk_get_rate - obtain the current clock rate (in Hz) for a clock source
+ */
+unsigned long clk_get_rate(struct clk *clk)
+{
+       unsigned long rate;
+
+       clk_lock();
+       rate = clk->get_rate(clk);
+       clk_unlock();
+
+       return rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+/*
+ * clk_set_rate - set the clock rate for a clock source
+ */
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+       int ret = -EINVAL;
+
+       /*
+        * Most system clocks can only be enabled or disabled, with
+        * the actual rate set as part of the peripheral dividers
+        * instead of high level clock control
+        */
+       if (clk->set_rate) {
+               clk_lock();
+               ret = clk->set_rate(clk, rate);
+               clk_unlock();
+       }
+
+       return ret;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+/*
+ * clk_round_rate - adjust a rate to the exact rate a clock can provide
+ */
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+       clk_lock();
+
+       if (clk->round_rate)
+               rate = clk->round_rate(clk, rate);
+       else
+               rate = clk->get_rate(clk);
+
+       clk_unlock();
+
+       return rate;
+}
+EXPORT_SYMBOL(clk_round_rate);
+
+/*
+ * clk_set_parent - set the parent clock source for this clock
+ */
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+       /* Clock re-parenting is not supported */
+       return -EINVAL;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
+/*
+ * clk_get_parent - get the parent clock source for this clock
+ */
+struct clk *clk_get_parent(struct clk *clk)
+{
+       return clk->parent;
+}
+EXPORT_SYMBOL(clk_get_parent);
+
+#define _REGISTER_CLOCK(d, n, c) \
+       { \
+               .dev_id = (d), \
+               .con_id = (n), \
+               .clk = &(c), \
+       },
+
+static struct clk_lookup lookups[] = {
+       _REGISTER_CLOCK(NULL, "osc_32KHz", osc_32KHz)
+       _REGISTER_CLOCK(NULL, "osc_pll397", osc_pll397)
+       _REGISTER_CLOCK(NULL, "osc_main", osc_main)
+       _REGISTER_CLOCK(NULL, "sys_ck", clk_sys)
+       _REGISTER_CLOCK(NULL, "arm_pll_ck", clk_armpll)
+       _REGISTER_CLOCK(NULL, "ck_pll5", clk_usbpll)
+       _REGISTER_CLOCK(NULL, "hclk_ck", clk_hclk)
+       _REGISTER_CLOCK(NULL, "pclk_ck", clk_pclk)
+       _REGISTER_CLOCK(NULL, "timer0_ck", clk_timer0)
+       _REGISTER_CLOCK(NULL, "timer1_ck", clk_timer1)
+       _REGISTER_CLOCK(NULL, "timer2_ck", clk_timer2)
+       _REGISTER_CLOCK(NULL, "timer3_ck", clk_timer3)
+       _REGISTER_CLOCK(NULL, "vfp9_ck", clk_vfp9)
+       _REGISTER_CLOCK(NULL, "clk_dmac", clk_dma)
+       _REGISTER_CLOCK("pnx4008-watchdog", NULL, clk_wdt)
+       _REGISTER_CLOCK(NULL, "uart3_ck", clk_uart3)
+       _REGISTER_CLOCK(NULL, "uart4_ck", clk_uart4)
+       _REGISTER_CLOCK(NULL, "uart5_ck", clk_uart5)
+       _REGISTER_CLOCK(NULL, "uart6_ck", clk_uart6)
+       _REGISTER_CLOCK("pnx-i2c.0", NULL, clk_i2c0)
+       _REGISTER_CLOCK("pnx-i2c.1", NULL, clk_i2c1)
+       _REGISTER_CLOCK("pnx-i2c.2", NULL, clk_i2c2)
+       _REGISTER_CLOCK("dev:ssp0", NULL, clk_ssp0)
+       _REGISTER_CLOCK("dev:ssp1", NULL, clk_ssp1)
+       _REGISTER_CLOCK("lpc32xx_keys.0", NULL, clk_kscan)
+       _REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand)
+       _REGISTER_CLOCK("tbd", "i2s0_ck", clk_i2s0)
+       _REGISTER_CLOCK("tbd", "i2s1_ck", clk_i2s1)
+       _REGISTER_CLOCK("lpc32xx-ts", NULL, clk_tsc)
+       _REGISTER_CLOCK("dev:mmc0", "MCLK", clk_mmc)
+       _REGISTER_CLOCK("lpc-net.0", NULL, clk_net)
+       _REGISTER_CLOCK("dev:clcd", NULL, clk_lcd)
+       _REGISTER_CLOCK("lpc32xx_udc", "ck_usbd", clk_usbd)
+       _REGISTER_CLOCK("lpc32xx_rtc", NULL, clk_rtc)
+};
+
+static int __init clk_init(void)
+{
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(lookups); i++)
+               clkdev_add(&lookups[i]);
+
+       /*
+        * Setup muxed SYSCLK for HCLK PLL base -this selects the
+        * parent clock used for the ARM PLL and is used to derive
+        * the many system clock rates in the device.
+        */
+       if (clk_is_sysclk_mainosc() != 0)
+               clk_sys.parent = &osc_main;
+       else
+               clk_sys.parent = &osc_pll397;
+
+       clk_sys.rate = clk_sys.parent->rate;
+
+       /* Compute the current ARM PLL and USB PLL frequencies */
+       local_update_armpll_rate();
+
+       /* Compute HCLK and PCLK bus rates */
+       clk_hclk.rate = clk_hclk.parent->rate / clk_get_hclk_div();
+       clk_pclk.rate = clk_pclk.parent->rate / clk_get_pclk_div();
+
+       /*
+        * Enable system clocks - this step is somewhat formal, as the
+        * clocks are already running, but it does get the clock data
+        * inline with the actual system state. Never disable these
+        * clocks as they will only stop if the system is going to sleep.
+        * In that case, the chip/system power management functions will
+        * handle clock gating.
+        */
+       if (clk_enable(&clk_hclk) || clk_enable(&clk_pclk))
+               printk(KERN_ERR "Error enabling system HCLK and PCLK\n");
+
+       /*
+        * Timers 0 and 1 were enabled and are being used by the high
+        * resolution tick function prior to this driver being initialized.
+        * Tag them now as used.
+        */
+       if (clk_enable(&clk_timer0) || clk_enable(&clk_timer1))
+               printk(KERN_ERR "Error enabling timer tick clocks\n");
+
+       return 0;
+}
+core_initcall(clk_init);
+

diff --git a/arch/arm/mach-lpc32xx/clock.h b/arch/arm/mach-lpc32xx/clock.h
new file mode 100644 (file)
index 0000000..c0a8434
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/clock.h
@@ -0,0 +1,38 @@
+/*
+ * arch/arm/mach-lpc32xx/clock.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LPC32XX_CLOCK_H
+#define __LPC32XX_CLOCK_H
+
+struct clk {
+       struct list_head node;
+       struct clk *parent;
+       u32 rate;
+       u32 usecount;
+
+       int (*set_rate) (struct clk *, unsigned long);
+       unsigned long (*round_rate) (struct clk *, unsigned long);
+       unsigned long (*get_rate) (struct clk *clk);
+       int (*enable) (struct clk *, int);
+
+       /* Register address and bit mask for simple clocks */
+       void __iomem *enable_reg;
+       u32 enable_mask;
+};
+
+#endif

diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
new file mode 100644 (file)
index 0000000..ee24dc2
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -0,0 +1,271 @@
+/*
+ * arch/arm/mach-lpc32xx/common.c
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/i2c-pnx.h>
+#include <linux/io.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/i2c.h>
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include "common.h"
+
+/*
+ * Watchdog timer
+ */
+static struct resource watchdog_resources[] = {
+       [0] = {
+               .start = LPC32XX_WDTIM_BASE,
+               .end = LPC32XX_WDTIM_BASE + SZ_4K - 1,
+               .flags = IORESOURCE_MEM,
+       },
+};
+
+struct platform_device lpc32xx_watchdog_device = {
+       .name = "pnx4008-watchdog",
+       .id = -1,
+       .num_resources = ARRAY_SIZE(watchdog_resources),
+       .resource = watchdog_resources,
+};
+
+/*
+ * I2C busses
+ */
+static struct i2c_pnx_data i2c0_data = {
+       .name = I2C_CHIP_NAME "1",
+       .base = LPC32XX_I2C1_BASE,
+       .irq = IRQ_LPC32XX_I2C_1,
+};
+
+static struct i2c_pnx_data i2c1_data = {
+       .name = I2C_CHIP_NAME "2",
+       .base = LPC32XX_I2C2_BASE,
+       .irq = IRQ_LPC32XX_I2C_2,
+};
+
+static struct i2c_pnx_data i2c2_data = {
+       .name = "USB-I2C",
+       .base = LPC32XX_OTG_I2C_BASE,
+       .irq = IRQ_LPC32XX_USB_I2C,
+};
+
+struct platform_device lpc32xx_i2c0_device = {
+       .name = "pnx-i2c",
+       .id = 0,
+       .dev = {
+               .platform_data = &i2c0_data,
+       },
+};
+
+struct platform_device lpc32xx_i2c1_device = {
+       .name = "pnx-i2c",
+       .id = 1,
+       .dev = {
+               .platform_data = &i2c1_data,
+       },
+};
+
+struct platform_device lpc32xx_i2c2_device = {
+       .name = "pnx-i2c",
+       .id = 2,
+       .dev = {
+               .platform_data = &i2c2_data,
+       },
+};
+
+/*
+ * Returns the unique ID for the device
+ */
+void lpc32xx_get_uid(u32 devid[4])
+{
+       int i;
+
+       for (i = 0; i < 4; i++)
+               devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2));
+}
+
+/*
+ * Returns SYSCLK source
+ * 0 = PLL397, 1 = main oscillator
+ */
+int clk_is_sysclk_mainosc(void)
+{
+       if ((__raw_readl(LPC32XX_CLKPWR_SYSCLK_CTRL) &
+               LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX) == 0)
+               return 1;
+
+       return 0;
+}
+
+/*
+ * System reset via the watchdog timer
+ */
+void lpc32xx_watchdog_reset(void)
+{
+       /* Make sure WDT clocks are enabled */
+       __raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
+               LPC32XX_CLKPWR_TIMER_CLK_CTRL);
+
+       /* Instant assert of RESETOUT_N with pulse length 1mS */
+       __raw_writel(13000, io_p2v(LPC32XX_WDTIM_BASE + 0x18));
+       __raw_writel(0x70, io_p2v(LPC32XX_WDTIM_BASE + 0xC));
+}
+
+/*
+ * Detects and returns IRAM size for the device variation
+ */
+#define LPC32XX_IRAM_BANK_SIZE SZ_128K
+static u32 iram_size;
+u32 lpc32xx_return_iram_size(void)
+{
+       if (iram_size == 0) {
+               u32 savedval1, savedval2;
+               void __iomem *iramptr1, *iramptr2;
+
+               iramptr1 = io_p2v(LPC32XX_IRAM_BASE);
+               iramptr2 = io_p2v(LPC32XX_IRAM_BASE + LPC32XX_IRAM_BANK_SIZE);
+               savedval1 = __raw_readl(iramptr1);
+               savedval2 = __raw_readl(iramptr2);
+
+               if (savedval1 == savedval2) {
+                       __raw_writel(savedval2 + 1, iramptr2);
+                       if (__raw_readl(iramptr1) == savedval2 + 1)
+                               iram_size = LPC32XX_IRAM_BANK_SIZE;
+                       else
+                               iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
+                       __raw_writel(savedval2, iramptr2);
+               } else
+                       iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
+       }
+
+       return iram_size;
+}
+
+/*
+ * Computes PLL rate from PLL register and input clock
+ */
+u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup)
+{
+       u32 ilfreq, p, m, n, fcco, fref, cfreq;
+       int mode;
+
+       /*
+        * PLL requirements
+        * ifreq must be >= 1MHz and <= 20MHz
+        * FCCO must be >= 156MHz and <= 320MHz
+        * FREF must be >= 1MHz and <= 27MHz
+        * Assume the passed input data is not valid
+        */
+
+       ilfreq = ifreq;
+       m = pllsetup->pll_m;
+       n = pllsetup->pll_n;
+       p = pllsetup->pll_p;
+
+       mode = (pllsetup->cco_bypass_b15 << 2) |
+               (pllsetup->direct_output_b14 << 1) |
+       pllsetup->fdbk_div_ctrl_b13;
+
+       switch (mode) {
+       case 0x0: /* Non-integer mode */
+               cfreq = (m * ilfreq) / (2 * p * n);
+               fcco = (m * ilfreq) / n;
+               fref = ilfreq / n;
+               break;
+
+       case 0x1: /* integer mode */
+               cfreq = (m * ilfreq) / n;
+               fcco = (m * ilfreq) / (n * 2 * p);
+               fref = ilfreq / n;
+               break;
+
+       case 0x2:
+       case 0x3: /* Direct mode */
+               cfreq = (m * ilfreq) / n;
+               fcco = cfreq;
+               fref = ilfreq / n;
+               break;
+
+       case 0x4:
+       case 0x5: /* Bypass mode */
+               cfreq = ilfreq / (2 * p);
+               fcco = 156000000;
+               fref = 1000000;
+               break;
+
+       case 0x6:
+       case 0x7: /* Direct bypass mode */
+       default:
+               cfreq = ilfreq;
+               fcco = 156000000;
+               fref = 1000000;
+               break;
+       }
+
+       if (fcco < 156000000 || fcco > 320000000)
+               cfreq = 0;
+
+       if (fref < 1000000 || fref > 27000000)
+               cfreq = 0;
+
+       return (u32) cfreq;
+}
+
+u32 clk_get_pclk_div(void)
+{
+       return 1 + ((__raw_readl(LPC32XX_CLKPWR_HCLK_DIV) >> 2) & 0x1F);
+}
+
+static struct map_desc lpc32xx_io_desc[] __initdata = {
+       {
+               .virtual        = IO_ADDRESS(LPC32XX_AHB0_START),
+               .pfn            = __phys_to_pfn(LPC32XX_AHB0_START),
+               .length         = LPC32XX_AHB0_SIZE,
+               .type           = MT_DEVICE
+       },
+       {
+               .virtual        = IO_ADDRESS(LPC32XX_AHB1_START),
+               .pfn            = __phys_to_pfn(LPC32XX_AHB1_START),
+               .length         = LPC32XX_AHB1_SIZE,
+               .type           = MT_DEVICE
+       },
+       {
+               .virtual        = IO_ADDRESS(LPC32XX_FABAPB_START),
+               .pfn            = __phys_to_pfn(LPC32XX_FABAPB_START),
+               .length         = LPC32XX_FABAPB_SIZE,
+               .type           = MT_DEVICE
+       },
+       {
+               .virtual        = IO_ADDRESS(LPC32XX_IRAM_BASE),
+               .pfn            = __phys_to_pfn(LPC32XX_IRAM_BASE),
+               .length         = (LPC32XX_IRAM_BANK_SIZE * 2),
+               .type           = MT_DEVICE
+       },
+};
+
+void __init lpc32xx_map_io(void)
+{
+       iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc));
+}

diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
new file mode 100644 (file)
index 0000000..f82211f
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -0,0 +1,73 @@
+/*
+ * arch/arm/mach-lpc32xx/common.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2009-2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LPC32XX_COMMON_H
+#define __LPC32XX_COMMON_H
+
+#include <linux/platform_device.h>
+
+/*
+ * Arch specific platform device structures
+ */
+extern struct platform_device lpc32xx_watchdog_device;
+extern struct platform_device lpc32xx_i2c0_device;
+extern struct platform_device lpc32xx_i2c1_device;
+extern struct platform_device lpc32xx_i2c2_device;
+
+/*
+ * Other arch specific structures and functions
+ */
+extern struct sys_timer lpc32xx_timer;
+extern void __init lpc32xx_init_irq(void);
+extern void __init lpc32xx_map_io(void);
+extern void __init lpc32xx_serial_init(void);
+extern void __init lpc32xx_gpio_init(void);
+
+/*
+ * Structure used for setting up and querying the PLLS
+ */
+struct clk_pll_setup {
+       int analog_on;
+       int cco_bypass_b15;
+       int direct_output_b14;
+       int fdbk_div_ctrl_b13;
+       int pll_p;
+       int pll_n;
+       u32 pll_m;
+};
+
+extern int clk_is_sysclk_mainosc(void);
+extern u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup);
+extern u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval);
+extern u32 clk_get_pclk_div(void);
+
+/*
+ * Returns the LPC32xx unique 128-bit chip ID
+ */
+extern void lpc32xx_get_uid(u32 devid[4]);
+
+extern void lpc32xx_watchdog_reset(void);
+extern u32 lpc32xx_return_iram_size(void);
+
+/*
+ * Pointers used for sizing and copying suspend function data
+ */
+extern int lpc32xx_sys_suspend(void);
+extern int lpc32xx_sys_suspend_sz;
+
+#endif

diff --git a/arch/arm/mach-lpc32xx/gpiolib.c b/arch/arm/mach-lpc32xx/gpiolib.c
new file mode 100644 (file)
index 0000000..69061ea
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/gpiolib.c
@@ -0,0 +1,446 @@
+/*
+ * arch/arm/mach-lpc32xx/gpiolib.c
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/gpio.h>
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include "common.h"
+
+#define LPC32XX_GPIO_P3_INP_STATE              _GPREG(0x000)
+#define LPC32XX_GPIO_P3_OUTP_SET               _GPREG(0x004)
+#define LPC32XX_GPIO_P3_OUTP_CLR               _GPREG(0x008)
+#define LPC32XX_GPIO_P3_OUTP_STATE             _GPREG(0x00C)
+#define LPC32XX_GPIO_P2_DIR_SET                        _GPREG(0x010)
+#define LPC32XX_GPIO_P2_DIR_CLR                        _GPREG(0x014)
+#define LPC32XX_GPIO_P2_DIR_STATE              _GPREG(0x018)
+#define LPC32XX_GPIO_P2_INP_STATE              _GPREG(0x01C)
+#define LPC32XX_GPIO_P2_OUTP_SET               _GPREG(0x020)
+#define LPC32XX_GPIO_P2_OUTP_CLR               _GPREG(0x024)
+#define LPC32XX_GPIO_P2_MUX_SET                        _GPREG(0x028)
+#define LPC32XX_GPIO_P2_MUX_CLR                        _GPREG(0x02C)
+#define LPC32XX_GPIO_P2_MUX_STATE              _GPREG(0x030)
+#define LPC32XX_GPIO_P0_INP_STATE              _GPREG(0x040)
+#define LPC32XX_GPIO_P0_OUTP_SET               _GPREG(0x044)
+#define LPC32XX_GPIO_P0_OUTP_CLR               _GPREG(0x048)
+#define LPC32XX_GPIO_P0_OUTP_STATE             _GPREG(0x04C)
+#define LPC32XX_GPIO_P0_DIR_SET                        _GPREG(0x050)
+#define LPC32XX_GPIO_P0_DIR_CLR                        _GPREG(0x054)
+#define LPC32XX_GPIO_P0_DIR_STATE              _GPREG(0x058)
+#define LPC32XX_GPIO_P1_INP_STATE              _GPREG(0x060)
+#define LPC32XX_GPIO_P1_OUTP_SET               _GPREG(0x064)
+#define LPC32XX_GPIO_P1_OUTP_CLR               _GPREG(0x068)
+#define LPC32XX_GPIO_P1_OUTP_STATE             _GPREG(0x06C)
+#define LPC32XX_GPIO_P1_DIR_SET                        _GPREG(0x070)
+#define LPC32XX_GPIO_P1_DIR_CLR                        _GPREG(0x074)
+#define LPC32XX_GPIO_P1_DIR_STATE              _GPREG(0x078)
+
+#define GPIO012_PIN_TO_BIT(x)                  (1 << (x))
+#define GPIO3_PIN_TO_BIT(x)                    (1 << ((x) + 25))
+#define GPO3_PIN_TO_BIT(x)                     (1 << (x))
+#define GPIO012_PIN_IN_SEL(x, y)               (((x) >> (y)) & 1)
+#define GPIO3_PIN_IN_SHIFT(x)                  ((x) == 5 ? 24 : 10 + (x))
+#define GPIO3_PIN_IN_SEL(x, y)                 ((x) >> GPIO3_PIN_IN_SHIFT(y))
+#define GPIO3_PIN5_IN_SEL(x)                   (((x) >> 24) & 1)
+#define GPI3_PIN_IN_SEL(x, y)                  (((x) >> (y)) & 1)
+
+struct gpio_regs {
+       void __iomem *inp_state;
+       void __iomem *outp_set;
+       void __iomem *outp_clr;
+       void __iomem *dir_set;
+       void __iomem *dir_clr;
+};
+
+/*
+ * GPIO names
+ */
+static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
+       "p0.0", "p0.1", "p0.2", "p0.3",
+       "p0.4", "p0.5", "p0.6", "p0.7"
+};
+
+static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = {
+       "p1.0", "p1.1", "p1.2", "p1.3",
+       "p1.4", "p1.5", "p1.6", "p1.7",
+       "p1.8", "p1.9", "p1.10", "p1.11",
+       "p1.12", "p1.13", "p1.14", "p1.15",
+       "p1.16", "p1.17", "p1.18", "p1.19",
+       "p1.20", "p1.21", "p1.22", "p1.23",
+};
+
+static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = {
+       "p2.0", "p2.1", "p2.2", "p2.3",
+       "p2.4", "p2.5", "p2.6", "p2.7",
+       "p2.8", "p2.9", "p2.10", "p2.11",
+       "p2.12"
+};
+
+static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = {
+       "gpi000", "gpio01", "gpio02", "gpio03",
+       "gpio04", "gpio05"
+};
+
+static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = {
+       "gpi00", "gpi01", "gpi02", "gpi03",
+       "gpi04", "gpi05", "gpi06", "gpi07",
+       "gpi08", "gpi09",  NULL,    NULL,
+        NULL,    NULL,    NULL,   "gpi15",
+       "gpi16", "gpi17", "gpi18", "gpi19",
+       "gpi20", "gpi21", "gpi22", "gpi23",
+       "gpi24", "gpi25", "gpi26", "gpi27"
+};
+
+static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = {
+       "gpo00", "gpo01", "gpo02", "gpo03",
+       "gpo04", "gpo05", "gpo06", "gpo07",
+       "gpo08", "gpo09", "gpo10", "gpo11",
+       "gpo12", "gpo13", "gpo14", "gpo15",
+       "gpo16", "gpo17", "gpo18", "gpo19",
+       "gpo20", "gpo21", "gpo22", "gpo23"
+};
+
+static struct gpio_regs gpio_grp_regs_p0 = {
+       .inp_state      = LPC32XX_GPIO_P0_INP_STATE,
+       .outp_set       = LPC32XX_GPIO_P0_OUTP_SET,
+       .outp_clr       = LPC32XX_GPIO_P0_OUTP_CLR,
+       .dir_set        = LPC32XX_GPIO_P0_DIR_SET,
+       .dir_clr        = LPC32XX_GPIO_P0_DIR_CLR,
+};
+
+static struct gpio_regs gpio_grp_regs_p1 = {
+       .inp_state      = LPC32XX_GPIO_P1_INP_STATE,
+       .outp_set       = LPC32XX_GPIO_P1_OUTP_SET,
+       .outp_clr       = LPC32XX_GPIO_P1_OUTP_CLR,
+       .dir_set        = LPC32XX_GPIO_P1_DIR_SET,
+       .dir_clr        = LPC32XX_GPIO_P1_DIR_CLR,
+};
+
+static struct gpio_regs gpio_grp_regs_p2 = {
+       .inp_state      = LPC32XX_GPIO_P2_INP_STATE,
+       .outp_set       = LPC32XX_GPIO_P2_OUTP_SET,
+       .outp_clr       = LPC32XX_GPIO_P2_OUTP_CLR,
+       .dir_set        = LPC32XX_GPIO_P2_DIR_SET,
+       .dir_clr        = LPC32XX_GPIO_P2_DIR_CLR,
+};
+
+static struct gpio_regs gpio_grp_regs_p3 = {
+       .inp_state      = LPC32XX_GPIO_P3_INP_STATE,
+       .outp_set       = LPC32XX_GPIO_P3_OUTP_SET,
+       .outp_clr       = LPC32XX_GPIO_P3_OUTP_CLR,
+       .dir_set        = LPC32XX_GPIO_P2_DIR_SET,
+       .dir_clr        = LPC32XX_GPIO_P2_DIR_CLR,
+};
+
+struct lpc32xx_gpio_chip {
+       struct gpio_chip        chip;
+       struct gpio_regs        *gpio_grp;
+};
+
+static inline struct lpc32xx_gpio_chip *to_lpc32xx_gpio(
+       struct gpio_chip *gpc)
+{
+       return container_of(gpc, struct lpc32xx_gpio_chip, chip);
+}
+
+static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
+       unsigned pin, int input)
+{
+       if (input)
+               __raw_writel(GPIO012_PIN_TO_BIT(pin),
+                       group->gpio_grp->dir_clr);
+       else
+               __raw_writel(GPIO012_PIN_TO_BIT(pin),
+                       group->gpio_grp->dir_set);
+}
+
+static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
+       unsigned pin, int input)
+{
+       u32 u = GPIO3_PIN_TO_BIT(pin);
+
+       if (input)
+               __raw_writel(u, group->gpio_grp->dir_clr);
+       else
+               __raw_writel(u, group->gpio_grp->dir_set);
+}
+
+static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
+       unsigned pin, int high)
+{
+       if (high)
+               __raw_writel(GPIO012_PIN_TO_BIT(pin),
+                       group->gpio_grp->outp_set);
+       else
+               __raw_writel(GPIO012_PIN_TO_BIT(pin),
+                       group->gpio_grp->outp_clr);
+}
+
+static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
+       unsigned pin, int high)
+{
+       u32 u = GPIO3_PIN_TO_BIT(pin);
+
+       if (high)
+               __raw_writel(u, group->gpio_grp->outp_set);
+       else
+               __raw_writel(u, group->gpio_grp->outp_clr);
+}
+
+static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
+       unsigned pin, int high)
+{
+       if (high)
+               __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
+       else
+               __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
+}
+
+static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
+       unsigned pin)
+{
+       return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
+               pin);
+}
+
+static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
+       unsigned pin)
+{
+       int state = __raw_readl(group->gpio_grp->inp_state);
+
+       /*
+        * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
+        * to bits 10..14, while GPIOP3-5 is mapped to bit 24.
+        */
+       return GPIO3_PIN_IN_SEL(state, pin);
+}
+
+static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
+       unsigned pin)
+{
+       return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
+}
+
+/*
+ * GENERIC_GPIO primitives.
+ */
+static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip,
+       unsigned pin)
+{
+       struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+       __set_gpio_dir_p012(group, pin, 1);
+
+       return 0;
+}
+
+static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip,
+       unsigned pin)
+{
+       struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+       __set_gpio_dir_p3(group, pin, 1);
+
+       return 0;
+}
+
+static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip,
+       unsigned pin)
+{
+       return 0;
+}
+
+static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin)
+{
+       struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+       return __get_gpio_state_p012(group, pin);
+}
+
+static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin)
+{
+       struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+       return __get_gpio_state_p3(group, pin);
+}
+
+static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin)
+{
+       struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+       return __get_gpi_state_p3(group, pin);
+}
+
+static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin,
+       int value)
+{
+       struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+       __set_gpio_dir_p012(group, pin, 0);
+
+       return 0;
+}
+
+static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin,
+       int value)
+{
+       struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+       __set_gpio_dir_p3(group, pin, 0);
+
+       return 0;
+}
+
+static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin,
+       int value)
+{
+       return 0;
+}
+
+static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin,
+       int value)
+{
+       struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+       __set_gpio_level_p012(group, pin, value);
+}
+
+static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin,
+       int value)
+{
+       struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+       __set_gpio_level_p3(group, pin, value);
+}
+
+static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin,
+       int value)
+{
+       struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+       __set_gpo_level_p3(group, pin, value);
+}
+
+static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
+{
+       if (pin < chip->ngpio)
+               return 0;
+
+       return -EINVAL;
+}
+
+static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
+       {
+               .chip = {
+                       .label                  = "gpio_p0",
+                       .direction_input        = lpc32xx_gpio_dir_input_p012,
+                       .get                    = lpc32xx_gpio_get_value_p012,
+                       .direction_output       = lpc32xx_gpio_dir_output_p012,
+                       .set                    = lpc32xx_gpio_set_value_p012,
+                       .request                = lpc32xx_gpio_request,
+                       .base                   = LPC32XX_GPIO_P0_GRP,
+                       .ngpio                  = LPC32XX_GPIO_P0_MAX,
+                       .names                  = gpio_p0_names,
+                       .can_sleep              = 0,
+               },
+               .gpio_grp = &gpio_grp_regs_p0,
+       },
+       {
+               .chip = {
+                       .label                  = "gpio_p1",
+                       .direction_input        = lpc32xx_gpio_dir_input_p012,
+                       .get                    = lpc32xx_gpio_get_value_p012,
+                       .direction_output       = lpc32xx_gpio_dir_output_p012,
+                       .set                    = lpc32xx_gpio_set_value_p012,
+                       .request                = lpc32xx_gpio_request,
+                       .base                   = LPC32XX_GPIO_P1_GRP,
+                       .ngpio                  = LPC32XX_GPIO_P1_MAX,
+                       .names                  = gpio_p1_names,
+                       .can_sleep              = 0,
+               },
+               .gpio_grp = &gpio_grp_regs_p1,
+       },
+       {
+               .chip = {
+                       .label                  = "gpio_p2",
+                       .direction_input        = lpc32xx_gpio_dir_input_p012,
+                       .get                    = lpc32xx_gpio_get_value_p012,
+                       .direction_output       = lpc32xx_gpio_dir_output_p012,
+                       .set                    = lpc32xx_gpio_set_value_p012,
+                       .request                = lpc32xx_gpio_request,
+                       .base                   = LPC32XX_GPIO_P2_GRP,
+                       .ngpio                  = LPC32XX_GPIO_P2_MAX,
+                       .names                  = gpio_p2_names,
+                       .can_sleep              = 0,
+               },
+               .gpio_grp = &gpio_grp_regs_p2,
+       },
+       {
+               .chip = {
+                       .label                  = "gpio_p3",
+                       .direction_input        = lpc32xx_gpio_dir_input_p3,
+                       .get                    = lpc32xx_gpio_get_value_p3,
+                       .direction_output       = lpc32xx_gpio_dir_output_p3,
+                       .set                    = lpc32xx_gpio_set_value_p3,
+                       .request                = lpc32xx_gpio_request,
+                       .base                   = LPC32XX_GPIO_P3_GRP,
+                       .ngpio                  = LPC32XX_GPIO_P3_MAX,
+                       .names                  = gpio_p3_names,
+                       .can_sleep              = 0,
+               },
+               .gpio_grp = &gpio_grp_regs_p3,
+       },
+       {
+               .chip = {
+                       .label                  = "gpi_p3",
+                       .direction_input        = lpc32xx_gpio_dir_in_always,
+                       .get                    = lpc32xx_gpi_get_value,
+                       .request                = lpc32xx_gpio_request,
+                       .base                   = LPC32XX_GPI_P3_GRP,
+                       .ngpio                  = LPC32XX_GPI_P3_MAX,
+                       .names                  = gpi_p3_names,
+                       .can_sleep              = 0,
+               },
+               .gpio_grp = &gpio_grp_regs_p3,
+       },
+       {
+               .chip = {
+                       .label                  = "gpo_p3",
+                       .direction_output       = lpc32xx_gpio_dir_out_always,
+                       .set                    = lpc32xx_gpo_set_value,
+                       .request                = lpc32xx_gpio_request,
+                       .base                   = LPC32XX_GPO_P3_GRP,
+                       .ngpio                  = LPC32XX_GPO_P3_MAX,
+                       .names                  = gpo_p3_names,
+                       .can_sleep              = 0,
+               },
+               .gpio_grp = &gpio_grp_regs_p3,
+       },
+};
+
+void __init lpc32xx_gpio_init(void)
+{
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++)
+               gpiochip_add(&lpc32xx_gpiochip[i].chip);
+}

diff --git a/arch/arm/plat-mxc/include/mach/board-pcm043.h b/arch/arm/mach-lpc32xx/include/mach/clkdev.h
similarity index 57%
rename from arch/arm/plat-mxc/include/mach/board-pcm043.h
rename to arch/arm/mach-lpc32xx/include/mach/clkdev.h
index 1ac4e1682e5c2f8840a778fd65a6cabf304927ad..9bf0637e29cefd9c6f5fd0c629d06def6305b9b1 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/board-pcm043.h
+++ b/arch/arm/mach-lpc32xx/include/mach/clkdev.h
@@ -1,5 +1,9 @@
 /*
- *  Copyright (C) 2008 Sascha Hauer, Pengutronix
+ * arch/arm/mach-lpc32xx/include/mach/clkdev.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -10,13 +14,12 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
-#ifndef __ASM_ARCH_MXC_BOARD_PCM043_H__
-#define __ASM_ARCH_MXC_BOARD_PCM043_H__
+#ifndef __ASM_ARCH_CLKDEV_H
+#define __ASM_ARCH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
 
-#endif /* __ASM_ARCH_MXC_BOARD_PCM043_H__ */
+#endif

diff --git a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h b/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
similarity index 55%
rename from arch/arm/plat-mxc/include/mach/board-mx35pdk.h
rename to arch/arm/mach-lpc32xx/include/mach/debug-macro.S
index 383f1c04df06b0e8c56f84191366e120696e35e2..621744d6b15205954bbad0980b89a2315c343d3f 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h
+++ b/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
@@ -1,5 +1,9 @@
 /*
- *  Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved
+ * arch/arm/mach-lpc32xx/include/mach/debug-macro.S
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -10,13 +14,18 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
-#ifndef __ASM_ARCH_MXC_BOARD_MX35PDK_H__
-#define __ASM_ARCH_MXC_BOARD_MX35PDK_H__
+/*
+ * Debug output is hardcoded to standard UART 5
+*/
+
+       .macro  addruart,rx, tmp
+       mrc     p15, 0, \rx, c1, c0
+       tst     \rx, #1                         @ MMU enabled?
+       ldreq   \rx, =0x40090000
+       ldrne   \rx, =0xF4090000
+       .endm
 
-#endif /* __ASM_ARCH_MXC_BOARD_MX35PDK_H__ */
+#define UART_SHIFT     2
+#include <asm/hardware/debug-8250.S>

diff --git a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
new file mode 100644 (file)
index 0000000..870227c
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
@@ -0,0 +1,47 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/entry-macro.S
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+
+#define LPC32XX_INTC_MASKED_STATUS_OFS 0x8
+
+       .macro  disable_fiq
+       .endm
+
+       .macro  get_irqnr_preamble, base, tmp
+       ldr     \base, =IO_ADDRESS(LPC32XX_MIC_BASE)
+       .endm
+
+       .macro  arch_ret_to_user, tmp1, tmp2
+       .endm
+
+/*
+ * Return IRQ number in irqnr. Also return processor Z flag status in CPSR
+ * as set if an interrupt is pending.
+ */
+       .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+       ldr     \irqstat, [\base, #LPC32XX_INTC_MASKED_STATUS_OFS]
+       clz     \irqnr, \irqstat
+       rsb     \irqnr, \irqnr, #31
+       teq     \irqstat, #0
+       .endm
+
+       .macro  irq_prio_table
+       .endm
+

diff --git a/arch/arm/mach-lpc32xx/include/mach/gpio.h b/arch/arm/mach-lpc32xx/include/mach/gpio.h
new file mode 100644 (file)
index 0000000..67d03da
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/gpio.h
@@ -0,0 +1,74 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/gpio.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+#include <asm-generic/gpio.h>
+
+/*
+ * Note!
+ * Muxed GP pins need to be setup to the GP state in the board level
+ * code prior to using this driver.
+ * GPI pins : 28xP3 group
+ * GPO pins : 24xP3 group
+ * GPIO pins: 8xP0 group, 24xP1 group, 13xP2 group, 6xP3 group
+ */
+
+#define LPC32XX_GPIO_P0_MAX 8
+#define LPC32XX_GPIO_P1_MAX 24
+#define LPC32XX_GPIO_P2_MAX 13
+#define LPC32XX_GPIO_P3_MAX 6
+#define LPC32XX_GPI_P3_MAX 28
+#define LPC32XX_GPO_P3_MAX 24
+
+#define LPC32XX_GPIO_P0_GRP 0
+#define LPC32XX_GPIO_P1_GRP (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX)
+#define LPC32XX_GPIO_P2_GRP (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX)
+#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX)
+#define LPC32XX_GPI_P3_GRP (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX)
+#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
+
+/*
+ * A specific GPIO can be selected with this macro
+ * ie, GPIO_05 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
+ * See the LPC32x0 User's guide for GPIO group numbers
+ */
+#define LPC32XX_GPIO(x, y) ((x) + (y))
+
+static inline int gpio_get_value(unsigned gpio)
+{
+       return __gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+       __gpio_set_value(gpio, value);
+}
+
+static inline int gpio_cansleep(unsigned gpio)
+{
+       return __gpio_cansleep(gpio);
+}
+
+static inline int gpio_to_irq(unsigned gpio)
+{
+       return __gpio_to_irq(gpio);
+}
+
+#endif

diff --git a/arch/arm/mach-lpc32xx/include/mach/hardware.h b/arch/arm/mach-lpc32xx/include/mach/hardware.h
new file mode 100644 (file)
index 0000000..33e1dde
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/hardware.h
@@ -0,0 +1,34 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/hardware.h
+ *
+ * Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/*
+ * Start of virtual addresses for IO devices
+ */
+#define IO_BASE                0xF0000000
+
+/*
+ * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0
+ */
+#define IO_ADDRESS(x)  (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
+                        IO_BASE)
+
+#define io_p2v(x)      ((void __iomem *) (unsigned long) IO_ADDRESS(x))
+#define io_v2p(x)      ((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff))
+
+#endif

diff --git a/arch/arm/mach-lpc32xx/include/mach/i2c.h b/arch/arm/mach-lpc32xx/include/mach/i2c.h
new file mode 100644 (file)
index 0000000..034dc92
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/i2c.h
@@ -0,0 +1,63 @@
+/*
+ * PNX4008-specific tweaks for I2C IP3204 block
+ *
+ * Author: Vitaly Wool <vwool@ru.mvista.com>
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#ifndef __ASM_ARCH_I2C_H
+#define __ASM_ARCH_I2C_H
+
+enum {
+       mstatus_tdi = 0x00000001,
+       mstatus_afi = 0x00000002,
+       mstatus_nai = 0x00000004,
+       mstatus_drmi = 0x00000008,
+       mstatus_active = 0x00000020,
+       mstatus_scl = 0x00000040,
+       mstatus_sda = 0x00000080,
+       mstatus_rff = 0x00000100,
+       mstatus_rfe = 0x00000200,
+       mstatus_tff = 0x00000400,
+       mstatus_tfe = 0x00000800,
+};
+
+enum {
+       mcntrl_tdie = 0x00000001,
+       mcntrl_afie = 0x00000002,
+       mcntrl_naie = 0x00000004,
+       mcntrl_drmie = 0x00000008,
+       mcntrl_daie = 0x00000020,
+       mcntrl_rffie = 0x00000040,
+       mcntrl_tffie = 0x00000080,
+       mcntrl_reset = 0x00000100,
+       mcntrl_cdbmode = 0x00000400,
+};
+
+enum {
+       rw_bit = 1 << 0,
+       start_bit = 1 << 8,
+       stop_bit = 1 << 9,
+};
+
+#define I2C_REG_RX(a)  ((a)->ioaddr)           /* Rx FIFO reg (RO) */
+#define I2C_REG_TX(a)  ((a)->ioaddr)           /* Tx FIFO reg (WO) */
+#define I2C_REG_STS(a) ((a)->ioaddr + 0x04)    /* Status reg (RO) */
+#define I2C_REG_CTL(a) ((a)->ioaddr + 0x08)    /* Ctl reg */
+#define I2C_REG_CKL(a) ((a)->ioaddr + 0x0c)    /* Clock divider low */
+#define I2C_REG_CKH(a) ((a)->ioaddr + 0x10)    /* Clock divider high */
+#define I2C_REG_ADR(a) ((a)->ioaddr + 0x14)    /* I2C address */
+#define I2C_REG_RFL(a) ((a)->ioaddr + 0x18)    /* Rx FIFO level (RO) */
+#define I2C_REG_TFL(a) ((a)->ioaddr + 0x1c)    /* Tx FIFO level (RO) */
+#define I2C_REG_RXB(a) ((a)->ioaddr + 0x20)    /* Num of bytes Rx-ed (RO) */
+#define I2C_REG_TXB(a) ((a)->ioaddr + 0x24)    /* Num of bytes Tx-ed (RO) */
+#define I2C_REG_TXS(a) ((a)->ioaddr + 0x28)    /* Tx slave FIFO (RO) */
+#define I2C_REG_STFL(a)        ((a)->ioaddr + 0x2c)    /* Tx slave FIFO level (RO) */
+
+#define I2C_CHIP_NAME          "PNX4008-I2C"
+
+#endif                         /* __ASM_ARCH_I2C_H */

diff --git a/arch/arm/plat-mxc/include/mach/board-pcm037.h b/arch/arm/mach-lpc32xx/include/mach/io.h
similarity index 57%
rename from arch/arm/plat-mxc/include/mach/board-pcm037.h
rename to arch/arm/mach-lpc32xx/include/mach/io.h
index 13411709b13a067bdc8c7adf9ec6d984acb98f75..9b59ab5cef8942d13108fed8fe8c01c6217ea3b8 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/board-pcm037.h
+++ b/arch/arm/mach-lpc32xx/include/mach/io.h
@@ -1,5 +1,9 @@
 /*
- *  Copyright (C) 2008 Sascha Hauer, Pengutronix
+ * arch/arm/mach-lpc32xx/include/mach/io.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -10,13 +14,14 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
-#ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__
-#define __ASM_ARCH_MXC_BOARD_PCM037_H__
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#define __io(a)                __typesafe_io(a)
+#define __mem_pci(a)   (a)
 
-#endif /* __ASM_ARCH_MXC_BOARD_PCM037_H__ */
+#endif

diff --git a/arch/arm/mach-lpc32xx/include/mach/irqs.h b/arch/arm/mach-lpc32xx/include/mach/irqs.h
new file mode 100644 (file)
index 0000000..2667f52
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/irqs.h
@@ -0,0 +1,117 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/irqs.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARM_ARCH_IRQS_H
+#define __ASM_ARM_ARCH_IRQS_H
+
+#define LPC32XX_SIC1_IRQ(n)            (32 + (n))
+#define LPC32XX_SIC2_IRQ(n)            (64 + (n))
+
+/*
+ * MIC interrupts
+ */
+#define IRQ_LPC32XX_SUB1IRQ            0
+#define IRQ_LPC32XX_SUB2IRQ            1
+#define IRQ_LPC32XX_PWM3               3
+#define IRQ_LPC32XX_PWM4               4
+#define IRQ_LPC32XX_HSTIMER            5
+#define IRQ_LPC32XX_WATCH              6
+#define IRQ_LPC32XX_UART_IIR3          7
+#define IRQ_LPC32XX_UART_IIR4          8
+#define IRQ_LPC32XX_UART_IIR5          9
+#define IRQ_LPC32XX_UART_IIR6          10
+#define IRQ_LPC32XX_FLASH              11
+#define IRQ_LPC32XX_SD1                        13
+#define IRQ_LPC32XX_LCD                        14
+#define IRQ_LPC32XX_SD0                        15
+#define IRQ_LPC32XX_TIMER0             16
+#define IRQ_LPC32XX_TIMER1             17
+#define IRQ_LPC32XX_TIMER2             18
+#define IRQ_LPC32XX_TIMER3             19
+#define IRQ_LPC32XX_SSP0               20
+#define IRQ_LPC32XX_SSP1               21
+#define IRQ_LPC32XX_I2S0               22
+#define IRQ_LPC32XX_I2S1               23
+#define IRQ_LPC32XX_UART_IIR7          24
+#define IRQ_LPC32XX_UART_IIR2          25
+#define IRQ_LPC32XX_UART_IIR1          26
+#define IRQ_LPC32XX_MSTIMER            27
+#define IRQ_LPC32XX_DMA                        28
+#define IRQ_LPC32XX_ETHERNET           29
+#define IRQ_LPC32XX_SUB1FIQ            30
+#define IRQ_LPC32XX_SUB2FIQ            31
+
+/*
+ * SIC1 interrupts start at offset 32
+ */
+#define IRQ_LPC32XX_JTAG_COMM_TX       LPC32XX_SIC1_IRQ(1)
+#define IRQ_LPC32XX_JTAG_COMM_RX       LPC32XX_SIC1_IRQ(2)
+#define IRQ_LPC32XX_GPI_11             LPC32XX_SIC1_IRQ(4)
+#define IRQ_LPC32XX_TS_P               LPC32XX_SIC1_IRQ(6)
+#define IRQ_LPC32XX_TS_IRQ             LPC32XX_SIC1_IRQ(7)
+#define IRQ_LPC32XX_TS_AUX             LPC32XX_SIC1_IRQ(8)
+#define IRQ_LPC32XX_SPI2               LPC32XX_SIC1_IRQ(12)
+#define IRQ_LPC32XX_PLLUSB             LPC32XX_SIC1_IRQ(13)
+#define IRQ_LPC32XX_PLLHCLK            LPC32XX_SIC1_IRQ(14)
+#define IRQ_LPC32XX_PLL397             LPC32XX_SIC1_IRQ(17)
+#define IRQ_LPC32XX_I2C_2              LPC32XX_SIC1_IRQ(18)
+#define IRQ_LPC32XX_I2C_1              LPC32XX_SIC1_IRQ(19)
+#define IRQ_LPC32XX_RTC                        LPC32XX_SIC1_IRQ(20)
+#define IRQ_LPC32XX_KEY                        LPC32XX_SIC1_IRQ(22)
+#define IRQ_LPC32XX_SPI1               LPC32XX_SIC1_IRQ(23)
+#define IRQ_LPC32XX_SW                 LPC32XX_SIC1_IRQ(24)
+#define IRQ_LPC32XX_USB_OTG_TIMER      LPC32XX_SIC1_IRQ(25)
+#define IRQ_LPC32XX_USB_OTG_ATX                LPC32XX_SIC1_IRQ(26)
+#define IRQ_LPC32XX_USB_HOST           LPC32XX_SIC1_IRQ(27)
+#define IRQ_LPC32XX_USB_DEV_DMA                LPC32XX_SIC1_IRQ(28)
+#define IRQ_LPC32XX_USB_DEV_LP         LPC32XX_SIC1_IRQ(29)
+#define IRQ_LPC32XX_USB_DEV_HP         LPC32XX_SIC1_IRQ(30)
+#define IRQ_LPC32XX_USB_I2C            LPC32XX_SIC1_IRQ(31)
+
+/*
+ * SIC2 interrupts start at offset 64
+ */
+#define IRQ_LPC32XX_GPIO_00            LPC32XX_SIC2_IRQ(0)
+#define IRQ_LPC32XX_GPIO_01            LPC32XX_SIC2_IRQ(1)
+#define IRQ_LPC32XX_GPIO_02            LPC32XX_SIC2_IRQ(2)
+#define IRQ_LPC32XX_GPIO_03            LPC32XX_SIC2_IRQ(3)
+#define IRQ_LPC32XX_GPIO_04            LPC32XX_SIC2_IRQ(4)
+#define IRQ_LPC32XX_GPIO_05            LPC32XX_SIC2_IRQ(5)
+#define IRQ_LPC32XX_SPI2_DATAIN                LPC32XX_SIC2_IRQ(6)
+#define IRQ_LPC32XX_U2_HCTS            LPC32XX_SIC2_IRQ(7)
+#define IRQ_LPC32XX_P0_P1_IRQ          LPC32XX_SIC2_IRQ(8)
+#define IRQ_LPC32XX_GPI_08             LPC32XX_SIC2_IRQ(9)
+#define IRQ_LPC32XX_GPI_09             LPC32XX_SIC2_IRQ(10)
+#define IRQ_LPC32XX_GPI_19             LPC32XX_SIC2_IRQ(11)
+#define IRQ_LPC32XX_U7_HCTS            LPC32XX_SIC2_IRQ(12)
+#define IRQ_LPC32XX_GPI_07             LPC32XX_SIC2_IRQ(15)
+#define IRQ_LPC32XX_SDIO               LPC32XX_SIC2_IRQ(18)
+#define IRQ_LPC32XX_U5_RX              LPC32XX_SIC2_IRQ(19)
+#define IRQ_LPC32XX_SPI1_DATAIN                LPC32XX_SIC2_IRQ(20)
+#define IRQ_LPC32XX_GPI_00             LPC32XX_SIC2_IRQ(22)
+#define IRQ_LPC32XX_GPI_01             LPC32XX_SIC2_IRQ(23)
+#define IRQ_LPC32XX_GPI_02             LPC32XX_SIC2_IRQ(24)
+#define IRQ_LPC32XX_GPI_03             LPC32XX_SIC2_IRQ(25)
+#define IRQ_LPC32XX_GPI_04             LPC32XX_SIC2_IRQ(26)
+#define IRQ_LPC32XX_GPI_05             LPC32XX_SIC2_IRQ(27)
+#define IRQ_LPC32XX_GPI_06             LPC32XX_SIC2_IRQ(28)
+#define IRQ_LPC32XX_SYSCLK             LPC32XX_SIC2_IRQ(31)
+
+#define NR_IRQS                                96
+
+#endif

diff --git a/arch/arm/mach-lpc32xx/include/mach/memory.h b/arch/arm/mach-lpc32xx/include/mach/memory.h
new file mode 100644 (file)
index 0000000..044e1ac
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/memory.h
@@ -0,0 +1,27 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/memory.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset of bank 0
+ */
+#define PHYS_OFFSET    UL(0x80000000)
+
+#endif

diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h
new file mode 100644 (file)
index 0000000..14ea8d1
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/platform.h
@@ -0,0 +1,694 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/platform.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_PLATFORM_H
+#define __ASM_ARCH_PLATFORM_H
+
+#define _SBF(f, v)                             ((v) << (f))
+#define _BIT(n)                                        _SBF(n, 1)
+
+/*
+ * AHB 0 physical base addresses
+ */
+#define LPC32XX_SLC_BASE                       0x20020000
+#define LPC32XX_SSP0_BASE                      0x20084000
+#define LPC32XX_SPI1_BASE                      0x20088000
+#define LPC32XX_SSP1_BASE                      0x2008C000
+#define LPC32XX_SPI2_BASE                      0x20090000
+#define LPC32XX_I2S0_BASE                      0x20094000
+#define LPC32XX_SD_BASE                                0x20098000
+#define LPC32XX_I2S1_BASE                      0x2009C000
+#define LPC32XX_MLC_BASE                       0x200A8000
+#define LPC32XX_AHB0_START                     LPC32XX_SLC_BASE
+#define LPC32XX_AHB0_SIZE                      0x00089000
+
+/*
+ * AHB 1 physical base addresses
+ */
+#define LPC32XX_DMA_BASE                       0x31000000
+#define LPC32XX_USB_BASE                       0x31020000
+#define LPC32XX_USBH_BASE                      0x31020000
+#define LPC32XX_USB_OTG_BASE                   0x31020000
+#define LPC32XX_OTG_I2C_BASE                   0x31020300
+#define LPC32XX_LCD_BASE                       0x31040000
+#define LPC32XX_ETHERNET_BASE                  0x31060000
+#define LPC32XX_EMC_BASE                       0x31080000
+#define LPC32XX_ETB_CFG_BASE                   0x310C0000
+#define LPC32XX_ETB_DATA_BASE                  0x310E0000
+#define LPC32XX_AHB1_START                     LPC32XX_DMA_BASE
+#define LPC32XX_AHB1_SIZE                      0x000E1000
+
+/*
+ * FAB physical base addresses
+ */
+#define LPC32XX_CLK_PM_BASE                    0x40004000
+#define LPC32XX_MIC_BASE                       0x40008000
+#define LPC32XX_SIC1_BASE                      0x4000C000
+#define LPC32XX_SIC2_BASE                      0x40010000
+#define LPC32XX_HS_UART1_BASE                  0x40014000
+#define LPC32XX_HS_UART2_BASE                  0x40018000
+#define LPC32XX_HS_UART7_BASE                  0x4001C000
+#define LPC32XX_RTC_BASE                       0x40024000
+#define LPC32XX_RTC_RAM_BASE                   0x40024080
+#define LPC32XX_GPIO_BASE                      0x40028000
+#define LPC32XX_PWM3_BASE                      0x4002C000
+#define LPC32XX_PWM4_BASE                      0x40030000
+#define LPC32XX_MSTIM_BASE                     0x40034000
+#define LPC32XX_HSTIM_BASE                     0x40038000
+#define LPC32XX_WDTIM_BASE                     0x4003C000
+#define LPC32XX_DEBUG_CTRL_BASE                        0x40040000
+#define LPC32XX_TIMER0_BASE                    0x40044000
+#define LPC32XX_ADC_BASE                       0x40048000
+#define LPC32XX_TIMER1_BASE                    0x4004C000
+#define LPC32XX_KSCAN_BASE                     0x40050000
+#define LPC32XX_UART_CTRL_BASE                 0x40054000
+#define LPC32XX_TIMER2_BASE                    0x40058000
+#define LPC32XX_PWM1_BASE                      0x4005C000
+#define LPC32XX_PWM2_BASE                      0x4005C004
+#define LPC32XX_TIMER3_BASE                    0x40060000
+
+/*
+ * APB physical base addresses
+ */
+#define LPC32XX_UART3_BASE                     0x40080000
+#define LPC32XX_UART4_BASE                     0x40088000
+#define LPC32XX_UART5_BASE                     0x40090000
+#define LPC32XX_UART6_BASE                     0x40098000
+#define LPC32XX_I2C1_BASE                      0x400A0000
+#define LPC32XX_I2C2_BASE                      0x400A8000
+
+/*
+ * FAB and APB base and sizing
+ */
+#define LPC32XX_FABAPB_START                   LPC32XX_CLK_PM_BASE
+#define LPC32XX_FABAPB_SIZE                    0x000A5000
+
+/*
+ * Internal memory bases and sizes
+ */
+#define LPC32XX_IRAM_BASE                      0x08000000
+#define LPC32XX_IROM_BASE                      0x0C000000
+
+/*
+ * External Static Memory Bank Address Space Bases
+ */
+#define LPC32XX_EMC_CS0_BASE                   0xE0000000
+#define LPC32XX_EMC_CS1_BASE                   0xE1000000
+#define LPC32XX_EMC_CS2_BASE                   0xE2000000
+#define LPC32XX_EMC_CS3_BASE                   0xE3000000
+
+/*
+ * External SDRAM Memory Bank Address Space Bases
+ */
+#define LPC32XX_EMC_DYCS0_BASE                 0x80000000
+#define LPC32XX_EMC_DYCS1_BASE                 0xA0000000
+
+/*
+ * Clock and crystal information
+ */
+#define LPC32XX_MAIN_OSC_FREQ                  13000000
+#define LPC32XX_CLOCK_OSC_FREQ                 32768
+
+/*
+ * Clock and Power control register offsets
+ */
+#define _PMREG(x)                              io_p2v(LPC32XX_CLK_PM_BASE +\
+                                               (x))
+#define LPC32XX_CLKPWR_DEBUG_CTRL              _PMREG(0x000)
+#define LPC32XX_CLKPWR_BOOTMAP                 _PMREG(0x014)
+#define LPC32XX_CLKPWR_P01_ER                  _PMREG(0x018)
+#define LPC32XX_CLKPWR_USBCLK_PDIV             _PMREG(0x01C)
+#define LPC32XX_CLKPWR_INT_ER                  _PMREG(0x020)
+#define LPC32XX_CLKPWR_INT_RS                  _PMREG(0x024)
+#define LPC32XX_CLKPWR_INT_SR                  _PMREG(0x028)
+#define LPC32XX_CLKPWR_INT_AP                  _PMREG(0x02C)
+#define LPC32XX_CLKPWR_PIN_ER                  _PMREG(0x030)
+#define LPC32XX_CLKPWR_PIN_RS                  _PMREG(0x034)
+#define LPC32XX_CLKPWR_PIN_SR                  _PMREG(0x038)
+#define LPC32XX_CLKPWR_PIN_AP                  _PMREG(0x03C)
+#define LPC32XX_CLKPWR_HCLK_DIV                        _PMREG(0x040)
+#define LPC32XX_CLKPWR_PWR_CTRL                        _PMREG(0x044)
+#define LPC32XX_CLKPWR_PLL397_CTRL             _PMREG(0x048)
+#define LPC32XX_CLKPWR_MAIN_OSC_CTRL           _PMREG(0x04C)
+#define LPC32XX_CLKPWR_SYSCLK_CTRL             _PMREG(0x050)
+#define LPC32XX_CLKPWR_LCDCLK_CTRL             _PMREG(0x054)
+#define LPC32XX_CLKPWR_HCLKPLL_CTRL            _PMREG(0x058)
+#define LPC32XX_CLKPWR_ADC_CLK_CTRL_1          _PMREG(0x060)
+#define LPC32XX_CLKPWR_USB_CTRL                        _PMREG(0x064)
+#define LPC32XX_CLKPWR_SDRAMCLK_CTRL           _PMREG(0x068)
+#define LPC32XX_CLKPWR_DDR_LAP_NOM             _PMREG(0x06C)
+#define LPC32XX_CLKPWR_DDR_LAP_COUNT           _PMREG(0x070)
+#define LPC32XX_CLKPWR_DDR_LAP_DELAY           _PMREG(0x074)
+#define LPC32XX_CLKPWR_SSP_CLK_CTRL            _PMREG(0x078)
+#define LPC32XX_CLKPWR_I2S_CLK_CTRL            _PMREG(0x07C)
+#define LPC32XX_CLKPWR_MS_CTRL                 _PMREG(0x080)
+#define LPC32XX_CLKPWR_MACCLK_CTRL             _PMREG(0x090)
+#define LPC32XX_CLKPWR_TEST_CLK_SEL            _PMREG(0x0A4)
+#define LPC32XX_CLKPWR_SFW_INT                 _PMREG(0x0A8)
+#define LPC32XX_CLKPWR_I2C_CLK_CTRL            _PMREG(0x0AC)
+#define LPC32XX_CLKPWR_KEY_CLK_CTRL            _PMREG(0x0B0)
+#define LPC32XX_CLKPWR_ADC_CLK_CTRL            _PMREG(0x0B4)
+#define LPC32XX_CLKPWR_PWM_CLK_CTRL            _PMREG(0x0B8)
+#define LPC32XX_CLKPWR_TIMER_CLK_CTRL          _PMREG(0x0BC)
+#define LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1  _PMREG(0x0C0)
+#define LPC32XX_CLKPWR_SPI_CLK_CTRL            _PMREG(0x0C4)
+#define LPC32XX_CLKPWR_NAND_CLK_CTRL           _PMREG(0x0C8)
+#define LPC32XX_CLKPWR_UART3_CLK_CTRL          _PMREG(0x0D0)
+#define LPC32XX_CLKPWR_UART4_CLK_CTRL          _PMREG(0x0D4)
+#define LPC32XX_CLKPWR_UART5_CLK_CTRL          _PMREG(0x0D8)
+#define LPC32XX_CLKPWR_UART6_CLK_CTRL          _PMREG(0x0DC)
+#define LPC32XX_CLKPWR_IRDA_CLK_CTRL           _PMREG(0x0E0)
+#define LPC32XX_CLKPWR_UART_CLK_CTRL           _PMREG(0x0E4)
+#define LPC32XX_CLKPWR_DMA_CLK_CTRL            _PMREG(0x0E8)
+#define LPC32XX_CLKPWR_AUTOCLOCK               _PMREG(0x0EC)
+#define LPC32XX_CLKPWR_DEVID(x)                        _PMREG(0x130 + (x))
+
+/*
+ * clkpwr_debug_ctrl register definitions
+*/
+#define LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT    _BIT(4)
+
+/*
+ * clkpwr_bootmap register definitions
+ */
+#define LPC32XX_CLKPWR_BOOTMAP_SEL_BIT         _BIT(1)
+
+/*
+ * clkpwr_start_gpio register bit definitions
+ */
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO23_BIT      _BIT(31)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO22_BIT      _BIT(30)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO21_BIT      _BIT(29)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO20_BIT      _BIT(28)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO19_BIT      _BIT(27)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO18_BIT      _BIT(26)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO17_BIT      _BIT(25)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO16_BIT      _BIT(24)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO15_BIT      _BIT(23)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO14_BIT      _BIT(22)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO13_BIT      _BIT(21)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO12_BIT      _BIT(20)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO11_BIT      _BIT(19)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO10_BIT      _BIT(18)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO9_BIT       _BIT(17)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO8_BIT       _BIT(16)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO7_BIT       _BIT(15)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO6_BIT       _BIT(14)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO5_BIT       _BIT(13)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO4_BIT       _BIT(12)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO3_BIT       _BIT(11)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO2_BIT       _BIT(10)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO1_BIT       _BIT(9)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO0_BIT       _BIT(8)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO7_BIT       _BIT(7)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO6_BIT       _BIT(6)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO5_BIT       _BIT(5)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO4_BIT       _BIT(4)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO3_BIT       _BIT(3)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO2_BIT       _BIT(2)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO1_BIT       _BIT(1)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO0_BIT       _BIT(0)
+
+/*
+ * clkpwr_usbclk_pdiv register definitions
+ */
+#define LPC32XX_CLKPWR_USBPDIV_PLL_MASK                0xF
+
+/*
+ * clkpwr_start_int, clkpwr_start_raw_sts_int, clkpwr_start_sts_int,
+ * clkpwr_start_pol_int, register bit definitions
+ */
+#define LPC32XX_CLKPWR_INTSRC_ADC_BIT          _BIT(31)
+#define LPC32XX_CLKPWR_INTSRC_TS_P_BIT         _BIT(30)
+#define LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT       _BIT(29)
+#define LPC32XX_CLKPWR_INTSRC_USBAHNEEDCLK_BIT _BIT(26)
+#define LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT      _BIT(25)
+#define LPC32XX_CLKPWR_INTSRC_RTC_BIT          _BIT(24)
+#define LPC32XX_CLKPWR_INTSRC_USBNEEDCLK_BIT   _BIT(23)
+#define LPC32XX_CLKPWR_INTSRC_USB_BIT          _BIT(22)
+#define LPC32XX_CLKPWR_INTSRC_I2C_BIT          _BIT(21)
+#define LPC32XX_CLKPWR_INTSRC_USBOTGTIMER_BIT  _BIT(20)
+#define LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT    _BIT(19)
+#define LPC32XX_CLKPWR_INTSRC_KEY_BIT          _BIT(16)
+#define LPC32XX_CLKPWR_INTSRC_MAC_BIT          _BIT(7)
+#define LPC32XX_CLKPWR_INTSRC_P0P1_BIT         _BIT(6)
+#define LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT      _BIT(5)
+#define LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT      _BIT(4)
+#define LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT      _BIT(3)
+#define LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT      _BIT(2)
+#define LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT      _BIT(1)
+#define LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT      _BIT(0)
+
+/*
+ * clkpwr_start_pin, clkpwr_start_raw_sts_pin, clkpwr_start_sts_pin,
+ * clkpwr_start_pol_pin register bit definitions
+ */
+#define LPC32XX_CLKPWR_EXTSRC_U7_RX_BIT                _BIT(31)
+#define LPC32XX_CLKPWR_EXTSRC_U7_HCTS_BIT      _BIT(30)
+#define LPC32XX_CLKPWR_EXTSRC_U6_IRRX_BIT      _BIT(28)
+#define LPC32XX_CLKPWR_EXTSRC_U5_RX_BIT                _BIT(26)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT       _BIT(25)
+#define LPC32XX_CLKPWR_EXTSRC_U3_RX_BIT                _BIT(24)
+#define LPC32XX_CLKPWR_EXTSRC_U2_HCTS_BIT      _BIT(23)
+#define LPC32XX_CLKPWR_EXTSRC_U2_RX_BIT                _BIT(22)
+#define LPC32XX_CLKPWR_EXTSRC_U1_RX_BIT                _BIT(21)
+#define LPC32XX_CLKPWR_EXTSRC_MSDIO_INT_BIT    _BIT(18)
+#define LPC32XX_CLKPWR_EXTSRC_MSDIO_SRT_BIT    _BIT(17)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT       _BIT(16)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT       _BIT(15)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT       _BIT(14)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT       _BIT(13)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT       _BIT(12)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT       _BIT(11)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT       _BIT(10)
+#define LPC32XX_CLKPWR_EXTSRC_SYSCLKEN_BIT     _BIT(9)
+#define LPC32XX_CLKPWR_EXTSRC_SPI1_DATIN_BIT   _BIT(8)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT       _BIT(7)
+#define LPC32XX_CLKPWR_EXTSRC_SPI2_DATIN_BIT   _BIT(6)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT       _BIT(5)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT       _BIT(4)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT       _BIT(3)
+
+/*
+ * clkpwr_hclk_div register definitions
+ */
+#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_STOP     (0x0 << 7)
+#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_NORM     (0x1 << 7)
+#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_HALF     (0x2 << 7)
+#define LPC32XX_CLKPWR_HCLKDIV_PCLK_DIV(n)     (((n) & 0x1F) << 2)
+#define LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(n)     ((n) & 0x3)
+
+/*
+ * clkpwr_pwr_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_CTRL_FORCE_PCLK         _BIT(10)
+#define LPC32XX_CLKPWR_SDRAM_SELF_RFSH         _BIT(9)
+#define LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH     _BIT(8)
+#define LPC32XX_CLKPWR_AUTO_SDRAM_SELF_RFSH    _BIT(7)
+#define LPC32XX_CLKPWR_HIGHCORE_STATE_BIT      _BIT(5)
+#define LPC32XX_CLKPWR_SYSCLKEN_STATE_BIT      _BIT(4)
+#define LPC32XX_CLKPWR_SYSCLKEN_GPIO_EN                _BIT(3)
+#define LPC32XX_CLKPWR_SELECT_RUN_MODE         _BIT(2)
+#define LPC32XX_CLKPWR_HIGHCORE_GPIO_EN                _BIT(1)
+#define LPC32XX_CLKPWR_STOP_MODE_CTRL          _BIT(0)
+
+/*
+ * clkpwr_pll397_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_PLL397_MSLOCK_STS       _BIT(10)
+#define LPC32XX_CLKPWR_PLL397_BYPASS           _BIT(9)
+#define LPC32XX_CLKPWR_PLL397_BIAS_NORM                0x000
+#define LPC32XX_CLKPWR_PLL397_BIAS_N12_5       0x040
+#define LPC32XX_CLKPWR_PLL397_BIAS_N25         0x080
+#define LPC32XX_CLKPWR_PLL397_BIAS_N37_5       0x0C0
+#define LPC32XX_CLKPWR_PLL397_BIAS_P12_5       0x100
+#define LPC32XX_CLKPWR_PLL397_BIAS_P25         0x140
+#define LPC32XX_CLKPWR_PLL397_BIAS_P37_5       0x180
+#define LPC32XX_CLKPWR_PLL397_BIAS_P50         0x1C0
+#define LPC32XX_CLKPWR_PLL397_BIAS_MASK                0x1C0
+#define LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS      _BIT(1)
+#define LPC32XX_CLKPWR_SYSCTRL_PLL397_STS      _BIT(0)
+
+/*
+ * clkpwr_main_osc_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_MOSC_ADD_CAP(n)         (((n) & 0x7F) << 2)
+#define LPC32XX_CLKPWR_MOSC_CAP_MASK           (0x7F << 2)
+#define LPC32XX_CLKPWR_TEST_MODE               _BIT(1)
+#define LPC32XX_CLKPWR_MOSC_DISABLE            _BIT(0)
+
+/*
+ * clkpwr_sysclk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_SYSCTRL_BP_TRIG(n)      (((n) & 0x3FF) << 2)
+#define LPC32XX_CLKPWR_SYSCTRL_BP_MASK         (0x3FF << 2)
+#define LPC32XX_CLKPWR_SYSCTRL_USEPLL397       _BIT(1)
+#define LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX       _BIT(0)
+
+/*
+ * clkpwr_lcdclk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT12   0x000
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16   0x040
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT15   0x080
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT24   0x0C0
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN4M   0x100
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN8C   0x140
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN4M  0x180
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN8C  0x1C0
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK     0x01C0
+#define LPC32XX_CLKPWR_LCDCTRL_CLK_EN          0x020
+#define LPC32XX_CLKPWR_LCDCTRL_SET_PSCALE(n)   ((n - 1) & 0x1F)
+#define LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK      0x001F
+
+/*
+ * clkpwr_hclkpll_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_HCLKPLL_POWER_UP                _BIT(16)
+#define LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS      _BIT(15)
+#define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS  _BIT(14)
+#define LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK   _BIT(13)
+#define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(n) (((n) & 0x3) << 11)
+#define LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(n) (((n) & 0x3) << 9)
+#define LPC32XX_CLKPWR_HCLKPLL_PLLM(n)         (((n) & 0xFF) << 1)
+#define LPC32XX_CLKPWR_HCLKPLL_PLL_STS         _BIT(0)
+
+/*
+ * clkpwr_adc_clk_ctrl_1 register definitions
+ */
+#define LPC32XX_CLKPWR_ADCCTRL1_RTDIV(n)       (((n) & 0xFF) << 0)
+#define LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL       _BIT(8)
+
+/*
+ * clkpwr_usb_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_USBCTRL_HCLK_EN         _BIT(24)
+#define LPC32XX_CLKPWR_USBCTRL_USBI2C_EN       _BIT(23)
+#define LPC32XX_CLKPWR_USBCTRL_USBDVND_EN      _BIT(22)
+#define LPC32XX_CLKPWR_USBCTRL_USBHSTND_EN     _BIT(21)
+#define LPC32XX_CLKPWR_USBCTRL_PU_ADD          (0x0 << 19)
+#define LPC32XX_CLKPWR_USBCTRL_BUS_KEEPER      (0x1 << 19)
+#define LPC32XX_CLKPWR_USBCTRL_PD_ADD          (0x3 << 19)
+#define LPC32XX_CLKPWR_USBCTRL_CLK_EN2         _BIT(18)
+#define LPC32XX_CLKPWR_USBCTRL_CLK_EN1         _BIT(17)
+#define LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP       _BIT(16)
+#define LPC32XX_CLKPWR_USBCTRL_CCO_BYPASS      _BIT(15)
+#define LPC32XX_CLKPWR_USBCTRL_POSTDIV_BYPASS  _BIT(14)
+#define LPC32XX_CLKPWR_USBCTRL_FDBK_SEL_FCLK   _BIT(13)
+#define LPC32XX_CLKPWR_USBCTRL_POSTDIV_2POW(n) (((n) & 0x3) << 11)
+#define LPC32XX_CLKPWR_USBCTRL_PREDIV_PLUS1(n) (((n) & 0x3) << 9)
+#define LPC32XX_CLKPWR_USBCTRL_FDBK_PLUS1(n)   (((n) & 0xFF) << 1)
+#define LPC32XX_CLKPWR_USBCTRL_PLL_STS         _BIT(0)
+
+/*
+ * clkpwr_sdramclk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_CLK     _BIT(22)
+#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW         _BIT(21)
+#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_DAT     _BIT(20)
+#define LPC32XX_CLKPWR_SDRCLK_SW_DDR_RESET     _BIT(19)
+#define LPC32XX_CLKPWR_SDRCLK_HCLK_DLY(n)      (((n) & 0x1F) << 14)
+#define LPC32XX_CLKPWR_SDRCLK_DLY_ADDR_STS     _BIT(13)
+#define LPC32XX_CLKPWR_SDRCLK_SENS_FACT(n)     (((n) & 0x7) << 10)
+#define LPC32XX_CLKPWR_SDRCLK_USE_CAL          _BIT(9)
+#define LPC32XX_CLKPWR_SDRCLK_DO_CAL           _BIT(8)
+#define LPC32XX_CLKPWR_SDRCLK_CAL_ON_RTC       _BIT(7)
+#define LPC32XX_CLKPWR_SDRCLK_DQS_DLY(n)       (((n) & 0x1F) << 2)
+#define LPC32XX_CLKPWR_SDRCLK_USE_DDR          _BIT(1)
+#define LPC32XX_CLKPWR_SDRCLK_CLK_DIS          _BIT(0)
+
+/*
+ * clkpwr_ssp_blk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1RX      _BIT(5)
+#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1TX      _BIT(4)
+#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0RX      _BIT(3)
+#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0TX      _BIT(2)
+#define LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN      _BIT(1)
+#define LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN      _BIT(0)
+
+/*
+ * clkpwr_i2s_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_I2SCTRL_I2S1_RX_FOR_TX  _BIT(6)
+#define LPC32XX_CLKPWR_I2SCTRL_I2S1_TX_FOR_RX  _BIT(5)
+#define LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA    _BIT(4)
+#define LPC32XX_CLKPWR_I2SCTRL_I2S0_RX_FOR_TX  _BIT(3)
+#define LPC32XX_CLKPWR_I2SCTRL_I2S0_TX_FOR_RX  _BIT(2)
+#define LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN      _BIT(1)
+#define LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN      _BIT(0)
+
+/*
+ * clkpwr_ms_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS    _BIT(10)
+#define LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN      _BIT(9)
+#define LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS      _BIT(8)
+#define LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS       _BIT(7)
+#define LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS       _BIT(6)
+#define LPC32XX_CLKPWR_MSCARD_SDCARD_EN                _BIT(5)
+#define LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(n)    ((n) & 0xF)
+
+/*
+ * clkpwr_macclk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_MACCTRL_NO_ENET_PIS     0x00
+#define LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS    0x08
+#define LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS   0x18
+#define LPC32XX_CLKPWR_MACCTRL_PINS_MSK                0x18
+#define LPC32XX_CLKPWR_MACCTRL_DMACLK_EN       _BIT(2)
+#define LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN      _BIT(1)
+#define LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN       _BIT(0)
+
+/*
+ * clkpwr_test_clk_sel register definitions
+ */
+#define LPC32XX_CLKPWR_TESTCLK1_SEL_PERCLK     (0x0 << 5)
+#define LPC32XX_CLKPWR_TESTCLK1_SEL_RTC                (0x1 << 5)
+#define LPC32XX_CLKPWR_TESTCLK1_SEL_MOSC       (0x2 << 5)
+#define LPC32XX_CLKPWR_TESTCLK1_SEL_MASK       (0x3 << 5)
+#define LPC32XX_CLKPWR_TESTCLK_TESTCLK1_EN     _BIT(4)
+#define LPC32XX_CLKPWR_TESTCLK2_SEL_HCLK       (0x0 << 1)
+#define LPC32XX_CLKPWR_TESTCLK2_SEL_PERCLK     (0x1 << 1)
+#define LPC32XX_CLKPWR_TESTCLK2_SEL_USBCLK     (0x2 << 1)
+#define LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC       (0x5 << 1)
+#define LPC32XX_CLKPWR_TESTCLK2_SEL_PLL397     (0x7 << 1)
+#define LPC32XX_CLKPWR_TESTCLK2_SEL_MASK       (0x7 << 1)
+#define LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN     _BIT(0)
+
+/*
+ * clkpwr_sw_int register definitions
+ */
+#define LPC32XX_CLKPWR_SW_INT(n)               (_BIT(0) | (((n) & 0x7F) << 1))
+#define LPC32XX_CLKPWR_SW_GET_ARG(n)           (((n) & 0xFE) >> 1)
+
+/*
+ * clkpwr_i2c_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE   _BIT(4)
+#define LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE     _BIT(3)
+#define LPC32XX_CLKPWR_I2CCLK_I2C1HI_DRIVE     _BIT(2)
+#define LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN       _BIT(1)
+#define LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN       _BIT(0)
+
+/*
+ * clkpwr_key_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN       0x1
+
+/*
+ * clkpwr_adc_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN     0x1
+
+/*
+ * clkpwr_pwm_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(n)      (((n) & 0xF) << 8)
+#define LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(n)      (((n) & 0xF) << 4)
+#define LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK     0x8
+#define LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN       0x4
+#define LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK     0x2
+#define LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN       0x1
+
+/*
+ * clkpwr_timer_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_PWMCLK_HSTIMER_EN       0x2
+#define LPC32XX_CLKPWR_PWMCLK_WDOG_EN          0x1
+
+/*
+ * clkpwr_timers_pwms_clk_ctrl_1 register definitions
+ */
+#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN     0x20
+#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN     0x10
+#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN     0x08
+#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN     0x04
+#define LPC32XX_CLKPWR_TMRPWMCLK_PWM4_EN       0x02
+#define LPC32XX_CLKPWR_TMRPWMCLK_PWM3_EN       0x01
+
+/*
+ * clkpwr_spi_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_SPICLK_SET_SPI2DATIO    0x80
+#define LPC32XX_CLKPWR_SPICLK_SET_SPI2CLK      0x40
+#define LPC32XX_CLKPWR_SPICLK_USE_SPI2         0x20
+#define LPC32XX_CLKPWR_SPICLK_SPI2CLK_EN       0x10
+#define LPC32XX_CLKPWR_SPICLK_SET_SPI1DATIO    0x08
+#define LPC32XX_CLKPWR_SPICLK_SET_SPI1CLK      0x04
+#define LPC32XX_CLKPWR_SPICLK_USE_SPI1         0x02
+#define LPC32XX_CLKPWR_SPICLK_SPI1CLK_EN       0x01
+
+/*
+ * clkpwr_nand_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC      0x20
+#define LPC32XX_CLKPWR_NANDCLK_DMA_RNB         0x10
+#define LPC32XX_CLKPWR_NANDCLK_DMA_INT         0x08
+#define LPC32XX_CLKPWR_NANDCLK_SEL_SLC         0x04
+#define LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN       0x02
+#define LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN       0x01
+
+/*
+ * clkpwr_uart3_clk_ctrl, clkpwr_uart4_clk_ctrl, clkpwr_uart5_clk_ctrl
+ * and clkpwr_uart6_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_UART_Y_DIV(y)           ((y) & 0xFF)
+#define LPC32XX_CLKPWR_UART_X_DIV(x)           (((x) & 0xFF) << 8)
+#define LPC32XX_CLKPWR_UART_USE_HCLK           _BIT(16)
+
+/*
+ * clkpwr_irda_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_IRDA_Y_DIV(y)           ((y) & 0xFF)
+#define LPC32XX_CLKPWR_IRDA_X_DIV(x)           (((x) & 0xFF) << 8)
+
+/*
+ * clkpwr_uart_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN    _BIT(3)
+#define LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN    _BIT(2)
+#define LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN    _BIT(1)
+#define LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN    _BIT(0)
+
+/*
+ * clkpwr_dmaclk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN       0x1
+
+/*
+ * clkpwr_autoclock register definitions
+ */
+#define LPC32XX_CLKPWR_AUTOCLK_USB_EN          0x40
+#define LPC32XX_CLKPWR_AUTOCLK_IRAM_EN         0x02
+#define LPC32XX_CLKPWR_AUTOCLK_IROM_EN         0x01
+
+/*
+ * Interrupt controller register offsets
+ */
+#define LPC32XX_INTC_MASK(x)                   io_p2v((x) + 0x00)
+#define LPC32XX_INTC_RAW_STAT(x)               io_p2v((x) + 0x04)
+#define LPC32XX_INTC_STAT(x)                   io_p2v((x) + 0x08)
+#define LPC32XX_INTC_POLAR(x)                  io_p2v((x) + 0x0C)
+#define LPC32XX_INTC_ACT_TYPE(x)               io_p2v((x) + 0x10)
+#define LPC32XX_INTC_TYPE(x)                   io_p2v((x) + 0x14)
+
+/*
+ * Timer/counter register offsets
+ */
+#define LCP32XX_TIMER_IR(x)                    io_p2v((x) + 0x00)
+#define LCP32XX_TIMER_TCR(x)                   io_p2v((x) + 0x04)
+#define LCP32XX_TIMER_TC(x)                    io_p2v((x) + 0x08)
+#define LCP32XX_TIMER_PR(x)                    io_p2v((x) + 0x0C)
+#define LCP32XX_TIMER_PC(x)                    io_p2v((x) + 0x10)
+#define LCP32XX_TIMER_MCR(x)                   io_p2v((x) + 0x14)
+#define LCP32XX_TIMER_MR0(x)                   io_p2v((x) + 0x18)
+#define LCP32XX_TIMER_MR1(x)                   io_p2v((x) + 0x1C)
+#define LCP32XX_TIMER_MR2(x)                   io_p2v((x) + 0x20)
+#define LCP32XX_TIMER_MR3(x)                   io_p2v((x) + 0x24)
+#define LCP32XX_TIMER_CCR(x)                   io_p2v((x) + 0x28)
+#define LCP32XX_TIMER_CR0(x)                   io_p2v((x) + 0x2C)
+#define LCP32XX_TIMER_CR1(x)                   io_p2v((x) + 0x30)
+#define LCP32XX_TIMER_CR2(x)                   io_p2v((x) + 0x34)
+#define LCP32XX_TIMER_CR3(x)                   io_p2v((x) + 0x38)
+#define LCP32XX_TIMER_EMR(x)                   io_p2v((x) + 0x3C)
+#define LCP32XX_TIMER_CTCR(x)                  io_p2v((x) + 0x70)
+
+/*
+ * ir register definitions
+ */
+#define LCP32XX_TIMER_CNTR_MTCH_BIT(n)         (1 << ((n) & 0x3))
+#define LCP32XX_TIMER_CNTR_CAPT_BIT(n)         (1 << (4 + ((n) & 0x3)))
+
+/*
+ * tcr register definitions
+ */
+#define LCP32XX_TIMER_CNTR_TCR_EN              0x1
+#define LCP32XX_TIMER_CNTR_TCR_RESET           0x2
+
+/*
+ * mcr register definitions
+ */
+#define LCP32XX_TIMER_CNTR_MCR_MTCH(n)         (0x1 << ((n) * 3))
+#define LCP32XX_TIMER_CNTR_MCR_RESET(n)                (0x1 << (((n) * 3) + 1))
+#define LCP32XX_TIMER_CNTR_MCR_STOP(n)         (0x1 << (((n) * 3) + 2))
+
+/*
+ * Standard UART register offsets
+ */
+#define LPC32XX_UART_DLL_FIFO(x)               io_p2v((x) + 0x00)
+#define LPC32XX_UART_DLM_IER(x)                        io_p2v((x) + 0x04)
+#define LPC32XX_UART_IIR_FCR(x)                        io_p2v((x) + 0x08)
+#define LPC32XX_UART_LCR(x)                    io_p2v((x) + 0x0C)
+#define LPC32XX_UART_MODEM_CTRL(x)             io_p2v((x) + 0x10)
+#define LPC32XX_UART_LSR(x)                    io_p2v((x) + 0x14)
+#define LPC32XX_UART_MODEM_STATUS(x)           io_p2v((x) + 0x18)
+#define LPC32XX_UART_RXLEV(x)                  io_p2v((x) + 0x1C)
+
+/*
+ * UART control structure offsets
+ */
+#define _UCREG(x)                              io_p2v(\
+                                               LPC32XX_UART_CTRL_BASE + (x))
+#define LPC32XX_UARTCTL_CTRL                   _UCREG(0x00)
+#define LPC32XX_UARTCTL_CLKMODE                        _UCREG(0x04)
+#define LPC32XX_UARTCTL_CLOOP                  _UCREG(0x08)
+
+/*
+ * ctrl register definitions
+ */
+#define LPC32XX_UART_U3_MD_CTRL_EN             _BIT(11)
+#define LPC32XX_UART_IRRX6_INV_EN              _BIT(10)
+#define LPC32XX_UART_HDPX_EN                   _BIT(9)
+#define LPC32XX_UART_UART6_IRDAMOD_BYPASS      _BIT(5)
+#define LPC32XX_RT_IRTX6_INV_EN                        _BIT(4)
+#define LPC32XX_RT_IRTX6_INV_MIR_EN            _BIT(3)
+#define LPC32XX_RT_RX_IRPULSE_3_16_115K                _BIT(2)
+#define LPC32XX_RT_TX_IRPULSE_3_16_115K                _BIT(1)
+#define LPC32XX_UART_U5_ROUTE_TO_USB           _BIT(0)
+
+/*
+ * clkmode register definitions
+ */
+#define LPC32XX_UART_ENABLED_CLOCKS(n)         (((n) >> 16) & 0x7F)
+#define LPC32XX_UART_ENABLED_CLOCK(n, u)       (((n) >> (16 + (u))) & 0x1)
+#define LPC32XX_UART_ENABLED_CLKS_ANY          _BIT(14)
+#define LPC32XX_UART_CLKMODE_OFF               0x0
+#define LPC32XX_UART_CLKMODE_ON                        0x1
+#define LPC32XX_UART_CLKMODE_AUTO              0x2
+#define LPC32XX_UART_CLKMODE_MASK(u)           (0x3 << ((((u) - 3) * 2) + 4))
+#define LPC32XX_UART_CLKMODE_LOAD(m, u)                ((m) << ((((u) - 3) * 2) + 4))
+
+/*
+ * GPIO Module Register offsets
+ */
+#define _GPREG(x)                              io_p2v(LPC32XX_GPIO_BASE + (x))
+#define LPC32XX_GPIO_P_MUX_SET                 _GPREG(0x100)
+#define LPC32XX_GPIO_P_MUX_CLR                 _GPREG(0x104)
+#define LPC32XX_GPIO_P_MUX_STATE               _GPREG(0x108)
+#define LPC32XX_GPIO_P3_MUX_SET                        _GPREG(0x110)
+#define LPC32XX_GPIO_P3_MUX_CLR                        _GPREG(0x114)
+#define LPC32XX_GPIO_P3_MUX_STATE              _GPREG(0x118)
+#define LPC32XX_GPIO_P0_MUX_SET                        _GPREG(0x120)
+#define LPC32XX_GPIO_P0_MUX_CLR                        _GPREG(0x124)
+#define LPC32XX_GPIO_P0_MUX_STATE              _GPREG(0x128)
+#define LPC32XX_GPIO_P1_MUX_SET                        _GPREG(0x130)
+#define LPC32XX_GPIO_P1_MUX_CLR                        _GPREG(0x134)
+#define LPC32XX_GPIO_P1_MUX_STATE              _GPREG(0x138)
+
+#endif

diff --git a/arch/arm/mach-lpc32xx/include/mach/system.h b/arch/arm/mach-lpc32xx/include/mach/system.h
new file mode 100644 (file)
index 0000000..df3b0de
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/system.h
@@ -0,0 +1,52 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/system.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+static void arch_idle(void)
+{
+       cpu_do_idle();
+}
+
+static inline void arch_reset(char mode, const char *cmd)
+{
+       extern void lpc32xx_watchdog_reset(void);
+
+       switch (mode) {
+       case 's':
+       case 'h':
+               printk(KERN_CRIT "RESET: Rebooting system\n");
+
+               /* Disable interrupts */
+               local_irq_disable();
+
+               lpc32xx_watchdog_reset();
+               break;
+
+       default:
+               /* Do nothing */
+               break;
+       }
+
+       /* Wait for watchdog to reset system */
+       while (1)
+               ;
+}
+
+#endif

diff --git a/arch/arm/mach-lpc32xx/include/mach/timex.h b/arch/arm/mach-lpc32xx/include/mach/timex.h
new file mode 100644 (file)
index 0000000..8d4066b
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/timex.h
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/timex.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+/*
+ * Rate in Hz of the main system oscillator. This value should match
+ * the value 'MAIN_OSC_FREQ' in platform.h
+ */
+#define CLOCK_TICK_RATE        13000000
+
+#endif

diff --git a/arch/arm/mach-lpc32xx/include/mach/uncompress.h b/arch/arm/mach-lpc32xx/include/mach/uncompress.h
new file mode 100644 (file)
index 0000000..c142487
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/uncompress.h
@@ -0,0 +1,60 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/uncompress.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARM_ARCH_UNCOMPRESS_H
+#define __ASM_ARM_ARCH_UNCOMPRESS_H
+
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+
+/*
+ * Uncompress output is hardcoded to standard UART 5
+ */
+
+#define UART_FIFO_CTL_TX_RESET (1 << 2)
+#define UART_STATUS_TX_MT      (1 << 6)
+
+#define _UARTREG(x)            (void __iomem *)(LPC32XX_UART5_BASE + (x))
+
+#define LPC32XX_UART_DLLFIFO_O 0x00
+#define LPC32XX_UART_IIRFCR_O  0x08
+#define LPC32XX_UART_LSR_O     0x14
+
+static inline void putc(int ch)
+{
+       /* Wait for transmit FIFO to empty */
+       while ((__raw_readl(_UARTREG(LPC32XX_UART_LSR_O)) &
+               UART_STATUS_TX_MT) == 0)
+               ;
+
+       __raw_writel((u32) ch, _UARTREG(LPC32XX_UART_DLLFIFO_O));
+}
+
+static inline void flush(void)
+{
+       __raw_writel(__raw_readl(_UARTREG(LPC32XX_UART_IIRFCR_O)) |
+               UART_FIFO_CTL_TX_RESET, _UARTREG(LPC32XX_UART_IIRFCR_O));
+}
+
+/* NULL functions; we don't presently need them */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+
+#endif

diff --git a/arch/arm/mach-lpc32xx/include/mach/vmalloc.h b/arch/arm/mach-lpc32xx/include/mach/vmalloc.h
new file mode 100644 (file)
index 0000000..d1d936c
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/vmalloc.h
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/vmalloc.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H
+
+#define VMALLOC_END    0xF0000000
+
+#endif

diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
new file mode 100644 (file)
index 0000000..bd0df26
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -0,0 +1,432 @@
+/*
+ * arch/arm/mach-lpc32xx/irq.c
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <mach/irqs.h>
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include "common.h"
+
+/*
+ * Default value representing the Activation polarity of all internal
+ * interrupt sources
+ */
+#define MIC_APR_DEFAULT                0x3FF0EFE0
+#define SIC1_APR_DEFAULT       0xFBD27186
+#define SIC2_APR_DEFAULT       0x801810C0
+
+/*
+ * Default value representing the Activation Type of all internal
+ * interrupt sources. All are level sensitive.
+ */
+#define MIC_ATR_DEFAULT                0x00000000
+#define SIC1_ATR_DEFAULT       0x00026000
+#define SIC2_ATR_DEFAULT       0x00000000
+
+struct lpc32xx_event_group_regs {
+       void __iomem *enab_reg;
+       void __iomem *edge_reg;
+       void __iomem *maskstat_reg;
+       void __iomem *rawstat_reg;
+};
+
+static const struct lpc32xx_event_group_regs lpc32xx_event_int_regs = {
+       .enab_reg = LPC32XX_CLKPWR_INT_ER,
+       .edge_reg = LPC32XX_CLKPWR_INT_AP,
+       .maskstat_reg = LPC32XX_CLKPWR_INT_SR,
+       .rawstat_reg = LPC32XX_CLKPWR_INT_RS,
+};
+
+static const struct lpc32xx_event_group_regs lpc32xx_event_pin_regs = {
+       .enab_reg = LPC32XX_CLKPWR_PIN_ER,
+       .edge_reg = LPC32XX_CLKPWR_PIN_AP,
+       .maskstat_reg = LPC32XX_CLKPWR_PIN_SR,
+       .rawstat_reg = LPC32XX_CLKPWR_PIN_RS,
+};
+
+struct lpc32xx_event_info {
+       const struct lpc32xx_event_group_regs *event_group;
+       u32 mask;
+};
+
+/*
+ * Maps an IRQ number to and event mask and register
+ */
+static const struct lpc32xx_event_info lpc32xx_events[NR_IRQS] = {
+       [IRQ_LPC32XX_GPI_08] = {
+               .event_group = &lpc32xx_event_pin_regs,
+               .mask = LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT,
+       },
+       [IRQ_LPC32XX_GPI_09] = {
+               .event_group = &lpc32xx_event_pin_regs,
+               .mask = LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT,
+       },
+       [IRQ_LPC32XX_GPI_19] = {
+               .event_group = &lpc32xx_event_pin_regs,
+               .mask = LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT,
+       },
+       [IRQ_LPC32XX_GPI_07] = {
+               .event_group = &lpc32xx_event_pin_regs,
+               .mask = LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT,
+       },
+       [IRQ_LPC32XX_GPI_00] = {
+               .event_group = &lpc32xx_event_pin_regs,
+               .mask = LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT,
+       },
+       [IRQ_LPC32XX_GPI_01] = {
+               .event_group = &lpc32xx_event_pin_regs,
+               .mask = LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT,
+       },
+       [IRQ_LPC32XX_GPI_02] = {
+               .event_group = &lpc32xx_event_pin_regs,
+               .mask = LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT,
+       },
+       [IRQ_LPC32XX_GPI_03] = {
+               .event_group = &lpc32xx_event_pin_regs,
+               .mask = LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT,
+       },
+       [IRQ_LPC32XX_GPI_04] = {
+               .event_group = &lpc32xx_event_pin_regs,
+               .mask = LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT,
+       },
+       [IRQ_LPC32XX_GPI_05] = {
+               .event_group = &lpc32xx_event_pin_regs,
+               .mask = LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT,
+       },
+       [IRQ_LPC32XX_GPI_06] = {
+               .event_group = &lpc32xx_event_pin_regs,
+               .mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT,
+       },
+       [IRQ_LPC32XX_GPIO_00] = {
+               .event_group = &lpc32xx_event_int_regs,
+               .mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT,
+       },
+       [IRQ_LPC32XX_GPIO_01] = {
+               .event_group = &lpc32xx_event_int_regs,
+               .mask = LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT,
+       },
+       [IRQ_LPC32XX_GPIO_02] = {
+               .event_group = &lpc32xx_event_int_regs,
+               .mask = LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT,
+       },
+       [IRQ_LPC32XX_GPIO_03] = {
+               .event_group = &lpc32xx_event_int_regs,
+               .mask = LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT,
+       },
+       [IRQ_LPC32XX_GPIO_04] = {
+               .event_group = &lpc32xx_event_int_regs,
+               .mask = LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT,
+       },
+       [IRQ_LPC32XX_GPIO_05] = {
+               .event_group = &lpc32xx_event_int_regs,
+               .mask = LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT,
+       },
+       [IRQ_LPC32XX_KEY] = {
+               .event_group = &lpc32xx_event_int_regs,
+               .mask = LPC32XX_CLKPWR_INTSRC_KEY_BIT,
+       },
+       [IRQ_LPC32XX_USB_OTG_ATX] = {
+               .event_group = &lpc32xx_event_int_regs,
+               .mask = LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT,
+       },
+       [IRQ_LPC32XX_USB_HOST] = {
+               .event_group = &lpc32xx_event_int_regs,
+               .mask = LPC32XX_CLKPWR_INTSRC_USB_BIT,
+       },
+       [IRQ_LPC32XX_RTC] = {
+               .event_group = &lpc32xx_event_int_regs,
+               .mask = LPC32XX_CLKPWR_INTSRC_RTC_BIT,
+       },
+       [IRQ_LPC32XX_MSTIMER] = {
+               .event_group = &lpc32xx_event_int_regs,
+               .mask = LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT,
+       },
+       [IRQ_LPC32XX_TS_AUX] = {
+               .event_group = &lpc32xx_event_int_regs,
+               .mask = LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT,
+       },
+       [IRQ_LPC32XX_TS_P] = {
+               .event_group = &lpc32xx_event_int_regs,
+               .mask = LPC32XX_CLKPWR_INTSRC_TS_P_BIT,
+       },
+       [IRQ_LPC32XX_TS_IRQ] = {
+               .event_group = &lpc32xx_event_int_regs,
+               .mask = LPC32XX_CLKPWR_INTSRC_ADC_BIT,
+       },
+};
+
+static void get_controller(unsigned int irq, unsigned int *base,
+       unsigned int *irqbit)
+{
+       if (irq < 32) {
+               *base = LPC32XX_MIC_BASE;
+               *irqbit = 1 << irq;
+       } else if (irq < 64) {
+               *base = LPC32XX_SIC1_BASE;
+               *irqbit = 1 << (irq - 32);
+       } else {
+               *base = LPC32XX_SIC2_BASE;
+               *irqbit = 1 << (irq - 64);
+       }
+}
+
+static void lpc32xx_mask_irq(unsigned int irq)
+{
+       unsigned int reg, ctrl, mask;
+
+       get_controller(irq, &ctrl, &mask);
+
+       reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask;
+       __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
+}
+
+static void lpc32xx_unmask_irq(unsigned int irq)
+{
+       unsigned int reg, ctrl, mask;
+
+       get_controller(irq, &ctrl, &mask);
+
+       reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask;
+       __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
+}
+
+static void lpc32xx_ack_irq(unsigned int irq)
+{
+       unsigned int ctrl, mask;
+
+       get_controller(irq, &ctrl, &mask);
+
+       __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl));
+
+       /* Also need to clear pending wake event */
+       if (lpc32xx_events[irq].mask != 0)
+               __raw_writel(lpc32xx_events[irq].mask,
+                       lpc32xx_events[irq].event_group->rawstat_reg);
+}
+
+static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level,
+       int use_edge)
+{
+       unsigned int reg, ctrl, mask;
+
+       get_controller(irq, &ctrl, &mask);
+
+       /* Activation level, high or low */
+       reg = __raw_readl(LPC32XX_INTC_POLAR(ctrl));
+       if (use_high_level)
+               reg |= mask;
+       else
+               reg &= ~mask;
+       __raw_writel(reg, LPC32XX_INTC_POLAR(ctrl));
+
+       /* Activation type, edge or level */
+       reg = __raw_readl(LPC32XX_INTC_ACT_TYPE(ctrl));
+       if (use_edge)
+               reg |= mask;
+       else
+               reg &= ~mask;
+       __raw_writel(reg, LPC32XX_INTC_ACT_TYPE(ctrl));
+
+       /* Use same polarity for the wake events */
+       if (lpc32xx_events[irq].mask != 0) {
+               reg = __raw_readl(lpc32xx_events[irq].event_group->edge_reg);
+
+               if (use_high_level)
+                       reg |= lpc32xx_events[irq].mask;
+               else
+                       reg &= ~lpc32xx_events[irq].mask;
+
+               __raw_writel(reg, lpc32xx_events[irq].event_group->edge_reg);
+       }
+}
+
+static int lpc32xx_set_irq_type(unsigned int irq, unsigned int type)
+{
+       switch (type) {
+       case IRQ_TYPE_EDGE_RISING:
+               /* Rising edge sensitive */
+               __lpc32xx_set_irq_type(irq, 1, 1);
+               break;
+
+       case IRQ_TYPE_EDGE_FALLING:
+               /* Falling edge sensitive */
+               __lpc32xx_set_irq_type(irq, 0, 1);
+               break;
+
+       case IRQ_TYPE_LEVEL_LOW:
+               /* Low level sensitive */
+               __lpc32xx_set_irq_type(irq, 0, 0);
+               break;
+
+       case IRQ_TYPE_LEVEL_HIGH:
+               /* High level sensitive */
+               __lpc32xx_set_irq_type(irq, 1, 0);
+               break;
+
+       /* Other modes are not supported */
+       default:
+               return -EINVAL;
+       }
+
+       /* Ok to use the level handler for all types */
+       set_irq_handler(irq, handle_level_irq);
+
+       return 0;
+}
+
+static int lpc32xx_irq_wake(unsigned int irqno, unsigned int state)
+{
+       unsigned long eventreg;
+
+       if (lpc32xx_events[irqno].mask != 0) {
+               eventreg = __raw_readl(lpc32xx_events[irqno].
+                       event_group->enab_reg);
+
+               if (state)
+                       eventreg |= lpc32xx_events[irqno].mask;
+               else
+                       eventreg &= ~lpc32xx_events[irqno].mask;
+
+               __raw_writel(eventreg,
+                       lpc32xx_events[irqno].event_group->enab_reg);
+
+               return 0;
+       }
+
+       /* Clear event */
+       __raw_writel(lpc32xx_events[irqno].mask,
+               lpc32xx_events[irqno].event_group->rawstat_reg);
+
+       return -ENODEV;
+}
+
+static void __init lpc32xx_set_default_mappings(unsigned int apr,
+       unsigned int atr, unsigned int offset)
+{
+       unsigned int i;
+
+       /* Set activation levels for each interrupt */
+       i = 0;
+       while (i < 32) {
+               __lpc32xx_set_irq_type(offset + i, ((apr >> i) & 0x1),
+                       ((atr >> i) & 0x1));
+               i++;
+       }
+}
+
+static struct irq_chip lpc32xx_irq_chip = {
+       .ack = lpc32xx_ack_irq,
+       .mask = lpc32xx_mask_irq,
+       .unmask = lpc32xx_unmask_irq,
+       .set_type = lpc32xx_set_irq_type,
+       .set_wake = lpc32xx_irq_wake
+};
+
+static void lpc32xx_sic1_handler(unsigned int irq, struct irq_desc *desc)
+{
+       unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC1_BASE));
+
+       while (ints != 0) {
+               int irqno = fls(ints) - 1;
+
+               ints &= ~(1 << irqno);
+
+               generic_handle_irq(LPC32XX_SIC1_IRQ(irqno));
+       }
+}
+
+static void lpc32xx_sic2_handler(unsigned int irq, struct irq_desc *desc)
+{
+       unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC2_BASE));
+
+       while (ints != 0) {
+               int irqno = fls(ints) - 1;
+
+               ints &= ~(1 << irqno);
+
+               generic_handle_irq(LPC32XX_SIC2_IRQ(irqno));
+       }
+}
+
+void __init lpc32xx_init_irq(void)
+{
+       unsigned int i;
+
+       /* Setup MIC */
+       __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));
+       __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_MIC_BASE));
+       __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_MIC_BASE));
+
+       /* Setup SIC1 */
+       __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));
+       __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE));
+       __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE));
+
+       /* Setup SIC2 */
+       __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
+       __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE));
+       __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE));
+
+       /* Configure supported IRQ's */
+       for (i = 0; i < NR_IRQS; i++) {
+               set_irq_chip(i, &lpc32xx_irq_chip);
+               set_irq_handler(i, handle_level_irq);
+               set_irq_flags(i, IRQF_VALID);
+       }
+
+       /* Set default mappings */
+       lpc32xx_set_default_mappings(MIC_APR_DEFAULT, MIC_ATR_DEFAULT, 0);
+       lpc32xx_set_default_mappings(SIC1_APR_DEFAULT, SIC1_ATR_DEFAULT, 32);
+       lpc32xx_set_default_mappings(SIC2_APR_DEFAULT, SIC2_ATR_DEFAULT, 64);
+
+       /* mask all interrupts except SUBIRQ */
+       __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));
+       __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));
+       __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
+
+       /* MIC SUBIRQx interrupts will route handling to the chain handlers */
+       set_irq_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler);
+       set_irq_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler);
+
+       /* Initially disable all wake events */
+       __raw_writel(0, LPC32XX_CLKPWR_P01_ER);
+       __raw_writel(0, LPC32XX_CLKPWR_INT_ER);
+       __raw_writel(0, LPC32XX_CLKPWR_PIN_ER);
+
+       /*
+        * Default wake activation polarities, all pin sources are low edge
+        * triggered
+        */
+       __raw_writel(LPC32XX_CLKPWR_INTSRC_TS_P_BIT |
+               LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT |
+               LPC32XX_CLKPWR_INTSRC_RTC_BIT,
+               LPC32XX_CLKPWR_INT_AP);
+       __raw_writel(0, LPC32XX_CLKPWR_PIN_AP);
+
+       /* Clear latched wake event states */
+       __raw_writel(__raw_readl(LPC32XX_CLKPWR_PIN_RS),
+               LPC32XX_CLKPWR_PIN_RS);
+       __raw_writel(__raw_readl(LPC32XX_CLKPWR_INT_RS),
+               LPC32XX_CLKPWR_INT_RS);
+}

diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
new file mode 100644 (file)
index 0000000..bc9a42d
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -0,0 +1,397 @@
+/*
+ * arch/arm/mach-lpc32xx/phy3250.c
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/sysdev.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/dma-mapping.h>
+#include <linux/device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/eeprom.h>
+#include <linux/leds.h>
+#include <linux/gpio.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/clcd.h>
+#include <linux/amba/pl022.h>
+
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include "common.h"
+
+/*
+ * Mapped GPIOLIB GPIOs
+ */
+#define SPI0_CS_GPIO   LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
+#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
+#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
+#define LED_GPIO       LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 1)
+
+/*
+ * AMBA LCD controller
+ */
+static struct clcd_panel conn_lcd_panel = {
+       .mode           = {
+               .name           = "QVGA portrait",
+               .refresh        = 60,
+               .xres           = 240,
+               .yres           = 320,
+               .pixclock       = 191828,
+               .left_margin    = 22,
+               .right_margin   = 11,
+               .upper_margin   = 2,
+               .lower_margin   = 1,
+               .hsync_len      = 5,
+               .vsync_len      = 2,
+               .sync           = 0,
+               .vmode          = FB_VMODE_NONINTERLACED,
+       },
+       .width          = -1,
+       .height         = -1,
+       .tim2           = (TIM2_IVS | TIM2_IHS),
+       .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
+                               CNTL_LCDBPP16_565),
+       .bpp            = 16,
+};
+#define PANEL_SIZE (3 * SZ_64K)
+
+static int lpc32xx_clcd_setup(struct clcd_fb *fb)
+{
+       dma_addr_t dma;
+
+       fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
+               PANEL_SIZE, &dma, GFP_KERNEL);
+       if (!fb->fb.screen_base) {
+               printk(KERN_ERR "CLCD: unable to map framebuffer\n");
+               return -ENOMEM;
+       }
+
+       fb->fb.fix.smem_start = dma;
+       fb->fb.fix.smem_len = PANEL_SIZE;
+       fb->panel = &conn_lcd_panel;
+
+       if (gpio_request(LCD_POWER_GPIO, "LCD power"))
+               printk(KERN_ERR "Error requesting gpio %u",
+                       LCD_POWER_GPIO);
+       else if (gpio_direction_output(LCD_POWER_GPIO, 1))
+               printk(KERN_ERR "Error setting gpio %u to output",
+                       LCD_POWER_GPIO);
+
+       if (gpio_request(BKL_POWER_GPIO, "LCD backlight power"))
+               printk(KERN_ERR "Error requesting gpio %u",
+                       BKL_POWER_GPIO);
+       else if (gpio_direction_output(BKL_POWER_GPIO, 1))
+               printk(KERN_ERR "Error setting gpio %u to output",
+                       BKL_POWER_GPIO);
+
+       return 0;
+}
+
+static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
+{
+       return dma_mmap_writecombine(&fb->dev->dev, vma,
+               fb->fb.screen_base, fb->fb.fix.smem_start,
+               fb->fb.fix.smem_len);
+}
+
+static void lpc32xx_clcd_remove(struct clcd_fb *fb)
+{
+       dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
+               fb->fb.screen_base, fb->fb.fix.smem_start);
+}
+
+/*
+ * On some early LCD modules (1307.0), the backlight logic is inverted.
+ * For those board variants, swap the disable and enable states for
+ * BKL_POWER_GPIO.
+*/
+static void clcd_disable(struct clcd_fb *fb)
+{
+       gpio_set_value(BKL_POWER_GPIO, 0);
+       gpio_set_value(LCD_POWER_GPIO, 0);
+}
+
+static void clcd_enable(struct clcd_fb *fb)
+{
+       gpio_set_value(BKL_POWER_GPIO, 1);
+       gpio_set_value(LCD_POWER_GPIO, 1);
+}
+
+static struct clcd_board lpc32xx_clcd_data = {
+       .name           = "Phytec LCD",
+       .check          = clcdfb_check,
+       .decode         = clcdfb_decode,
+       .disable        = clcd_disable,
+       .enable         = clcd_enable,
+       .setup          = lpc32xx_clcd_setup,
+       .mmap           = lpc32xx_clcd_mmap,
+       .remove         = lpc32xx_clcd_remove,
+};
+
+static struct amba_device lpc32xx_clcd_device = {
+       .dev                            = {
+               .coherent_dma_mask      = ~0,
+               .init_name              = "dev:clcd",
+               .platform_data          = &lpc32xx_clcd_data,
+       },
+       .res                            = {
+               .start                  = LPC32XX_LCD_BASE,
+               .end                    = (LPC32XX_LCD_BASE + SZ_4K - 1),
+               .flags                  = IORESOURCE_MEM,
+       },
+       .dma_mask                       = ~0,
+       .irq                            = {IRQ_LPC32XX_LCD, NO_IRQ},
+};
+
+/*
+ * AMBA SSP (SPI)
+ */
+static void phy3250_spi_cs_set(u32 control)
+{
+       gpio_set_value(SPI0_CS_GPIO, (int) control);
+}
+
+static struct pl022_config_chip spi0_chip_info = {
+       .lbm                    = LOOPBACK_DISABLED,
+       .com_mode               = INTERRUPT_TRANSFER,
+       .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
+       .hierarchy              = SSP_MASTER,
+       .slave_tx_disable       = 0,
+       .endian_tx              = SSP_TX_LSB,
+       .endian_rx              = SSP_RX_LSB,
+       .data_size              = SSP_DATA_BITS_8,
+       .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
+       .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
+       .clk_phase              = SSP_CLK_FIRST_EDGE,
+       .clk_pol                = SSP_CLK_POL_IDLE_LOW,
+       .ctrl_len               = SSP_BITS_8,
+       .wait_state             = SSP_MWIRE_WAIT_ZERO,
+       .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
+       .cs_control             = phy3250_spi_cs_set,
+};
+
+static struct pl022_ssp_controller lpc32xx_ssp0_data = {
+       .bus_id                 = 0,
+       .num_chipselect         = 1,
+       .enable_dma             = 0,
+};
+
+static struct amba_device lpc32xx_ssp0_device = {
+       .dev                            = {
+               .coherent_dma_mask      = ~0,
+               .init_name              = "dev:ssp0",
+               .platform_data          = &lpc32xx_ssp0_data,
+       },
+       .res                            = {
+               .start                  = LPC32XX_SSP0_BASE,
+               .end                    = (LPC32XX_SSP0_BASE + SZ_4K - 1),
+               .flags                  = IORESOURCE_MEM,
+       },
+       .dma_mask                       = ~0,
+       .irq                            = {IRQ_LPC32XX_SSP0, NO_IRQ},
+};
+
+/* AT25 driver registration */
+static int __init phy3250_spi_board_register(void)
+{
+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+       static struct spi_board_info info[] = {
+               {
+                       .modalias = "spidev",
+                       .max_speed_hz = 5000000,
+                       .bus_num = 0,
+                       .chip_select = 0,
+                       .controller_data = &spi0_chip_info,
+               },
+       };
+
+#else
+       static struct spi_eeprom eeprom = {
+               .name = "at25256a",
+               .byte_len = 0x8000,
+               .page_size = 64,
+               .flags = EE_ADDR2,
+       };
+
+       static struct spi_board_info info[] = {
+               {
+                       .modalias = "at25",
+                       .max_speed_hz = 5000000,
+                       .bus_num = 0,
+                       .chip_select = 0,
+                       .platform_data = &eeprom,
+                       .controller_data = &spi0_chip_info,
+               },
+       };
+#endif
+       return spi_register_board_info(info, ARRAY_SIZE(info));
+}
+arch_initcall(phy3250_spi_board_register);
+
+static struct i2c_board_info __initdata phy3250_i2c_board_info[] = {
+       {
+               I2C_BOARD_INFO("pcf8563", 0x51),
+       },
+};
+
+static struct gpio_led phy_leds[] = {
+       {
+               .name                   = "led0",
+               .gpio                   = LED_GPIO,
+               .active_low             = 1,
+               .default_trigger        = "heartbeat",
+       },
+};
+
+static struct gpio_led_platform_data led_data = {
+       .leds = phy_leds,
+       .num_leds = ARRAY_SIZE(phy_leds),
+};
+
+static struct platform_device lpc32xx_gpio_led_device = {
+       .name                   = "leds-gpio",
+       .id                     = -1,
+       .dev.platform_data      = &led_data,
+};
+
+static struct platform_device *phy3250_devs[] __initdata = {
+       &lpc32xx_i2c0_device,
+       &lpc32xx_i2c1_device,
+       &lpc32xx_i2c2_device,
+       &lpc32xx_watchdog_device,
+       &lpc32xx_gpio_led_device,
+};
+
+static struct amba_device *amba_devs[] __initdata = {
+       &lpc32xx_clcd_device,
+       &lpc32xx_ssp0_device,
+};
+
+/*
+ * Board specific functions
+ */
+static void __init phy3250_board_init(void)
+{
+       u32 tmp;
+       int i;
+
+       lpc32xx_gpio_init();
+
+       /* Register GPIOs used on this board */
+       if (gpio_request(SPI0_CS_GPIO, "spi0 cs"))
+               printk(KERN_ERR "Error requesting gpio %u",
+                       SPI0_CS_GPIO);
+       else if (gpio_direction_output(SPI0_CS_GPIO, 1))
+               printk(KERN_ERR "Error setting gpio %u to output",
+                       SPI0_CS_GPIO);
+
+       /* Setup network interface for RMII mode */
+       tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
+       tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
+       tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
+       __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
+
+       /* Setup SLC NAND controller muxing */
+       __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
+               LPC32XX_CLKPWR_NAND_CLK_CTRL);
+
+       /* Setup LCD muxing to RGB565 */
+       tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
+               ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
+               LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK);
+       tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
+       __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
+
+       /* Set up I2C pull levels */
+       tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
+       tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
+               LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
+       __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
+
+       /* Disable IrDA pulsing support on UART6 */
+       tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
+       tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
+       __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
+
+       /* Enable DMA for I2S1 channel */
+       tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL);
+       tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA;
+       __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL);
+
+       lpc32xx_serial_init();
+
+       /*
+        * AMBA peripheral clocks need to be enabled prior to AMBA device
+        * detection or a data fault will occur, so enable the clocks
+        * here. However, we don't want to enable them if the peripheral
+        * isn't included in the image
+        */
+#ifdef CONFIG_FB_ARMCLCD
+       tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
+       __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
+               LPC32XX_CLKPWR_LCDCLK_CTRL);
+#endif
+#ifdef CONFIG_SPI_PL022
+       tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
+       __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
+               LPC32XX_CLKPWR_SSP_CLK_CTRL);
+#endif
+
+       platform_add_devices(phy3250_devs, ARRAY_SIZE(phy3250_devs));
+       for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
+               struct amba_device *d = amba_devs[i];
+               amba_device_register(d, &iomem_resource);
+       }
+
+       /* Test clock needed for UDA1380 initial init */
+       __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
+               LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
+               LPC32XX_CLKPWR_TEST_CLK_SEL);
+
+       i2c_register_board_info(0, phy3250_i2c_board_info,
+               ARRAY_SIZE(phy3250_i2c_board_info));
+}
+
+static int __init lpc32xx_display_uid(void)
+{
+       u32 uid[4];
+
+       lpc32xx_get_uid(uid);
+
+       printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
+               uid[3], uid[2], uid[1], uid[0]);
+
+       return 1;
+}
+arch_initcall(lpc32xx_display_uid);
+
+MACHINE_START(PHY3250, "Phytec 3250 board with the LPC3250 Microcontroller")
+       /* Maintainer: Kevin Wells, NXP Semiconductors */
+       .phys_io        = LPC32XX_UART5_BASE,
+       .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
+       .boot_params    = 0x80000100,
+       .map_io         = lpc32xx_map_io,
+       .init_irq       = lpc32xx_init_irq,
+       .timer          = &lpc32xx_timer,
+       .init_machine   = phy3250_board_init,
+MACHINE_END

diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c
new file mode 100644 (file)
index 0000000..a6e2aed
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/pm.c
@@ -0,0 +1,146 @@
+/*
+ * arch/arm/mach-lpc32xx/pm.c
+ *
+ * Original authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
+ * Modified by Kevin Wells <kevin.wells@nxp.com>
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+/*
+ * LPC32XX CPU and system power management
+ *
+ * The LCP32XX has three CPU modes for controlling system power: run,
+ * direct-run, and halt modes. When switching between halt and run modes,
+ * the CPU transistions through direct-run mode. For Linux, direct-run
+ * mode is not used in normal operation. Halt mode is used when the
+ * system is fully suspended.
+ *
+ * Run mode:
+ * The ARM CPU clock (HCLK_PLL), HCLK bus clock, and PCLK bus clocks are
+ * derived from the HCLK PLL. The HCLK and PCLK bus rates are divided from
+ * the HCLK_PLL rate. Linux runs in this mode.
+ *
+ * Direct-run mode:
+ * The ARM CPU clock, HCLK bus clock, and PCLK bus clocks are driven from
+ * SYSCLK. SYSCLK is usually around 13MHz, but may vary based on SYSCLK
+ * source or the frequency of the main oscillator. In this mode, the
+ * HCLK_PLL can be safely enabled, changed, or disabled.
+ *
+ * Halt mode:
+ * SYSCLK is gated off and the CPU and system clocks are halted.
+ * Peripherals based on the 32KHz oscillator clock (ie, RTC, touch,
+ * key scanner, etc.) still operate if enabled. In this state, an enabled
+ * system event (ie, GPIO state change, RTC match, key press, etc.) will
+ * wake the system up back into direct-run mode.
+ *
+ * DRAM refresh
+ * DRAM clocking and refresh are slightly different for systems with DDR
+ * DRAM or regular SDRAM devices. If SDRAM is used in the system, the
+ * SDRAM will still be accessible in direct-run mode. In DDR based systems,
+ * a transistion to direct-run mode will stop all DDR accesses (no clocks).
+ * Because of this, the code to switch power modes and the code to enter
+ * and exit DRAM self-refresh modes must not be executed in DRAM. A small
+ * section of IRAM is used instead for this.
+ *
+ * Suspend is handled with the following logic:
+ *  Backup a small area of IRAM used for the suspend code
+ *  Copy suspend code to IRAM
+ *  Transfer control to code in IRAM
+ *  Places DRAMs in self-refresh mode
+ *  Enter direct-run mode
+ *  Save state of HCLK_PLL PLL
+ *  Disable HCLK_PLL PLL
+ *  Enter halt mode - CPU and buses will stop
+ *  System enters direct-run mode when an enabled event occurs
+ *  HCLK PLL state is restored
+ *  Run mode is entered
+ *  DRAMS are placed back into normal mode
+ *  Code execution returns from IRAM
+ *  IRAM code are used for suspend is restored
+ *  Suspend mode is exited
+ */
+
+#include <linux/suspend.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+
+#include <asm/cacheflush.h>
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include "common.h"
+#include "clock.h"
+
+#define TEMP_IRAM_AREA  IO_ADDRESS(LPC32XX_IRAM_BASE)
+
+/*
+ * Both STANDBY and MEM suspend states are handled the same with no
+ * loss of CPU or memory state
+ */
+static int lpc32xx_pm_enter(suspend_state_t state)
+{
+       int (*lpc32xx_suspend_ptr) (void);
+       void *iram_swap_area;
+
+       /* Allocate some space for temporary IRAM storage */
+       iram_swap_area = kmalloc(lpc32xx_sys_suspend_sz, GFP_KERNEL);
+       if (!iram_swap_area) {
+               printk(KERN_ERR
+                      "PM Suspend: cannot allocate memory to save portion "
+                       "of SRAM\n");
+               return -ENOMEM;
+       }
+
+       /* Backup a small area of IRAM used for the suspend code */
+       memcpy(iram_swap_area, (void *) TEMP_IRAM_AREA,
+               lpc32xx_sys_suspend_sz);
+
+       /*
+        * Copy code to suspend system into IRAM. The suspend code
+        * needs to run from IRAM as DRAM may no longer be available
+        * when the PLL is stopped.
+        */
+       memcpy((void *) TEMP_IRAM_AREA, &lpc32xx_sys_suspend,
+               lpc32xx_sys_suspend_sz);
+       flush_icache_range((unsigned long)TEMP_IRAM_AREA,
+               (unsigned long)(TEMP_IRAM_AREA) + lpc32xx_sys_suspend_sz);
+
+       /* Transfer to suspend code in IRAM */
+       lpc32xx_suspend_ptr = (void *) TEMP_IRAM_AREA;
+       flush_cache_all();
+       (void) lpc32xx_suspend_ptr();
+
+       /* Restore original IRAM contents */
+       memcpy((void *) TEMP_IRAM_AREA, iram_swap_area,
+               lpc32xx_sys_suspend_sz);
+
+       kfree(iram_swap_area);
+
+       return 0;
+}
+
+static struct platform_suspend_ops lpc32xx_pm_ops = {
+       .valid  = suspend_valid_only_mem,
+       .enter  = lpc32xx_pm_enter,
+};
+
+#define EMC_DYN_MEM_CTRL_OFS 0x20
+#define EMC_SRMMC           (1 << 3)
+#define EMC_CTRL_REG io_p2v(LPC32XX_EMC_BASE + EMC_DYN_MEM_CTRL_OFS)
+static int __init lpc32xx_pm_init(void)
+{
+       /*
+        * Setup SDRAM self-refresh clock to automatically disable o
+        * start of self-refresh. This only needs to be done once.
+        */
+       __raw_writel(__raw_readl(EMC_CTRL_REG) | EMC_SRMMC, EMC_CTRL_REG);
+
+       suspend_set_ops(&lpc32xx_pm_ops);
+
+       return 0;
+}
+arch_initcall(lpc32xx_pm_init);

diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c
new file mode 100644 (file)
index 0000000..429cfdb
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/serial.c
@@ -0,0 +1,190 @@
+/*
+ * arch/arm/mach-lpc32xx/serial.c
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/serial_reg.h>
+#include <linux/serial_8250.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include "common.h"
+
+#define LPC32XX_SUART_FIFO_SIZE        64
+
+/* Standard 8250/16550 compatible serial ports */
+static struct plat_serial8250_port serial_std_platform_data[] = {
+#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT
+       {
+               .membase        = io_p2v(LPC32XX_UART5_BASE),
+               .mapbase        = LPC32XX_UART5_BASE,
+               .irq            = IRQ_LPC32XX_UART_IIR5,
+               .uartclk        = LPC32XX_MAIN_OSC_FREQ,
+               .regshift       = 2,
+               .iotype         = UPIO_MEM32,
+               .flags          = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
+                                       UPF_SKIP_TEST,
+       },
+#endif
+#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
+       {
+               .membase        = io_p2v(LPC32XX_UART3_BASE),
+               .mapbase        = LPC32XX_UART3_BASE,
+               .irq            = IRQ_LPC32XX_UART_IIR3,
+               .uartclk        = LPC32XX_MAIN_OSC_FREQ,
+               .regshift       = 2,
+               .iotype         = UPIO_MEM32,
+               .flags          = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
+                                       UPF_SKIP_TEST,
+       },
+#endif
+#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
+       {
+               .membase        = io_p2v(LPC32XX_UART4_BASE),
+               .mapbase        = LPC32XX_UART4_BASE,
+               .irq            = IRQ_LPC32XX_UART_IIR4,
+               .uartclk        = LPC32XX_MAIN_OSC_FREQ,
+               .regshift       = 2,
+               .iotype         = UPIO_MEM32,
+               .flags          = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
+                                       UPF_SKIP_TEST,
+       },
+#endif
+#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
+       {
+               .membase        = io_p2v(LPC32XX_UART6_BASE),
+               .mapbase        = LPC32XX_UART6_BASE,
+               .irq            = IRQ_LPC32XX_UART_IIR6,
+               .uartclk        = LPC32XX_MAIN_OSC_FREQ,
+               .regshift       = 2,
+               .iotype         = UPIO_MEM32,
+               .flags          = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
+                                       UPF_SKIP_TEST,
+       },
+#endif
+       { },
+};
+
+struct uartinit {
+       char *uart_ck_name;
+       u32 ck_mode_mask;
+       void __iomem *pdiv_clk_reg;
+};
+
+static struct uartinit uartinit_data[] __initdata = {
+#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT
+       {
+               .uart_ck_name = "uart5_ck",
+               .ck_mode_mask =
+                       LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5),
+               .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,
+       },
+#endif
+#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
+       {
+               .uart_ck_name = "uart3_ck",
+               .ck_mode_mask =
+                       LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3),
+               .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,
+       },
+#endif
+#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
+       {
+               .uart_ck_name = "uart4_ck",
+               .ck_mode_mask =
+                       LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4),
+               .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,
+       },
+#endif
+#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
+       {
+               .uart_ck_name = "uart6_ck",
+               .ck_mode_mask =
+                       LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6),
+               .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,
+       },
+#endif
+};
+
+static struct platform_device serial_std_platform_device = {
+       .name                   = "serial8250",
+       .id                     = 0,
+       .dev                    = {
+               .platform_data  = serial_std_platform_data,
+       },
+};
+
+static struct platform_device *lpc32xx_serial_devs[] __initdata = {
+       &serial_std_platform_device,
+};
+
+void __init lpc32xx_serial_init(void)
+{
+       u32 tmp, clkmodes = 0;
+       struct clk *clk;
+       unsigned int puart;
+       int i, j;
+
+       /* UART clocks are off, let clock driver manage them */
+       __raw_writel(0, LPC32XX_CLKPWR_UART_CLK_CTRL);
+
+       for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
+               clk = clk_get(NULL, uartinit_data[i].uart_ck_name);
+               if (!IS_ERR(clk)) {
+                       clk_enable(clk);
+                       serial_std_platform_data[i].uartclk =
+                               clk_get_rate(clk);
+               }
+
+               /* Fall back on main osc rate if clock rate return fails */
+               if (serial_std_platform_data[i].uartclk == 0)
+                       serial_std_platform_data[i].uartclk =
+                               LPC32XX_MAIN_OSC_FREQ;
+
+               /* Setup UART clock modes for all UARTs, disable autoclock */
+               clkmodes |= uartinit_data[i].ck_mode_mask;
+
+               /* pre-UART clock divider set to 1 */
+               __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg);
+       }
+
+       /* This needs to be done after all UART clocks are setup */
+       __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);
+       for (i = 0; i < ARRAY_SIZE(uartinit_data) - 1; i++) {
+               /* Force a flush of the RX FIFOs to work around a HW bug */
+               puart = serial_std_platform_data[i].mapbase;
+               __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
+               __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
+               j = LPC32XX_SUART_FIFO_SIZE;
+               while (j--)
+                       tmp = __raw_readl(LPC32XX_UART_DLL_FIFO(puart));
+               __raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
+       }
+
+       /* Disable UART5->USB transparent mode or USB won't work */
+       tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
+       tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
+       __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
+
+       platform_add_devices(lpc32xx_serial_devs,
+               ARRAY_SIZE(lpc32xx_serial_devs));
+}

diff --git a/arch/arm/mach-lpc32xx/suspend.S b/arch/arm/mach-lpc32xx/suspend.S
new file mode 100644 (file)
index 0000000..374f9f0
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/suspend.S
@@ -0,0 +1,151 @@
+/*
+ * arch/arm/mach-lpc32xx/suspend.S
+ *
+ * Original authors: Dmitry Chigirev, Vitaly Wool <source@mvista.com>
+ * Modified by Kevin Wells <kevin.wells@nxp.com>
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <mach/platform.h>
+#include <mach/hardware.h>
+
+/* Using named register defines makes the code easier to follow */
+#define WORK1_REG                      r0
+#define WORK2_REG                      r1
+#define SAVED_HCLK_DIV_REG             r2
+#define SAVED_HCLK_PLL_REG             r3
+#define SAVED_DRAM_CLKCTRL_REG         r4
+#define SAVED_PWR_CTRL_REG             r5
+#define CLKPWRBASE_REG                 r6
+#define EMCBASE_REG                    r7
+
+#define LPC32XX_EMC_STATUS_OFFS                0x04
+#define LPC32XX_EMC_STATUS_BUSY                0x1
+#define LPC32XX_EMC_STATUS_SELF_RFSH   0x4
+
+#define LPC32XX_CLKPWR_PWR_CTRL_OFFS   0x44
+#define LPC32XX_CLKPWR_HCLK_DIV_OFFS   0x40
+#define LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS 0x58
+
+#define CLKPWR_PCLK_DIV_MASK           0xFFFFFE7F
+
+       .text
+
+ENTRY(lpc32xx_sys_suspend)
+       @ Save a copy of the used registers in IRAM, r0 is corrupted
+       adr     r0, tmp_stack_end
+       stmfd   r0!, {r3 - r7, sp, lr}
+
+       @ Load a few common register addresses
+       adr     WORK1_REG, reg_bases
+       ldr     CLKPWRBASE_REG, [WORK1_REG, #0]
+       ldr     EMCBASE_REG, [WORK1_REG, #4]
+
+       ldr     SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
+               #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+       orr     WORK1_REG, SAVED_PWR_CTRL_REG, #LPC32XX_CLKPWR_SDRAM_SELF_RFSH
+
+       @ Wait for SDRAM busy status to go busy and then idle
+       @ This guarantees a small windows where DRAM isn't busy
+1:
+       ldr     WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
+       and     WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
+       cmp     WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
+       bne     1b @ Branch while idle
+2:
+       ldr     WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
+       and     WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
+       cmp     WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
+       beq     2b @ Branch until idle
+
+       @ Setup self-refresh with support for manual exit of
+       @ self-refresh mode
+       str     WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+       orr     WORK2_REG, WORK1_REG, #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
+       str     WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+       str     WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+
+       @ Wait for self-refresh acknowledge, clocks to the DRAM device
+       @ will automatically stop on start of self-refresh
+3:
+       ldr     WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
+       and     WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
+       cmp     WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
+       bne     3b @ Branch until self-refresh mode starts
+
+       @ Enter direct-run mode from run mode
+       bic     WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_SELECT_RUN_MODE
+       str     WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+
+       @ Safe disable of DRAM clock in EMC block, prevents DDR sync
+       @ issues on restart
+       ldr     SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
+               #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
+       and     WORK2_REG, SAVED_HCLK_DIV_REG, #CLKPWR_PCLK_DIV_MASK
+       str     WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
+
+       @ Save HCLK PLL state and disable HCLK PLL
+       ldr     SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
+               #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
+       bic     WORK2_REG, SAVED_HCLK_PLL_REG, #LPC32XX_CLKPWR_HCLKPLL_POWER_UP
+       str     WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
+
+       @ Enter stop mode until an enabled event occurs
+       orr     WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL
+       str     WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+       .rept 9
+       nop
+       .endr
+
+       @ Clear stop status
+       bic     WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL
+
+       @ Restore original HCLK PLL value and wait for PLL lock
+       str     SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
+               #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
+4:
+       ldr     WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
+       and     WORK2_REG, WORK2_REG, #LPC32XX_CLKPWR_HCLKPLL_PLL_STS
+       bne     4b
+
+       @ Re-enter run mode with self-refresh flag cleared, but no DRAM
+       @ update yet. DRAM is still in self-refresh
+       str     SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
+               #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+
+       @ Restore original DRAM clock mode to restore DRAM clocks
+       str     SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
+               #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
+
+       @ Clear self-refresh mode
+       orr     WORK1_REG, SAVED_PWR_CTRL_REG,\
+               #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
+       str     WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+       str     SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
+               #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+
+       @ Wait for EMC to clear self-refresh mode
+5:
+       ldr     WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
+       and     WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
+       bne     5b @ Branch until self-refresh has exited
+
+       @ restore regs and return
+       adr     r0, tmp_stack
+       ldmfd   r0!, {r3 - r7, sp, pc}
+
+reg_bases:
+       .long   IO_ADDRESS(LPC32XX_CLK_PM_BASE)
+       .long   IO_ADDRESS(LPC32XX_EMC_BASE)
+
+tmp_stack:
+       .long   0, 0, 0, 0, 0, 0, 0
+tmp_stack_end:
+
+ENTRY(lpc32xx_sys_suspend_sz)
+       .word   . - lpc32xx_sys_suspend

diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c
new file mode 100644 (file)
index 0000000..630dd4a
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/timer.c
@@ -0,0 +1,182 @@
+/*
+ * arch/arm/mach-lpc32xx/timer.c
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2009 - 2010 NXP Semiconductors
+ * Copyright (C) 2009 Fontys University of Applied Sciences, Eindhoven
+ *                    Ed Schouten <e.schouten@fontys.nl>
+ *                    Laurens Timmermans <l.timmermans@fontys.nl>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/time.h>
+#include <linux/err.h>
+#include <linux/clockchips.h>
+
+#include <asm/mach/time.h>
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include "common.h"
+
+static cycle_t lpc32xx_clksrc_read(struct clocksource *cs)
+{
+       return (cycle_t)__raw_readl(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE));
+}
+
+static struct clocksource lpc32xx_clksrc = {
+       .name   = "lpc32xx_clksrc",
+       .shift  = 24,
+       .rating = 300,
+       .read   = lpc32xx_clksrc_read,
+       .mask   = CLOCKSOURCE_MASK(32),
+       .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static int lpc32xx_clkevt_next_event(unsigned long delta,
+    struct clock_event_device *dev)
+{
+       __raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
+               LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+       __raw_writel(delta, LCP32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
+       __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
+               LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+
+       return 0;
+}
+
+static void lpc32xx_clkevt_mode(enum clock_event_mode mode,
+    struct clock_event_device *dev)
+{
+       switch (mode) {
+       case CLOCK_EVT_MODE_PERIODIC:
+               WARN_ON(1);
+               break;
+
+       case CLOCK_EVT_MODE_ONESHOT:
+       case CLOCK_EVT_MODE_SHUTDOWN:
+               /*
+                * Disable the timer. When using oneshot, we must also
+                * disable the timer to wait for the first call to
+                * set_next_event().
+                */
+               __raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+               break;
+
+       case CLOCK_EVT_MODE_UNUSED:
+       case CLOCK_EVT_MODE_RESUME:
+               break;
+       }
+}
+
+static struct clock_event_device lpc32xx_clkevt = {
+       .name           = "lpc32xx_clkevt",
+       .features       = CLOCK_EVT_FEAT_ONESHOT,
+       .shift          = 32,
+       .rating         = 300,
+       .set_next_event = lpc32xx_clkevt_next_event,
+       .set_mode       = lpc32xx_clkevt_mode,
+};
+
+static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id)
+{
+       struct clock_event_device *evt = &lpc32xx_clkevt;
+
+       /* Clear match */
+       __raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
+               LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
+
+       evt->event_handler(evt);
+
+       return IRQ_HANDLED;
+}
+
+static struct irqaction lpc32xx_timer_irq = {
+       .name           = "LPC32XX Timer Tick",
+       .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+       .handler        = lpc32xx_timer_interrupt,
+};
+
+/*
+ * The clock management driver isn't initialized at this point, so the
+ * clocks need to be enabled here manually and then tagged as used in
+ * the clock driver initialization
+ */
+static void __init lpc32xx_timer_init(void)
+{
+       u32 clkrate, pllreg;
+
+       /* Enable timer clock */
+       __raw_writel(LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN |
+               LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
+               LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1);
+
+       /*
+        * The clock driver isn't initialized at this point. So determine if
+        * the SYSCLK is driven from the PLL397 or main oscillator and then use
+        * it to compute the PLL frequency and the PCLK divider to get the base
+        * timer rates. This rate is needed to compute the tick rate.
+        */
+       if (clk_is_sysclk_mainosc() != 0)
+               clkrate = LPC32XX_MAIN_OSC_FREQ;
+       else
+               clkrate = 397 * LPC32XX_CLOCK_OSC_FREQ;
+
+       /* Get ARM HCLKPLL register and convert it into a frequency */
+       pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
+       clkrate = clk_get_pllrate_from_reg(clkrate, pllreg);
+
+       /* Get PCLK divider and divide ARM PLL clock by it to get timer rate */
+       clkrate = clkrate / clk_get_pclk_div();
+
+       /* Initial timer setup */
+       __raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+       __raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
+               LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
+       __raw_writel(1, LCP32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
+       __raw_writel(LCP32XX_TIMER_CNTR_MCR_MTCH(0) |
+               LCP32XX_TIMER_CNTR_MCR_STOP(0) |
+               LCP32XX_TIMER_CNTR_MCR_RESET(0),
+               LCP32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
+
+       /* Setup tick interrupt */
+       setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq);
+
+       /* Setup the clockevent structure. */
+       lpc32xx_clkevt.mult = div_sc(clkrate, NSEC_PER_SEC,
+               lpc32xx_clkevt.shift);
+       lpc32xx_clkevt.max_delta_ns = clockevent_delta2ns(-1,
+               &lpc32xx_clkevt);
+       lpc32xx_clkevt.min_delta_ns = clockevent_delta2ns(1,
+               &lpc32xx_clkevt) + 1;
+       lpc32xx_clkevt.cpumask = cpumask_of(0);
+       clockevents_register_device(&lpc32xx_clkevt);
+
+       /* Use timer1 as clock source. */
+       __raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
+               LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
+       __raw_writel(0, LCP32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
+       __raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
+       __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
+               LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
+       lpc32xx_clksrc.mult = clocksource_hz2mult(clkrate,
+               lpc32xx_clksrc.shift);
+       clocksource_register(&lpc32xx_clksrc);
+}
+
+struct sys_timer lpc32xx_timer = {
+       .init           = &lpc32xx_timer_init,
+};
+

diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 66677f0acaed287fb5bde8b48f054334af195703..7ff8020d4d2422f0f509e7bb8aec2631dca60f72 100644 (file)
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -15,7 +15,7 @@ obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
 obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
 obj-$(CONFIG_MSM_SMD) += last_radio_log.o
 
-obj-$(CONFIG_MACH_TROUT) += board-trout.o devices-msm7x00.o
+obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o devices-msm7x00.o
 obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
 obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
 obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o

diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c
new file mode 100644 (file)
index 0000000..523d213
--- /dev/null
+++ b/arch/arm/mach-msm/board-trout-gpio.c
@@ -0,0 +1,112 @@
+/*
+ * linux/arch/arm/mach-msm/gpio.c
+ *
+ * Copyright (C) 2005 HP Labs
+ * Copyright (C) 2008 Google, Inc.
+ * Copyright (C) 2009 Pavel Machek <pavel@ucw.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+
+#include "board-trout.h"
+
+struct msm_gpio_chip {
+       struct gpio_chip        chip;
+       void __iomem            *reg;   /* Base of register bank */
+       u8                      shadow;
+};
+
+#define to_msm_gpio_chip(c) container_of(c, struct msm_gpio_chip, chip)
+
+static int msm_gpiolib_get(struct gpio_chip *chip, unsigned offset)
+{
+       struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip);
+       unsigned mask = 1 << offset;
+
+       return !!(readb(msm_gpio->reg) & mask);
+}
+
+static void msm_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
+{
+       struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip);
+       unsigned mask = 1 << offset;
+
+       if (val)
+               msm_gpio->shadow |= mask;
+       else
+               msm_gpio->shadow &= ~mask;
+
+       writeb(msm_gpio->shadow, msm_gpio->reg);
+}
+
+static int msm_gpiolib_direction_input(struct gpio_chip *chip,
+                                       unsigned offset)
+{
+       msm_gpiolib_set(chip, offset, 0);
+       return 0;
+}
+
+static int msm_gpiolib_direction_output(struct gpio_chip *chip,
+                                        unsigned offset, int val)
+{
+       msm_gpiolib_set(chip, offset, val);
+       return 0;
+}
+
+#define TROUT_GPIO_BANK(name, reg_num, base_gpio, shadow_val)          \
+       {                                                               \
+               .chip = {                                               \
+                       .label            = name,                       \
+                       .direction_input  = msm_gpiolib_direction_input,\
+                       .direction_output = msm_gpiolib_direction_output, \
+                       .get              = msm_gpiolib_get,            \
+                       .set              = msm_gpiolib_set,            \
+                       .base             = base_gpio,                  \
+                       .ngpio            = 8,                          \
+               },                                                      \
+               .reg = (void *) reg_num + TROUT_CPLD_BASE,              \
+               .shadow = shadow_val,                                   \
+       }
+
+static struct msm_gpio_chip msm_gpio_banks[] = {
+#if defined(CONFIG_MSM_DEBUG_UART1)
+       /* H2W pins <-> UART1 */
+       TROUT_GPIO_BANK("MISC2", 0x00,   TROUT_GPIO_MISC2_BASE, 0x40),
+#else
+       /* H2W pins <-> UART3, Bluetooth <-> UART1 */
+       TROUT_GPIO_BANK("MISC2", 0x00,   TROUT_GPIO_MISC2_BASE, 0x80),
+#endif
+       /* I2C pull */
+       TROUT_GPIO_BANK("MISC3", 0x02,   TROUT_GPIO_MISC3_BASE, 0x04),
+       TROUT_GPIO_BANK("MISC4", 0x04,   TROUT_GPIO_MISC4_BASE, 0),
+       /* mmdi 32k en */
+       TROUT_GPIO_BANK("MISC5", 0x06,   TROUT_GPIO_MISC5_BASE, 0x04),
+       TROUT_GPIO_BANK("INT2", 0x08,    TROUT_GPIO_INT2_BASE,  0),
+       TROUT_GPIO_BANK("MISC1", 0x0a,   TROUT_GPIO_MISC1_BASE, 0),
+       TROUT_GPIO_BANK("VIRTUAL", 0x12, TROUT_GPIO_VIRTUAL_BASE, 0),
+};
+
+/*
+ * Called from the processor-specific init to enable GPIO pin support.
+ */
+int __init trout_init_gpio(void)
+{
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++)
+               gpiochip_add(&msm_gpio_banks[i].chip);
+
+       return 0;
+}
+
+postcore_initcall(trout_init_gpio);
+

diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index dca5a5f062dce229fe98b9e00fe5f18e5ff40620..e69a1502e4e8dc80cac9dd620497b5adddd0e6d4 100644 (file)
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -50,7 +50,6 @@ static void __init trout_fixup(struct machine_desc *desc, struct tag *tags,
 {
        mi->nr_banks = 1;
        mi->bank[0].start = PHYS_OFFSET;
-       mi->bank[0].node = PHYS_TO_NID(PHYS_OFFSET);
        mi->bank[0].size = (101*1024*1024);
 }
 

diff --git a/arch/arm/mach-msm/board-trout.h b/arch/arm/mach-msm/board-trout.h
index 4f345a5a0a61c7a0cd223a996e07b8650cddd52a..651851c3e1dd14d21ef24c497667dbe2f5d5828d 100644 (file)
--- a/arch/arm/mach-msm/board-trout.h
+++ b/arch/arm/mach-msm/board-trout.h
@@ -1,5 +1,162 @@
+/* linux/arch/arm/mach-msm/board-trout.h
+** Author: Brian Swetland <swetland@google.com>
+*/
+#ifndef __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
+#define __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
+
+#include <mach/board.h>
+
+#define MSM_SMI_BASE           0x00000000
+#define MSM_SMI_SIZE           0x00800000
+
+#define MSM_EBI_BASE           0x10000000
+#define MSM_EBI_SIZE           0x06e00000
+
+#define MSM_PMEM_GPU0_BASE     0x00000000
+#define MSM_PMEM_GPU0_SIZE     0x00700000
+
+#define MSM_PMEM_MDP_BASE      0x02000000
+#define MSM_PMEM_MDP_SIZE      0x00800000
+
+#define MSM_PMEM_ADSP_BASE      0x02800000
+#define MSM_PMEM_ADSP_SIZE     0x00800000
+
+#define MSM_PMEM_CAMERA_BASE   0x03000000
+#define MSM_PMEM_CAMERA_SIZE   0x00800000
+
+#define MSM_FB_BASE            0x03800000
+#define MSM_FB_SIZE            0x00100000
+
+#define MSM_LINUX_BASE         MSM_EBI_BASE
+#define MSM_LINUX_SIZE         0x06500000
+
+#define MSM_PMEM_GPU1_SIZE     0x800000
+#define MSM_PMEM_GPU1_BASE     (MSM_RAM_CONSOLE_BASE - MSM_PMEM_GPU1_SIZE)
+
+#define MSM_RAM_CONSOLE_BASE   (MSM_EBI_BASE + 0x6d00000)
+#define MSM_RAM_CONSOLE_SIZE   (128 * SZ_1K)
+
+#if (MSM_FB_BASE + MSM_FB_SIZE) >= (MSM_PMEM_GPU1_BASE)
+#error invalid memory map
+#endif
+
+#define DECLARE_MSM_IOMAP
+#include <mach/msm_iomap.h>
+
+#define TROUT_4_BALL_UP_0     1
+#define TROUT_4_BALL_LEFT_0   18
+#define TROUT_4_BALL_DOWN_0   57
+#define TROUT_4_BALL_RIGHT_0  91
+
+#define TROUT_5_BALL_UP_0     94
+#define TROUT_5_BALL_LEFT_0   18
+#define TROUT_5_BALL_DOWN_0   90
+#define TROUT_5_BALL_RIGHT_0  19
+
+#define TROUT_POWER_KEY     20
+
+#define TROUT_4_TP_LS_EN    19
+#define TROUT_5_TP_LS_EN    1
 
 #define TROUT_CPLD_BASE   0xE8100000
 #define TROUT_CPLD_START  0x98000000
 #define TROUT_CPLD_SIZE   SZ_4K
 
+#define TROUT_GPIO_CABLE_IN1           (83)
+#define TROUT_GPIO_CABLE_IN2           (49)
+
+#define TROUT_GPIO_START (128)
+
+#define TROUT_GPIO_INT_MASK0_REG            (0x0c)
+#define TROUT_GPIO_INT_STAT0_REG            (0x0e)
+#define TROUT_GPIO_INT_MASK1_REG            (0x14)
+#define TROUT_GPIO_INT_STAT1_REG            (0x10)
+
+#define TROUT_GPIO_HAPTIC_PWM               (28)
+#define TROUT_GPIO_PS_HOLD                  (25)
+
+#define TROUT_GPIO_MISC2_BASE               (TROUT_GPIO_START + 0x00)
+#define TROUT_GPIO_MISC3_BASE               (TROUT_GPIO_START + 0x08)
+#define TROUT_GPIO_MISC4_BASE               (TROUT_GPIO_START + 0x10)
+#define TROUT_GPIO_MISC5_BASE               (TROUT_GPIO_START + 0x18)
+#define TROUT_GPIO_INT2_BASE                (TROUT_GPIO_START + 0x20)
+#define TROUT_GPIO_MISC1_BASE               (TROUT_GPIO_START + 0x28)
+#define TROUT_GPIO_VIRTUAL_BASE             (TROUT_GPIO_START + 0x30)
+#define TROUT_GPIO_INT5_BASE                (TROUT_GPIO_START + 0x48)
+
+#define TROUT_GPIO_CHARGER_EN               (TROUT_GPIO_MISC2_BASE + 0)
+#define TROUT_GPIO_ISET                     (TROUT_GPIO_MISC2_BASE + 1)
+#define TROUT_GPIO_H2W_DAT_DIR              (TROUT_GPIO_MISC2_BASE + 2)
+#define TROUT_GPIO_H2W_CLK_DIR              (TROUT_GPIO_MISC2_BASE + 3)
+#define TROUT_GPIO_H2W_DAT_GPO              (TROUT_GPIO_MISC2_BASE + 4)
+#define TROUT_GPIO_H2W_CLK_GPO              (TROUT_GPIO_MISC2_BASE + 5)
+#define TROUT_GPIO_H2W_SEL0                 (TROUT_GPIO_MISC2_BASE + 6)
+#define TROUT_GPIO_H2W_SEL1                 (TROUT_GPIO_MISC2_BASE + 7)
+
+#define TROUT_GPIO_SPOTLIGHT_EN             (TROUT_GPIO_MISC3_BASE + 0)
+#define TROUT_GPIO_FLASH_EN                 (TROUT_GPIO_MISC3_BASE + 1)
+#define TROUT_GPIO_I2C_PULL                 (TROUT_GPIO_MISC3_BASE + 2)
+#define TROUT_GPIO_TP_I2C_PULL              (TROUT_GPIO_MISC3_BASE + 3)
+#define TROUT_GPIO_TP_EN                    (TROUT_GPIO_MISC3_BASE + 4)
+#define TROUT_GPIO_JOG_EN                   (TROUT_GPIO_MISC3_BASE + 5)
+#define TROUT_GPIO_UI_LED_EN                (TROUT_GPIO_MISC3_BASE + 6)
+#define TROUT_GPIO_QTKEY_LED_EN             (TROUT_GPIO_MISC3_BASE + 7)
+
+#define TROUT_GPIO_VCM_PWDN                 (TROUT_GPIO_MISC4_BASE + 0)
+#define TROUT_GPIO_USB_H2W_SW               (TROUT_GPIO_MISC4_BASE + 1)
+#define TROUT_GPIO_COMPASS_RST_N            (TROUT_GPIO_MISC4_BASE + 2)
+#define TROUT_GPIO_HAPTIC_EN_UP             (TROUT_GPIO_MISC4_BASE + 3)
+#define TROUT_GPIO_HAPTIC_EN_MAIN           (TROUT_GPIO_MISC4_BASE + 4)
+#define TROUT_GPIO_USB_PHY_RST_N            (TROUT_GPIO_MISC4_BASE + 5)
+#define TROUT_GPIO_WIFI_PA_RESETX           (TROUT_GPIO_MISC4_BASE + 6)
+#define TROUT_GPIO_WIFI_EN                  (TROUT_GPIO_MISC4_BASE + 7)
+
+#define TROUT_GPIO_BT_32K_EN                (TROUT_GPIO_MISC5_BASE + 0)
+#define TROUT_GPIO_MAC_32K_EN               (TROUT_GPIO_MISC5_BASE + 1)
+#define TROUT_GPIO_MDDI_32K_EN              (TROUT_GPIO_MISC5_BASE + 2)
+#define TROUT_GPIO_COMPASS_32K_EN           (TROUT_GPIO_MISC5_BASE + 3)
+
+#define TROUT_GPIO_NAVI_ACT_N               (TROUT_GPIO_INT2_BASE + 0)
+#define TROUT_GPIO_COMPASS_IRQ              (TROUT_GPIO_INT2_BASE + 1)
+#define TROUT_GPIO_SLIDING_DET              (TROUT_GPIO_INT2_BASE + 2)
+#define TROUT_GPIO_AUD_HSMIC_DET_N          (TROUT_GPIO_INT2_BASE + 3)
+#define TROUT_GPIO_SD_DOOR_N                (TROUT_GPIO_INT2_BASE + 4)
+#define TROUT_GPIO_CAM_BTN_STEP1_N          (TROUT_GPIO_INT2_BASE + 5)
+#define TROUT_GPIO_CAM_BTN_STEP2_N          (TROUT_GPIO_INT2_BASE + 6)
+#define TROUT_GPIO_TP_ATT_N                 (TROUT_GPIO_INT2_BASE + 7)
+#define TROUT_GPIO_BANK0_FIRST_INT_SOURCE   (TROUT_GPIO_NAVI_ACT_N)
+#define TROUT_GPIO_BANK0_LAST_INT_SOURCE    (TROUT_GPIO_TP_ATT_N)
+
+#define TROUT_GPIO_H2W_DAT_GPI              (TROUT_GPIO_MISC1_BASE + 0)
+#define TROUT_GPIO_H2W_CLK_GPI              (TROUT_GPIO_MISC1_BASE + 1)
+#define TROUT_GPIO_CPLD128_VER_0            (TROUT_GPIO_MISC1_BASE + 4)
+#define TROUT_GPIO_CPLD128_VER_1            (TROUT_GPIO_MISC1_BASE + 5)
+#define TROUT_GPIO_CPLD128_VER_2            (TROUT_GPIO_MISC1_BASE + 6)
+#define TROUT_GPIO_CPLD128_VER_3            (TROUT_GPIO_MISC1_BASE + 7)
+
+#define TROUT_GPIO_SDMC_CD_N                (TROUT_GPIO_VIRTUAL_BASE + 0)
+#define TROUT_GPIO_END                      (TROUT_GPIO_SDMC_CD_N)
+#define TROUT_GPIO_BANK1_FIRST_INT_SOURCE   (TROUT_GPIO_SDMC_CD_N)
+#define TROUT_GPIO_BANK1_LAST_INT_SOURCE    (TROUT_GPIO_SDMC_CD_N)
+
+#define TROUT_GPIO_VIRTUAL_TO_REAL_OFFSET \
+       (TROUT_GPIO_INT5_BASE - TROUT_GPIO_VIRTUAL_BASE)
+
+#define TROUT_INT_START (NR_MSM_IRQS + NR_GPIO_IRQS)
+#define TROUT_INT_BANK0_COUNT (8)
+#define TROUT_INT_BANK1_START (TROUT_INT_START + TROUT_INT_BANK0_COUNT)
+#define TROUT_INT_BANK1_COUNT (1)
+#define TROUT_INT_END (TROUT_INT_START + TROUT_INT_BANK0_COUNT + \
+                       TROUT_INT_BANK1_COUNT - 1)
+#define TROUT_GPIO_TO_INT(n) (((n) <= TROUT_GPIO_BANK0_LAST_INT_SOURCE) ? \
+       (TROUT_INT_START - TROUT_GPIO_BANK0_FIRST_INT_SOURCE + (n)) : \
+       (TROUT_INT_BANK1_START - TROUT_GPIO_BANK1_FIRST_INT_SOURCE + (n)))
+
+#define TROUT_INT_TO_BANK(n) ((n - TROUT_INT_START) / TROUT_INT_BANK0_COUNT)
+#define TROUT_INT_TO_MASK(n) (1U << ((n - TROUT_INT_START) & 7))
+#define TROUT_BANK_TO_MASK_REG(bank) \
+       (bank ? TROUT_GPIO_INT_MASK1_REG : TROUT_GPIO_INT_MASK0_REG)
+#define TROUT_BANK_TO_STAT_REG(bank) \
+       (bank ? TROUT_GPIO_INT_STAT1_REG : TROUT_GPIO_INT_STAT0_REG)
+
+#endif /* GUARD */

diff --git a/arch/arm/mach-msm/include/mach/gpio.h b/arch/arm/mach-msm/include/mach/gpio.h
index 262b441b4374a94dd71e90cc9ed1ce1d3b230d90..83e47c0d5c2e451de5f459653053684beb786ee8 100644 (file)
--- a/arch/arm/mach-msm/include/mach/gpio.h
+++ b/arch/arm/mach-msm/include/mach/gpio.h
@@ -16,6 +16,13 @@
 #ifndef __ASM_ARCH_MSM_GPIO_H
 #define __ASM_ARCH_MSM_GPIO_H
 
+#include <asm-generic/gpio.h>
+
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+#define gpio_to_irq     __gpio_to_irq
+
 /**
  * struct msm_gpio - GPIO pin description
  * @gpio_cfg - configuration bitmap, as per gpio_tlmm_config()

diff --git a/arch/arm/mach-mx1/Kconfig b/arch/arm/mach-mx1/Kconfig
deleted file mode 100644 (file)
index eb7660f..0000000
--- a/arch/arm/mach-mx1/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-if ARCH_MX1
-
-comment "MX1 platforms:"
-
-config MACH_MXLADS
-       bool
-
-config ARCH_MX1ADS
-       bool "MX1ADS platform"
-       select MACH_MXLADS
-       help
-         Say Y here if you are using Motorola MX1ADS/MXLADS boards
-
-config MACH_SCB9328
-       bool "Synertronixx scb9328"
-       help
-         Say Y here if you are using a Synertronixx scb9328 board
-
-endif

diff --git a/arch/arm/mach-mx1/Makefile b/arch/arm/mach-mx1/Makefile
deleted file mode 100644 (file)
index fc2ddf8..0000000
--- a/arch/arm/mach-mx1/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-# Object file lists.
-
-EXTRA_CFLAGS += -DIMX_NEEDS_DEPRECATED_SYMBOLS
-obj-y                  += generic.o clock.o devices.o
-
-# Support for CMOS sensor interface
-obj-$(CONFIG_MX1_VIDEO)        += ksym_mx1.o mx1_camera_fiq.o
-
-# Specific board support
-obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
-obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o

diff --git a/arch/arm/mach-mx1/Makefile.boot b/arch/arm/mach-mx1/Makefile.boot
deleted file mode 100644 (file)
index 8ed1492..0000000
--- a/arch/arm/mach-mx1/Makefile.boot
+++ /dev/null
@@ -1,4 +0,0 @@
-   zreladdr-y  := 0x08008000
-params_phys-y  := 0x08000100
-initrd_phys-y  := 0x08800000
-

diff --git a/arch/arm/mach-mx1/crm_regs.h b/arch/arm/mach-mx1/crm_regs.h
deleted file mode 100644 (file)
index 22e866f..0000000
--- a/arch/arm/mach-mx1/crm_regs.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
- *
- * This file may be distributed under the terms of the GNU General
- * Public License, version 2.
- */
-
-#ifndef __ARCH_ARM_MACH_MX1_CRM_REGS_H__
-#define __ARCH_ARM_MACH_MX1_CRM_REGS_H__
-
-#define CCM_BASE       IO_ADDRESS(CCM_BASE_ADDR)
-#define SCM_BASE       IO_ADDRESS(SCM_BASE_ADDR)
-
-/* CCM register addresses */
-#define CCM_CSCR       (CCM_BASE + 0x0)
-#define CCM_MPCTL0     (CCM_BASE + 0x4)
-#define CCM_MPCTL1     (CCM_BASE + 0x8)
-#define CCM_SPCTL0     (CCM_BASE + 0xC)
-#define CCM_SPCTL1     (CCM_BASE + 0x10)
-#define CCM_PCDR       (CCM_BASE + 0x20)
-
-#define CCM_CSCR_CLKO_OFFSET   29
-#define CCM_CSCR_CLKO_MASK     (0x7 << 29)
-#define CCM_CSCR_USB_OFFSET    26
-#define CCM_CSCR_USB_MASK      (0x7 << 26)
-#define CCM_CSCR_SPLL_RESTART  (1 << 22)
-#define CCM_CSCR_MPLL_RESTART  (1 << 21)
-#define CCM_CSCR_OSC_EN_SHIFT  17
-#define CCM_CSCR_SYSTEM_SEL    (1 << 16)
-#define CCM_CSCR_BCLK_OFFSET   10
-#define CCM_CSCR_BCLK_MASK     (0xF << 10)
-#define CCM_CSCR_PRESC         (1 << 15)
-#define CCM_CSCR_SPEN          (1 << 1)
-#define CCM_CSCR_MPEN          (1 << 0)
-
-#define CCM_PCDR_PCLK3_OFFSET  16
-#define CCM_PCDR_PCLK3_MASK    (0x7F << 16)
-#define CCM_PCDR_PCLK2_OFFSET  4
-#define CCM_PCDR_PCLK2_MASK    (0xF << 4)
-#define CCM_PCDR_PCLK1_OFFSET  0
-#define CCM_PCDR_PCLK1_MASK    0xF
-
-/* SCM register addresses */
-#define SCM_SIDR       (SCM_BASE + 0x0)
-#define SCM_FMCR       (SCM_BASE + 0x4)
-#define SCM_GPCR       (SCM_BASE + 0x8)
-#define SCM_GCCR       (SCM_BASE + 0xC)
-
-#define SCM_GCCR_DMA_CLK_EN_OFFSET     3
-#define SCM_GCCR_CSI_CLK_EN_OFFSET     2
-#define SCM_GCCR_MMA_CLK_EN_OFFSET     1
-#define SCM_GCCR_USBD_CLK_EN_OFFSET    0
-
-#endif /* __ARCH_ARM_MACH_MX2_CRM_REGS_H__ */

diff --git a/arch/arm/mach-mx1/devices.c b/arch/arm/mach-mx1/devices.c
deleted file mode 100644 (file)
index b6be29d..0000000
--- a/arch/arm/mach-mx1/devices.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
- * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
- * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA  02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <mach/irqs.h>
-#include <mach/hardware.h>
-
-#include "devices.h"
-
-static struct resource imx_csi_resources[] = {
-       {
-               .start  = 0x00224000,
-               .end    = 0x00224010,
-               .flags  = IORESOURCE_MEM,
-       }, {
-               .start  = CSI_INT,
-               .end    = CSI_INT,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static u64 imx_csi_dmamask = 0xffffffffUL;
-
-struct platform_device imx_csi_device = {
-       .name           = "mx1-camera",
-       .id             = 0, /* This is used to put cameras on this interface */
-       .dev            = {
-               .dma_mask = &imx_csi_dmamask,
-               .coherent_dma_mask = 0xffffffff,
-       },
-       .resource       = imx_csi_resources,
-       .num_resources  = ARRAY_SIZE(imx_csi_resources),
-};
-
-static struct resource imx_i2c_resources[] = {
-       {
-               .start  = 0x00217000,
-               .end    = 0x00217010,
-               .flags  = IORESOURCE_MEM,
-       }, {
-               .start  = I2C_INT,
-               .end    = I2C_INT,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device imx_i2c_device = {
-       .name           = "imx-i2c",
-       .id             = 0,
-       .resource       = imx_i2c_resources,
-       .num_resources  = ARRAY_SIZE(imx_i2c_resources),
-};
-
-static struct resource imx_uart1_resources[] = {
-       {
-               .start  = UART1_BASE_ADDR,
-               .end    = UART1_BASE_ADDR + 0xD0,
-               .flags  = IORESOURCE_MEM,
-       }, {
-               .start  = UART1_MINT_RX,
-               .end    = UART1_MINT_RX,
-               .flags  = IORESOURCE_IRQ,
-       }, {
-               .start  = UART1_MINT_TX,
-               .end    = UART1_MINT_TX,
-               .flags  = IORESOURCE_IRQ,
-       }, {
-               .start  = UART1_MINT_RTS,
-               .end    = UART1_MINT_RTS,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device imx_uart1_device = {
-       .name           = "imx-uart",
-       .id             = 0,
-       .num_resources  = ARRAY_SIZE(imx_uart1_resources),
-       .resource       = imx_uart1_resources,
-};
-
-static struct resource imx_uart2_resources[] = {
-       {
-               .start  = UART2_BASE_ADDR,
-               .end    = UART2_BASE_ADDR + 0xD0,
-               .flags  = IORESOURCE_MEM,
-       }, {
-               .start  = UART2_MINT_RX,
-               .end    = UART2_MINT_RX,
-               .flags  = IORESOURCE_IRQ,
-       }, {
-               .start  = UART2_MINT_TX,
-               .end    = UART2_MINT_TX,
-               .flags  = IORESOURCE_IRQ,
-       }, {
-               .start  = UART2_MINT_RTS,
-               .end    = UART2_MINT_RTS,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device imx_uart2_device = {
-       .name           = "imx-uart",
-       .id             = 1,
-       .num_resources  = ARRAY_SIZE(imx_uart2_resources),
-       .resource       = imx_uart2_resources,
-};
-
-static struct resource imx_rtc_resources[] = {
-       {
-               .start  = 0x00204000,
-               .end    = 0x00204024,
-               .flags  = IORESOURCE_MEM,
-       }, {
-               .start  = RTC_INT,
-               .end    = RTC_INT,
-               .flags  = IORESOURCE_IRQ,
-       }, {
-               .start  = RTC_SAMINT,
-               .end    = RTC_SAMINT,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device imx_rtc_device = {
-       .name           = "rtc-imx",
-       .id             = 0,
-       .resource       = imx_rtc_resources,
-       .num_resources  = ARRAY_SIZE(imx_rtc_resources),
-};
-
-static struct resource imx_wdt_resources[] = {
-       {
-               .start  = 0x00201000,
-               .end    = 0x00201008,
-               .flags  = IORESOURCE_MEM,
-       }, {
-               .start  = WDT_INT,
-               .end    = WDT_INT,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device imx_wdt_device = {
-       .name           = "imx-wdt",
-       .id             = 0,
-       .resource       = imx_wdt_resources,
-       .num_resources  = ARRAY_SIZE(imx_wdt_resources),
-};
-
-static struct resource imx_usb_resources[] = {
-       {
-               .start  = 0x00212000,
-               .end    = 0x00212148,
-               .flags  = IORESOURCE_MEM,
-       }, {
-               .start  = USBD_INT0,
-               .end    = USBD_INT0,
-               .flags  = IORESOURCE_IRQ,
-       }, {
-               .start  = USBD_INT1,
-               .end    = USBD_INT1,
-               .flags  = IORESOURCE_IRQ,
-       }, {
-               .start  = USBD_INT2,
-               .end    = USBD_INT2,
-               .flags  = IORESOURCE_IRQ,
-       }, {
-               .start  = USBD_INT3,
-               .end    = USBD_INT3,
-               .flags  = IORESOURCE_IRQ,
-       }, {
-               .start  = USBD_INT4,
-               .end    = USBD_INT4,
-               .flags  = IORESOURCE_IRQ,
-       }, {
-               .start  = USBD_INT5,
-               .end    = USBD_INT5,
-               .flags  = IORESOURCE_IRQ,
-       }, {
-               .start  = USBD_INT6,
-               .end    = USBD_INT6,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device imx_usb_device = {
-       .name           = "imx_udc",
-       .id             = 0,
-       .num_resources  = ARRAY_SIZE(imx_usb_resources),
-       .resource       = imx_usb_resources,
-};
-
-/* GPIO port description */
-static struct mxc_gpio_port imx_gpio_ports[] = {
-       {
-               .chip.label = "gpio-0",
-               .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR),
-               .irq = GPIO_INT_PORTA,
-               .virtual_irq_start = MXC_GPIO_IRQ_START,
-       }, {
-               .chip.label = "gpio-1",
-               .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
-               .irq = GPIO_INT_PORTB,
-               .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
-       }, {
-               .chip.label = "gpio-2",
-               .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
-               .irq = GPIO_INT_PORTC,
-               .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
-       }, {
-               .chip.label = "gpio-3",
-               .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
-               .irq = GPIO_INT_PORTD,
-               .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
-       }
-};
-
-int __init mxc_register_gpios(void)
-{
-       return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
-}

diff --git a/arch/arm/mach-mx1/devices.h b/arch/arm/mach-mx1/devices.h
deleted file mode 100644 (file)
index 0da5d7c..0000000
--- a/arch/arm/mach-mx1/devices.h
+++ /dev/null
@@ -1,7 +0,0 @@
-extern struct platform_device imx_csi_device;
-extern struct platform_device imx_i2c_device;
-extern struct platform_device imx_uart1_device;
-extern struct platform_device imx_uart2_device;
-extern struct platform_device imx_rtc_device;
-extern struct platform_device imx_wdt_device;
-extern struct platform_device imx_usb_device;

diff --git a/arch/arm/mach-mx2/serial.c b/arch/arm/mach-mx2/serial.c
deleted file mode 100644 (file)
index 1c0c835..0000000
--- a/arch/arm/mach-mx2/serial.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/serial.h>
-#include <mach/hardware.h>
-#include <mach/imx-uart.h>
-#include "devices.h"
-
-static struct resource uart0[] = {
-       {
-               .start = MX2x_UART1_BASE_ADDR,
-               .end = MX2x_UART1_BASE_ADDR + 0x0B5,
-               .flags = IORESOURCE_MEM,
-       }, {
-               .start = MX2x_INT_UART1,
-               .end = MX2x_INT_UART1,
-               .flags = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device mxc_uart_device0 = {
-       .name = "imx-uart",
-       .id = 0,
-       .resource = uart0,
-       .num_resources = ARRAY_SIZE(uart0),
-};
-
-static struct resource uart1[] = {
-       {
-               .start = MX2x_UART2_BASE_ADDR,
-               .end = MX2x_UART2_BASE_ADDR + 0x0B5,
-               .flags = IORESOURCE_MEM,
-       }, {
-               .start = MX2x_INT_UART2,
-               .end = MX2x_INT_UART2,
-               .flags = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device mxc_uart_device1 = {
-       .name = "imx-uart",
-       .id = 1,
-       .resource = uart1,
-       .num_resources = ARRAY_SIZE(uart1),
-};
-
-static struct resource uart2[] = {
-       {
-               .start = MX2x_UART3_BASE_ADDR,
-               .end = MX2x_UART3_BASE_ADDR + 0x0B5,
-               .flags = IORESOURCE_MEM,
-       }, {
-               .start = MX2x_INT_UART3,
-               .end = MX2x_INT_UART3,
-               .flags = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device mxc_uart_device2 = {
-       .name = "imx-uart",
-       .id = 2,
-       .resource = uart2,
-       .num_resources = ARRAY_SIZE(uart2),
-};
-
-static struct resource uart3[] = {
-       {
-               .start = MX2x_UART4_BASE_ADDR,
-               .end = MX2x_UART4_BASE_ADDR + 0x0B5,
-               .flags = IORESOURCE_MEM,
-       }, {
-               .start = MX2x_INT_UART4,
-               .end = MX2x_INT_UART4,
-               .flags = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device mxc_uart_device3 = {
-       .name = "imx-uart",
-       .id = 3,
-       .resource = uart3,
-       .num_resources = ARRAY_SIZE(uart3),
-};
-
-#ifdef CONFIG_MACH_MX27
-static struct resource uart4[] = {
-       {
-               .start = MX27_UART5_BASE_ADDR,
-               .end = MX27_UART5_BASE_ADDR + 0x0B5,
-               .flags = IORESOURCE_MEM,
-       }, {
-               .start = MX27_INT_UART5,
-               .end = MX27_INT_UART5,
-               .flags = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device mxc_uart_device4 = {
-       .name = "imx-uart",
-       .id = 4,
-       .resource = uart4,
-       .num_resources = ARRAY_SIZE(uart4),
-};
-
-static struct resource uart5[] = {
-       {
-               .start = MX27_UART6_BASE_ADDR,
-               .end = MX27_UART6_BASE_ADDR + 0x0B5,
-               .flags = IORESOURCE_MEM,
-       }, {
-               .start = MX27_INT_UART6,
-               .end = MX27_INT_UART6,
-               .flags = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device mxc_uart_device5 = {
-       .name = "imx-uart",
-       .id = 5,
-       .resource = uart5,
-       .num_resources = ARRAY_SIZE(uart5),
-};
-#endif

diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig
index 54d217314ee9a3b57030af0f26f747d4d834e828..c71a7bc19284bf64b14f939f3094bfc501631240 100644 (file)
--- a/arch/arm/mach-mx25/Kconfig
+++ b/arch/arm/mach-mx25/Kconfig
@@ -4,5 +4,28 @@ comment "MX25 platforms:"
 
 config MACH_MX25_3DS
        bool "Support MX25PDK (3DS) Platform"
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_MXC_NAND
+
+config MACH_EUKREA_CPUIMX25
+       bool "Support Eukrea CPUIMX25 Platform"
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_MXC_NAND
+       select MXC_ULPI if USB_ULPI
+
+choice
+       prompt "Baseboard"
+       depends on MACH_EUKREA_CPUIMX25
+       default MACH_EUKREA_MBIMXSD25_BASEBOARD
+
+config MACH_EUKREA_MBIMXSD25_BASEBOARD
+       prompt "Eukrea MBIMXSD development board"
+       bool
+       help
+         This adds board specific devices that can be found on Eukrea's
+         MBIMXSD evaluation board.
+
+endchoice
 
 endif

diff --git a/arch/arm/mach-mx25/Makefile b/arch/arm/mach-mx25/Makefile
index 10cebc5ced8c0a0e15748fd7027effbee446d3f2..d9e46ce00a4ec747d92a47041ed98bebdeb3aa34 100644 (file)
--- a/arch/arm/mach-mx25/Makefile
+++ b/arch/arm/mach-mx25/Makefile
@@ -1,3 +1,5 @@
 obj-y                          := mm.o devices.o
 obj-$(CONFIG_ARCH_MX25)                += clock.o
-obj-$(CONFIG_MACH_MX25_3DS)    += mach-mx25pdk.o
+obj-$(CONFIG_MACH_MX25_3DS)    += mach-mx25_3ds.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX25)             += mach-cpuimx25.o
+obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD)  += eukrea_mbimxsd-baseboard.o

diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
index 155014993b13cc18d7724ca5d3d03604c7a103e1..40c7cc41cee372c906e3339f5da50f9e709f36df 100644 (file)
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-mx25/clock.c
@@ -109,6 +109,16 @@ static unsigned long get_rate_uart(struct clk *clk)
        return get_rate_per(15);
 }
 
+static unsigned long get_rate_ssi2(struct clk *clk)
+{
+       return get_rate_per(14);
+}
+
+static unsigned long get_rate_ssi1(struct clk *clk)
+{
+       return get_rate_per(13);
+}
+
 static unsigned long get_rate_i2c(struct clk *clk)
 {
        return get_rate_per(6);
@@ -129,9 +139,17 @@ static unsigned long get_rate_lcdc(struct clk *clk)
        return get_rate_per(7);
 }
 
+static unsigned long get_rate_csi(struct clk *clk)
+{
+       return get_rate_per(0);
+}
+
 static unsigned long get_rate_otg(struct clk *clk)
 {
-       return 48000000; /* FIXME */
+       unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
+       unsigned long rate = get_rate_upll();
+
+       return (cctl & (1 << 23)) ? 0 : rate / ((0x3F & (cctl >> 16)) + 1);
 }
 
 static int clk_cgcr_enable(struct clk *clk)
@@ -166,14 +184,40 @@ static void clk_cgcr_disable(struct clk *clk)
                .secondary      = s,                    \
        }
 
+/*
+ * Note: the following IPG clock gating bits are wrongly marked "Reserved" in
+ * the i.MX25 Reference Manual Rev 1, table 15-13. The information below is
+ * taken from the Freescale released BSP.
+ *
+ * bit reg     offset  clock
+ *
+ * 0   CGCR1   0       AUDMUX
+ * 12  CGCR1   12      ESAI
+ * 16  CGCR1   16      GPIO1
+ * 17  CGCR1   17      GPIO2
+ * 18  CGCR1   18      GPIO3
+ * 23  CGCR1   23      I2C1
+ * 24  CGCR1   24      I2C2
+ * 25  CGCR1   25      I2C3
+ * 27  CGCR1   27      IOMUXC
+ * 28  CGCR1   28      KPP
+ * 30  CGCR1   30      OWIRE
+ * 36  CGCR2   4       RTIC
+ * 51  CGCR2   19      WDOG
+ */
+
 DEFINE_CLOCK(gpt_clk,    0, CCM_CGCR0,  5, get_rate_gpt, NULL, NULL);
 DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL);
+DEFINE_CLOCK(ssi1_per_clk, 0, CCM_CGCR0, 13, get_rate_ipg, NULL, NULL);
+DEFINE_CLOCK(ssi2_per_clk, 0, CCM_CGCR0, 14, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(cspi1_clk,  0, CCM_CGCR1,  5, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(cspi2_clk,  0, CCM_CGCR1,  6, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(cspi3_clk,  0, CCM_CGCR1,  7, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL,       NULL, NULL);
 DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL,      NULL, NULL);
 DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0,  7, NULL,      NULL, &lcdc_ahb_clk);
+DEFINE_CLOCK(csi_ahb_clk, 0, CCM_CGCR0, 18, get_rate_csi, NULL, NULL);
+DEFINE_CLOCK(csi_per_clk, 0, CCM_CGCR0, 0, get_rate_csi, NULL, &csi_ahb_clk);
 DEFINE_CLOCK(uart1_clk,  0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk);
 DEFINE_CLOCK(uart2_clk,  0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk);
 DEFINE_CLOCK(uart3_clk,  0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk);
@@ -191,6 +235,13 @@ DEFINE_CLOCK(i2c_clk,       0, CCM_CGCR0,  6, get_rate_i2c, NULL, NULL);
 DEFINE_CLOCK(fec_clk,   0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
 DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1,  8, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(lcdc_clk,  0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
+DEFINE_CLOCK(wdt_clk,    0, CCM_CGCR2, 19, get_rate_ipg, NULL,  NULL);
+DEFINE_CLOCK(ssi1_clk,  0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk);
+DEFINE_CLOCK(ssi2_clk,  1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk);
+DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL);
+DEFINE_CLOCK(csi_clk,    0, CCM_CGCR1,  4, get_rate_csi, NULL,  &csi_per_clk);
+DEFINE_CLOCK(can1_clk,  0, CCM_CGCR1,  2, get_rate_ipg, NULL, NULL);
+DEFINE_CLOCK(can2_clk,  0, CCM_CGCR1,  3, get_rate_ipg, NULL, NULL);
 
 #define _REGISTER_CLOCK(d, n, c)       \
        {                               \
@@ -217,7 +268,7 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk)
        _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk)
        _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm4_clk)
-       _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk)
+       _REGISTER_CLOCK("imx-keypad", NULL, kpp_clk)
        _REGISTER_CLOCK("mx25-adc", NULL, tsc_clk)
        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
        _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk)
@@ -225,6 +276,13 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK("fec.0", NULL, fec_clk)
        _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk)
        _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
+       _REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk)
+       _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
+       _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
+       _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
+       _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
+       _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
+       _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
 };
 
 int __init mx25_clocks_init(void)
@@ -238,9 +296,13 @@ int __init mx25_clocks_init(void)
        __raw_writel((1 << 19), CRM_BASE + CCM_CGCR0);
        __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1);
        __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2);
+#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
+       clk_enable(&uart1_clk);
+#endif
 
-       /* Clock source for lcdc is upll */
-       __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7), CRM_BASE + 0x64);
+       /* Clock source for lcdc and csi is upll */
+       __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7) | (1 << 0),
+                       CRM_BASE + 0x64);
 
        mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
 

diff --git a/arch/arm/mach-mx25/devices-imx25.h b/arch/arm/mach-mx25/devices-imx25.h
new file mode 100644 (file)
index 0000000..d86a7c3
--- /dev/null
+++ b/arch/arm/mach-mx25/devices-imx25.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx25.h>
+#include <mach/devices-common.h>
+
+#define imx25_add_flexcan0(pdata)      \
+       imx_add_flexcan(0, MX25_CAN1_BASE_ADDR, SZ_16K, MX25_INT_CAN1, pdata)
+#define imx25_add_flexcan1(pdata)      \
+       imx_add_flexcan(1, MX25_CAN2_BASE_ADDR, SZ_16K, MX25_INT_CAN2, pdata)
+
+#define imx25_add_imx_i2c0(pdata)      \
+       imx_add_imx_i2c(0, MX25_I2C1_BASE_ADDR, SZ_16K, MX25_INT_I2C1, pdata)
+#define imx25_add_imx_i2c1(pdata)      \
+       imx_add_imx_i2c(1, MX25_I2C2_BASE_ADDR, SZ_16K, MX25_INT_I2C2, pdata)
+#define imx25_add_imx_i2c2(pdata)      \
+       imx_add_imx_i2c(2, MX25_I2C3_BASE_ADDR, SZ_16K, MX25_INT_I2C3, pdata)
+
+#define imx25_add_imx_uart0(pdata)     \
+       imx_add_imx_uart_1irq(0, MX25_UART1_BASE_ADDR, SZ_16K, MX25_INT_UART1, pdata)
+#define imx25_add_imx_uart1(pdata)     \
+       imx_add_imx_uart_1irq(1, MX25_UART2_BASE_ADDR, SZ_16K, MX25_INT_UART2, pdata)
+#define imx25_add_imx_uart2(pdata)     \
+       imx_add_imx_uart_1irq(2, MX25_UART3_BASE_ADDR, SZ_16K, MX25_INT_UART3, pdata)
+#define imx25_add_imx_uart3(pdata)     \
+       imx_add_imx_uart_1irq(3, MX25_UART4_BASE_ADDR, SZ_16K, MX25_INT_UART4, pdata)
+#define imx25_add_imx_uart4(pdata)     \
+       imx_add_imx_uart_1irq(4, MX25_UART5_BASE_ADDR, SZ_16K, MX25_INT_UART5, pdata)
+
+#define imx25_add_mxc_nand(pdata)      \
+       imx_add_mxc_nand_v21(MX25_NFC_BASE_ADDR, MX25_INT_NANDFC, pdata)
+
+#define imx25_add_spi_imx0(pdata)      \
+       imx_add_spi_imx(0, MX25_CSPI1_BASE_ADDR, SZ_16K, MX25_INT_CSPI1, pdata)
+#define imx25_add_spi_imx1(pdata)      \
+       imx_add_spi_imx(1, MX25_CSPI2_BASE_ADDR, SZ_16K, MX25_INT_CSPI2, pdata)
+#define imx25_add_spi_imx2(pdata)      \
+       imx_add_spi_imx(2, MX25_CSPI3_BASE_ADDR, SZ_16K, MX25_INT_CSPI3, pdata)

diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
index 3a405fa400eb064a6a8e612027709b7601cb4d34..3468eb15b2367fd1a4c197bf76d3b59af4b3372a 100644 (file)
--- a/arch/arm/mach-mx25/devices.c
+++ b/arch/arm/mach-mx25/devices.c
@@ -22,103 +22,6 @@
 #include <mach/mx25.h>
 #include <mach/irqs.h>
 
-static struct resource uart0[] = {
-       {
-               .start = 0x43f90000,
-               .end = 0x43f93fff,
-               .flags = IORESOURCE_MEM,
-       }, {
-               .start = 45,
-               .end = 45,
-               .flags = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device mxc_uart_device0 = {
-       .name = "imx-uart",
-       .id = 0,
-       .resource = uart0,
-       .num_resources = ARRAY_SIZE(uart0),
-};
-
-static struct resource uart1[] = {
-       {
-               .start = 0x43f94000,
-               .end = 0x43f97fff,
-               .flags = IORESOURCE_MEM,
-       }, {
-               .start = 32,
-               .end = 32,
-               .flags = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device mxc_uart_device1 = {
-       .name = "imx-uart",
-       .id = 1,
-       .resource = uart1,
-       .num_resources = ARRAY_SIZE(uart1),
-};
-
-static struct resource uart2[] = {
-       {
-               .start = 0x5000c000,
-               .end = 0x5000ffff,
-               .flags = IORESOURCE_MEM,
-       }, {
-               .start = 18,
-               .end = 18,
-               .flags = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device mxc_uart_device2 = {
-       .name = "imx-uart",
-       .id = 2,
-       .resource = uart2,
-       .num_resources = ARRAY_SIZE(uart2),
-};
-
-static struct resource uart3[] = {
-       {
-               .start = 0x50008000,
-               .end = 0x5000bfff,
-               .flags = IORESOURCE_MEM,
-       }, {
-               .start = 5,
-               .end = 5,
-               .flags = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device mxc_uart_device3 = {
-       .name = "imx-uart",
-       .id = 3,
-       .resource = uart3,
-       .num_resources = ARRAY_SIZE(uart3),
-};
-
-static struct resource uart4[] = {
-       {
-               .start = 0x5002c000,
-               .end = 0x5002ffff,
-               .flags = IORESOURCE_MEM,
-       }, {
-               .start = 40,
-               .end = 40,
-               .flags = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device mxc_uart_device4 = {
-       .name = "imx-uart",
-       .id = 4,
-       .resource = uart4,
-       .num_resources = ARRAY_SIZE(uart4),
-};
-
-#define MX25_OTG_BASE_ADDR 0x53FF4000
-
 static u64 otg_dmamask = DMA_BIT_MASK(32);
 
 static struct resource mxc_otg_resources[] = {
@@ -181,63 +84,6 @@ struct platform_device mxc_usbh2 = {
        .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
 };
 
-static struct resource mxc_spi_resources0[] = {
-       {
-              .start = 0x43fa4000,
-              .end = 0x43fa7fff,
-              .flags = IORESOURCE_MEM,
-       }, {
-              .start = 14,
-              .end = 14,
-              .flags = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device mxc_spi_device0 = {
-       .name = "spi_imx",
-       .id = 0,
-       .num_resources = ARRAY_SIZE(mxc_spi_resources0),
-       .resource = mxc_spi_resources0,
-};
-
-static struct resource mxc_spi_resources1[] = {
-       {
-              .start = 0x50010000,
-              .end = 0x50013fff,
-              .flags = IORESOURCE_MEM,
-       }, {
-              .start = 13,
-              .end = 13,
-              .flags = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device mxc_spi_device1 = {
-       .name = "spi_imx",
-       .id = 1,
-       .num_resources = ARRAY_SIZE(mxc_spi_resources1),
-       .resource = mxc_spi_resources1,
-};
-
-static struct resource mxc_spi_resources2[] = {
-       {
-              .start = 0x50004000,
-              .end = 0x50007fff,
-              .flags = IORESOURCE_MEM,
-       }, {
-              .start = 0,
-              .end = 0,
-              .flags = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device mxc_spi_device2 = {
-       .name = "spi_imx",
-       .id = 2,
-       .num_resources = ARRAY_SIZE(mxc_spi_resources2),
-       .resource = mxc_spi_resources2,
-};
-
 static struct resource mxc_pwm_resources0[] = {
        {
                .start  = 0x53fe0000,
@@ -333,63 +179,6 @@ struct platform_device mxc_pwm_device3 = {
        .resource = mxc_pwm_resources3,
 };
 
-static struct resource mxc_i2c_1_resources[] = {
-       {
-               .start  = 0x43f80000,
-               .end    = 0x43f83fff,
-               .flags  = IORESOURCE_MEM,
-       }, {
-               .start  = 3,
-               .end    = 3,
-               .flags  = IORESOURCE_IRQ,
-       }
-};
-
-struct platform_device mxc_i2c_device0 = {
-       .name = "imx-i2c",
-       .id = 0,
-       .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
-       .resource = mxc_i2c_1_resources,
-};
-
-static struct resource mxc_i2c_2_resources[] = {
-       {
-               .start  = 0x43f98000,
-               .end    = 0x43f9bfff,
-               .flags  = IORESOURCE_MEM,
-       }, {
-               .start  = 4,
-               .end    = 4,
-               .flags  = IORESOURCE_IRQ,
-       }
-};
-
-struct platform_device mxc_i2c_device1 = {
-       .name = "imx-i2c",
-       .id = 1,
-       .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
-       .resource = mxc_i2c_2_resources,
-};
-
-static struct resource mxc_i2c_3_resources[] = {
-       {
-               .start  = 0x43f84000,
-               .end    = 0x43f87fff,
-               .flags  = IORESOURCE_MEM,
-       }, {
-               .start  = 10,
-               .end    = 10,
-               .flags  = IORESOURCE_IRQ,
-       }
-};
-
-struct platform_device mxc_i2c_device2 = {
-       .name = "imx-i2c",
-       .id = 2,
-       .num_resources = ARRAY_SIZE(mxc_i2c_3_resources),
-       .resource = mxc_i2c_3_resources,
-};
-
 static struct mxc_gpio_port imx_gpio_ports[] = {
        {
                .chip.label = "gpio-0",
@@ -414,7 +203,7 @@ static struct mxc_gpio_port imx_gpio_ports[] = {
        }
 };
 
-int __init mxc_register_gpios(void)
+int __init imx25_register_gpios(void)
 {
        return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
 }
@@ -439,26 +228,6 @@ struct platform_device mx25_fec_device = {
        .resource       = mx25_fec_resources,
 };
 
-static struct resource mxc_nand_resources[] = {
-       {
-               .start  = MX25_NFC_BASE_ADDR,
-               .end    = MX25_NFC_BASE_ADDR + 0x1fff,
-               .flags  = IORESOURCE_MEM,
-       },
-       {
-               .start  = MX25_INT_NANDFC,
-               .end    = MX25_INT_NANDFC,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device mxc_nand_device = {
-       .name           = "mxc_nand",
-       .id             = 0,
-       .num_resources  = ARRAY_SIZE(mxc_nand_resources),
-       .resource       = mxc_nand_resources,
-};
-
 static struct resource mx25_rtc_resources[] = {
        {
                .start  = MX25_DRYICE_BASE_ADDR,
@@ -515,3 +284,83 @@ struct platform_device mxc_wdt = {
        .num_resources = ARRAY_SIZE(mxc_wdt_resources),
        .resource = mxc_wdt_resources,
 };
+
+static struct resource mx25_kpp_resources[] = {
+       {
+               .start  = MX25_KPP_BASE_ADDR,
+               .end    = MX25_KPP_BASE_ADDR + 0xf,
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .start  = MX25_INT_KPP,
+               .end    = MX25_INT_KPP,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+struct platform_device mx25_kpp_device = {
+       .name   = "imx-keypad",
+       .id     = -1,
+       .num_resources  = ARRAY_SIZE(mx25_kpp_resources),
+       .resource       = mx25_kpp_resources,
+};
+
+static struct resource imx_ssi_resources0[] = {
+       {
+               .start  = MX25_SSI1_BASE_ADDR,
+               .end    = MX25_SSI1_BASE_ADDR + 0x3fff,
+               .flags  = IORESOURCE_MEM,
+       }, {
+               .start  = MX25_INT_SSI1,
+               .end    = MX25_INT_SSI1,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct resource imx_ssi_resources1[] = {
+       {
+               .start  = MX25_SSI2_BASE_ADDR,
+               .end    = MX25_SSI2_BASE_ADDR + 0x3fff,
+               .flags  = IORESOURCE_MEM
+       }, {
+               .start  = MX25_INT_SSI2,
+               .end    = MX25_INT_SSI2,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+struct platform_device imx_ssi_device0 = {
+       .name = "imx-ssi",
+       .id = 0,
+       .num_resources = ARRAY_SIZE(imx_ssi_resources0),
+       .resource = imx_ssi_resources0,
+};
+
+struct platform_device imx_ssi_device1 = {
+       .name = "imx-ssi",
+       .id = 1,
+       .num_resources = ARRAY_SIZE(imx_ssi_resources1),
+       .resource = imx_ssi_resources1,
+};
+
+static struct resource mx25_csi_resources[] = {
+       {
+               .start  = MX25_CSI_BASE_ADDR,
+               .end    = MX25_CSI_BASE_ADDR + 0xfff,
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .start  = MX25_INT_CSI,
+               .flags  = IORESOURCE_IRQ
+       },
+};
+
+struct platform_device mx25_csi_device = {
+       .name   = "mx2-camera",
+       .id     = 0,
+       .num_resources  = ARRAY_SIZE(mx25_csi_resources),
+       .resource       = mx25_csi_resources,
+       .dev            = {
+               .coherent_dma_mask = 0xffffffff,
+       },
+};

diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h
index cee12c0a0be68e5988fcc8f914c94705dfe92beb..4aceb68e35a77003e11505dfb3eca338006263fb 100644 (file)
--- a/arch/arm/mach-mx25/devices.h
+++ b/arch/arm/mach-mx25/devices.h
@@ -1,24 +1,16 @@
-extern struct platform_device mxc_uart_device0;
-extern struct platform_device mxc_uart_device1;
-extern struct platform_device mxc_uart_device2;
-extern struct platform_device mxc_uart_device3;
-extern struct platform_device mxc_uart_device4;
 extern struct platform_device mxc_otg;
 extern struct platform_device otg_udc_device;
 extern struct platform_device mxc_usbh2;
-extern struct platform_device mxc_spi_device0;
-extern struct platform_device mxc_spi_device1;
-extern struct platform_device mxc_spi_device2;
 extern struct platform_device mxc_pwm_device0;
 extern struct platform_device mxc_pwm_device1;
 extern struct platform_device mxc_pwm_device2;
 extern struct platform_device mxc_pwm_device3;
 extern struct platform_device mxc_keypad_device;
-extern struct platform_device mxc_i2c_device0;
-extern struct platform_device mxc_i2c_device1;
-extern struct platform_device mxc_i2c_device2;
 extern struct platform_device mx25_fec_device;
-extern struct platform_device mxc_nand_device;
 extern struct platform_device mx25_rtc_device;
 extern struct platform_device mx25_fb_device;
 extern struct platform_device mxc_wdt;
+extern struct platform_device mx25_kpp_device;
+extern struct platform_device imx_ssi_device0;
+extern struct platform_device imx_ssi_device1;
+extern struct platform_device mx25_csi_device;

diff --git a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
new file mode 100644 (file)
index 0000000..91931dc
--- /dev/null
+++ b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
@@ -0,0 +1,260 @@
+/*
+ * Copyright (C) 2010 Eric Benard - eric@eukrea.com
+ *
+ * Based on pcm970-baseboard.c which is :
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <video/platform_lcd.h>
+
+#include <mach/hardware.h>
+#include <mach/iomux-mx25.h>
+#include <mach/common.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/mx25.h>
+#include <mach/imx-uart.h>
+#include <mach/imxfb.h>
+#include <mach/ssi.h>
+#include <mach/audmux.h>
+
+#include "devices-imx25.h"
+#include "devices.h"
+
+static struct pad_desc eukrea_mbimxsd_pads[] = {
+       /* LCD */
+       MX25_PAD_LD0__LD0,
+       MX25_PAD_LD1__LD1,
+       MX25_PAD_LD2__LD2,
+       MX25_PAD_LD3__LD3,
+       MX25_PAD_LD4__LD4,
+       MX25_PAD_LD5__LD5,
+       MX25_PAD_LD6__LD6,
+       MX25_PAD_LD7__LD7,
+       MX25_PAD_LD8__LD8,
+       MX25_PAD_LD9__LD9,
+       MX25_PAD_LD10__LD10,
+       MX25_PAD_LD11__LD11,
+       MX25_PAD_LD12__LD12,
+       MX25_PAD_LD13__LD13,
+       MX25_PAD_LD14__LD14,
+       MX25_PAD_LD15__LD15,
+       MX25_PAD_GPIO_E__LD16,
+       MX25_PAD_GPIO_F__LD17,
+       MX25_PAD_HSYNC__HSYNC,
+       MX25_PAD_VSYNC__VSYNC,
+       MX25_PAD_LSCLK__LSCLK,
+       MX25_PAD_OE_ACD__OE_ACD,
+       MX25_PAD_CONTRAST__CONTRAST,
+       /* LCD_PWR */
+       MX25_PAD_PWM__GPIO_1_26,
+       /* LED */
+       MX25_PAD_POWER_FAIL__GPIO_3_19,
+       /* SWITCH */
+       MX25_PAD_VSTBY_ACK__GPIO_3_18,
+       /* UART2 */
+       MX25_PAD_UART2_RTS__UART2_RTS,
+       MX25_PAD_UART2_CTS__UART2_CTS,
+       MX25_PAD_UART2_TXD__UART2_TXD,
+       MX25_PAD_UART2_RXD__UART2_RXD,
+       /* SD1 */
+       MX25_PAD_SD1_CMD__SD1_CMD,
+       MX25_PAD_SD1_CLK__SD1_CLK,
+       MX25_PAD_SD1_DATA0__SD1_DATA0,
+       MX25_PAD_SD1_DATA1__SD1_DATA1,
+       MX25_PAD_SD1_DATA2__SD1_DATA2,
+       MX25_PAD_SD1_DATA3__SD1_DATA3,
+       /* SD1 CD */
+       MX25_PAD_DE_B__GPIO_2_20,
+       /* I2S */
+       MX25_PAD_KPP_COL3__AUD5_TXFS,
+       MX25_PAD_KPP_COL2__AUD5_TXC,
+       MX25_PAD_KPP_COL1__AUD5_RXD,
+       MX25_PAD_KPP_COL0__AUD5_TXD,
+};
+
+#define GPIO_LED1      83
+#define GPIO_SWITCH1   82
+#define GPIO_SD1CD     52
+#define GPIO_LCDPWR    26
+
+static struct imx_fb_videomode eukrea_mximxsd_modes[] = {
+       {
+               .mode   = {
+                       .name           = "CMO-QVGA",
+                       .refresh        = 60,
+                       .xres           = 320,
+                       .yres           = 240,
+                       .pixclock       = KHZ2PICOS(6500),
+                       .left_margin    = 30,
+                       .right_margin   = 38,
+                       .upper_margin   = 20,
+                       .lower_margin   = 3,
+                       .hsync_len      = 15,
+                       .vsync_len      = 4,
+               },
+               .bpp    = 16,
+               .pcr    = 0xCAD08B80,
+       },
+};
+
+static struct imx_fb_platform_data eukrea_mximxsd_fb_pdata = {
+       .mode           = eukrea_mximxsd_modes,
+       .num_modes      = ARRAY_SIZE(eukrea_mximxsd_modes),
+       .pwmr           = 0x00A903FF,
+       .lscr1          = 0x00120300,
+       .dmacr          = 0x00040060,
+};
+
+static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
+                                  unsigned int power)
+{
+       if (power)
+               gpio_direction_output(GPIO_LCDPWR, 1);
+       else
+               gpio_direction_output(GPIO_LCDPWR, 0);
+}
+
+static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = {
+       .set_power              = eukrea_mbimxsd_lcd_power_set,
+};
+
+static struct platform_device eukrea_mbimxsd_lcd_powerdev = {
+       .name                   = "platform-lcd",
+       .dev.platform_data      = &eukrea_mbimxsd_lcd_power_data,
+};
+
+static struct gpio_led eukrea_mbimxsd_leds[] = {
+       {
+               .name                   = "led1",
+               .default_trigger        = "heartbeat",
+               .active_low             = 1,
+               .gpio                   = GPIO_LED1,
+       },
+};
+
+static struct gpio_led_platform_data eukrea_mbimxsd_led_info = {
+       .leds           = eukrea_mbimxsd_leds,
+       .num_leds       = ARRAY_SIZE(eukrea_mbimxsd_leds),
+};
+
+static struct platform_device eukrea_mbimxsd_leds_gpio = {
+       .name   = "leds-gpio",
+       .id     = -1,
+       .dev    = {
+               .platform_data  = &eukrea_mbimxsd_led_info,
+       },
+};
+
+static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
+       {
+               .gpio           = GPIO_SWITCH1,
+               .code           = BTN_0,
+               .desc           = "BP1",
+               .active_low     = 1,
+               .wakeup         = 1,
+       },
+};
+
+static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
+       .buttons        = eukrea_mbimxsd_gpio_buttons,
+       .nbuttons       = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
+};
+
+static struct platform_device eukrea_mbimxsd_button_device = {
+       .name           = "gpio-keys",
+       .id             = -1,
+       .num_resources  = 0,
+       .dev            = {
+               .platform_data  = &eukrea_mbimxsd_button_data,
+       }
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+       &eukrea_mbimxsd_leds_gpio,
+       &eukrea_mbimxsd_button_device,
+       &eukrea_mbimxsd_lcd_powerdev,
+};
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+       .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
+       {
+               I2C_BOARD_INFO("tlv320aic23", 0x1a),
+       },
+};
+
+struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = {
+       .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
+};
+
+/*
+ * system init for baseboard usage. Will be called by cpuimx25 init.
+ *
+ * Add platform devices present on this baseboard and init
+ * them from CPU side as far as required to use them later on
+ */
+void __init eukrea_mbimxsd_baseboard_init(void)
+{
+       if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
+                       ARRAY_SIZE(eukrea_mbimxsd_pads)))
+               printk(KERN_ERR "error setting mbimxsd pads !\n");
+
+#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
+       /* SSI unit master I2S codec connected to SSI_AUD5*/
+       mxc_audmux_v2_configure_port(0,
+                       MXC_AUDMUX_V2_PTCR_SYN |
+                       MXC_AUDMUX_V2_PTCR_TFSDIR |
+                       MXC_AUDMUX_V2_PTCR_TFSEL(4) |
+                       MXC_AUDMUX_V2_PTCR_TCLKDIR |
+                       MXC_AUDMUX_V2_PTCR_TCSEL(4),
+                       MXC_AUDMUX_V2_PDCR_RXDSEL(4)
+       );
+       mxc_audmux_v2_configure_port(4,
+                       MXC_AUDMUX_V2_PTCR_SYN,
+                       MXC_AUDMUX_V2_PDCR_RXDSEL(0)
+       );
+#endif
+
+       imx25_add_imx_uart1(&uart_pdata);
+       mxc_register_device(&mx25_fb_device, &eukrea_mximxsd_fb_pdata);
+       mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata);
+
+       gpio_request(GPIO_LED1, "LED1");
+       gpio_direction_output(GPIO_LED1, 1);
+       gpio_free(GPIO_LED1);
+
+       gpio_request(GPIO_SWITCH1, "SWITCH1");
+       gpio_direction_input(GPIO_SWITCH1);
+       gpio_free(GPIO_SWITCH1);
+
+       gpio_request(GPIO_LCDPWR, "LCDPWR");
+       gpio_direction_output(GPIO_LCDPWR, 1);
+       gpio_free(GPIO_SWITCH1);
+
+       i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
+                               ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
+
+       platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}

diff --git a/arch/arm/mach-mx25/mach-cpuimx25.c b/arch/arm/mach-mx25/mach-cpuimx25.c
new file mode 100644 (file)
index 0000000..56b2e26
--- /dev/null
+++ b/arch/arm/mach-mx25/mach-cpuimx25.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright 2009 Sascha Hauer, <kernel@pengutronix.de>
+ * Copyright 2010 Eric Bénard - Eukréa Electromatique, <eric@eukrea.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/fec.h>
+#include <linux/platform_device.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <linux/fsl_devices.h>
+
+#include <mach/eukrea-baseboards.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/memory.h>
+#include <asm/mach/map.h>
+#include <mach/common.h>
+#include <mach/mx25.h>
+#include <mach/mxc_nand.h>
+#include <mach/imxfb.h>
+#include <mach/mxc_ehci.h>
+#include <mach/ulpi.h>
+#include <mach/iomux-mx25.h>
+
+#include "devices-imx25.h"
+#include "devices.h"
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+       .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct pad_desc eukrea_cpuimx25_pads[] = {
+       /* FEC - RMII */
+       MX25_PAD_FEC_MDC__FEC_MDC,
+       MX25_PAD_FEC_MDIO__FEC_MDIO,
+       MX25_PAD_FEC_TDATA0__FEC_TDATA0,
+       MX25_PAD_FEC_TDATA1__FEC_TDATA1,
+       MX25_PAD_FEC_TX_EN__FEC_TX_EN,
+       MX25_PAD_FEC_RDATA0__FEC_RDATA0,
+       MX25_PAD_FEC_RDATA1__FEC_RDATA1,
+       MX25_PAD_FEC_RX_DV__FEC_RX_DV,
+       MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
+       /* I2C1 */
+       MX25_PAD_I2C1_CLK__I2C1_CLK,
+       MX25_PAD_I2C1_DAT__I2C1_DAT,
+};
+
+static struct fec_platform_data mx25_fec_pdata = {
+       .phy    = PHY_INTERFACE_MODE_RMII,
+};
+
+static const struct mxc_nand_platform_data
+eukrea_cpuimx25_nand_board_info __initconst = {
+       .width          = 1,
+       .hw_ecc         = 1,
+       .flash_bbt      = 1,
+};
+
+static const struct imxi2c_platform_data
+eukrea_cpuimx25_i2c0_data __initconst = {
+       .bitrate = 100000,
+};
+
+static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = {
+       {
+               I2C_BOARD_INFO("pcf8563", 0x51),
+       },
+};
+
+static struct mxc_usbh_platform_data otg_pdata = {
+       .portsc = MXC_EHCI_MODE_UTMI,
+       .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
+};
+
+static struct mxc_usbh_platform_data usbh2_pdata = {
+       .portsc = MXC_EHCI_MODE_SERIAL,
+       .flags  = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
+                 MXC_EHCI_IPPUE_DOWN,
+};
+
+static struct fsl_usb2_platform_data otg_device_pdata = {
+       .operating_mode = FSL_USB2_DR_DEVICE,
+       .phy_mode       = FSL_USB2_PHY_UTMI,
+};
+
+static int otg_mode_host;
+
+static int __init eukrea_cpuimx25_otg_mode(char *options)
+{
+       if (!strcmp(options, "host"))
+               otg_mode_host = 1;
+       else if (!strcmp(options, "device"))
+               otg_mode_host = 0;
+       else
+               pr_info("otg_mode neither \"host\" nor \"device\". "
+                       "Defaulting to device\n");
+       return 0;
+}
+__setup("otg_mode=", eukrea_cpuimx25_otg_mode);
+
+static void __init eukrea_cpuimx25_init(void)
+{
+       if (mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads,
+                       ARRAY_SIZE(eukrea_cpuimx25_pads)))
+               printk(KERN_ERR "error setting cpuimx25 pads !\n");
+
+       imx25_add_imx_uart0(&uart_pdata);
+       imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info);
+       mxc_register_device(&mx25_rtc_device, NULL);
+       mxc_register_device(&mx25_fec_device, &mx25_fec_pdata);
+
+       i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices,
+                               ARRAY_SIZE(eukrea_cpuimx25_i2c_devices));
+       imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data);
+
+#if defined(CONFIG_USB_ULPI)
+       if (otg_mode_host) {
+               otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                               USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+
+               mxc_register_device(&mxc_otg, &otg_pdata);
+       }
+       mxc_register_device(&mxc_usbh2, &usbh2_pdata);
+#endif
+       if (!otg_mode_host)
+               mxc_register_device(&otg_udc_device, &otg_device_pdata);
+
+#ifdef CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD
+       eukrea_mbimxsd_baseboard_init();
+#endif
+}
+
+static void __init eukrea_cpuimx25_timer_init(void)
+{
+       mx25_clocks_init();
+}
+
+static struct sys_timer eukrea_cpuimx25_timer = {
+       .init   = eukrea_cpuimx25_timer_init,
+};
+
+MACHINE_START(EUKREA_CPUIMX25, "Eukrea CPUIMX25")
+       /* Maintainer: Eukrea Electromatique */
+       .phys_io        = MX25_AIPS1_BASE_ADDR,
+       .io_pg_offst    = ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+       .boot_params    = MX25_PHYS_OFFSET + 0x100,
+       .map_io         = mx25_map_io,
+       .init_irq       = mx25_init_irq,
+       .init_machine   = eukrea_cpuimx25_init,
+       .timer          = &eukrea_cpuimx25_timer,
+MACHINE_END

diff --git a/arch/arm/mach-mx25/mach-mx25pdk.c b/arch/arm/mach-mx25/mach-mx25_3ds.c
similarity index 76%
rename from arch/arm/mach-mx25/mach-mx25pdk.c
rename to arch/arm/mach-mx25/mach-mx25_3ds.c
index 83d74109e7d837fb8e53f4c803652e4bae4cae4d..62bc21f11a714aa46df5e439d4965f340d59460a 100644 (file)
--- a/arch/arm/mach-mx25/mach-mx25pdk.c
+++ b/arch/arm/mach-mx25/mach-mx25_3ds.c
@@ -16,6 +16,12 @@
  * Boston, MA  02110-1301, USA.
  */
 
+/*
+ * This machine is known as:
+ *  - i.MX25 3-Stack Development System
+ *  - i.MX25 Platform Development Kit (i.MX25 PDK)
+ */
+
 #include <linux/types.h>
 #include <linux/init.h>
 #include <linux/delay.h>
@@ -24,6 +30,7 @@
 #include <linux/gpio.h>
 #include <linux/fec.h>
 #include <linux/platform_device.h>
+#include <linux/input/matrix_keypad.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -32,14 +39,14 @@
 #include <asm/memory.h>
 #include <asm/mach/map.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/mx25.h>
-#include <mach/mxc_nand.h>
 #include <mach/imxfb.h>
-#include "devices.h"
 #include <mach/iomux-mx25.h>
 
-static struct imxuart_platform_data uart_pdata = {
+#include "devices-imx25.h"
+#include "devices.h"
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -80,6 +87,16 @@ static struct pad_desc mx25pdk_pads[] = {
        MX25_PAD_LSCLK__LSCLK,
        MX25_PAD_OE_ACD__OE_ACD,
        MX25_PAD_CONTRAST__CONTRAST,
+
+       /* Keypad */
+       MX25_PAD_KPP_ROW0__KPP_ROW0,
+       MX25_PAD_KPP_ROW1__KPP_ROW1,
+       MX25_PAD_KPP_ROW2__KPP_ROW2,
+       MX25_PAD_KPP_ROW3__KPP_ROW3,
+       MX25_PAD_KPP_COL0__KPP_COL0,
+       MX25_PAD_KPP_COL1__KPP_COL1,
+       MX25_PAD_KPP_COL2__KPP_COL2,
+       MX25_PAD_KPP_COL3__KPP_COL3,
 };
 
 static struct fec_platform_data mx25_fec_pdata = {
@@ -103,7 +120,8 @@ static void __init mx25pdk_fec_reset(void)
        gpio_set_value(FEC_RESET_B_GPIO, 1);
 }
 
-static struct mxc_nand_platform_data mx25pdk_nand_board_info = {
+static const struct mxc_nand_platform_data
+mx25pdk_nand_board_info __initconst = {
        .width          = 1,
        .hw_ecc         = 1,
        .flash_bbt      = 1,
@@ -137,19 +155,45 @@ static struct imx_fb_platform_data mx25pdk_fb_pdata = {
        .dmacr          = 0x00020010,
 };
 
+static const uint32_t mx25pdk_keymap[] = {
+       KEY(0, 0, KEY_UP),
+       KEY(0, 1, KEY_DOWN),
+       KEY(0, 2, KEY_VOLUMEDOWN),
+       KEY(0, 3, KEY_HOME),
+       KEY(1, 0, KEY_RIGHT),
+       KEY(1, 1, KEY_LEFT),
+       KEY(1, 2, KEY_ENTER),
+       KEY(1, 3, KEY_VOLUMEUP),
+       KEY(2, 0, KEY_F6),
+       KEY(2, 1, KEY_F8),
+       KEY(2, 2, KEY_F9),
+       KEY(2, 3, KEY_F10),
+       KEY(3, 0, KEY_F1),
+       KEY(3, 1, KEY_F2),
+       KEY(3, 2, KEY_F3),
+       KEY(3, 3, KEY_POWER),
+};
+
+static struct matrix_keymap_data mx25pdk_keymap_data = {
+       .keymap         = mx25pdk_keymap,
+       .keymap_size    = ARRAY_SIZE(mx25pdk_keymap),
+};
+
 static void __init mx25pdk_init(void)
 {
        mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
                        ARRAY_SIZE(mx25pdk_pads));
 
-       mxc_register_device(&mxc_uart_device0, &uart_pdata);
+       imx25_add_imx_uart0(&uart_pdata);
        mxc_register_device(&mxc_usbh2, NULL);
-       mxc_register_device(&mxc_nand_device, &mx25pdk_nand_board_info);
+       imx25_add_mxc_nand(&mx25pdk_nand_board_info);
        mxc_register_device(&mx25_rtc_device, NULL);
        mxc_register_device(&mx25_fb_device, &mx25pdk_fb_pdata);
+       mxc_register_device(&mxc_wdt, NULL);
 
        mx25pdk_fec_reset();
        mxc_register_device(&mx25_fec_device, &mx25_fec_pdata);
+       mxc_register_device(&mx25_kpp_device, &mx25pdk_keymap_data);
 }
 
 static void __init mx25pdk_timer_init(void)

diff --git a/arch/arm/mach-mx25/mm.c b/arch/arm/mach-mx25/mm.c
index a7e587ff3e9ebc5b0821f4a506548b7bd7e1b817..bb677111fb0f11cca20f5ff143cf397412b92587 100644 (file)
--- a/arch/arm/mach-mx25/mm.c
+++ b/arch/arm/mach-mx25/mm.c
@@ -14,10 +14,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/mm.h>
@@ -69,8 +65,11 @@ void __init mx25_map_io(void)
        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
 
+int imx25_register_gpios(void);
+
 void __init mx25_init_irq(void)
 {
        mxc_init_irq((void __iomem *)MX25_AVIC_BASE_ADDR_VIRT);
+       imx25_register_gpios();
 }
 

diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 344753fdf25ef47ac6856ff5058f9cc8a193120a..85beece802aab702a71331f63fd6ff7065adb7bb 100644 (file)
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -15,6 +15,8 @@ comment "MX3 platforms:"
 config MACH_MX31ADS
        bool "Support MX31ADS platforms"
        select ARCH_MX31
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_IMX_UART
        default y
        help
          Include support for MX31ADS platform. This includes specific
@@ -34,6 +36,9 @@ config MACH_MX31ADS_WM1133_EV1
 config MACH_PCM037
        bool "Support Phytec pcm037 (i.MX31) platforms"
        select ARCH_MX31
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_MXC_NAND
        select MXC_ULPI if USB_ULPI
        help
          Include support for Phytec pcm037 platform. This includes
@@ -42,6 +47,7 @@ config MACH_PCM037
 config MACH_PCM037_EET
        bool "Support pcm037 EET board extensions"
        depends on MACH_PCM037
+       select IMX_HAVE_PLATFORM_SPI_IMX
        help
          Add support for PCM037 EET baseboard extensions. If you are using the
          OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel
@@ -51,6 +57,9 @@ config MACH_MX31LITE
        bool "Support MX31 LITEKIT (LogicPD)"
        select ARCH_MX31
        select MXC_ULPI if USB_ULPI
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_MXC_NAND
+       select IMX_HAVE_PLATFORM_SPI_IMX
        help
          Include support for MX31 LITEKIT platform. This includes specific
          configurations for the board and its peripherals.
@@ -58,6 +67,10 @@ config MACH_MX31LITE
 config MACH_MX31_3DS
        bool "Support MX31PDK (3DS)"
        select ARCH_MX31
+       select MXC_DEBUG_BOARD
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_MXC_NAND
+       select IMX_HAVE_PLATFORM_SPI_IMX
        help
          Include support for MX31PDK (3DS) platform. This includes specific
          configurations for the board and its peripherals.
@@ -74,6 +87,9 @@ config MACH_MX31_3DS_MXC_NAND_USE_BBT
 config MACH_MX31MOBOARD
        bool "Support mx31moboard platforms (EPFL Mobots group)"
        select ARCH_MX31
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_SPI_IMX
        select MXC_ULPI if USB_ULPI
        help
          Include support for mx31moboard platform. This includes specific
@@ -82,6 +98,8 @@ config MACH_MX31MOBOARD
 config MACH_MX31LILLY
        bool "Support MX31 LILLY-1131 platforms (INCO startec)"
        select ARCH_MX31
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_SPI_IMX
        select MXC_ULPI if USB_ULPI
        help
          Include support for mx31 based LILLY1131 modules. This includes
@@ -90,6 +108,7 @@ config MACH_MX31LILLY
 config MACH_QONG
        bool "Support Dave/DENX QongEVB-LITE platform"
        select ARCH_MX31
+       select IMX_HAVE_PLATFORM_IMX_UART
        help
          Include support for Dave/DENX QongEVB-LITE platform. This includes
          specific configurations for the board and its peripherals.
@@ -97,6 +116,10 @@ config MACH_QONG
 config MACH_PCM043
        bool "Support Phytec pcm043 (i.MX35) platforms"
        select ARCH_MX35
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_MXC_NAND
+       select IMX_HAVE_PLATFORM_FLEXCAN
        select MXC_ULPI if USB_ULPI
        help
          Include support for Phytec pcm043 platform. This includes
@@ -105,6 +128,9 @@ config MACH_PCM043
 config MACH_ARMADILLO5X0
        bool "Support Atmark Armadillo-500 Development Base Board"
        select ARCH_MX31
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_MXC_NAND
        select MXC_ULPI if USB_ULPI
        help
          Include support for Atmark Armadillo-500 platform. This includes
@@ -113,6 +139,7 @@ config MACH_ARMADILLO5X0
 config MACH_MX35_3DS
        bool "Support MX35PDK platform"
        select ARCH_MX35
+       select IMX_HAVE_PLATFORM_IMX_UART
        default n
        help
          Include support for MX35PDK platform. This includes specific
@@ -121,8 +148,34 @@ config MACH_MX35_3DS
 config MACH_KZM_ARM11_01
        bool "Support KZM-ARM11-01(Kyoto Microcomputer)"
        select ARCH_MX31
+       select IMX_HAVE_PLATFORM_IMX_UART
        help
          Include support for KZM-ARM11-01. This includes specific
          configurations for the board and its peripherals.
 
+config MACH_EUKREA_CPUIMX35
+       bool "Support Eukrea CPUIMX35 Platform"
+       select ARCH_MX35
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_MXC_NAND
+       select MXC_ULPI if USB_ULPI
+       help
+         Include support for Eukrea CPUIMX35 platform. This includes
+         specific configurations for the board and its peripherals.
+
+choice
+       prompt "Baseboard"
+       depends on MACH_EUKREA_CPUIMX35
+       default MACH_EUKREA_MBIMXSD35_BASEBOARD
+
+config MACH_EUKREA_MBIMXSD35_BASEBOARD
+       prompt "Eukrea MBIMXSD development board"
+       bool
+       help
+         This adds board specific devices that can be found on Eukrea's
+         MBIMXSD evaluation board.
+
+endchoice
+
 endif

diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index 5d650fda5d5d3f0653c0cedc287068d98eb0a476..2bd7beceb99182879a7100d14e6d54dd5cdac6a2 100644 (file)
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -22,5 +22,7 @@ obj-$(CONFIG_MACH_MX31MOBOARD)        += mach-mx31moboard.o mx31moboard-devboard.o \
 obj-$(CONFIG_MACH_QONG)                += mach-qong.o
 obj-$(CONFIG_MACH_PCM043)      += mach-pcm043.o
 obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
-obj-$(CONFIG_MACH_MX35_3DS)    += mach-mx35pdk.o
+obj-$(CONFIG_MACH_MX35_3DS)    += mach-mx35_3ds.o
 obj-$(CONFIG_MACH_KZM_ARM11_01)        += mach-kzm_arm11_01.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX35)     += mach-cpuimx35.o
+obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD)  += eukrea_mbimxsd-baseboard.o

diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
index 9f3e943e22326cf0b0f8024194414de457a66356..d3af0fdf8475f7ef0d67b3afbb080df739c36431 100644 (file)
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ b/arch/arm/mach-mx3/clock-imx35.c
@@ -359,7 +359,7 @@ DEFINE_CLOCK(i2c1_clk,   0, CCM_CGR1, 10, get_rate_ipg_per, NULL);
 DEFINE_CLOCK(i2c2_clk,   1, CCM_CGR1, 12, get_rate_ipg_per, NULL);
 DEFINE_CLOCK(i2c3_clk,   2, CCM_CGR1, 14, get_rate_ipg_per, NULL);
 DEFINE_CLOCK(iomuxc_clk, 0, CCM_CGR1, 16, NULL, NULL);
-DEFINE_CLOCK(ipu_clk,    0, CCM_CGR1, 18, NULL, NULL);
+DEFINE_CLOCK(ipu_clk,    0, CCM_CGR1, 18, get_rate_ahb, NULL);
 DEFINE_CLOCK(kpp_clk,    0, CCM_CGR1, 20, get_rate_ipg, NULL);
 DEFINE_CLOCK(mlb_clk,    0, CCM_CGR1, 22, get_rate_ahb, NULL);
 DEFINE_CLOCK(mshc_clk,   0, CCM_CGR1, 24, get_rate_mshc, NULL);
@@ -428,8 +428,8 @@ static struct clk nfc_clk = {
 static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK(NULL, "asrc", asrc_clk)
        _REGISTER_CLOCK(NULL, "ata", ata_clk)
-       _REGISTER_CLOCK(NULL, "can", can1_clk)
-       _REGISTER_CLOCK(NULL, "can", can2_clk)
+       _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
+       _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
        _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
        _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
        _REGISTER_CLOCK(NULL, "ect", ect_clk)

diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h
new file mode 100644 (file)
index 0000000..3b1a44a
--- /dev/null
+++ b/arch/arm/mach-mx3/devices-imx31.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx31.h>
+#include <mach/devices-common.h>
+
+#define imx31_add_imx_i2c0(pdata)      \
+       imx_add_imx_i2c(0, MX31_I2C1_BASE_ADDR, SZ_4K, MX31_INT_I2C1, pdata)
+#define imx31_add_imx_i2c1(pdata)      \
+       imx_add_imx_i2c(1, MX31_I2C2_BASE_ADDR, SZ_4K, MX31_INT_I2C2, pdata)
+#define imx31_add_imx_i2c2(pdata)      \
+       imx_add_imx_i2c(2, MX31_I2C3_BASE_ADDR, SZ_4K, MX31_INT_I2C3, pdata)
+
+#define imx31_add_imx_uart0(pdata)     \
+       imx_add_imx_uart_1irq(0, MX31_UART1_BASE_ADDR, SZ_16K, MX31_INT_UART1, pdata)
+#define imx31_add_imx_uart1(pdata)     \
+       imx_add_imx_uart_1irq(1, MX31_UART2_BASE_ADDR, SZ_16K, MX31_INT_UART2, pdata)
+#define imx31_add_imx_uart2(pdata)     \
+       imx_add_imx_uart_1irq(2, MX31_UART3_BASE_ADDR, SZ_16K, MX31_INT_UART3, pdata)
+#define imx31_add_imx_uart3(pdata)     \
+       imx_add_imx_uart_1irq(3, MX31_UART4_BASE_ADDR, SZ_16K, MX31_INT_UART4, pdata)
+#define imx31_add_imx_uart4(pdata)     \
+       imx_add_imx_uart_1irq(4, MX31_UART5_BASE_ADDR, SZ_16K, MX31_INT_UART5, pdata)
+
+#define imx31_add_mxc_nand(pdata)      \
+       imx_add_mxc_nand_v1(MX31_NFC_BASE_ADDR, MX31_INT_NANDFC, pdata)
+
+#define imx31_add_spi_imx0(pdata)      \
+       imx_add_spi_imx(0, MX31_CSPI1_BASE_ADDR, SZ_4K, MX31_INT_CSPI1, pdata)
+#define imx31_add_spi_imx1(pdata)      \
+       imx_add_spi_imx(1, MX31_CSPI2_BASE_ADDR, SZ_4K, MX31_INT_CSPI2, pdata)
+#define imx31_add_spi_imx2(pdata)      \
+       imx_add_spi_imx(2, MX31_CSPI3_BASE_ADDR, SZ_4K, MX31_INT_CSPI3, pdata)

diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h
new file mode 100644 (file)
index 0000000..f6a431a
--- /dev/null
+++ b/arch/arm/mach-mx3/devices-imx35.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx35.h>
+#include <mach/devices-common.h>
+
+#define imx35_add_flexcan0(pdata)      \
+       imx_add_flexcan(0, MX35_CAN1_BASE_ADDR, SZ_16K, MX35_INT_CAN1, pdata)
+#define imx35_add_flexcan1(pdata)      \
+       imx_add_flexcan(1, MX35_CAN2_BASE_ADDR, SZ_16K, MX35_INT_CAN2, pdata)
+
+#define imx35_add_imx_i2c0(pdata)      \
+       imx_add_imx_i2c(0, MX35_I2C1_BASE_ADDR, SZ_4K, MX35_INT_I2C1, pdata)
+#define imx35_add_imx_i2c1(pdata)      \
+       imx_add_imx_i2c(1, MX35_I2C2_BASE_ADDR, SZ_4K, MX35_INT_I2C2, pdata)
+#define imx35_add_imx_i2c2(pdata)      \
+       imx_add_imx_i2c(2, MX35_I2C3_BASE_ADDR, SZ_4K, MX35_INT_I2C3, pdata)
+
+#define imx35_add_imx_uart0(pdata)     \
+       imx_add_imx_uart_1irq(0, MX35_UART1_BASE_ADDR, SZ_16K, MX35_INT_UART1, pdata)
+#define imx35_add_imx_uart1(pdata)     \
+       imx_add_imx_uart_1irq(1, MX35_UART2_BASE_ADDR, SZ_16K, MX35_INT_UART2, pdata)
+#define imx35_add_imx_uart2(pdata)     \
+       imx_add_imx_uart_1irq(2, MX35_UART3_BASE_ADDR, SZ_16K, MX35_INT_UART3, pdata)
+
+#define imx35_add_mxc_nand(pdata)      \
+       imx_add_mxc_nand_v21(MX35_NFC_BASE_ADDR, MX35_INT_NANDFC, pdata)
+
+#define imx35_add_spi_imx0(pdata)      \
+       imx_add_spi_imx(0, MX35_CSPI1_BASE_ADDR, SZ_4K, MX35_INT_CSPI1, pdata)
+#define imx35_add_spi_imx1(pdata)      \
+       imx_add_spi_imx(1, MX35_CSPI2_BASE_ADDR, SZ_4K, MX35_INT_CSPI2, pdata)

diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index db7acd6e910160cc230736ff3eb441eff255f2d0..a4fd1a26fc91982d200d76c7a152eb5c62610a7b 100644 (file)
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -25,108 +25,10 @@
 #include <mach/hardware.h>
 #include <mach/irqs.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/mx3_camera.h>
 
 #include "devices.h"
 
-static struct resource uart0[] = {
-       {
-               .start = UART1_BASE_ADDR,
-               .end = UART1_BASE_ADDR + 0x0B5,
-               .flags = IORESOURCE_MEM,
-       }, {
-               .start = MXC_INT_UART1,
-               .end = MXC_INT_UART1,
-               .flags = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device mxc_uart_device0 = {
-       .name = "imx-uart",
-       .id = 0,
-       .resource = uart0,
-       .num_resources = ARRAY_SIZE(uart0),
-};
-
-static struct resource uart1[] = {
-       {
-               .start = UART2_BASE_ADDR,
-               .end = UART2_BASE_ADDR + 0x0B5,
-               .flags = IORESOURCE_MEM,
-       }, {
-               .start = MXC_INT_UART2,
-               .end = MXC_INT_UART2,
-               .flags = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device mxc_uart_device1 = {
-       .name = "imx-uart",
-       .id = 1,
-       .resource = uart1,
-       .num_resources = ARRAY_SIZE(uart1),
-};
-
-static struct resource uart2[] = {
-       {
-               .start = UART3_BASE_ADDR,
-               .end = UART3_BASE_ADDR + 0x0B5,
-               .flags = IORESOURCE_MEM,
-       }, {
-               .start = MXC_INT_UART3,
-               .end = MXC_INT_UART3,
-               .flags = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device mxc_uart_device2 = {
-       .name = "imx-uart",
-       .id = 2,
-       .resource = uart2,
-       .num_resources = ARRAY_SIZE(uart2),
-};
-
-#ifdef CONFIG_ARCH_MX31
-static struct resource uart3[] = {
-       {
-               .start = UART4_BASE_ADDR,
-               .end = UART4_BASE_ADDR + 0x0B5,
-               .flags = IORESOURCE_MEM,
-       }, {
-               .start = MXC_INT_UART4,
-               .end = MXC_INT_UART4,
-               .flags = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device mxc_uart_device3 = {
-       .name = "imx-uart",
-       .id = 3,
-       .resource = uart3,
-       .num_resources = ARRAY_SIZE(uart3),
-};
-
-static struct resource uart4[] = {
-       {
-               .start = UART5_BASE_ADDR,
-               .end = UART5_BASE_ADDR + 0x0B5,
-               .flags = IORESOURCE_MEM,
-       }, {
-               .start = MXC_INT_UART5,
-               .end = MXC_INT_UART5,
-               .flags = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device mxc_uart_device4 = {
-       .name = "imx-uart",
-       .id = 4,
-       .resource = uart4,
-       .num_resources = ARRAY_SIZE(uart4),
-};
-#endif /* CONFIG_ARCH_MX31 */
-
 /* GPIO port description */
 static struct mxc_gpio_port imx_gpio_ports[] = {
        {
@@ -147,7 +49,7 @@ static struct mxc_gpio_port imx_gpio_ports[] = {
        }
 };
 
-int __init mxc_register_gpios(void)
+int __init imx3x_register_gpios(void)
 {
        return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
 }
@@ -167,82 +69,6 @@ struct platform_device mxc_w1_master_device = {
        .resource = mxc_w1_master_resources,
 };
 
-static struct resource mxc_nand_resources[] = {
-       {
-               .start  = 0, /* runtime dependent */
-               .end    = 0,
-               .flags  = IORESOURCE_MEM,
-       }, {
-               .start  = MXC_INT_NANDFC,
-               .end    = MXC_INT_NANDFC,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device mxc_nand_device = {
-       .name = "mxc_nand",
-       .id = 0,
-       .num_resources = ARRAY_SIZE(mxc_nand_resources),
-       .resource = mxc_nand_resources,
-};
-
-static struct resource mxc_i2c0_resources[] = {
-       {
-               .start = I2C_BASE_ADDR,
-               .end = I2C_BASE_ADDR + SZ_4K - 1,
-               .flags = IORESOURCE_MEM,
-       }, {
-               .start = MXC_INT_I2C,
-               .end = MXC_INT_I2C,
-               .flags = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device mxc_i2c_device0 = {
-       .name = "imx-i2c",
-       .id = 0,
-       .num_resources = ARRAY_SIZE(mxc_i2c0_resources),
-       .resource = mxc_i2c0_resources,
-};
-
-static struct resource mxc_i2c1_resources[] = {
-       {
-               .start = I2C2_BASE_ADDR,
-               .end = I2C2_BASE_ADDR + SZ_4K - 1,
-               .flags = IORESOURCE_MEM,
-       }, {
-               .start = MXC_INT_I2C2,
-               .end = MXC_INT_I2C2,
-               .flags = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device mxc_i2c_device1 = {
-       .name = "imx-i2c",
-       .id = 1,
-       .num_resources = ARRAY_SIZE(mxc_i2c1_resources),
-       .resource = mxc_i2c1_resources,
-};
-
-static struct resource mxc_i2c2_resources[] = {
-       {
-               .start = I2C3_BASE_ADDR,
-               .end = I2C3_BASE_ADDR + SZ_4K - 1,
-               .flags = IORESOURCE_MEM,
-       }, {
-               .start = MXC_INT_I2C3,
-               .end = MXC_INT_I2C3,
-               .flags = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device mxc_i2c_device2 = {
-       .name = "imx-i2c",
-       .id = 2,
-       .num_resources = ARRAY_SIZE(mxc_i2c2_resources),
-       .resource = mxc_i2c2_resources,
-};
-
 #ifdef CONFIG_ARCH_MX31
 static struct resource mxcsdhc0_resources[] = {
        {
@@ -455,68 +281,7 @@ struct platform_device mxc_usbh2 = {
        .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
 };
 
-/*
- * SPI master controller
- * 3 channels
- */
-static struct resource mxc_spi_0_resources[] = {
-       {
-              .start = CSPI1_BASE_ADDR,
-              .end = CSPI1_BASE_ADDR + SZ_4K - 1,
-              .flags = IORESOURCE_MEM,
-       }, {
-              .start = MXC_INT_CSPI1,
-              .end = MXC_INT_CSPI1,
-              .flags = IORESOURCE_IRQ,
-       },
-};
-
-static struct resource mxc_spi_1_resources[] = {
-       {
-               .start = CSPI2_BASE_ADDR,
-               .end = CSPI2_BASE_ADDR + SZ_4K - 1,
-               .flags = IORESOURCE_MEM,
-       }, {
-               .start = MXC_INT_CSPI2,
-               .end = MXC_INT_CSPI2,
-               .flags = IORESOURCE_IRQ,
-       },
-};
-
-static struct resource mxc_spi_2_resources[] = {
-       {
-               .start = CSPI3_BASE_ADDR,
-               .end = CSPI3_BASE_ADDR + SZ_4K - 1,
-               .flags = IORESOURCE_MEM,
-       }, {
-               .start = MXC_INT_CSPI3,
-               .end = MXC_INT_CSPI3,
-               .flags = IORESOURCE_IRQ,
-       },
-};
-
-struct platform_device mxc_spi_device0 = {
-       .name = "spi_imx",
-       .id = 0,
-       .num_resources = ARRAY_SIZE(mxc_spi_0_resources),
-       .resource = mxc_spi_0_resources,
-};
-
-struct platform_device mxc_spi_device1 = {
-       .name = "spi_imx",
-       .id = 1,
-       .num_resources = ARRAY_SIZE(mxc_spi_1_resources),
-       .resource = mxc_spi_1_resources,
-};
-
-struct platform_device mxc_spi_device2 = {
-       .name = "spi_imx",
-       .id = 2,
-       .num_resources = ARRAY_SIZE(mxc_spi_2_resources),
-       .resource = mxc_spi_2_resources,
-};
-
-#ifdef CONFIG_ARCH_MX35
+#if defined(CONFIG_ARCH_MX35)
 static struct resource mxc_fec_resources[] = {
        {
                .start  = MXC_FEC_BASE_ADDR,
@@ -628,16 +393,15 @@ struct platform_device imx_kpp_device = {
 
 static int __init mx3_devices_init(void)
 {
+#if defined(CONFIG_ARCH_MX31)
        if (cpu_is_mx31()) {
-               mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR;
-               mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff;
                imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR;
                imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff;
                mxc_register_device(&mxc_rnga_device, NULL);
        }
+#endif
+#if defined(CONFIG_ARCH_MX35)
        if (cpu_is_mx35()) {
-               mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
-               mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0x1fff;
                otg_resources[0].start = MX35_OTG_BASE_ADDR;
                otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
                otg_resources[1].start = MXC_INT_USBOTG;
@@ -653,6 +417,7 @@ static int __init mx3_devices_init(void)
                imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
                imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
        }
+#endif
 
        return 0;
 }

diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index 2c3c8646a29ef701c3872483ddf44901332b4858..e5535234839f5e1ae8159d0513e8bf9c0952d7c7 100644 (file)
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -1,14 +1,4 @@
-
-extern struct platform_device mxc_uart_device0;
-extern struct platform_device mxc_uart_device1;
-extern struct platform_device mxc_uart_device2;
-extern struct platform_device mxc_uart_device3;
-extern struct platform_device mxc_uart_device4;
 extern struct platform_device mxc_w1_master_device;
-extern struct platform_device mxc_nand_device;
-extern struct platform_device mxc_i2c_device0;
-extern struct platform_device mxc_i2c_device1;
-extern struct platform_device mxc_i2c_device2;
 extern struct platform_device mx3_ipu;
 extern struct platform_device mx3_fb;
 extern struct platform_device mx3_camera;
@@ -20,9 +10,6 @@ extern struct platform_device mxc_otg_host;
 extern struct platform_device mxc_usbh1;
 extern struct platform_device mxc_usbh2;
 extern struct platform_device mxc_rnga_device;
-extern struct platform_device mxc_spi_device0;
-extern struct platform_device mxc_spi_device1;
-extern struct platform_device mxc_spi_device2;
 extern struct platform_device imx_ssi_device0;
 extern struct platform_device imx_ssi_device1;
 extern struct platform_device imx_ssi_device1;

diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
new file mode 100644 (file)
index 0000000..1dc5004
--- /dev/null
+++ b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
@@ -0,0 +1,263 @@
+/*
+ * Copyright (C) 2010 Eric Benard - eric@eukrea.com
+ *
+ * Based on pcm970-baseboard.c which is :
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <video/platform_lcd.h>
+#include <linux/i2c.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx35.h>
+#include <mach/ipu.h>
+#include <mach/mx3fb.h>
+#include <mach/audmux.h>
+#include <mach/ssi.h>
+
+#include "devices-imx35.h"
+#include "devices.h"
+
+static const struct fb_videomode fb_modedb[] = {
+       {
+               .name           = "CMO_QVGA",
+               .refresh        = 60,
+               .xres           = 320,
+               .yres           = 240,
+               .pixclock       = KHZ2PICOS(6500),
+               .left_margin    = 68,
+               .right_margin   = 20,
+               .upper_margin   = 15,
+               .lower_margin   = 4,
+               .hsync_len      = 30,
+               .vsync_len      = 3,
+               .sync           = 0,
+               .vmode          = FB_VMODE_NONINTERLACED,
+               .flag           = 0,
+       },
+};
+
+static struct ipu_platform_data mx3_ipu_data = {
+       .irq_base = MXC_IPU_IRQ_START,
+};
+
+static struct mx3fb_platform_data mx3fb_pdata = {
+       .dma_dev        = &mx3_ipu.dev,
+       .name           = "CMO_QVGA",
+       .mode           = fb_modedb,
+       .num_modes      = ARRAY_SIZE(fb_modedb),
+};
+
+static struct pad_desc eukrea_mbimxsd_pads[] = {
+       /* LCD */
+       MX35_PAD_LD0__IPU_DISPB_DAT_0,
+       MX35_PAD_LD1__IPU_DISPB_DAT_1,
+       MX35_PAD_LD2__IPU_DISPB_DAT_2,
+       MX35_PAD_LD3__IPU_DISPB_DAT_3,
+       MX35_PAD_LD4__IPU_DISPB_DAT_4,
+       MX35_PAD_LD5__IPU_DISPB_DAT_5,
+       MX35_PAD_LD6__IPU_DISPB_DAT_6,
+       MX35_PAD_LD7__IPU_DISPB_DAT_7,
+       MX35_PAD_LD8__IPU_DISPB_DAT_8,
+       MX35_PAD_LD9__IPU_DISPB_DAT_9,
+       MX35_PAD_LD10__IPU_DISPB_DAT_10,
+       MX35_PAD_LD11__IPU_DISPB_DAT_11,
+       MX35_PAD_LD12__IPU_DISPB_DAT_12,
+       MX35_PAD_LD13__IPU_DISPB_DAT_13,
+       MX35_PAD_LD14__IPU_DISPB_DAT_14,
+       MX35_PAD_LD15__IPU_DISPB_DAT_15,
+       MX35_PAD_LD16__IPU_DISPB_DAT_16,
+       MX35_PAD_LD17__IPU_DISPB_DAT_17,
+       MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
+       MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
+       MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
+       MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
+       /* Backlight */
+       MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
+       /* LCD_PWR */
+       MX35_PAD_D3_CLS__GPIO1_4,
+       /* LED */
+       MX35_PAD_LD23__GPIO3_29,
+       /* SWITCH */
+       MX35_PAD_LD19__GPIO3_25,
+       /* UART2 */
+       MX35_PAD_CTS2__UART2_CTS,
+       MX35_PAD_RTS2__UART2_RTS,
+       MX35_PAD_TXD2__UART2_TXD_MUX,
+       MX35_PAD_RXD2__UART2_RXD_MUX,
+       /* I2S */
+       MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
+       MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
+       MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
+       MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
+};
+
+#define GPIO_LED1      (2 * 32 + 29)
+#define GPIO_SWITCH1   (2 * 32 + 25)
+#define GPIO_LCDPWR    (4)
+
+static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
+                                  unsigned int power)
+{
+       if (power)
+               gpio_direction_output(GPIO_LCDPWR, 1);
+       else
+               gpio_direction_output(GPIO_LCDPWR, 0);
+}
+
+static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = {
+       .set_power              = eukrea_mbimxsd_lcd_power_set,
+};
+
+static struct platform_device eukrea_mbimxsd_lcd_powerdev = {
+       .name                   = "platform-lcd",
+       .dev.platform_data      = &eukrea_mbimxsd_lcd_power_data,
+};
+
+static struct gpio_led eukrea_mbimxsd_leds[] = {
+       {
+               .name                   = "led1",
+               .default_trigger        = "heartbeat",
+               .active_low             = 1,
+               .gpio                   = GPIO_LED1,
+       },
+};
+
+static struct gpio_led_platform_data eukrea_mbimxsd_led_info = {
+       .leds           = eukrea_mbimxsd_leds,
+       .num_leds       = ARRAY_SIZE(eukrea_mbimxsd_leds),
+};
+
+static struct platform_device eukrea_mbimxsd_leds_gpio = {
+       .name   = "leds-gpio",
+       .id     = -1,
+       .dev    = {
+               .platform_data  = &eukrea_mbimxsd_led_info,
+       },
+};
+
+static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
+       {
+               .gpio           = GPIO_SWITCH1,
+               .code           = BTN_0,
+               .desc           = "BP1",
+               .active_low     = 1,
+               .wakeup         = 1,
+       },
+};
+
+static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
+       .buttons        = eukrea_mbimxsd_gpio_buttons,
+       .nbuttons       = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
+};
+
+static struct platform_device eukrea_mbimxsd_button_device = {
+       .name           = "gpio-keys",
+       .id             = -1,
+       .num_resources  = 0,
+       .dev            = {
+               .platform_data  = &eukrea_mbimxsd_button_data,
+       }
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+       &eukrea_mbimxsd_leds_gpio,
+       &eukrea_mbimxsd_button_device,
+       &eukrea_mbimxsd_lcd_powerdev,
+};
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+       .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
+       {
+               I2C_BOARD_INFO("tlv320aic23", 0x1a),
+       },
+};
+
+struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = {
+       .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
+};
+
+/*
+ * system init for baseboard usage. Will be called by cpuimx35 init.
+ *
+ * Add platform devices present on this baseboard and init
+ * them from CPU side as far as required to use them later on
+ */
+void __init eukrea_mbimxsd_baseboard_init(void)
+{
+       if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
+                       ARRAY_SIZE(eukrea_mbimxsd_pads)))
+               printk(KERN_ERR "error setting mbimxsd pads !\n");
+
+#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
+       /* SSI unit master I2S codec connected to SSI_AUD4 */
+       mxc_audmux_v2_configure_port(0,
+                       MXC_AUDMUX_V2_PTCR_SYN |
+                       MXC_AUDMUX_V2_PTCR_TFSDIR |
+                       MXC_AUDMUX_V2_PTCR_TFSEL(3) |
+                       MXC_AUDMUX_V2_PTCR_TCLKDIR |
+                       MXC_AUDMUX_V2_PTCR_TCSEL(3),
+                       MXC_AUDMUX_V2_PDCR_RXDSEL(3)
+       );
+       mxc_audmux_v2_configure_port(3,
+                       MXC_AUDMUX_V2_PTCR_SYN,
+                       MXC_AUDMUX_V2_PDCR_RXDSEL(0)
+       );
+#endif
+
+       imx35_add_imx_uart1(&uart_pdata);
+       mxc_register_device(&mx3_ipu, &mx3_ipu_data);
+       mxc_register_device(&mx3_fb, &mx3fb_pdata);
+
+       mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata);
+
+       gpio_request(GPIO_LED1, "LED1");
+       gpio_direction_output(GPIO_LED1, 1);
+       gpio_free(GPIO_LED1);
+
+       gpio_request(GPIO_SWITCH1, "SWITCH1");
+       gpio_direction_input(GPIO_SWITCH1);
+       gpio_free(GPIO_SWITCH1);
+
+       gpio_request(GPIO_LCDPWR, "LCDPWR");
+       gpio_direction_output(GPIO_LCDPWR, 1);
+       gpio_free(GPIO_SWITCH1);
+
+       i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
+                               ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
+
+       platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}

diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c
index 5f72ec91af2d62c97acbdff70fbccd4988c292b5..96aadcadb4ff094b1b5eeaaebc502b68cd87a370 100644 (file)
--- a/arch/arm/mach-mx3/mach-armadillo5x0.c
+++ b/arch/arm/mach-mx3/mach-armadillo5x0.c
@@ -48,16 +48,14 @@
 #include <asm/mach/map.h>
 
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
-#include <mach/board-armadillo5x0.h>
 #include <mach/mmc.h>
 #include <mach/ipu.h>
 #include <mach/mx3fb.h>
-#include <mach/mxc_nand.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 #include "crm_regs.h"
 
@@ -301,7 +299,8 @@ static struct platform_device armadillo5x0_button_device = {
 /*
  * NAND Flash
  */
-static struct mxc_nand_platform_data armadillo5x0_nand_flash_pdata = {
+static const struct mxc_nand_platform_data
+armadillo5x0_nand_board_info __initconst = {
        .width          = 1,
        .hw_ecc         = 1,
 };
@@ -493,13 +492,12 @@ static struct platform_device armadillo5x0_smc911x_device = {
 };
 
 /* UART device data */
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
 
 static struct platform_device *devices[] __initdata = {
        &armadillo5x0_smc911x_device,
-       &mxc_i2c_device1,
        &armadillo5x0_button_device,
 };
 
@@ -512,10 +510,11 @@ static void __init armadillo5x0_init(void)
                        ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0");
 
        platform_add_devices(devices, ARRAY_SIZE(devices));
+       imx31_add_imx_i2c1(NULL);
 
        /* Register UART */
-       mxc_register_device(&mxc_uart_device0, &uart_pdata);
-       mxc_register_device(&mxc_uart_device1, &uart_pdata);
+       imx31_add_imx_uart0(&uart_pdata);
+       imx31_add_imx_uart1(&uart_pdata);
 
        /* SMSC9118 IRQ pin */
        gpio_direction_input(MX31_PIN_GPIO1_0);
@@ -532,7 +531,7 @@ static void __init armadillo5x0_init(void)
                            &armadillo5x0_nor_flash_pdata);
 
        /* Register NAND Flash */
-       mxc_register_device(&mxc_nand_device, &armadillo5x0_nand_flash_pdata);
+       imx31_add_mxc_nand(&armadillo5x0_nand_board_info);
 
        /* set NAND page size to 2k if not configured via boot mode pins */
        __raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR);

diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c
new file mode 100644 (file)
index 0000000..63f970f
--- /dev/null
+++ b/arch/arm/mach-mx3/mach-cpuimx35.c
@@ -0,0 +1,227 @@
+/*
+ * Copyright (C) 2010 Eric Benard - eric@eukrea.com
+ * Copyright (C) 2009 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/memory.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/i2c/tsc2007.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <linux/fsl_devices.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+#include <mach/eukrea-baseboards.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx35.h>
+#include <mach/mxc_nand.h>
+#include <mach/mxc_ehci.h>
+#include <mach/ulpi.h>
+
+#include "devices-imx35.h"
+#include "devices.h"
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+       .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static const struct imxi2c_platform_data
+eukrea_cpuimx35_i2c0_data __initconst = {
+       .bitrate = 50000,
+};
+
+#define TSC2007_IRQGPIO                (2 * 32 + 2)
+static int ts_get_pendown_state(void)
+{
+       int val = 0;
+       gpio_free(TSC2007_IRQGPIO);
+       gpio_request(TSC2007_IRQGPIO, NULL);
+       gpio_direction_input(TSC2007_IRQGPIO);
+
+       val = gpio_get_value(TSC2007_IRQGPIO);
+
+       gpio_free(TSC2007_IRQGPIO);
+       gpio_request(TSC2007_IRQGPIO, NULL);
+
+       return val ? 0 : 1;
+}
+
+static int ts_init(void)
+{
+       gpio_request(TSC2007_IRQGPIO, NULL);
+       return 0;
+}
+
+static struct tsc2007_platform_data tsc2007_info = {
+       .model                  = 2007,
+       .x_plate_ohms           = 180,
+       .get_pendown_state      = ts_get_pendown_state,
+       .init_platform_hw       = ts_init,
+};
+
+static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
+       {
+               I2C_BOARD_INFO("pcf8563", 0x51),
+       }, {
+               I2C_BOARD_INFO("tsc2007", 0x48),
+               .type           = "tsc2007",
+               .platform_data  = &tsc2007_info,
+               .irq            = gpio_to_irq(TSC2007_IRQGPIO),
+       },
+};
+
+static struct platform_device *devices[] __initdata = {
+       &mxc_fec_device,
+       &imx_wdt_device0,
+};
+
+static struct pad_desc eukrea_cpuimx35_pads[] = {
+       /* UART1 */
+       MX35_PAD_CTS1__UART1_CTS,
+       MX35_PAD_RTS1__UART1_RTS,
+       MX35_PAD_TXD1__UART1_TXD_MUX,
+       MX35_PAD_RXD1__UART1_RXD_MUX,
+       /* FEC */
+       MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
+       MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
+       MX35_PAD_FEC_RX_DV__FEC_RX_DV,
+       MX35_PAD_FEC_COL__FEC_COL,
+       MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
+       MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
+       MX35_PAD_FEC_TX_EN__FEC_TX_EN,
+       MX35_PAD_FEC_MDC__FEC_MDC,
+       MX35_PAD_FEC_MDIO__FEC_MDIO,
+       MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
+       MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
+       MX35_PAD_FEC_CRS__FEC_CRS,
+       MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
+       MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
+       MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
+       MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
+       MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
+       MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+       /* I2C1 */
+       MX35_PAD_I2C1_CLK__I2C1_SCL,
+       MX35_PAD_I2C1_DAT__I2C1_SDA,
+       /* TSC2007 IRQ */
+       MX35_PAD_ATA_DA2__GPIO3_2,
+};
+
+static const struct mxc_nand_platform_data
+eukrea_cpuimx35_nand_board_info __initconst = {
+       .width          = 1,
+       .hw_ecc         = 1,
+       .flash_bbt      = 1,
+};
+
+static struct mxc_usbh_platform_data otg_pdata = {
+       .portsc = MXC_EHCI_MODE_UTMI,
+       .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
+};
+
+static struct mxc_usbh_platform_data usbh1_pdata = {
+       .portsc = MXC_EHCI_MODE_SERIAL,
+       .flags  = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
+                 MXC_EHCI_IPPUE_DOWN,
+};
+
+static struct fsl_usb2_platform_data otg_device_pdata = {
+       .operating_mode = FSL_USB2_DR_DEVICE,
+       .phy_mode       = FSL_USB2_PHY_UTMI,
+};
+
+static int otg_mode_host;
+
+static int __init eukrea_cpuimx35_otg_mode(char *options)
+{
+       if (!strcmp(options, "host"))
+               otg_mode_host = 1;
+       else if (!strcmp(options, "device"))
+               otg_mode_host = 0;
+       else
+               pr_info("otg_mode neither \"host\" nor \"device\". "
+                       "Defaulting to device\n");
+       return 0;
+}
+__setup("otg_mode=", eukrea_cpuimx35_otg_mode);
+
+/*
+ * Board specific initialization.
+ */
+static void __init mxc_board_init(void)
+{
+       mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
+                       ARRAY_SIZE(eukrea_cpuimx35_pads));
+
+       platform_add_devices(devices, ARRAY_SIZE(devices));
+
+       imx35_add_imx_uart0(&uart_pdata);
+       imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info);
+
+       i2c_register_board_info(0, eukrea_cpuimx35_i2c_devices,
+                       ARRAY_SIZE(eukrea_cpuimx35_i2c_devices));
+       imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data);
+
+#if defined(CONFIG_USB_ULPI)
+       if (otg_mode_host) {
+               otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                               USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+
+               mxc_register_device(&mxc_otg_host, &otg_pdata);
+       }
+       mxc_register_device(&mxc_usbh1, &usbh1_pdata);
+#endif
+       if (!otg_mode_host)
+               mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
+
+#ifdef CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD
+       eukrea_mbimxsd_baseboard_init();
+#endif
+}
+
+static void __init eukrea_cpuimx35_timer_init(void)
+{
+       mx35_clocks_init();
+}
+
+struct sys_timer eukrea_cpuimx35_timer = {
+       .init   = eukrea_cpuimx35_timer_init,
+};
+
+MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35")
+       /* Maintainer: Eukrea Electromatique */
+       .phys_io        = MX35_AIPS1_BASE_ADDR,
+       .io_pg_offst    = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+       .boot_params    = MX3x_PHYS_OFFSET + 0x100,
+       .map_io         = mx35_map_io,
+       .init_irq       = mx35_init_irq,
+       .init_machine   = mxc_board_init,
+       .timer          = &eukrea_cpuimx35_timer,
+MACHINE_END

diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
index f085d5d1a6de7c560d42fba0809b29d73a04a6e9..5b23e416d6c704c904385895f4bbf82dabfba56e 100644 (file)
--- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
@@ -16,10 +16,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/gpio.h>
@@ -37,13 +33,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 
-#include <mach/board-kzmarm11.h>
 #include <mach/clock.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/memory.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 #define KZM_ARM11_IO_ADDRESS(x) (                                      \
@@ -51,6 +46,23 @@
        IMX_IO_ADDRESS(x, MX31_CS5) ?:                                  \
        MX31_IO_ADDRESS(x))
 
+/*
+ *  KZM-ARM11-01 Board Control Registers on FPGA
+ */
+#define KZM_ARM11_CTL1         (MX31_CS4_BASE_ADDR + 0x1000)
+#define KZM_ARM11_CTL2         (MX31_CS4_BASE_ADDR + 0x1001)
+#define KZM_ARM11_RSW1         (MX31_CS4_BASE_ADDR + 0x1002)
+#define KZM_ARM11_BACK_LIGHT   (MX31_CS4_BASE_ADDR + 0x1004)
+#define KZM_ARM11_FPGA_REV     (MX31_CS4_BASE_ADDR + 0x1008)
+#define KZM_ARM11_7SEG_LED     (MX31_CS4_BASE_ADDR + 0x1010)
+#define KZM_ARM11_LEDS         (MX31_CS4_BASE_ADDR + 0x1020)
+#define KZM_ARM11_DIPSW2       (MX31_CS4_BASE_ADDR + 0x1003)
+
+/*
+ * External UART for touch panel on FPGA
+ */
+#define KZM_ARM11_16550                (MX31_CS4_BASE_ADDR + 0x1050)
+
 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
 /*
  * KZM-ARM11-01 has an external UART on FPGA
@@ -173,15 +185,14 @@ static inline int kzm_init_smsc9118(void)
 #endif
 
 #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
 
 static void __init kzm_init_imx_uart(void)
 {
-       mxc_register_device(&mxc_uart_device0, &uart_pdata);
-
-       mxc_register_device(&mxc_uart_device1, &uart_pdata);
+       imx31_add_imx_uart0(&uart_pdata);
+       imx31_add_imx_uart1(&uart_pdata);
 }
 #else
 static inline void kzm_init_imx_uart(void)

diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 58e57291b79d876fb6bdf04fe6da2020c36d9e1b..6fe69e124d30faa27d23a239ba903f0a76cb1c15 100644 (file)
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/delay.h>
@@ -22,7 +18,6 @@
 #include <linux/clk.h>
 #include <linux/irq.h>
 #include <linux/gpio.h>
-#include <linux/smsc911x.h>
 #include <linux/platform_device.h>
 #include <linux/mfd/mc13783.h>
 #include <linux/spi/spi.h>
@@ -37,19 +32,47 @@
 #include <asm/memory.h>
 #include <asm/mach/map.h>
 #include <mach/common.h>
-#include <mach/board-mx31_3ds.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
-#include <mach/mxc_nand.h>
-#include <mach/spi.h>
+#include <mach/3ds_debugboard.h>
+
+#include "devices-imx31.h"
 #include "devices.h"
 
-/*!
- * @file mx31_3ds.c
- *
- * @brief This file contains the board-specific initialization routines.
- *
- * @ingroup System
+/* Definitions for components on the Debug board */
+
+/* Base address of CPLD controller on the Debug board */
+#define DEBUG_BASE_ADDRESS             CS5_IO_ADDRESS(MX3x_CS5_BASE_ADDR)
+
+/* LAN9217 ethernet base address */
+#define LAN9217_BASE_ADDR              MX3x_CS5_BASE_ADDR
+
+/* CPLD config and interrupt base address */
+#define CPLD_ADDR                      (DEBUG_BASE_ADDRESS + 0x20000)
+
+/* status, interrupt */
+#define CPLD_INT_STATUS_REG            (CPLD_ADDR + 0x10)
+#define CPLD_INT_MASK_REG              (CPLD_ADDR + 0x38)
+#define CPLD_INT_RESET_REG             (CPLD_ADDR + 0x20)
+/* magic word for debug CPLD */
+#define CPLD_MAGIC_NUMBER1_REG         (CPLD_ADDR + 0x40)
+#define CPLD_MAGIC_NUMBER2_REG         (CPLD_ADDR + 0x48)
+/* CPLD code version */
+#define CPLD_CODE_VER_REG              (CPLD_ADDR + 0x50)
+/* magic word for debug CPLD */
+#define CPLD_MAGIC_NUMBER3_REG         (CPLD_ADDR + 0x58)
+
+/* CPLD IRQ line for external uart, external ethernet etc */
+#define EXPIO_PARENT_INT       IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
+
+#define MXC_EXP_IO_BASE                (MXC_BOARD_IRQ_START)
+#define MXC_IRQ_TO_EXPIO(irq)  ((irq) - MXC_EXP_IO_BASE)
+
+#define EXPIO_INT_ENET         (MXC_EXP_IO_BASE + 0)
+
+#define MXC_MAX_EXP_IO_LINES   16
+
+/*
+ * This file contains the board-specific initialization routines.
  */
 
 static int mx31_3ds_pins[] = {
@@ -145,7 +168,7 @@ static int spi1_internal_chipselect[] = {
        MXC_SPI_CS(2),
 };
 
-static struct spi_imx_master spi1_pdata = {
+static const struct spi_imx_master spi1_pdata __initconst = {
        .chipselect     = spi1_internal_chipselect,
        .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
 };
@@ -165,7 +188,8 @@ static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
 /*
  * NAND Flash
  */
-static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = {
+static const struct mxc_nand_platform_data
+mx31_3ds_nand_board_info __initconst = {
        .width          = 1,
        .hw_ecc         = 1,
 #ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
@@ -182,8 +206,10 @@ static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = {
 
 #define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
 
-static void mx31_3ds_usbotg_init(void)
+static int mx31_3ds_usbotg_init(void)
 {
+       int err;
+
        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
@@ -197,10 +223,25 @@ static void mx31_3ds_usbotg_init(void)
        mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
        mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
 
-       gpio_request(USBOTG_RST_B, "otgusb-reset");
-       gpio_direction_output(USBOTG_RST_B, 0);
+       err = gpio_request(USBOTG_RST_B, "otgusb-reset");
+       if (err) {
+               pr_err("Failed to request the USB OTG reset gpio\n");
+               return err;
+       }
+
+       err = gpio_direction_output(USBOTG_RST_B, 0);
+       if (err) {
+               pr_err("Failed to drive the USB OTG reset gpio\n");
+               goto usbotg_free_reset;
+       }
+
        mdelay(1);
        gpio_set_value(USBOTG_RST_B, 1);
+       return 0;
+
+usbotg_free_reset:
+       gpio_free(USBOTG_RST_B);
+       return err;
 }
 
 static struct fsl_usb2_platform_data usbotg_pdata = {
@@ -208,178 +249,16 @@ static struct fsl_usb2_platform_data usbotg_pdata = {
        .phy_mode       = FSL_USB2_PHY_ULPI,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
 
-/*
- * Support for the SMSC9217 on the Debug board.
- */
-
-static struct smsc911x_platform_config smsc911x_config = {
-       .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-       .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
-       .flags          = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
-       .phy_interface  = PHY_INTERFACE_MODE_MII,
-};
-
-static struct resource smsc911x_resources[] = {
-       {
-               .start          = LAN9217_BASE_ADDR,
-               .end            = LAN9217_BASE_ADDR + 0xff,
-               .flags          = IORESOURCE_MEM,
-       }, {
-               .start          = EXPIO_INT_ENET,
-               .end            = EXPIO_INT_ENET,
-               .flags          = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device smsc911x_device = {
-       .name           = "smsc911x",
-       .id             = -1,
-       .num_resources  = ARRAY_SIZE(smsc911x_resources),
-       .resource       = smsc911x_resources,
-       .dev            = {
-               .platform_data = &smsc911x_config,
-       },
-};
-
-/*
- * Routines for the CPLD on the debug board. It contains a CPLD handling
- * LEDs, switches, interrupts for Ethernet.
- */
-
-static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
-{
-       uint32_t imr_val;
-       uint32_t int_valid;
-       uint32_t expio_irq;
-
-       imr_val = __raw_readw(CPLD_INT_MASK_REG);
-       int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val;
-
-       expio_irq = MXC_EXP_IO_BASE;
-       for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
-               if ((int_valid & 1) == 0)
-                       continue;
-               generic_handle_irq(expio_irq);
-       }
-}
-
-/*
- * Disable an expio pin's interrupt by setting the bit in the imr.
- * @param irq           an expio virtual irq number
- */
-static void expio_mask_irq(uint32_t irq)
-{
-       uint16_t reg;
-       uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
-
-       /* mask the interrupt */
-       reg = __raw_readw(CPLD_INT_MASK_REG);
-       reg |= 1 << expio;
-       __raw_writew(reg, CPLD_INT_MASK_REG);
-}
-
-/*
- * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
- * @param irq           an expanded io virtual irq number
- */
-static void expio_ack_irq(uint32_t irq)
-{
-       uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
-
-       /* clear the interrupt status */
-       __raw_writew(1 << expio, CPLD_INT_RESET_REG);
-       __raw_writew(0, CPLD_INT_RESET_REG);
-       /* mask the interrupt */
-       expio_mask_irq(irq);
-}
-
-/*
- * Enable a expio pin's interrupt by clearing the bit in the imr.
- * @param irq           a expio virtual irq number
- */
-static void expio_unmask_irq(uint32_t irq)
-{
-       uint16_t reg;
-       uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
-
-       /* unmask the interrupt */
-       reg = __raw_readw(CPLD_INT_MASK_REG);
-       reg &= ~(1 << expio);
-       __raw_writew(reg, CPLD_INT_MASK_REG);
-}
-
-static struct irq_chip expio_irq_chip = {
-       .ack = expio_ack_irq,
-       .mask = expio_mask_irq,
-       .unmask = expio_unmask_irq,
-};
-
-static int __init mx31_3ds_init_expio(void)
-{
-       int i;
-       int ret;
-
-       /* Check if there's a debug board connected */
-       if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) ||
-           (__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) ||
-           (__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) {
-               /* No Debug board found */
-               return -ENODEV;
-       }
-
-       pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
-               __raw_readw(CPLD_CODE_VER_REG));
-
-       /*
-        * Configure INT line as GPIO input
-        */
-       ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq");
-       if (ret)
-               pr_warning("could not get LAN irq gpio\n");
-       else
-               gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
-
-       /* Disable the interrupts and clear the status */
-       __raw_writew(0, CPLD_INT_MASK_REG);
-       __raw_writew(0xFFFF, CPLD_INT_RESET_REG);
-       __raw_writew(0, CPLD_INT_RESET_REG);
-       __raw_writew(0x1F, CPLD_INT_MASK_REG);
-       for (i = MXC_EXP_IO_BASE;
-            i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
-            i++) {
-               set_irq_chip(i, &expio_irq_chip);
-               set_irq_handler(i, handle_level_irq);
-               set_irq_flags(i, IRQF_VALID);
-       }
-       set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
-       set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);
-
-       return 0;
-}
-
-/*
- * This structure defines the MX31 memory map.
- */
-static struct map_desc mx31_3ds_io_desc[] __initdata = {
-       {
-               .virtual = MX31_CS5_BASE_ADDR_VIRT,
-               .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
-               .length = MX31_CS5_SIZE,
-               .type = MT_DEVICE,
-       },
-};
-
 /*
  * Set up static virtual mappings.
  */
 static void __init mx31_3ds_map_io(void)
 {
        mx31_map_io();
-       iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
 }
 
 /*!
@@ -390,10 +269,10 @@ static void __init mxc_board_init(void)
        mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
                                      "mx31_3ds");
 
-       mxc_register_device(&mxc_uart_device0, &uart_pdata);
-       mxc_register_device(&mxc_nand_device, &imx31_3ds_nand_flash_pdata);
+       imx31_add_imx_uart0(&uart_pdata);
+       imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
 
-       mxc_register_device(&mxc_spi_device1, &spi1_pdata);
+       imx31_add_spi_imx0(&spi1_pdata);
        spi_register_board_info(mx31_3ds_spi_devs,
                                                ARRAY_SIZE(mx31_3ds_spi_devs));
 
@@ -402,8 +281,9 @@ static void __init mxc_board_init(void)
        mx31_3ds_usbotg_init();
        mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
 
-       if (!mx31_3ds_init_expio())
-               platform_device_register(&smsc911x_device);
+       if (!mxc_expio_init(CS5_BASE_ADDR, EXPIO_PARENT_INT))
+               printk(KERN_WARNING "Init of the debugboard failed, all "
+                                   "devices on the board are unusable.\n");
 }
 
 static void __init mx31_3ds_timer_init(void)

diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c
index b3d1a1895c20f4f2eab29d99e832c09fbc096373..94b3e7c4240408451aa08446c9b991ad179be699 100644 (file)
--- a/arch/arm/mach-mx3/mach-mx31ads.c
+++ b/arch/arm/mach-mx3/mach-mx31ads.c
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/types.h>
@@ -33,8 +29,6 @@
 #include <asm/memory.h>
 #include <asm/mach/map.h>
 #include <mach/common.h>
-#include <mach/board-mx31ads.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 
 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
@@ -43,14 +37,45 @@
 #include <linux/mfd/wm8350/pmic.h>
 #endif
 
+#include "devices-imx31.h"
 #include "devices.h"
 
-/*!
- * @file mx31ads.c
- *
- * @brief This file contains the board-specific initialization routines.
- *
- * @ingroup System
+/* Base address of PBC controller */
+#define PBC_BASE_ADDRESS        MX31_CS4_BASE_ADDR_VIRT
+/* Offsets for the PBC Controller register */
+
+/* PBC Board interrupt status register */
+#define PBC_INTSTATUS           0x000016
+
+/* PBC Board interrupt current status register */
+#define PBC_INTCURR_STATUS      0x000018
+
+/* PBC Interrupt mask register set address */
+#define PBC_INTMASK_SET         0x00001A
+
+/* PBC Interrupt mask register clear address */
+#define PBC_INTMASK_CLEAR       0x00001C
+
+/* External UART A */
+#define PBC_SC16C652_UARTA      0x010000
+
+/* External UART B */
+#define PBC_SC16C652_UARTB      0x010010
+
+#define PBC_INTSTATUS_REG      (PBC_INTSTATUS + PBC_BASE_ADDRESS)
+#define PBC_INTMASK_SET_REG    (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
+#define PBC_INTMASK_CLEAR_REG  (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
+#define EXPIO_PARENT_INT       IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
+
+#define MXC_EXP_IO_BASE                (MXC_BOARD_IRQ_START)
+#define MXC_IRQ_TO_EXPIO(irq)  ((irq) - MXC_EXP_IO_BASE)
+
+#define EXPIO_INT_XUART_INTA   (MXC_EXP_IO_BASE + 10)
+#define EXPIO_INT_XUART_INTB   (MXC_EXP_IO_BASE + 11)
+
+#define MXC_MAX_EXP_IO_LINES   16
+/*
+ * This file contains the board-specific initialization routines.
  */
 
 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
@@ -98,7 +123,7 @@ static inline int mxc_init_extuart(void)
 #endif
 
 #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -112,7 +137,7 @@ static unsigned int uart_pins[] = {
 static inline void mxc_init_imx_uart(void)
 {
        mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
-       mxc_register_device(&mxc_uart_device0, &uart_pdata);
+       imx31_add_imx_uart0(&uart_pdata);
 }
 #else /* !SERIAL_IMX */
 static inline void mxc_init_imx_uart(void)
@@ -475,7 +500,7 @@ static void mxc_init_i2c(void)
        mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
        mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
 
-       mxc_register_device(&mxc_i2c_device1, NULL);
+       imx31_add_imx_i2c1(NULL);
 }
 #else
 static void mxc_init_i2c(void)

diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
index b2c7f512070fe450b710db83da53ce439a2a2bd4..8f66f65e80e2079a3dae7e70ddb2a530960d8f98 100644 (file)
--- a/arch/arm/mach-mx3/mach-mx31lilly.c
+++ b/arch/arm/mach-mx3/mach-mx31lilly.c
@@ -18,10 +18,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/types.h>
@@ -46,10 +42,10 @@
 #include <mach/common.h>
 #include <mach/iomux-mx3.h>
 #include <mach/board-mx31lilly.h>
-#include <mach/spi.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 /*
@@ -269,12 +265,12 @@ static int spi_internal_chipselect[] = {
        MXC_SPI_CS(2),
 };
 
-static struct spi_imx_master spi0_pdata = {
+static const struct spi_imx_master spi0_pdata __initconst = {
        .chipselect = spi_internal_chipselect,
        .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
 };
 
-static struct spi_imx_master spi1_pdata = {
+static const struct spi_imx_master spi1_pdata __initconst = {
        .chipselect = spi_internal_chipselect,
        .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
 };
@@ -289,6 +285,7 @@ static struct spi_board_info mc13783_dev __initdata = {
        .bus_num        = 1,
        .chip_select    = 0,
        .platform_data  = &mc13783_pdata,
+       .irq            = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
 };
 
 static struct platform_device *devices[] __initdata = {
@@ -331,8 +328,8 @@ static void __init mx31lilly_board_init(void)
        mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS1__SS1, "SPI2_SS1");
        mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS2__SS2, "SPI2_SS2");
 
-       mxc_register_device(&mxc_spi_device0, &spi0_pdata);
-       mxc_register_device(&mxc_spi_device1, &spi1_pdata);
+       imx31_add_spi_imx0(&spi0_pdata);
+       imx31_add_spi_imx1(&spi1_pdata);
        spi_register_board_info(&mc13783_dev, 1);
 
        platform_add_devices(devices, ARRAY_SIZE(devices));

diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c
index 2b6d1140087740dbc72c157f47770620432a9575..da236c497d2ae38f2d6f01ca765df1957e1be8a1 100644 (file)
--- a/arch/arm/mach-mx3/mach-mx31lite.c
+++ b/arch/arm/mach-mx3/mach-mx31lite.c
@@ -13,10 +13,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/types.h>
@@ -42,14 +38,12 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/board-mx31lite.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/irqs.h>
-#include <mach/mxc_nand.h>
-#include <mach/spi.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 /*
@@ -69,7 +63,8 @@ static unsigned int mx31lite_pins[] = {
        MX31_PIN_CSPI2_SS2__SS2,
 };
 
-static struct mxc_nand_platform_data mx31lite_nand_board_info = {
+static const struct mxc_nand_platform_data
+mx31lite_nand_board_info __initconst  = {
        .width = 1,
        .hw_ecc = 1,
 };
@@ -112,7 +107,7 @@ static int spi_internal_chipselect[] = {
        MXC_SPI_CS(0),
 };
 
-static struct spi_imx_master spi1_pdata = {
+static const struct spi_imx_master spi1_pdata __initconst = {
        .chipselect     = spi_internal_chipselect,
        .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
 };
@@ -253,9 +248,9 @@ static void __init mxc_board_init(void)
 
        /* NOR and NAND flash */
        platform_device_register(&physmap_flash_device);
-       mxc_register_device(&mxc_nand_device, &mx31lite_nand_board_info);
+       imx31_add_mxc_nand(&mx31lite_nand_board_info);
 
-       mxc_register_device(&mxc_spi_device1, &spi1_pdata);
+       imx31_add_spi_imx1(&spi1_pdata);
        spi_register_board_info(&mc13783_spi_dev, 1);
 
 #if defined(CONFIG_USB_ULPI)

diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
index 62b5e40165dfea0692b06c97865f2094d053439d..67776bc61c336cc09dfd2c31f7408a20875e79e9 100644 (file)
--- a/arch/arm/mach-mx3/mach-mx31moboard.c
+++ b/arch/arm/mach-mx3/mach-mx31moboard.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/delay.h>
@@ -42,16 +38,15 @@
 #include <mach/board-mx31moboard.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/ipu.h>
-#include <mach/i2c.h>
 #include <mach/mmc.h>
 #include <mach/mxc_ehci.h>
 #include <mach/mx3_camera.h>
 #include <mach/spi.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 static unsigned int moboard_pins[] = {
@@ -130,24 +125,36 @@ static struct platform_device mx31moboard_flash = {
 
 static int moboard_uart0_init(struct platform_device *pdev)
 {
-       gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack");
-       gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0);
-       return 0;
+       int ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack");
+       if (ret)
+               return ret;
+
+       ret = gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0);
+       if (ret)
+               gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1));
+
+       return ret;
+}
+
+static void moboard_uart0_exit(struct platform_device *pdev)
+{
+       gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1));
 }
 
-static struct imxuart_platform_data uart0_pdata = {
+static const struct imxuart_platform_data uart0_pdata __initconst = {
        .init = moboard_uart0_init,
+       .exit = moboard_uart0_exit,
 };
 
-static struct imxuart_platform_data uart4_pdata = {
+static const struct imxuart_platform_data uart4_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static struct imxi2c_platform_data moboard_i2c0_pdata = {
+static const struct imxi2c_platform_data moboard_i2c0_data __initconst = {
        .bitrate = 400000,
 };
 
-static struct imxi2c_platform_data moboard_i2c1_pdata = {
+static const struct imxi2c_platform_data moboard_i2c1_data __initconst = {
        .bitrate = 100000,
 };
 
@@ -156,7 +163,7 @@ static int moboard_spi1_cs[] = {
        MXC_SPI_CS(2),
 };
 
-static struct spi_imx_master moboard_spi1_master = {
+static const struct spi_imx_master moboard_spi1_pdata __initconst = {
        .chipselect     = moboard_spi1_cs,
        .num_chipselect = ARRAY_SIZE(moboard_spi1_cs),
 };
@@ -286,7 +293,7 @@ static int moboard_spi2_cs[] = {
        MXC_SPI_CS(1),
 };
 
-static struct spi_imx_master moboard_spi2_master = {
+static const struct spi_imx_master moboard_spi2_pdata __initconst = {
        .chipselect     = moboard_spi2_cs,
        .num_chipselect = ARRAY_SIZE(moboard_spi2_cs),
 };
@@ -499,15 +506,14 @@ static void __init mxc_board_init(void)
 
        platform_add_devices(devices, ARRAY_SIZE(devices));
 
-       mxc_register_device(&mxc_uart_device0, &uart0_pdata);
-
-       mxc_register_device(&mxc_uart_device4, &uart4_pdata);
+       imx31_add_imx_uart0(&uart0_pdata);
+       imx31_add_imx_uart4(&uart4_pdata);
 
-       mxc_register_device(&mxc_i2c_device0, &moboard_i2c0_pdata);
-       mxc_register_device(&mxc_i2c_device1, &moboard_i2c1_pdata);
+       imx31_add_imx_i2c0(&moboard_i2c0_data);
+       imx31_add_imx_i2c1(&moboard_i2c1_data);
 
-       mxc_register_device(&mxc_spi_device1, &moboard_spi1_master);
-       mxc_register_device(&mxc_spi_device2, &moboard_spi2_master);
+       imx31_add_spi_imx1(&moboard_spi1_pdata);
+       imx31_add_spi_imx2(&moboard_spi2_pdata);
 
        gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3), "pmic-irq");
        gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));

diff --git a/arch/arm/mach-mx3/mach-mx35pdk.c b/arch/arm/mach-mx3/mach-mx35_3ds.c
similarity index 89%
rename from arch/arm/mach-mx3/mach-mx35pdk.c
rename to arch/arm/mach-mx3/mach-mx35_3ds.c
index bcac84d4dca4b71681626388cd2659edf0b10406..1c30d7212f17901a6703cb33d687ddab926ad3cd 100644 (file)
--- a/arch/arm/mach-mx3/mach-mx35pdk.c
+++ b/arch/arm/mach-mx3/mach-mx35_3ds.c
@@ -12,10 +12,12 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * This machine is known as:
+ *  - i.MX35 3-Stack Development System
+ *  - i.MX35 Platform Development Kit (i.MX35 PDK)
  */
 
 #include <linux/types.h>
@@ -32,12 +34,12 @@
 
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx35.h>
 
+#include "devices-imx35.h"
 #include "devices.h"
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -90,7 +92,7 @@ static void __init mxc_board_init(void)
 
        platform_add_devices(devices, ARRAY_SIZE(devices));
 
-       mxc_register_device(&mxc_uart_device0, &uart_pdata);
+       imx35_add_imx_uart0(&uart_pdata);
 
        mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
 }

diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index cce41066238338d4c09284835227b0dcd33deca4..8a292dd1a7146311394a90540af4811a60df804f 100644 (file)
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/types.h>
@@ -43,20 +39,17 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <mach/board-pcm037.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/i2c.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/ipu.h>
 #include <mach/mmc.h>
 #include <mach/mx3_camera.h>
 #include <mach/mx3fb.h>
-#include <mach/mxc_nand.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 #include "pcm037.h"
 
@@ -225,7 +218,7 @@ static struct platform_device pcm037_flash = {
        .num_resources = 1,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -279,16 +272,17 @@ static struct platform_device pcm037_sram_device = {
        .resource = &pcm038_sram_resource,
 };
 
-static struct mxc_nand_platform_data pcm037_nand_board_info = {
+static const struct mxc_nand_platform_data
+pcm037_nand_board_info __initconst = {
        .width = 1,
        .hw_ecc = 1,
 };
 
-static struct imxi2c_platform_data pcm037_i2c_1_data = {
+static const struct imxi2c_platform_data pcm037_i2c1_data __initconst = {
        .bitrate = 100000,
 };
 
-static struct imxi2c_platform_data pcm037_i2c_2_data = {
+static const struct imxi2c_platform_data pcm037_i2c2_data __initconst = {
        .bitrate = 20000,
 };
 
@@ -545,6 +539,7 @@ static struct platform_device pcm970_sja1000 = {
        .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
 };
 
+#if defined(CONFIG_USB_ULPI)
 static struct mxc_usbh_platform_data otg_pdata = {
        .portsc = MXC_EHCI_MODE_ULPI,
        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
@@ -554,6 +549,7 @@ static struct mxc_usbh_platform_data usbh2_pdata = {
        .portsc = MXC_EHCI_MODE_ULPI,
        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
+#endif
 
 static struct fsl_usb2_platform_data otg_device_pdata = {
        .operating_mode = FSL_USB2_DR_DEVICE,
@@ -581,7 +577,6 @@ __setup("otg_mode=", pcm037_otg_mode);
 static void __init mxc_board_init(void)
 {
        int ret;
-       u32 tmp;
 
        mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
 
@@ -614,9 +609,10 @@ static void __init mxc_board_init(void)
 
        platform_add_devices(devices, ARRAY_SIZE(devices));
 
-       mxc_register_device(&mxc_uart_device0, &uart_pdata);
-       mxc_register_device(&mxc_uart_device1, &uart_pdata);
-       mxc_register_device(&mxc_uart_device2, &uart_pdata);
+       imx31_add_imx_uart0(&uart_pdata);
+       /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */
+       imx31_add_imx_uart1(&uart_pdata);
+       imx31_add_imx_uart2(&uart_pdata);
 
        mxc_register_device(&mxc_w1_master_device, NULL);
 
@@ -634,10 +630,10 @@ static void __init mxc_board_init(void)
        i2c_register_board_info(1, pcm037_i2c_devices,
                        ARRAY_SIZE(pcm037_i2c_devices));
 
-       mxc_register_device(&mxc_i2c_device1, &pcm037_i2c_1_data);
-       mxc_register_device(&mxc_i2c_device2, &pcm037_i2c_2_data);
+       imx31_add_imx_i2c1(&pcm037_i2c1_data);
+       imx31_add_imx_i2c2(&pcm037_i2c2_data);
 
-       mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
+       imx31_add_mxc_nand(&pcm037_nand_board_info);
        mxc_register_device(&mxcsdhc_device0, &sdhc_pdata);
        mxc_register_device(&mx3_ipu, &mx3_ipu_data);
        mxc_register_device(&mx3_fb, &mx3fb_pdata);

diff --git a/arch/arm/mach-mx3/mach-pcm037_eet.c b/arch/arm/mach-mx3/mach-pcm037_eet.c
index 8d386000fc40d1f9c161ae1e121ec5a6466cba1e..c8b98218efeec9d32882333faa52c41458ce2f37 100644 (file)
--- a/arch/arm/mach-mx3/mach-pcm037_eet.c
+++ b/arch/arm/mach-mx3/mach-pcm037_eet.c
@@ -13,9 +13,6 @@
 #include <linux/spi/spi.h>
 
 #include <mach/common.h>
-#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
-#include <mach/spi.h>
-#endif
 #include <mach/iomux-mx3.h>
 
 #include <asm/mach-types.h>
@@ -64,7 +61,7 @@ static struct spi_board_info pcm037_spi_dev[] = {
 #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
 static int pcm037_spi1_cs[] = {MXC_SPI_CS(1), IOMUX_TO_GPIO(MX31_PIN_KEY_COL7)};
 
-struct spi_imx_master pcm037_spi1_master = {
+static const struct spi_imx_master pcm037_spi1_pdata __initconst = {
        .chipselect = pcm037_spi1_cs,
        .num_chipselect = ARRAY_SIZE(pcm037_spi1_cs),
 };
@@ -184,7 +181,7 @@ static int eet_init_devices(void)
        /* SPI */
        spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev));
 #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
-       mxc_register_device(&mxc_spi_device0, &pcm037_spi1_master);
+       imx35_add_spi_imx0(&pcm037_spi1_pdata);
 #endif
 
        platform_device_register(&pcm037_gpio_keys_device);

diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
index 78d9185a9d4ba7f46937f47ffe893935e897b4bb..47f5311b301a18170fa30c86de22cd0d2b64495b 100644 (file)
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/types.h>
@@ -40,19 +36,15 @@
 
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
-#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
-#include <mach/i2c.h>
-#endif
 #include <mach/iomux-mx35.h>
 #include <mach/ipu.h>
 #include <mach/mx3fb.h>
-#include <mach/mxc_nand.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 #include <mach/audmux.h>
 #include <mach/ssi.h>
 
+#include "devices-imx35.h"
 #include "devices.h"
 
 static const struct fb_videomode fb_modedb[] = {
@@ -122,12 +114,12 @@ static struct platform_device pcm043_flash = {
        .num_resources = 1,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
 
 #if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
-static struct imxi2c_platform_data pcm043_i2c_1_data = {
+static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = {
        .bitrate = 50000,
 };
 
@@ -222,6 +214,9 @@ static struct pad_desc pcm043_pads[] = {
        MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
        MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
        MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
+       /* CAN2 */
+       MX35_PAD_TX5_RX0__CAN2_TXCAN,
+       MX35_PAD_TX4_RX1__CAN2_RXCAN,
 };
 
 #define AC97_GPIO_TXFS (1 * 32 + 31)
@@ -304,11 +299,13 @@ static struct imx_ssi_platform_data pcm043_ssi_pdata = {
        .flags = IMX_SSI_USE_AC97,
 };
 
-static struct mxc_nand_platform_data pcm037_nand_board_info = {
+static const struct mxc_nand_platform_data
+pcm037_nand_board_info __initconst = {
        .width = 1,
        .hw_ecc = 1,
 };
 
+#if defined(CONFIG_USB_ULPI)
 static struct mxc_usbh_platform_data otg_pdata = {
        .portsc = MXC_EHCI_MODE_UTMI,
        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
@@ -319,6 +316,7 @@ static struct mxc_usbh_platform_data usbh1_pdata = {
        .flags  = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
                  MXC_EHCI_IPPUE_DOWN,
 };
+#endif
 
 static struct fsl_usb2_platform_data otg_device_pdata = {
        .operating_mode = FSL_USB2_DR_DEVICE,
@@ -361,17 +359,17 @@ static void __init mxc_board_init(void)
 
        platform_add_devices(devices, ARRAY_SIZE(devices));
 
-       mxc_register_device(&mxc_uart_device0, &uart_pdata);
-       mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
+       imx35_add_imx_uart0(&uart_pdata);
+       imx35_add_mxc_nand(&pcm037_nand_board_info);
        mxc_register_device(&imx_ssi_device0, &pcm043_ssi_pdata);
 
-       mxc_register_device(&mxc_uart_device1, &uart_pdata);
+       imx35_add_imx_uart1(&uart_pdata);
 
 #if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
        i2c_register_board_info(0, pcm043_i2c_devices,
                        ARRAY_SIZE(pcm043_i2c_devices));
 
-       mxc_register_device(&mxc_i2c_device0, &pcm043_i2c_1_data);
+       imx35_add_imx_i2c0(&pcm043_i2c0_data);
 #endif
 
        mxc_register_device(&mx3_ipu, &mx3_ipu_data);
@@ -390,6 +388,7 @@ static void __init mxc_board_init(void)
        if (!otg_mode_host)
                mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
 
+       imx35_add_flexcan1(NULL);
 }
 
 static void __init pcm043_timer_init(void)

diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-mx3/mach-qong.c
index e5b5b8323a1793aad3115e4694a8e9bd149155f5..d44ac70222a592246e643b31f8572fcdaf846544 100644 (file)
--- a/arch/arm/mach-mx3/mach-qong.c
+++ b/arch/arm/mach-mx3/mach-qong.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/types.h>
@@ -34,9 +30,9 @@
 #include <mach/common.h>
 #include <asm/page.h>
 #include <asm/setup.h>
-#include <mach/board-qong.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
+
+#include "devices-imx31.h"
 #include "devices.h"
 
 /* FPGA defines */
@@ -62,7 +58,7 @@
  * This file contains the board-specific initialization routines.
  */
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -73,11 +69,11 @@ static int uart_pins[] = {
        MX31_PIN_RXD1__RXD1
 };
 
-static inline void mxc_init_imx_uart(void)
+static inline void __init mxc_init_imx_uart(void)
 {
        mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins),
                        "uart-0");
-       mxc_register_device(&mxc_uart_device0, &uart_pdata);
+       imx31_add_imx_uart0(&uart_pdata);
 }
 
 static struct resource dnet_resources[] = {
@@ -116,7 +112,7 @@ static struct physmap_flash_data qong_flash_data = {
 
 static struct resource qong_flash_resource = {
        .start = MX31_CS0_BASE_ADDR,
-       .end = MX31_CS0_BASE_ADDR + QONG_NOR_SIZE - 1,
+       .end = MX31_CS0_BASE_ADDR + SZ_128M - 1,
        .flags = IORESOURCE_MEM,
 };
 

diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index 6858a4f9806cd69f3f0ffe95641d87d342cdd899..20e48c0195c4f8533c7d43113f0ce3965c0ef143 100644 (file)
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -14,10 +14,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/mm.h>
@@ -97,9 +93,12 @@ void __init mx35_map_io(void)
 }
 #endif
 
+int imx3x_register_gpios(void);
+
 void __init mx31_init_irq(void)
 {
        mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
+       imx3x_register_gpios();
 }
 
 void __init mx35_init_irq(void)

diff --git a/arch/arm/mach-mx3/mx31lilly-db.c b/arch/arm/mach-mx3/mx31lilly-db.c
index 7aebd74a12e8c075b3d5dadde345e9c4fea91752..827fd3c802012d7135fbca269456dbf12968d5d1 100644 (file)
--- a/arch/arm/mach-mx3/mx31lilly-db.c
+++ b/arch/arm/mach-mx3/mx31lilly-db.c
@@ -18,10 +18,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/kernel.h>
@@ -36,13 +32,13 @@
 
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/board-mx31lilly.h>
 #include <mach/mmc.h>
 #include <mach/mx3fb.h>
 #include <mach/ipu.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 /*
@@ -96,7 +92,7 @@ static unsigned int lilly_db_board_pins[] __initdata = {
 };
 
 /* UART */
-static struct imxuart_platform_data uart_pdata __initdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -217,9 +213,9 @@ void __init mx31lilly_db_init(void)
        mxc_iomux_setup_multiple_pins(lilly_db_board_pins,
                                        ARRAY_SIZE(lilly_db_board_pins),
                                        "development board pins");
-       mxc_register_device(&mxc_uart_device0, &uart_pdata);
-       mxc_register_device(&mxc_uart_device1, &uart_pdata);
-       mxc_register_device(&mxc_uart_device2, &uart_pdata);
+       imx31_add_imx_uart0(&uart_pdata);
+       imx31_add_imx_uart1(&uart_pdata);
+       imx31_add_imx_uart2(&uart_pdata);
        mxc_register_device(&mxcsdhc_device0, &mmc_pdata);
        mx31lilly_init_fb();
 }

diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c
index 5f05bfbec38054187324565e3d421a3da01110c9..7b0e74e275ba77110cf73e3173b20ec438796fdc 100644 (file)
--- a/arch/arm/mach-mx3/mx31lite-db.c
+++ b/arch/arm/mach-mx3/mx31lite-db.c
@@ -18,10 +18,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/kernel.h>
@@ -37,12 +33,11 @@
 
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/board-mx31lite.h>
 #include <mach/mmc.h>
-#include <mach/spi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 /*
@@ -76,7 +71,7 @@ static unsigned int litekit_db_board_pins[] __initdata = {
 };
 
 /* UART */
-static struct imxuart_platform_data uart_pdata __initdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -161,7 +156,7 @@ static int spi_internal_chipselect[] = {
        MXC_SPI_CS(2),
 };
 
-static struct spi_imx_master spi0_pdata = {
+static const struct spi_imx_master spi0_pdata __initconst = {
        .chipselect     = spi_internal_chipselect,
        .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
 };
@@ -201,9 +196,9 @@ void __init mx31lite_db_init(void)
        mxc_iomux_setup_multiple_pins(litekit_db_board_pins,
                                        ARRAY_SIZE(litekit_db_board_pins),
                                        "development board pins");
-       mxc_register_device(&mxc_uart_device0, &uart_pdata);
+       imx31_add_imx_uart0(&uart_pdata);
        mxc_register_device(&mxcsdhc_device0, &mmc_pdata);
-       mxc_register_device(&mxc_spi_device0, &spi0_pdata);
+       imx31_add_spi_imx0(&spi0_pdata);
        platform_device_register(&litekit_led_device);
        mxc_register_device(&imx_wdt_device0, NULL);
        mxc_register_device(&imx_rtc_device0, NULL);

diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
index 582299cb2c08be52c6d0cbd9f8c010d123fca33e..fc395a7a8599e78bf2c2096c523e50a0d0fb28aa 100644 (file)
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/gpio.h>
@@ -27,13 +23,13 @@
 #include <linux/usb/otg.h>
 
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/hardware.h>
 #include <mach/mmc.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 static unsigned int devboard_pins[] = {
@@ -56,7 +52,7 @@ static unsigned int devboard_pins[] = {
        MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -230,7 +226,7 @@ void __init mx31moboard_devboard_init(void)
        mxc_iomux_setup_multiple_pins(devboard_pins, ARRAY_SIZE(devboard_pins),
                "devboard");
 
-       mxc_register_device(&mxc_uart_device1, &uart_pdata);
+       imx31_add_imx_uart1(&uart_pdata);
 
        mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
 

diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
index 4930f8c27e661fd5c8612c0369d7e79779f1cf7d..0551eb39d97eec32f7694538838eae418940da80 100644 (file)
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/delay.h>

diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c
index 293eea6d9d97cbd9ffb5cdcbed1409ab685e6a31..40c3e7564cb61c43d77cbd1b01793262e6552eca 100644 (file)
--- a/arch/arm/mach-mx3/mx31moboard-smartbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/delay.h>
@@ -30,7 +26,6 @@
 
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/board-mx31moboard.h>
 #include <mach/mxc_ehci.h>
@@ -38,6 +33,7 @@
 
 #include <media/soc_camera.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 static unsigned int smartbot_pins[] = {
@@ -59,7 +55,7 @@ static unsigned int smartbot_pins[] = {
        MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -183,8 +179,7 @@ void __init mx31moboard_smartbot_init(int board)
        mxc_iomux_setup_multiple_pins(smartbot_pins, ARRAY_SIZE(smartbot_pins),
                "smartbot");
 
-       mxc_register_device(&mxc_uart_device1, &uart_pdata);
-
+       imx31_add_imx_uart1(&uart_pdata);
 
        switch (board) {
        case MX31SMARTBOT:

diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 1576d51e676c913cad7c5e4c6f5cfc379d7d336f..0848db5dd364dd5bb5b90ae03f3accf6eeb711aa 100644 (file)
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -15,4 +15,31 @@ config MACH_MX51_BABBAGE
          u-boot. This includes specific configurations for the board and its
          peripherals.
 
+config MACH_MX51_3DS
+       bool "Support MX51PDK (3DS)"
+       select MXC_DEBUG_BOARD
+       help
+         Include support for MX51PDK (3DS) platform. This includes specific
+         configurations for the board and its peripherals.
+
+config MACH_EUKREA_CPUIMX51
+       bool "Support Eukrea CPUIMX51 module"
+       help
+         Include support for Eukrea CPUIMX51 platform. This includes
+         specific configurations for the module and its peripherals.
+
+choice
+       prompt "Baseboard"
+       depends on MACH_EUKREA_CPUIMX51
+       default MACH_EUKREA_MBIMX51_BASEBOARD
+
+config MACH_EUKREA_MBIMX51_BASEBOARD
+       prompt "Eukrea MBIMX51 development board"
+       bool
+       help
+         This adds board specific devices that can be found on Eukrea's
+         MBIMX51 evaluation board.
+
+endchoice
+
 endif

diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index bf23f869ef511817f38be14ec7dcf48b3f82263c..86c66e7f52f3dc0855509587703e6972de2c483e 100644 (file)
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -6,4 +6,6 @@
 obj-y   := cpu.o mm.o clock-mx51.o devices.o
 
 obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
-
+obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
+obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o

diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
new file mode 100644 (file)
index 0000000..623607a
--- /dev/null
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -0,0 +1,293 @@
+/*
+ *
+ * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
+ *
+ * based on board-mx51_babbage.c which is
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/fsl_devices.h>
+
+#include <mach/eukrea-baseboards.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx51.h>
+#include <mach/i2c.h>
+#include <mach/mxc_ehci.h>
+
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "devices.h"
+
+#define CPUIMX51_USBH1_STP     (0*32 + 27)
+#define CPUIMX51_QUARTA_GPIO   (2*32 + 28)
+#define CPUIMX51_QUARTB_GPIO   (2*32 + 25)
+#define CPUIMX51_QUARTC_GPIO   (2*32 + 26)
+#define CPUIMX51_QUARTD_GPIO   (2*32 + 27)
+#define CPUIMX51_QUARTA_IRQ    (MXC_INTERNAL_IRQS + CPUIMX51_QUARTA_GPIO)
+#define CPUIMX51_QUARTB_IRQ    (MXC_INTERNAL_IRQS + CPUIMX51_QUARTB_GPIO)
+#define CPUIMX51_QUARTC_IRQ    (MXC_INTERNAL_IRQS + CPUIMX51_QUARTC_GPIO)
+#define CPUIMX51_QUARTD_IRQ    (MXC_INTERNAL_IRQS + CPUIMX51_QUARTD_GPIO)
+#define CPUIMX51_QUART_XTAL    14745600
+#define CPUIMX51_QUART_REGSHIFT        17
+
+/* USB_CTRL_1 */
+#define MX51_USB_CTRL_1_OFFSET         0x10
+#define MX51_USB_CTRL_UH1_EXT_CLK_EN   (1 << 25)
+
+#define        MX51_USB_PLLDIV_12_MHZ          0x00
+#define        MX51_USB_PLL_DIV_19_2_MHZ       0x01
+#define        MX51_USB_PLL_DIV_24_MHZ         0x02
+
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+static struct plat_serial8250_port serial_platform_data[] = {
+       {
+               .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
+               .irq = CPUIMX51_QUARTA_IRQ,
+               .irqflags = IRQF_TRIGGER_HIGH,
+               .uartclk = CPUIMX51_QUART_XTAL,
+               .regshift = CPUIMX51_QUART_REGSHIFT,
+               .iotype = UPIO_MEM,
+               .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+       }, {
+               .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000),
+               .irq = CPUIMX51_QUARTB_IRQ,
+               .irqflags = IRQF_TRIGGER_HIGH,
+               .uartclk = CPUIMX51_QUART_XTAL,
+               .regshift = CPUIMX51_QUART_REGSHIFT,
+               .iotype = UPIO_MEM,
+               .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+       }, {
+               .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000),
+               .irq = CPUIMX51_QUARTC_IRQ,
+               .irqflags = IRQF_TRIGGER_HIGH,
+               .uartclk = CPUIMX51_QUART_XTAL,
+               .regshift = CPUIMX51_QUART_REGSHIFT,
+               .iotype = UPIO_MEM,
+               .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+       }, {
+               .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000),
+               .irq = CPUIMX51_QUARTD_IRQ,
+               .irqflags = IRQF_TRIGGER_HIGH,
+               .uartclk = CPUIMX51_QUART_XTAL,
+               .regshift = CPUIMX51_QUART_REGSHIFT,
+               .iotype = UPIO_MEM,
+               .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+       }, {
+       }
+};
+
+static struct platform_device serial_device = {
+       .name = "serial8250",
+       .id = 0,
+       .dev = {
+               .platform_data = serial_platform_data,
+       },
+};
+#endif
+
+static struct platform_device *devices[] __initdata = {
+       &mxc_fec_device,
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+       &serial_device,
+#endif
+};
+
+static struct pad_desc eukrea_cpuimx51_pads[] = {
+       /* UART1 */
+       MX51_PAD_UART1_RXD__UART1_RXD,
+       MX51_PAD_UART1_TXD__UART1_TXD,
+       MX51_PAD_UART1_RTS__UART1_RTS,
+       MX51_PAD_UART1_CTS__UART1_CTS,
+
+       /* I2C2 */
+       MX51_PAD_GPIO_1_2__I2C2_SCL,
+       MX51_PAD_GPIO_1_3__I2C2_SDA,
+       MX51_PAD_NANDF_D10__GPIO_3_30,
+
+       /* QUART IRQ */
+       MX51_PAD_NANDF_D15__GPIO_3_25,
+       MX51_PAD_NANDF_D14__GPIO_3_26,
+       MX51_PAD_NANDF_D13__GPIO_3_27,
+       MX51_PAD_NANDF_D12__GPIO_3_28,
+
+       /* USB HOST1 */
+       MX51_PAD_USBH1_CLK__USBH1_CLK,
+       MX51_PAD_USBH1_DIR__USBH1_DIR,
+       MX51_PAD_USBH1_NXT__USBH1_NXT,
+       MX51_PAD_USBH1_DATA0__USBH1_DATA0,
+       MX51_PAD_USBH1_DATA1__USBH1_DATA1,
+       MX51_PAD_USBH1_DATA2__USBH1_DATA2,
+       MX51_PAD_USBH1_DATA3__USBH1_DATA3,
+       MX51_PAD_USBH1_DATA4__USBH1_DATA4,
+       MX51_PAD_USBH1_DATA5__USBH1_DATA5,
+       MX51_PAD_USBH1_DATA6__USBH1_DATA6,
+       MX51_PAD_USBH1_DATA7__USBH1_DATA7,
+       MX51_PAD_USBH1_STP__USBH1_STP,
+};
+
+static struct imxuart_platform_data uart_pdata = {
+       .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct imxi2c_platform_data eukrea_cpuimx51_i2c_data = {
+       .bitrate = 100000,
+};
+
+static struct i2c_board_info eukrea_cpuimx51_i2c_devices[] = {
+       {
+               I2C_BOARD_INFO("pcf8563", 0x51),
+       },
+};
+
+/* This function is board specific as the bit mask for the plldiv will also
+be different for other Freescale SoCs, thus a common bitmask is not
+possible and cannot get place in /plat-mxc/ehci.c.*/
+static int initialize_otg_port(struct platform_device *pdev)
+{
+       u32 v;
+       void __iomem *usb_base;
+       void __iomem *usbother_base;
+
+       usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+       usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
+
+       /* Set the PHY clock to 19.2MHz */
+       v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+       v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
+       v |= MX51_USB_PLL_DIV_19_2_MHZ;
+       __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+       iounmap(usb_base);
+       return 0;
+}
+
+static int initialize_usbh1_port(struct platform_device *pdev)
+{
+       u32 v;
+       void __iomem *usb_base;
+       void __iomem *usbother_base;
+
+       usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+       usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
+
+       /* The clock for the USBH1 ULPI port will come externally from the PHY. */
+       v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
+       __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
+       iounmap(usb_base);
+       return 0;
+}
+
+static struct mxc_usbh_platform_data dr_utmi_config = {
+       .init           = initialize_otg_port,
+       .portsc = MXC_EHCI_UTMI_16BIT,
+       .flags  = MXC_EHCI_INTERNAL_PHY,
+};
+
+static struct fsl_usb2_platform_data usb_pdata = {
+       .operating_mode = FSL_USB2_DR_DEVICE,
+       .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
+};
+
+static struct mxc_usbh_platform_data usbh1_config = {
+       .init           = initialize_usbh1_port,
+       .portsc = MXC_EHCI_MODE_ULPI,
+       .flags  = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
+};
+
+static int otg_mode_host;
+
+static int __init eukrea_cpuimx51_otg_mode(char *options)
+{
+       if (!strcmp(options, "host"))
+               otg_mode_host = 1;
+       else if (!strcmp(options, "device"))
+               otg_mode_host = 0;
+       else
+               pr_info("otg_mode neither \"host\" nor \"device\". "
+                       "Defaulting to device\n");
+       return 0;
+}
+__setup("otg_mode=", eukrea_cpuimx51_otg_mode);
+
+/*
+ * Board specific initialization.
+ */
+static void __init eukrea_cpuimx51_init(void)
+{
+       mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads,
+                                       ARRAY_SIZE(eukrea_cpuimx51_pads));
+
+       mxc_register_device(&mxc_uart_device0, &uart_pdata);
+       gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq");
+       gpio_direction_input(CPUIMX51_QUARTA_GPIO);
+       gpio_free(CPUIMX51_QUARTA_GPIO);
+       gpio_request(CPUIMX51_QUARTB_GPIO, "quartb_irq");
+       gpio_direction_input(CPUIMX51_QUARTB_GPIO);
+       gpio_free(CPUIMX51_QUARTB_GPIO);
+       gpio_request(CPUIMX51_QUARTC_GPIO, "quartc_irq");
+       gpio_direction_input(CPUIMX51_QUARTC_GPIO);
+       gpio_free(CPUIMX51_QUARTC_GPIO);
+       gpio_request(CPUIMX51_QUARTD_GPIO, "quartd_irq");
+       gpio_direction_input(CPUIMX51_QUARTD_GPIO);
+       gpio_free(CPUIMX51_QUARTD_GPIO);
+
+       platform_add_devices(devices, ARRAY_SIZE(devices));
+
+       mxc_register_device(&mxc_i2c_device1, &eukrea_cpuimx51_i2c_data);
+       i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices,
+                               ARRAY_SIZE(eukrea_cpuimx51_i2c_devices));
+
+       if (otg_mode_host)
+               mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
+       else {
+               initialize_otg_port(NULL);
+               mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
+       }
+       mxc_register_device(&mxc_usbh1_device, &usbh1_config);
+
+#ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD
+       eukrea_mbimx51_baseboard_init();
+#endif
+}
+
+static void __init eukrea_cpuimx51_timer_init(void)
+{
+       mx51_clocks_init(32768, 24000000, 22579200, 0);
+}
+
+static struct sys_timer mxc_timer = {
+       .init   = eukrea_cpuimx51_timer_init,
+};
+
+MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
+       /* Maintainer: Eric Bénard <eric@eukrea.com> */
+       .phys_io = MX51_AIPS1_BASE_ADDR,
+       .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+       .boot_params = PHYS_OFFSET + 0x100,
+       .map_io = mx51_map_io,
+       .init_irq = mx51_init_irq,
+       .init_machine = eukrea_cpuimx51_init,
+       .timer = &mxc_timer,
+MACHINE_END

diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
new file mode 100644 (file)
index 0000000..f95c2fd
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -0,0 +1,164 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/input/matrix_keypad.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx51.h>
+#include <mach/imx-uart.h>
+#include <mach/3ds_debugboard.h>
+
+#include "devices.h"
+
+#define EXPIO_PARENT_INT       (MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
+
+static struct pad_desc mx51_3ds_pads[] = {
+       /* UART1 */
+       MX51_PAD_UART1_RXD__UART1_RXD,
+       MX51_PAD_UART1_TXD__UART1_TXD,
+       MX51_PAD_UART1_RTS__UART1_RTS,
+       MX51_PAD_UART1_CTS__UART1_CTS,
+
+       /* UART2 */
+       MX51_PAD_UART2_RXD__UART2_RXD,
+       MX51_PAD_UART2_TXD__UART2_TXD,
+       MX51_PAD_EIM_D25__UART2_CTS,
+       MX51_PAD_EIM_D26__UART2_RTS,
+
+       /* UART3 */
+       MX51_PAD_UART3_RXD__UART3_RXD,
+       MX51_PAD_UART3_TXD__UART3_TXD,
+       MX51_PAD_EIM_D24__UART3_CTS,
+       MX51_PAD_EIM_D27__UART3_RTS,
+
+       /* CPLD PARENT IRQ PIN */
+       MX51_PAD_GPIO_1_6__GPIO_1_6,
+
+       /* KPP */
+       MX51_PAD_KEY_ROW0__KEY_ROW0,
+       MX51_PAD_KEY_ROW1__KEY_ROW1,
+       MX51_PAD_KEY_ROW2__KEY_ROW2,
+       MX51_PAD_KEY_ROW3__KEY_ROW3,
+       MX51_PAD_KEY_COL0__KEY_COL0,
+       MX51_PAD_KEY_COL1__KEY_COL1,
+       MX51_PAD_KEY_COL2__KEY_COL2,
+       MX51_PAD_KEY_COL3__KEY_COL3,
+       MX51_PAD_KEY_COL4__KEY_COL4,
+       MX51_PAD_KEY_COL5__KEY_COL5,
+};
+
+/* Serial ports */
+#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
+static struct imxuart_platform_data uart_pdata = {
+       .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static inline void mxc_init_imx_uart(void)
+{
+       mxc_register_device(&mxc_uart_device0, &uart_pdata);
+       mxc_register_device(&mxc_uart_device1, &uart_pdata);
+       mxc_register_device(&mxc_uart_device2, &uart_pdata);
+}
+#else /* !SERIAL_IMX */
+static inline void mxc_init_imx_uart(void)
+{
+}
+#endif /* SERIAL_IMX */
+
+#if defined(CONFIG_KEYBOARD_IMX) || defined(CONFIG_KEYBOARD_IMX_MODULE)
+static int mx51_3ds_board_keymap[] = {
+       KEY(0, 0, KEY_1),
+       KEY(0, 1, KEY_2),
+       KEY(0, 2, KEY_3),
+       KEY(0, 3, KEY_F1),
+       KEY(0, 4, KEY_UP),
+       KEY(0, 5, KEY_F2),
+
+       KEY(1, 0, KEY_4),
+       KEY(1, 1, KEY_5),
+       KEY(1, 2, KEY_6),
+       KEY(1, 3, KEY_LEFT),
+       KEY(1, 4, KEY_SELECT),
+       KEY(1, 5, KEY_RIGHT),
+
+       KEY(2, 0, KEY_7),
+       KEY(2, 1, KEY_8),
+       KEY(2, 2, KEY_9),
+       KEY(2, 3, KEY_F3),
+       KEY(2, 4, KEY_DOWN),
+       KEY(2, 5, KEY_F4),
+
+       KEY(3, 0, KEY_0),
+       KEY(3, 1, KEY_OK),
+       KEY(3, 2, KEY_ESC),
+       KEY(3, 3, KEY_ENTER),
+       KEY(3, 4, KEY_MENU),
+       KEY(3, 5, KEY_BACK)
+};
+
+static struct matrix_keymap_data mx51_3ds_map_data = {
+       .keymap         = mx51_3ds_board_keymap,
+       .keymap_size    = ARRAY_SIZE(mx51_3ds_board_keymap),
+};
+
+static void mxc_init_keypad(void)
+{
+       mxc_register_device(&mxc_keypad_device, &mx51_3ds_map_data);
+}
+#else
+static inline void mxc_init_keypad(void)
+{
+}
+#endif
+
+/*
+ * Board specific initialization.
+ */
+static void __init mxc_board_init(void)
+{
+       mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
+                                       ARRAY_SIZE(mx51_3ds_pads));
+       mxc_init_imx_uart();
+
+       if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT))
+               printk(KERN_WARNING "Init of the debugboard failed, all "
+                                   "devices on the board are unusable.\n");
+
+       mxc_init_keypad();
+}
+
+static void __init mx51_3ds_timer_init(void)
+{
+       mx51_clocks_init(32768, 24000000, 22579200, 0);
+}
+
+static struct sys_timer mxc_timer = {
+       .init   = mx51_3ds_timer_init,
+};
+
+MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
+       /* Maintainer: Freescale Semiconductor, Inc. */
+       .phys_io = MX51_AIPS1_BASE_ADDR,
+       .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+       .boot_params = PHYS_OFFSET + 0x100,
+       .map_io = mx51_map_io,
+       .init_irq = mx51_init_irq,
+       .init_machine = mxc_board_init,
+       .timer = &mxc_timer,
+MACHINE_END

diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index ed885f9d7b73d51e0c19e4ba1c227e95f6dbb09e..6e384d92e625d107279c14228964553525aa6c53 100644 (file)
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -12,6 +12,7 @@
 
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/i2c.h>
 #include <linux/gpio.h>
 #include <linux/delay.h>
 #include <linux/io.h>
@@ -21,6 +22,7 @@
 #include <mach/hardware.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx51.h>
+#include <mach/i2c.h>
 #include <mach/mxc_ehci.h>
 
 #include <asm/irq.h>
@@ -64,6 +66,18 @@ static struct pad_desc mx51babbage_pads[] = {
        MX51_PAD_EIM_D27__UART3_RTS,
        MX51_PAD_EIM_D24__UART3_CTS,
 
+       /* I2C1 */
+       MX51_PAD_EIM_D16__I2C1_SDA,
+       MX51_PAD_EIM_D19__I2C1_SCL,
+
+       /* I2C2 */
+       MX51_PAD_KEY_COL4__I2C2_SCL,
+       MX51_PAD_KEY_COL5__I2C2_SDA,
+
+       /* HSI2C */
+       MX51_PAD_I2C1_CLK__HSI2C_CLK,
+       MX51_PAD_I2C1_DAT__HSI2C_DAT,
+
        /* USB HOST1 */
        MX51_PAD_USBH1_CLK__USBH1_CLK,
        MX51_PAD_USBH1_DIR__USBH1_DIR,
@@ -78,7 +92,7 @@ static struct pad_desc mx51babbage_pads[] = {
        MX51_PAD_USBH1_DATA7__USBH1_DATA7,
 
        /* USB HUB reset line*/
-       MX51_PAD_GPIO_1_7__GPIO1_7,
+       MX51_PAD_GPIO_1_7__GPIO_1_7,
 };
 
 /* Serial ports */
@@ -99,6 +113,14 @@ static inline void mxc_init_imx_uart(void)
 }
 #endif /* SERIAL_IMX */
 
+static struct imxi2c_platform_data babbage_i2c_data = {
+       .bitrate = 100000,
+};
+
+static struct imxi2c_platform_data babbage_hsi2c_data = {
+       .bitrate = 400000,
+};
+
 static int gpio_usbh1_active(void)
 {
        struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27;
@@ -230,6 +252,10 @@ static void __init mxc_board_init(void)
        mxc_init_imx_uart();
        platform_add_devices(devices, ARRAY_SIZE(devices));
 
+       mxc_register_device(&mxc_i2c_device0, &babbage_i2c_data);
+       mxc_register_device(&mxc_i2c_device1, &babbage_i2c_data);
+       mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
+
        if (otg_mode_host)
                mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
        else {

diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index d9f612d3370e8849bea8bfb568bc3d0c4f3839ec..6af69def357f92d2f177d19d8fc7bce330ff5666 100644 (file)
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -758,6 +758,10 @@ static struct clk gpt_32k_clk = {
        .parent = &ckil_clk,
 };
 
+static struct clk kpp_clk = {
+       .id = 0,
+};
+
 #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)    \
        static struct clk name = {                      \
                .id             = i,                    \
@@ -798,6 +802,14 @@ DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
 DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
        NULL,  NULL, &ipg_clk, NULL);
 
+/* I2C */
+DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET,
+       NULL, NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET,
+       NULL, NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
+       NULL, NULL, &ipg_clk, NULL);
+
 /* FEC */
 DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
        NULL,  NULL, &ipg_clk, NULL);
@@ -815,12 +827,16 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
        _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
        _REGISTER_CLOCK("fec.0", NULL, fec_clk)
+       _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
+       _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
+       _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk)
        _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk)
        _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk)
        _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk)
        _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk)
        _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
        _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
+       _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
 };
 
 static void clk_tree_init(void)

diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
index 7130449aacdcff6671cea5fe794a418916bdac34..1920ff4963b211376822d2021d4e4bded6b268f1 100644 (file)
--- a/arch/arm/mach-mx5/devices.c
+++ b/arch/arm/mach-mx5/devices.c
@@ -93,6 +93,64 @@ struct platform_device mxc_fec_device = {
        .resource = mxc_fec_resources,
 };
 
+static struct resource mxc_i2c0_resources[] = {
+       {
+               .start = MX51_I2C1_BASE_ADDR,
+               .end = MX51_I2C1_BASE_ADDR + SZ_4K - 1,
+               .flags = IORESOURCE_MEM,
+       }, {
+               .start = MX51_MXC_INT_I2C1,
+               .end = MX51_MXC_INT_I2C1,
+               .flags = IORESOURCE_IRQ,
+       },
+};
+
+struct platform_device mxc_i2c_device0 = {
+       .name = "imx-i2c",
+       .id = 0,
+       .num_resources = ARRAY_SIZE(mxc_i2c0_resources),
+       .resource = mxc_i2c0_resources,
+};
+
+static struct resource mxc_i2c1_resources[] = {
+       {
+               .start = MX51_I2C2_BASE_ADDR,
+               .end = MX51_I2C2_BASE_ADDR + SZ_4K - 1,
+               .flags = IORESOURCE_MEM,
+       }, {
+               .start = MX51_MXC_INT_I2C2,
+               .end = MX51_MXC_INT_I2C2,
+               .flags = IORESOURCE_IRQ,
+       },
+};
+
+struct platform_device mxc_i2c_device1 = {
+       .name = "imx-i2c",
+       .id = 1,
+       .num_resources = ARRAY_SIZE(mxc_i2c1_resources),
+       .resource = mxc_i2c1_resources,
+};
+
+static struct resource mxc_hsi2c_resources[] = {
+       {
+               .start = MX51_HSI2C_DMA_BASE_ADDR,
+               .end = MX51_HSI2C_DMA_BASE_ADDR + SZ_16K - 1,
+               .flags = IORESOURCE_MEM,
+       },
+       {
+               .start = MX51_MXC_INT_HS_I2C,
+               .end = MX51_MXC_INT_HS_I2C,
+               .flags = IORESOURCE_IRQ,
+       },
+};
+
+struct platform_device mxc_hsi2c_device = {
+       .name = "imx-i2c",
+       .id = 2,
+       .num_resources = ARRAY_SIZE(mxc_hsi2c_resources),
+       .resource = mxc_hsi2c_resources
+};
+
 static u64 usb_dma_mask = DMA_BIT_MASK(32);
 
 static struct resource usbotg_resources[] = {
@@ -168,34 +226,57 @@ struct platform_device mxc_wdt = {
        .resource = mxc_wdt_resources,
 };
 
+static struct resource mxc_kpp_resources[] = {
+       {
+               .start = MX51_MXC_INT_KPP,
+               .end = MX51_MXC_INT_KPP,
+               .flags = IORESOURCE_IRQ,
+       } , {
+               .start = MX51_KPP_BASE_ADDR,
+               .end = MX51_KPP_BASE_ADDR + 0x8 - 1,
+               .flags = IORESOURCE_MEM,
+       },
+};
+
+struct platform_device mxc_keypad_device = {
+       .name = "imx-keypad",
+       .id = 0,
+       .num_resources = ARRAY_SIZE(mxc_kpp_resources),
+       .resource = mxc_kpp_resources,
+};
+
 static struct mxc_gpio_port mxc_gpio_ports[] = {
        {
                .chip.label = "gpio-0",
                .base = MX51_IO_ADDRESS(MX51_GPIO1_BASE_ADDR),
                .irq = MX51_MXC_INT_GPIO1_LOW,
+               .irq_high = MX51_MXC_INT_GPIO1_HIGH,
                .virtual_irq_start = MXC_GPIO_IRQ_START
        },
        {
                .chip.label = "gpio-1",
                .base = MX51_IO_ADDRESS(MX51_GPIO2_BASE_ADDR),
                .irq = MX51_MXC_INT_GPIO2_LOW,
+               .irq_high = MX51_MXC_INT_GPIO2_HIGH,
                .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 1
        },
        {
                .chip.label = "gpio-2",
                .base = MX51_IO_ADDRESS(MX51_GPIO3_BASE_ADDR),
                .irq = MX51_MXC_INT_GPIO3_LOW,
+               .irq_high = MX51_MXC_INT_GPIO3_HIGH,
                .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 2
        },
        {
                .chip.label = "gpio-3",
                .base = MX51_IO_ADDRESS(MX51_GPIO4_BASE_ADDR),
                .irq = MX51_MXC_INT_GPIO4_LOW,
+               .irq_high = MX51_MXC_INT_GPIO4_HIGH,
                .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3
        },
 };
 
-int __init mxc_register_gpios(void)
+int __init imx51_register_gpios(void)
 {
        return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
 }

diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
index c879ae71cd5b03e2995b3cee1d45f550d857ca47..e509cfaad1d466b4209fd36a5b01d9b4464a3d1a 100644 (file)
--- a/arch/arm/mach-mx5/devices.h
+++ b/arch/arm/mach-mx5/devices.h
@@ -6,3 +6,7 @@ extern struct platform_device mxc_usbdr_host_device;
 extern struct platform_device mxc_usbh1_device;
 extern struct platform_device mxc_usbdr_udc_device;
 extern struct platform_device mxc_wdt;
+extern struct platform_device mxc_i2c_device0;
+extern struct platform_device mxc_i2c_device1;
+extern struct platform_device mxc_hsi2c_device;
+extern struct platform_device mxc_keypad_device;

diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
new file mode 100644 (file)
index 0000000..ffa93d1
--- /dev/null
+++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
@@ -0,0 +1,200 @@
+/*
+ *
+ * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/fsl_devices.h>
+#include <linux/i2c/tsc2007.h>
+#include <linux/leds.h>
+#include <linux/input/matrix_keypad.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx51.h>
+
+#include <asm/mach/arch.h>
+
+#include "devices.h"
+
+#define MBIMX51_TSC2007_GPIO   (2*32 + 30)
+#define MBIMX51_TSC2007_IRQ    (MXC_INTERNAL_IRQS + MBIMX51_TSC2007_GPIO)
+#define MBIMX51_LED0           (2*32 + 5)
+#define MBIMX51_LED1           (2*32 + 6)
+#define MBIMX51_LED2           (2*32 + 7)
+#define MBIMX51_LED3           (2*32 + 8)
+
+static struct gpio_led mbimx51_leds[] = {
+       {
+               .name                   = "led0",
+               .default_trigger        = "heartbeat",
+               .active_low             = 1,
+               .gpio                   = MBIMX51_LED0,
+       },
+       {
+               .name                   = "led1",
+               .default_trigger        = "nand-disk",
+               .active_low             = 1,
+               .gpio                   = MBIMX51_LED1,
+       },
+       {
+               .name                   = "led2",
+               .default_trigger        = "mmc0",
+               .active_low             = 1,
+               .gpio                   = MBIMX51_LED2,
+       },
+       {
+               .name                   = "led3",
+               .default_trigger        = "default-on",
+               .active_low             = 1,
+               .gpio                   = MBIMX51_LED3,
+       },
+};
+
+static struct gpio_led_platform_data mbimx51_leds_info = {
+       .leds           = mbimx51_leds,
+       .num_leds       = ARRAY_SIZE(mbimx51_leds),
+};
+
+static struct platform_device mbimx51_leds_gpio = {
+       .name   = "leds-gpio",
+       .id     = -1,
+       .dev    = {
+               .platform_data  = &mbimx51_leds_info,
+       },
+};
+
+static struct platform_device *devices[] __initdata = {
+       &mbimx51_leds_gpio,
+};
+
+static struct pad_desc mbimx51_pads[] = {
+       /* UART2 */
+       MX51_PAD_UART2_RXD__UART2_RXD,
+       MX51_PAD_UART2_TXD__UART2_TXD,
+
+       /* UART3 */
+       MX51_PAD_UART3_RXD__UART3_RXD,
+       MX51_PAD_UART3_TXD__UART3_TXD,
+       MX51_PAD_KEY_COL4__UART3_RTS,
+       MX51_PAD_KEY_COL5__UART3_CTS,
+
+       /* TSC2007 IRQ */
+       MX51_PAD_NANDF_D10__GPIO_3_30,
+
+       /* LEDS */
+       MX51_PAD_DISPB2_SER_DIN__GPIO_3_5,
+       MX51_PAD_DISPB2_SER_DIO__GPIO_3_6,
+       MX51_PAD_DISPB2_SER_CLK__GPIO_3_7,
+       MX51_PAD_DISPB2_SER_RS__GPIO_3_8,
+
+       /* KPP */
+       MX51_PAD_KEY_ROW0__KEY_ROW0,
+       MX51_PAD_KEY_ROW1__KEY_ROW1,
+       MX51_PAD_KEY_ROW2__KEY_ROW2,
+       MX51_PAD_KEY_ROW3__KEY_ROW3,
+       MX51_PAD_KEY_COL0__KEY_COL0,
+       MX51_PAD_KEY_COL1__KEY_COL1,
+       MX51_PAD_KEY_COL2__KEY_COL2,
+       MX51_PAD_KEY_COL3__KEY_COL3,
+};
+
+static struct imxuart_platform_data uart_pdata = {
+       .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static int mbimx51_keymap[] = {
+       KEY(0, 0, KEY_1),
+       KEY(0, 1, KEY_2),
+       KEY(0, 2, KEY_3),
+       KEY(0, 3, KEY_UP),
+
+       KEY(1, 0, KEY_4),
+       KEY(1, 1, KEY_5),
+       KEY(1, 2, KEY_6),
+       KEY(1, 3, KEY_LEFT),
+
+       KEY(2, 0, KEY_7),
+       KEY(2, 1, KEY_8),
+       KEY(2, 2, KEY_9),
+       KEY(2, 3, KEY_RIGHT),
+
+       KEY(3, 0, KEY_0),
+       KEY(3, 1, KEY_DOWN),
+       KEY(3, 2, KEY_ESC),
+       KEY(3, 3, KEY_ENTER),
+};
+
+static struct matrix_keymap_data mbimx51_map_data = {
+       .keymap         = mbimx51_keymap,
+       .keymap_size    = ARRAY_SIZE(mbimx51_keymap),
+};
+
+static int tsc2007_get_pendown_state(void)
+{
+       return !gpio_get_value(MBIMX51_TSC2007_GPIO);
+}
+
+struct tsc2007_platform_data tsc2007_data = {
+       .model = 2007,
+       .x_plate_ohms = 180,
+       .get_pendown_state = tsc2007_get_pendown_state,
+};
+
+static struct i2c_board_info mbimx51_i2c_devices[] = {
+       {
+               I2C_BOARD_INFO("tsc2007", 0x48),
+               .irq  = MBIMX51_TSC2007_IRQ,
+               .platform_data = &tsc2007_data,
+       },
+};
+
+/*
+ * baseboard initialization.
+ */
+void __init eukrea_mbimx51_baseboard_init(void)
+{
+       mxc_iomux_v3_setup_multiple_pads(mbimx51_pads,
+                                       ARRAY_SIZE(mbimx51_pads));
+
+       mxc_register_device(&mxc_uart_device1, NULL);
+       mxc_register_device(&mxc_uart_device2, &uart_pdata);
+
+       gpio_request(MBIMX51_LED0, "LED0");
+       gpio_direction_output(MBIMX51_LED0, 1);
+       gpio_free(MBIMX51_LED0);
+       gpio_request(MBIMX51_LED1, "LED1");
+       gpio_direction_output(MBIMX51_LED1, 1);
+       gpio_free(MBIMX51_LED1);
+       gpio_request(MBIMX51_LED2, "LED2");
+       gpio_direction_output(MBIMX51_LED2, 1);
+       gpio_free(MBIMX51_LED2);
+       gpio_request(MBIMX51_LED3, "LED3");
+       gpio_direction_output(MBIMX51_LED3, 1);
+       gpio_free(MBIMX51_LED3);
+
+       platform_add_devices(devices, ARRAY_SIZE(devices));
+
+       mxc_register_device(&mxc_keypad_device, &mbimx51_map_data);
+
+       gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq");
+       gpio_direction_input(MBIMX51_TSC2007_GPIO);
+       set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING);
+       i2c_register_board_info(1, mbimx51_i2c_devices,
+                               ARRAY_SIZE(mbimx51_i2c_devices));
+}

diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index b7677ef80cc4388a4c414c4b7c8e1269137227a6..bc3f30db8d9a0f2df94debe9bf556000f58b0e91 100644 (file)
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -65,6 +65,8 @@ void __init mx51_map_io(void)
        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
 
+int imx51_register_gpios(void);
+
 void __init mx51_init_irq(void)
 {
        unsigned long tzic_addr;
@@ -80,4 +82,5 @@ void __init mx51_init_irq(void)
                panic("unable to map TZIC interrupt controller\n");
 
        tzic_init_irq(tzic_virt);
+       imx51_register_gpios();
 }

diff --git a/arch/arm/mach-mxc91231/crm_regs.h b/arch/arm/mach-mxc91231/crm_regs.h
index ce4f5905818982580bae7b24fca1a6ea0a67573d..b989baccd67507f76b5aa8dcc5fb7d6a2f67029f 100644 (file)
--- a/arch/arm/mach-mxc91231/crm_regs.h
+++ b/arch/arm/mach-mxc91231/crm_regs.h
@@ -11,11 +11,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
  */
 
 #ifndef _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_

diff --git a/arch/arm/mach-mxc91231/devices.c b/arch/arm/mach-mxc91231/devices.c
index 353bd977b393b3e87e21dd83c866776a69479d0b..027af4f0d18aed1a40c97f448f43daa2028efc32 100644 (file)
--- a/arch/arm/mach-mxc91231/devices.c
+++ b/arch/arm/mach-mxc91231/devices.c
@@ -135,7 +135,7 @@ static struct mxc_gpio_port mxc_gpio_ports[] = {
        },
 };
 
-int __init mxc_register_gpios(void)
+int __init mxc91231_register_gpios(void)
 {
        return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
 }

diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c
index 6becda3ff331ddf4196dc8a6667cbd543decd07e..aeccfd755fee6a9af9307a31a766a31fd091f7d5 100644 (file)
--- a/arch/arm/mach-mxc91231/mm.c
+++ b/arch/arm/mach-mxc91231/mm.c
@@ -15,11 +15,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
  */
 
 #include <linux/mm.h>
@@ -88,7 +83,10 @@ void __init mxc91231_map_io(void)
        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
 
+int mxc91231_register_gpios(void);
+
 void __init mxc91231_init_irq(void)
 {
+       mxc91231_register_gpios();
        mxc_init_irq(MXC91231_IO_ADDRESS(MXC91231_AVIC_BASE_ADDR));
 }

diff --git a/arch/arm/mach-nomadik/clock.c b/arch/arm/mach-nomadik/clock.c
index f035f4185274160757e11d32377509defbdfb1b7..89f793adf77643093c9e465c35447553102ae295 100644 (file)
--- a/arch/arm/mach-nomadik/clock.c
+++ b/arch/arm/mach-nomadik/clock.c
@@ -53,6 +53,10 @@ static struct clk clk_default;
        }
 
 static struct clk_lookup lookups[] = {
+       {
+               .con_id         = "apb_pclk",
+               .clk            = &clk_default,
+       },
        CLK(&clk_24, "mtu0"),
        CLK(&clk_24, "mtu1"),
        CLK(&clk_48, "uart0"),

diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index b18d7c28ab7ab49ae246d0aa3477d2f25773ce71..3b02d3b944af401cbe3f41918a45fec3a982b266 100644 (file)
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -1,3 +1,7 @@
+if ARCH_OMAP1
+
+menu "TI OMAP1 specific features"
+
 comment "OMAP Core Type"
        depends on ARCH_OMAP1
 
@@ -224,6 +228,12 @@ config OMAP_ARM_120MHZ
        help
           Enable 120MHz clock for OMAP CPU. If unsure, say N.
 
+config OMAP_ARM_96MHZ
+       bool "OMAP ARM 96 MHz CPU"
+       depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
+       help
+          Enable 96MHz clock for OMAP CPU. If unsure, say N.
+
 config OMAP_ARM_60MHZ
        bool "OMAP ARM 60 MHz CPU"
        depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
@@ -237,3 +247,6 @@ config OMAP_ARM_30MHZ
        help
           Enable 30MHz clock for OMAP CPU. If unsure, say N.
 
+endmenu
+
+endif

diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index ea231c7a550a7d3ff891cd0f38729906967c2786..facfaeb1ae5cb2837ff71903f793b9453e1b769c 100644 (file)
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -23,6 +23,9 @@ obj-y                                 += $(i2c-omap-m) $(i2c-omap-y)
 
 led-y := leds.o
 
+usb-fs-$(CONFIG_USB)                   := usb.o
+obj-y                                  += $(usb-fs-m) $(usb-fs-y)
+
 # Specific board support
 obj-$(CONFIG_MACH_OMAP_H2)             += board-h2.o board-h2-mmc.o
 obj-$(CONFIG_MACH_OMAP_INNOVATOR)      += board-innovator.o

diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index fdd1dd53fa9ceddcc5738687b36215d31c3b8ca0..41992ab71961ce6b1448ac0df659ced75ed94684 100644 (file)
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -235,7 +235,7 @@ static void __init ams_delta_init(void)
        /* Clear latch2 (NAND, LCD, modem enable) */
        ams_delta_latch2_write(~0, 0);
 
-       omap_usb_init(&ams_delta_usb_config);
+       omap1_usb_init(&ams_delta_usb_config);
        platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices));
 
 #ifdef CONFIG_AMS_DELTA_FIQ
@@ -301,6 +301,7 @@ MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")
        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
        .boot_params    = 0x10000100,
        .map_io         = ams_delta_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = ams_delta_init_irq,
        .init_machine   = ams_delta_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 096f2ed102cbe5aa8fff6a3632022f999776c51d..180ce79e5eacf9cae09583e568b2bc232d155a00 100644 (file)
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -292,6 +292,18 @@ static void __init omap_fsample_init(void)
        omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
        omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
 
+       /* Mux pins for keypad */
+       omap_cfg_reg(E2_7XX_KBR0);
+       omap_cfg_reg(J7_7XX_KBR1);
+       omap_cfg_reg(E1_7XX_KBR2);
+       omap_cfg_reg(F3_7XX_KBR3);
+       omap_cfg_reg(D2_7XX_KBR4);
+       omap_cfg_reg(C2_7XX_KBC0);
+       omap_cfg_reg(D3_7XX_KBC1);
+       omap_cfg_reg(E4_7XX_KBC2);
+       omap_cfg_reg(F4_7XX_KBC3);
+       omap_cfg_reg(E3_7XX_KBC4);
+
        platform_add_devices(devices, ARRAY_SIZE(devices));
 
        omap_board_config = fsample_config;
@@ -378,6 +390,7 @@ MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
        .boot_params    = 0x10000100,
        .map_io         = omap_fsample_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = omap_fsample_init_irq,
        .init_machine   = omap_fsample_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index e1195a3467b86106a60c258a429c664ca818569e..93b9ab8fc3be092d82d00ec8ef5cc934a0ac3cd0 100644 (file)
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -72,12 +72,12 @@ static void __init omap_generic_init(void)
                omap_cfg_reg(UART3_TX);
                omap_cfg_reg(UART3_RX);
 
-               omap_usb_init(&generic1510_usb_config);
+               omap1_usb_init(&generic1510_usb_config);
        }
 #endif
 #if defined(CONFIG_ARCH_OMAP16XX)
        if (!cpu_is_omap1510()) {
-               omap_usb_init(&generic1610_usb_config);
+               omap1_usb_init(&generic1610_usb_config);
        }
 #endif
 
@@ -98,6 +98,7 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710")
        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
        .boot_params    = 0x10000100,
        .map_io         = omap_generic_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = omap_generic_init_irq,
        .init_machine   = omap_generic_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index d1100e4f65aca736c6113643c1310cff4bc2a9b4..d2cda58bcc480873c9befbd9806366f358283779 100644 (file)
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -292,15 +292,6 @@ static struct platform_device h2_kp_device = {
 
 #define H2_IRDA_FIRSEL_GPIO_PIN        17
 
-#if defined(CONFIG_OMAP_IR) || defined(CONFIG_OMAP_IR_MODULE)
-static int h2_transceiver_mode(struct device *dev, int state)
-{
-       /* SIR when low, else MIR/FIR when HIGH */
-       gpio_set_value(H2_IRDA_FIRSEL_GPIO_PIN, !(state & IR_SIRMODE));
-       return 0;
-}
-#endif
-
 static struct omap_irda_config h2_irda_data = {
        .transceiver_cap        = IR_SIRMODE | IR_MIRMODE | IR_FIRMODE,
        .rx_channel             = OMAP_DMA_UART3_RX,
@@ -437,14 +428,18 @@ static void __init h2_init(void)
        /* omap_cfg_reg(U19_ARMIO1); */         /* CD */
        omap_cfg_reg(BALLOUT_V8_ARMIO3);        /* WP */
 
-       /* Irda */
-#if defined(CONFIG_OMAP_IR) || defined(CONFIG_OMAP_IR_MODULE)
-       omap_writel(omap_readl(FUNC_MUX_CTRL_A) | 7, FUNC_MUX_CTRL_A);
-       if (gpio_request(H2_IRDA_FIRSEL_GPIO_PIN, "IRDA mode") < 0)
-               BUG();
-       gpio_direction_output(H2_IRDA_FIRSEL_GPIO_PIN, 0);
-       h2_irda_data.transceiver_mode = h2_transceiver_mode;
-#endif
+       /* Mux pins for keypad */
+       omap_cfg_reg(F18_1610_KBC0);
+       omap_cfg_reg(D20_1610_KBC1);
+       omap_cfg_reg(D19_1610_KBC2);
+       omap_cfg_reg(E18_1610_KBC3);
+       omap_cfg_reg(C21_1610_KBC4);
+       omap_cfg_reg(G18_1610_KBR0);
+       omap_cfg_reg(F19_1610_KBR1);
+       omap_cfg_reg(H14_1610_KBR2);
+       omap_cfg_reg(E20_1610_KBR3);
+       omap_cfg_reg(E19_1610_KBR4);
+       omap_cfg_reg(N19_1610_KBR5);
 
        platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices));
        omap_board_config = h2_config;
@@ -452,7 +447,7 @@ static void __init h2_init(void)
        omap_serial_init();
        omap_register_i2c_bus(1, 100, h2_i2c_board_info,
                              ARRAY_SIZE(h2_i2c_board_info));
-       omap_usb_init(&h2_usb_config);
+       omap1_usb_init(&h2_usb_config);
        h2_mmc_init();
 }
 
@@ -467,6 +462,7 @@ MACHINE_START(OMAP_H2, "TI-H2")
        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
        .boot_params    = 0x10000100,
        .map_io         = h2_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = h2_init_irq,
        .init_machine   = h2_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index a53ab8297d25eb05185b433d310ab2dd415290bf..c2ef4ff846c74608adbc3f5041d1ab53aa8e6eb4 100644 (file)
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -397,6 +397,19 @@ static void __init h3_init(void)
        /* GPIO10 pullup/down register, Enable pullup on GPIO10 */
        omap_cfg_reg(V2_1710_GPIO10);
 
+       /* Mux pins for keypad */
+       omap_cfg_reg(F18_1610_KBC0);
+       omap_cfg_reg(D20_1610_KBC1);
+       omap_cfg_reg(D19_1610_KBC2);
+       omap_cfg_reg(E18_1610_KBC3);
+       omap_cfg_reg(C21_1610_KBC4);
+       omap_cfg_reg(G18_1610_KBR0);
+       omap_cfg_reg(F19_1610_KBR1);
+       omap_cfg_reg(H14_1610_KBR2);
+       omap_cfg_reg(E20_1610_KBR3);
+       omap_cfg_reg(E19_1610_KBR4);
+       omap_cfg_reg(N19_1610_KBR5);
+
        platform_add_devices(devices, ARRAY_SIZE(devices));
        spi_register_board_info(h3_spi_board_info,
                                ARRAY_SIZE(h3_spi_board_info));
@@ -405,7 +418,7 @@ static void __init h3_init(void)
        omap_serial_init();
        omap_register_i2c_bus(1, 100, h3_i2c_board_info,
                              ARRAY_SIZE(h3_i2c_board_info));
-       omap_usb_init(&h3_usb_config);
+       omap1_usb_init(&h3_usb_config);
        h3_mmc_init();
 }
 
@@ -437,6 +450,7 @@ MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
        .boot_params    = 0x10000100,
        .map_io         = h3_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = h3_init_irq,
        .init_machine   = h3_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 8e313b4b99a9d91145201f1d2e28a4a022a7f151..311899ff5ffcdfee5425f2f949cd1828863eea2b 100644 (file)
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -287,7 +287,7 @@ static void __init htcherald_init(void)
        htcherald_disable_watchdog();
 
        htcherald_usb_enable();
-       omap_usb_init(&htcherald_usb_config);
+       omap1_usb_init(&htcherald_usb_config);
 }
 
 static void __init htcherald_init_irq(void)
@@ -304,6 +304,7 @@ MACHINE_START(HERALD, "HTC Herald")
        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
        .boot_params    = 0x10000100,
        .map_io         = htcherald_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = htcherald_init_irq,
        .init_machine   = htcherald_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index 5d12fd35681b24041695fd3a324bb5a8f2d226bc..3daf87ad25765813f2aabe95090954df565bc132 100644 (file)
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -422,13 +422,13 @@ static void __init innovator_init(void)
 
 #ifdef CONFIG_ARCH_OMAP15XX
        if (cpu_is_omap1510()) {
-               omap_usb_init(&innovator1510_usb_config);
+               omap1_usb_init(&innovator1510_usb_config);
                innovator_config[1].data = &innovator1510_lcd_config;
        }
 #endif
 #ifdef CONFIG_ARCH_OMAP16XX
        if (cpu_is_omap1610()) {
-               omap_usb_init(&h2_usb_config);
+               omap1_usb_init(&h2_usb_config);
                innovator_config[1].data = &innovator1610_lcd_config;
        }
 #endif
@@ -463,6 +463,7 @@ MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
        .boot_params    = 0x10000100,
        .map_io         = innovator_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = innovator_init_irq,
        .init_machine   = innovator_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 71e1a3fad0ead110b7947e555af8c652da261695..51a4539aecf54ba1a7046227a695d2014610ce30 100644 (file)
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -32,7 +32,6 @@
 #include <plat/board.h>
 #include <plat/keypad.h>
 #include <plat/common.h>
-#include <plat/dsp_common.h>
 #include <plat/hwa742.h>
 #include <plat/lcd_mipid.h>
 #include <plat/mmc.h>
@@ -242,138 +241,6 @@ static inline void nokia770_mmc_init(void)
 }
 #endif
 
-#if    defined(CONFIG_OMAP_DSP)
-/*
- * audio power control
- */
-#define        HEADPHONE_GPIO          14
-#define        AMPLIFIER_CTRL_GPIO     58
-
-static struct clk *dspxor_ck;
-static DEFINE_MUTEX(audio_pwr_lock);
-/*
- * audio_pwr_state
- * +--+-------------------------+---------------------------------------+
- * |-1|down                    |power-up request -> 0                  |
- * +--+-------------------------+---------------------------------------+
- * | 0|up                      |power-down(1) request -> 1             |
- * |  |                                |power-down(2) request -> (ignore)      |
- * +--+-------------------------+---------------------------------------+
- * | 1|up,                     |power-up request -> 0                  |
- * |  |received down(1) request        |power-down(2) request -> -1            |
- * +--+-------------------------+---------------------------------------+
- */
-static int audio_pwr_state = -1;
-
-static inline void aic23_power_up(void)
-{
-}
-static inline void aic23_power_down(void)
-{
-}
-
-/*
- * audio_pwr_up / down should be called under audio_pwr_lock
- */
-static void nokia770_audio_pwr_up(void)
-{
-       clk_enable(dspxor_ck);
-
-       /* Turn on codec */
-       aic23_power_up();
-
-       if (gpio_get_value(HEADPHONE_GPIO))
-               /* HP not connected, turn on amplifier */
-               gpio_set_value(AMPLIFIER_CTRL_GPIO, 1);
-       else
-               /* HP connected, do not turn on amplifier */
-               printk("HP connected\n");
-}
-
-static void codec_delayed_power_down(struct work_struct *work)
-{
-       mutex_lock(&audio_pwr_lock);
-       if (audio_pwr_state == -1)
-               aic23_power_down();
-       clk_disable(dspxor_ck);
-       mutex_unlock(&audio_pwr_lock);
-}
-
-static DECLARE_DELAYED_WORK(codec_power_down_work, codec_delayed_power_down);
-
-static void nokia770_audio_pwr_down(void)
-{
-       /* Turn off amplifier */
-       gpio_set_value(AMPLIFIER_CTRL_GPIO, 0);
-
-       /* Turn off codec: schedule delayed work */
-       schedule_delayed_work(&codec_power_down_work, HZ / 20); /* 50ms */
-}
-
-static int
-nokia770_audio_pwr_up_request(struct dsp_kfunc_device *kdev, int stage)
-{
-       mutex_lock(&audio_pwr_lock);
-       if (audio_pwr_state == -1)
-               nokia770_audio_pwr_up();
-       /* force audio_pwr_state = 0, even if it was 1. */
-       audio_pwr_state = 0;
-       mutex_unlock(&audio_pwr_lock);
-       return 0;
-}
-
-static int
-nokia770_audio_pwr_down_request(struct dsp_kfunc_device *kdev, int stage)
-{
-       mutex_lock(&audio_pwr_lock);
-       switch (stage) {
-       case 1:
-               if (audio_pwr_state == 0)
-                       audio_pwr_state = 1;
-               break;
-       case 2:
-               if (audio_pwr_state == 1) {
-                       nokia770_audio_pwr_down();
-                       audio_pwr_state = -1;
-               }
-               break;
-       }
-       mutex_unlock(&audio_pwr_lock);
-       return 0;
-}
-
-static struct dsp_kfunc_device nokia770_audio_device = {
-       .name    = "audio",
-       .type    = DSP_KFUNC_DEV_TYPE_AUDIO,
-       .enable  = nokia770_audio_pwr_up_request,
-       .disable = nokia770_audio_pwr_down_request,
-};
-
-static __init int omap_dsp_init(void)
-{
-       int ret;
-
-       dspxor_ck = clk_get(0, "dspxor_ck");
-       if (IS_ERR(dspxor_ck)) {
-               printk(KERN_ERR "couldn't acquire dspxor_ck\n");
-               return PTR_ERR(dspxor_ck);
-       }
-
-       ret = dsp_kfunc_device_register(&nokia770_audio_device);
-       if (ret) {
-               printk(KERN_ERR
-                      "KFUNC device registration faild: %s\n",
-                      nokia770_audio_device.name);
-               goto out;
-       }
-       return 0;
- out:
-       return ret;
-}
-#else
-#define omap_dsp_init()                do {} while (0)
-#endif /* CONFIG_OMAP_DSP */
-
 static void __init omap_nokia770_init(void)
 {
        platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices));
@@ -382,11 +249,10 @@ static void __init omap_nokia770_init(void)
        omap_gpio_init();
        omap_serial_init();
        omap_register_i2c_bus(1, 100, NULL, 0);
-       omap_dsp_init();
        hwa742_dev_init();
        ads7846_dev_init();
        mipid_dev_init();
-       omap_usb_init(&nokia770_usb_config);
+       omap1_usb_init(&nokia770_usb_config);
        nokia770_mmc_init();
 }
 
@@ -400,6 +266,7 @@ MACHINE_START(NOKIA770, "Nokia 770")
        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
        .boot_params    = 0x10000100,
        .map_io         = omap_nokia770_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = omap_nokia770_init_irq,
        .init_machine   = omap_nokia770_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 80d862001def595ef2fada032e909a9bcd9aea01..679740cc1e9020e8ea0200524215c31f92827178 100644 (file)
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -560,7 +560,7 @@ static void __init osk_init(void)
        l |= (3 << 1);
        omap_writel(l, USB_TRANSCEIVER_CTRL);
 
-       omap_usb_init(&osk_usb_config);
+       omap1_usb_init(&osk_usb_config);
 
        /* irq for tps65010 chip */
        /* bootloader effectively does:  omap_cfg_reg(U19_1610_MPUIO1); */
@@ -584,6 +584,7 @@ MACHINE_START(OMAP_OSK, "TI-OSK")
        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
        .boot_params    = 0x10000100,
        .map_io         = osk_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = osk_init_irq,
        .init_machine   = osk_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 569b4c9085cd8b952f91716ebe7e00984ebe7169..782bb257a85d9a901b4478eaf4923abe877e849d 100644 (file)
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -213,90 +213,6 @@ static struct omap_lcd_config palmte_lcd_config __initdata = {
        .ctrl_name      = "internal",
 };
 
-#ifdef CONFIG_APM
-/*
- * Values measured in 10 minute intervals averaged over 10 samples.
- * May differ slightly from device to device but should be accurate
- * enough to give basic idea of battery life left and trigger
- * potential alerts.
- */
-static const int palmte_battery_sample[] = {
-       2194, 2157, 2138, 2120,
-       2104, 2089, 2075, 2061,
-       2048, 2038, 2026, 2016,
-       2008, 1998, 1989, 1980,
-       1970, 1958, 1945, 1928,
-       1910, 1888, 1860, 1827,
-       1791, 1751, 1709, 1656,
-};
-
-#define INTERVAL               10
-#define BATTERY_HIGH_TRESHOLD  66
-#define BATTERY_LOW_TRESHOLD   33
-
-static void palmte_get_power_status(struct apm_power_info *info, int *battery)
-{
-       int charging, batt, hi, lo, mid;
-
-       charging = !gpio_get_value(PALMTE_DC_GPIO);
-       batt = battery[0];
-       if (charging)
-               batt -= 60;
-
-       hi = ARRAY_SIZE(palmte_battery_sample);
-       lo = 0;
-
-       info->battery_flag = 0;
-       info->units = APM_UNITS_MINS;
-
-       if (batt > palmte_battery_sample[lo]) {
-               info->battery_life = 100;
-               info->time = INTERVAL * ARRAY_SIZE(palmte_battery_sample);
-       } else if (batt <= palmte_battery_sample[hi - 1]) {
-               info->battery_life = 0;
-               info->time = 0;
-       } else {
-               while (hi > lo + 1) {
-                       mid = (hi + lo) >> 1;
-                       if (batt <= palmte_battery_sample[mid])
-                               lo = mid;
-                       else
-                               hi = mid;
-               }
-
-               mid = palmte_battery_sample[lo] - palmte_battery_sample[hi];
-               hi = palmte_battery_sample[lo] - batt;
-               info->battery_life = 100 - (100 * lo + 100 * hi / mid) /
-                       ARRAY_SIZE(palmte_battery_sample);
-               info->time = INTERVAL * (ARRAY_SIZE(palmte_battery_sample) -
-                               lo) - INTERVAL * hi / mid;
-       }
-
-       if (charging) {
-               info->ac_line_status = APM_AC_ONLINE;
-               info->battery_status = APM_BATTERY_STATUS_CHARGING;
-               info->battery_flag |= APM_BATTERY_FLAG_CHARGING;
-       } else {
-               info->ac_line_status = APM_AC_OFFLINE;
-               if (info->battery_life > BATTERY_HIGH_TRESHOLD)
-                       info->battery_status = APM_BATTERY_STATUS_HIGH;
-               else if (info->battery_life > BATTERY_LOW_TRESHOLD)
-                       info->battery_status = APM_BATTERY_STATUS_LOW;
-               else
-                       info->battery_status = APM_BATTERY_STATUS_CRITICAL;
-       }
-
-       if (info->battery_life > BATTERY_HIGH_TRESHOLD)
-               info->battery_flag |= APM_BATTERY_FLAG_HIGH;
-       else if (info->battery_life > BATTERY_LOW_TRESHOLD)
-               info->battery_flag |= APM_BATTERY_FLAG_LOW;
-       else
-               info->battery_flag |= APM_BATTERY_FLAG_CRITICAL;
-}
-#else
-#define palmte_get_power_status        NULL
-#endif
-
 static struct omap_board_config_kernel palmte_config[] __initdata = {
        { OMAP_TAG_LCD,         &palmte_lcd_config },
 };
@@ -359,7 +275,7 @@ static void __init omap_palmte_init(void)
        spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info));
        palmte_misc_gpio_setup();
        omap_serial_init();
-       omap_usb_init(&palmte_usb_config);
+       omap1_usb_init(&palmte_usb_config);
        omap_register_i2c_bus(1, 100, NULL, 0);
 }
 
@@ -373,6 +289,7 @@ MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
        .boot_params    = 0x10000100,
        .map_io         = omap_palmte_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = omap_palmte_init_irq,
        .init_machine   = omap_palmte_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 6ad49a2cc1a03af4368628ddef06896786d6c3ae..0b35ef54a64fa47f47bc4d369e450034b03543b9 100644 (file)
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -307,7 +307,7 @@ static void __init omap_palmtt_init(void)
 
        spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo));
        omap_serial_init();
-       omap_usb_init(&palmtt_usb_config);
+       omap1_usb_init(&palmtt_usb_config);
        omap_register_i2c_bus(1, 100, NULL, 0);
 }
 
@@ -321,6 +321,7 @@ MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T")
        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
        .boot_params    = 0x10000100,
        .map_io         = omap_palmtt_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = omap_palmtt_init_irq,
        .init_machine   = omap_palmtt_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 6641de9257efa047cbf02d94e37506675913c354..66362903b6e238ec1646e336e74377488a4ccea7 100644 (file)
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -325,7 +325,7 @@ omap_palmz71_init(void)
 
        spi_register_board_info(palmz71_boardinfo,
                                ARRAY_SIZE(palmz71_boardinfo));
-       omap_usb_init(&palmz71_usb_config);
+       omap1_usb_init(&palmz71_usb_config);
        omap_serial_init();
        omap_register_i2c_bus(1, 100, NULL, 0);
        palmz71_gpio_setup(0);
@@ -338,10 +338,12 @@ omap_palmz71_map_io(void)
 }
 
 MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71")
-       .phys_io = 0xfff00000,
-       .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
-       .boot_params = 0x10000100,.map_io = omap_palmz71_map_io,
-       .init_irq = omap_palmz71_init_irq,
-       .init_machine = omap_palmz71_init,
-       .timer = &omap_timer,
+       .phys_io        = 0xfff00000,
+       .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
+       .boot_params    = 0x10000100,
+       .map_io         = omap_palmz71_map_io,
+       .reserve        = omap_reserve,
+       .init_irq       = omap_palmz71_init_irq,
+       .init_machine   = omap_palmz71_init,
+       .timer          = &omap_timer,
 MACHINE_END

diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index e854d5741c8889daad675ae230bef5848bdcf6fa..34ab354758b0b5f835d1b97607f5286884d13eda 100644 (file)
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -260,6 +260,18 @@ static void __init omap_perseus2_init(void)
        omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
        omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
 
+       /* Mux pins for keypad */
+       omap_cfg_reg(E2_7XX_KBR0);
+       omap_cfg_reg(J7_7XX_KBR1);
+       omap_cfg_reg(E1_7XX_KBR2);
+       omap_cfg_reg(F3_7XX_KBR3);
+       omap_cfg_reg(D2_7XX_KBR4);
+       omap_cfg_reg(C2_7XX_KBC0);
+       omap_cfg_reg(D3_7XX_KBC1);
+       omap_cfg_reg(E4_7XX_KBC2);
+       omap_cfg_reg(F4_7XX_KBC3);
+       omap_cfg_reg(E3_7XX_KBC4);
+
        platform_add_devices(devices, ARRAY_SIZE(devices));
 
        omap_board_config = perseus2_config;
@@ -339,6 +351,7 @@ MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
        .boot_params    = 0x10000100,
        .map_io         = omap_perseus2_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = omap_perseus2_init_irq,
        .init_machine   = omap_perseus2_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 2fb1e5f8e2ec5c637a992007123842bf7e48d2f3..2eb148b8de937aa5f8e839ea7ba07d85806c0869 100644 (file)
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -392,7 +392,7 @@ static void __init omap_sx1_init(void)
        omap_board_config_size = ARRAY_SIZE(sx1_config);
        omap_serial_init();
        omap_register_i2c_bus(1, 100, NULL, 0);
-       omap_usb_init(&sx1_usb_config);
+       omap1_usb_init(&sx1_usb_config);
        sx1_mmc_init();
 
        /* turn on USB power */
@@ -423,7 +423,8 @@ MACHINE_START(SX1, "OMAP310 based Siemens SX1")
        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
        .boot_params    = 0x10000100,
        .map_io         = omap_sx1_map_io,
-       .init_irq               = omap_sx1_init_irq,
+       .reserve        = omap_reserve,
+       .init_irq       = omap_sx1_init_irq,
        .init_machine   = omap_sx1_init,
        .timer          = &omap_timer,
 MACHINE_END

diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 87b9436fe7c0c011972fd24b7da43716a5aad5fd..6b3cf14bc7572e8884366db6ffa8cc4e4c0ef6ed 100644 (file)
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -198,7 +198,7 @@ static void __init voiceblue_init(void)
        omap_board_config = voiceblue_config;
        omap_board_config_size = ARRAY_SIZE(voiceblue_config);
        omap_serial_init();
-       omap_usb_init(&voiceblue_usb_config);
+       omap1_usb_init(&voiceblue_usb_config);
        omap_register_i2c_bus(1, 100, NULL, 0);
 
        /* There is a good chance board is going up, so enable power LED
@@ -287,6 +287,7 @@ MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
        .boot_params    = 0x10000100,
        .map_io         = voiceblue_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = voiceblue_init_irq,
        .init_machine   = voiceblue_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 6bbb1b8b82947776845bc4e7f9ece576995a42d4..b8c7fb9d792108adbccb8b342083c7551830924f 100644 (file)
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -11,7 +11,6 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/list.h>
 #include <linux/errno.h>
@@ -34,9 +33,9 @@
 __u32 arm_idlect1_mask;
 struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
 
-/*-------------------------------------------------------------------------
+/*
  * Omap1 specific clock functions
- *-------------------------------------------------------------------------*/
+ */
 
 unsigned long omap1_uart_recalc(struct clk *clk)
 {
@@ -523,7 +522,8 @@ const struct clkops clkops_dspck = {
        .disable        = omap1_clk_disable_dsp_domain,
 };
 
-static int omap1_clk_enable_uart_functional(struct clk *clk)
+/* XXX SYSC register handling does not belong in the clock framework */
+static int omap1_clk_enable_uart_functional_16xx(struct clk *clk)
 {
        int ret;
        struct uart_clk *uclk;
@@ -539,7 +539,8 @@ static int omap1_clk_enable_uart_functional(struct clk *clk)
        return ret;
 }
 
-static void omap1_clk_disable_uart_functional(struct clk *clk)
+/* XXX SYSC register handling does not belong in the clock framework */
+static void omap1_clk_disable_uart_functional_16xx(struct clk *clk)
 {
        struct uart_clk *uclk;
 
@@ -550,9 +551,10 @@ static void omap1_clk_disable_uart_functional(struct clk *clk)
        omap1_clk_disable_generic(clk);
 }
 
-const struct clkops clkops_uart = {
-       .enable         = omap1_clk_enable_uart_functional,
-       .disable        = omap1_clk_disable_uart_functional,
+/* XXX SYSC register handling does not belong in the clock framework */
+const struct clkops clkops_uart_16xx = {
+       .enable         = omap1_clk_enable_uart_functional_16xx,
+       .disable        = omap1_clk_disable_uart_functional_16xx,
 };
 
 long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
@@ -572,9 +574,9 @@ int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
        return ret;
 }
 
-/*-------------------------------------------------------------------------
+/*
  * Omap1 clock reset and init functions
- *-------------------------------------------------------------------------*/
+ */
 
 #ifdef CONFIG_OMAP_RESET_CLOCKS
 

diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
index 75d0d7d90bff6b08fbd6e5d6ff8e8496a5680d96..eaf09efb91caec613eeb73e961e7fbd77a93cf21 100644 (file)
--- a/arch/arm/mach-omap1/clock.h
+++ b/arch/arm/mach-omap1/clock.h
@@ -107,7 +107,7 @@ extern struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
 
 extern const struct clkops clkops_dspck;
 extern const struct clkops clkops_dummy;
-extern const struct clkops clkops_uart;
+extern const struct clkops clkops_uart_16xx;
 extern const struct clkops clkops_generic;
 
 #endif

diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index aa8558adbf1c0416d81dd89c6c43dd5eab0424ca..af54114b8f08660c447a35fbc2d4fbbb2482df69 100644 (file)
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -8,6 +8,10 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
+ *
+ * To do:
+ * - Clocks that are only available on some chips should be marked with the
+ *   chips that they are present on.
  */
 
 #include <linux/kernel.h>
@@ -23,9 +27,49 @@
 
 #include "clock.h"
 
-/*------------------------------------------------------------------------
+/* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
+#define IDL_CLKOUT_ARM_SHIFT                   12
+#define IDLTIM_ARM_SHIFT                       9
+#define IDLAPI_ARM_SHIFT                       8
+#define IDLIF_ARM_SHIFT                                6
+#define IDLLB_ARM_SHIFT                                4       /* undocumented? */
+#define OMAP1510_IDLLCD_ARM_SHIFT              3       /* undocumented? */
+#define IDLPER_ARM_SHIFT                       2
+#define IDLXORP_ARM_SHIFT                      1
+#define IDLWDT_ARM_SHIFT                       0
+
+/* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */
+#define CONF_MOD_UART3_CLK_MODE_R              31
+#define CONF_MOD_UART2_CLK_MODE_R              30
+#define CONF_MOD_UART1_CLK_MODE_R              29
+#define CONF_MOD_MMC_SD_CLK_REQ_R              23
+#define CONF_MOD_MCBSP3_AUXON                  20
+
+/* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */
+#define CONF_MOD_SOSSI_CLK_EN_R                        16
+
+/* Some OTG_SYSCON_2-specific bit fields */
+#define OTG_SYSCON_2_UHOST_EN_SHIFT            8
+
+/* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */
+#define SOFT_MMC2_DPLL_REQ_SHIFT       13
+#define SOFT_MMC_DPLL_REQ_SHIFT                12
+#define SOFT_UART3_DPLL_REQ_SHIFT      11
+#define SOFT_UART2_DPLL_REQ_SHIFT      10
+#define SOFT_UART1_DPLL_REQ_SHIFT      9
+#define SOFT_USB_OTG_DPLL_REQ_SHIFT    8
+#define SOFT_CAM_DPLL_REQ_SHIFT                7
+#define SOFT_COM_MCKO_REQ_SHIFT                6
+#define SOFT_PERIPH_REQ_SHIFT          5       /* sys_ck gate for UART2 ? */
+#define USB_REQ_EN_SHIFT               4
+#define SOFT_USB_REQ_SHIFT             3       /* sys_ck gate for USB host? */
+#define SOFT_SDW_REQ_SHIFT             2       /* sys_ck gate for Bluetooth? */
+#define SOFT_COM_REQ_SHIFT             1       /* sys_ck gate for com proc? */
+#define SOFT_DPLL_REQ_SHIFT            0
+
+/*
  * Omap1 clocks
- *-------------------------------------------------------------------------*/
+ */
 
 static struct clk ck_ref = {
        .name           = "ck_ref",
@@ -54,7 +98,7 @@ static struct arm_idlect1_clk ck_dpll1out = {
                .enable_bit     = EN_CKOUT_ARM,
                .recalc         = &followparent_recalc,
        },
-       .idlect_shift   = 12,
+       .idlect_shift   = IDL_CLKOUT_ARM_SHIFT,
 };
 
 static struct clk sossi_ck = {
@@ -63,7 +107,7 @@ static struct clk sossi_ck = {
        .parent         = &ck_dpll1out.clk,
        .flags          = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
-       .enable_bit     = 16,
+       .enable_bit     = CONF_MOD_SOSSI_CLK_EN_R,
        .recalc         = &omap1_sossi_recalc,
        .set_rate       = &omap1_set_sossi_rate,
 };
@@ -91,7 +135,7 @@ static struct arm_idlect1_clk armper_ck = {
                .round_rate     = omap1_clk_round_rate_ckctl_arm,
                .set_rate       = omap1_clk_set_rate_ckctl_arm,
        },
-       .idlect_shift   = 2,
+       .idlect_shift   = IDLPER_ARM_SHIFT,
 };
 
 /*
@@ -118,7 +162,7 @@ static struct arm_idlect1_clk armxor_ck = {
                .enable_bit     = EN_XORPCK,
                .recalc         = &followparent_recalc,
        },
-       .idlect_shift   = 1,
+       .idlect_shift   = IDLXORP_ARM_SHIFT,
 };
 
 static struct arm_idlect1_clk armtim_ck = {
@@ -131,7 +175,7 @@ static struct arm_idlect1_clk armtim_ck = {
                .enable_bit     = EN_TIMCK,
                .recalc         = &followparent_recalc,
        },
-       .idlect_shift   = 9,
+       .idlect_shift   = IDLTIM_ARM_SHIFT,
 };
 
 static struct arm_idlect1_clk armwdt_ck = {
@@ -145,7 +189,7 @@ static struct arm_idlect1_clk armwdt_ck = {
                .fixed_div      = 14,
                .recalc         = &omap_fixed_divisor_recalc,
        },
-       .idlect_shift   = 0,
+       .idlect_shift   = IDLWDT_ARM_SHIFT,
 };
 
 static struct clk arminth_ck16xx = {
@@ -212,7 +256,6 @@ static struct clk dsptim_ck = {
        .recalc         = &followparent_recalc,
 };
 
-/* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
 static struct arm_idlect1_clk tc_ck = {
        .clk = {
                .name           = "tc_ck",
@@ -224,7 +267,7 @@ static struct arm_idlect1_clk tc_ck = {
                .round_rate     = omap1_clk_round_rate_ckctl_arm,
                .set_rate       = omap1_clk_set_rate_ckctl_arm,
        },
-       .idlect_shift   = 6,
+       .idlect_shift   = IDLIF_ARM_SHIFT,
 };
 
 static struct clk arminth_ck1510 = {
@@ -304,7 +347,7 @@ static struct arm_idlect1_clk api_ck = {
                .enable_bit     = EN_APICK,
                .recalc         = &followparent_recalc,
        },
-       .idlect_shift   = 8,
+       .idlect_shift   = IDLAPI_ARM_SHIFT,
 };
 
 static struct arm_idlect1_clk lb_ck = {
@@ -317,7 +360,7 @@ static struct arm_idlect1_clk lb_ck = {
                .enable_bit     = EN_LBCK,
                .recalc         = &followparent_recalc,
        },
-       .idlect_shift   = 4,
+       .idlect_shift   = IDLLB_ARM_SHIFT,
 };
 
 static struct clk rhea1_ck = {
@@ -359,9 +402,15 @@ static struct arm_idlect1_clk lcd_ck_1510 = {
                .round_rate     = omap1_clk_round_rate_ckctl_arm,
                .set_rate       = omap1_clk_set_rate_ckctl_arm,
        },
-       .idlect_shift   = 3,
+       .idlect_shift   = OMAP1510_IDLLCD_ARM_SHIFT,
 };
 
+/*
+ * XXX The enable_bit here is misused - it simply switches between 12MHz
+ * and 48MHz.  Reimplement with clksel.
+ *
+ * XXX does this need SYSC register handling?
+ */
 static struct clk uart1_1510 = {
        .name           = "uart1_ck",
        .ops            = &clkops_null,
@@ -370,25 +419,37 @@ static struct clk uart1_1510 = {
        .rate           = 12000000,
        .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
-       .enable_bit     = 29,   /* Chooses between 12MHz and 48MHz */
+       .enable_bit     = CONF_MOD_UART1_CLK_MODE_R,
        .set_rate       = &omap1_set_uart_rate,
        .recalc         = &omap1_uart_recalc,
 };
 
+/*
+ * XXX The enable_bit here is misused - it simply switches between 12MHz
+ * and 48MHz.  Reimplement with clksel.
+ *
+ * XXX SYSC register handling does not belong in the clock framework
+ */
 static struct uart_clk uart1_16xx = {
        .clk    = {
                .name           = "uart1_ck",
-               .ops            = &clkops_uart,
+               .ops            = &clkops_uart_16xx,
                /* Direct from ULPD, no real parent */
                .parent         = &armper_ck.clk,
                .rate           = 48000000,
                .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
                .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
-               .enable_bit     = 29,
+               .enable_bit     = CONF_MOD_UART1_CLK_MODE_R,
        },
        .sysc_addr      = 0xfffb0054,
 };
 
+/*
+ * XXX The enable_bit here is misused - it simply switches between 12MHz
+ * and 48MHz.  Reimplement with clksel.
+ *
+ * XXX does this need SYSC register handling?
+ */
 static struct clk uart2_ck = {
        .name           = "uart2_ck",
        .ops            = &clkops_null,
@@ -397,11 +458,17 @@ static struct clk uart2_ck = {
        .rate           = 12000000,
        .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
-       .enable_bit     = 30,   /* Chooses between 12MHz and 48MHz */
+       .enable_bit     = CONF_MOD_UART2_CLK_MODE_R,
        .set_rate       = &omap1_set_uart_rate,
        .recalc         = &omap1_uart_recalc,
 };
 
+/*
+ * XXX The enable_bit here is misused - it simply switches between 12MHz
+ * and 48MHz.  Reimplement with clksel.
+ *
+ * XXX does this need SYSC register handling?
+ */
 static struct clk uart3_1510 = {
        .name           = "uart3_ck",
        .ops            = &clkops_null,
@@ -410,21 +477,27 @@ static struct clk uart3_1510 = {
        .rate           = 12000000,
        .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
-       .enable_bit     = 31,   /* Chooses between 12MHz and 48MHz */
+       .enable_bit     = CONF_MOD_UART3_CLK_MODE_R,
        .set_rate       = &omap1_set_uart_rate,
        .recalc         = &omap1_uart_recalc,
 };
 
+/*
+ * XXX The enable_bit here is misused - it simply switches between 12MHz
+ * and 48MHz.  Reimplement with clksel.
+ *
+ * XXX SYSC register handling does not belong in the clock framework
+ */
 static struct uart_clk uart3_16xx = {
        .clk    = {
                .name           = "uart3_ck",
-               .ops            = &clkops_uart,
+               .ops            = &clkops_uart_16xx,
                /* Direct from ULPD, no real parent */
                .parent         = &armper_ck.clk,
                .rate           = 48000000,
                .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
                .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
-               .enable_bit     = 31,
+               .enable_bit     = CONF_MOD_UART3_CLK_MODE_R,
        },
        .sysc_addr      = 0xfffb9854,
 };
@@ -457,7 +530,7 @@ static struct clk usb_hhc_ck16xx = {
        /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
        .flags          = ENABLE_REG_32BIT,
        .enable_reg     = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
-       .enable_bit     = 8 /* UHOST_EN */,
+       .enable_bit     = OTG_SYSCON_2_UHOST_EN_SHIFT
 };
 
 static struct clk usb_dc_ck = {
@@ -466,7 +539,7 @@ static struct clk usb_dc_ck = {
        /* Direct from ULPD, no parent */
        .rate           = 48000000,
        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
-       .enable_bit     = 4,
+       .enable_bit     = USB_REQ_EN_SHIFT,
 };
 
 static struct clk usb_dc_ck7xx = {
@@ -475,7 +548,25 @@ static struct clk usb_dc_ck7xx = {
        /* Direct from ULPD, no parent */
        .rate           = 48000000,
        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
-       .enable_bit     = 8,
+       .enable_bit     = SOFT_USB_OTG_DPLL_REQ_SHIFT,
+};
+
+static struct clk uart1_7xx = {
+       .name           = "uart1_ck",
+       .ops            = &clkops_generic,
+       /* Direct from ULPD, no parent */
+       .rate           = 12000000,
+       .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
+       .enable_bit     = 9,
+};
+
+static struct clk uart2_7xx = {
+       .name           = "uart2_ck",
+       .ops            = &clkops_generic,
+       /* Direct from ULPD, no parent */
+       .rate           = 12000000,
+       .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
+       .enable_bit     = 11,
 };
 
 static struct clk mclk_1510 = {
@@ -484,7 +575,7 @@ static struct clk mclk_1510 = {
        /* Direct from ULPD, no parent. May be enabled by ext hardware. */
        .rate           = 12000000,
        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
-       .enable_bit     = 6,
+       .enable_bit     = SOFT_COM_MCKO_REQ_SHIFT,
 };
 
 static struct clk mclk_16xx = {
@@ -524,9 +615,13 @@ static struct clk mmc1_ck = {
        .rate           = 48000000,
        .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
-       .enable_bit     = 23,
+       .enable_bit     = CONF_MOD_MMC_SD_CLK_REQ_R,
 };
 
+/*
+ * XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as
+ * CONF_MOD_MCBSP3_AUXON ??
+ */
 static struct clk mmc2_ck = {
        .name           = "mmc2_ck",
        .ops            = &clkops_generic,
@@ -546,7 +641,7 @@ static struct clk mmc3_ck = {
        .rate           = 48000000,
        .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
-       .enable_bit     = 12,
+       .enable_bit     = SOFT_MMC_DPLL_REQ_SHIFT,
 };
 
 static struct clk virtual_ck_mpu = {
@@ -620,7 +715,9 @@ static struct omap_clk omap_clks[] = {
        /* ULPD clocks */
        CLK(NULL,       "uart1_ck",     &uart1_1510,    CK_1510 | CK_310),
        CLK(NULL,       "uart1_ck",     &uart1_16xx.clk, CK_16XX),
+       CLK(NULL,       "uart1_ck",     &uart1_7xx,     CK_7XX),
        CLK(NULL,       "uart2_ck",     &uart2_ck,      CK_16XX | CK_1510 | CK_310),
+       CLK(NULL,       "uart2_ck",     &uart2_7xx,     CK_7XX),
        CLK(NULL,       "uart3_ck",     &uart3_1510,    CK_1510 | CK_310),
        CLK(NULL,       "uart3_ck",     &uart3_16xx.clk, CK_16XX),
        CLK(NULL,       "usb_clko",     &usb_clko,      CK_16XX | CK_1510 | CK_310),

diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 16e43e52ce2f65e6b5f72cdac0cfe992b7c47c85..aa0725608fb17ec51e15cc077f0f3198a19018ab 100644 (file)
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -63,43 +63,7 @@ static void omap_init_rtc(void)
 static inline void omap_init_rtc(void) {}
 #endif
 
-#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
-
-#if defined(CONFIG_ARCH_OMAP15XX)
-#  define OMAP1_MBOX_SIZE      0x23
-#  define INT_DSP_MAILBOX1     INT_1510_DSP_MAILBOX1
-#elif defined(CONFIG_ARCH_OMAP16XX)
-#  define OMAP1_MBOX_SIZE      0x2f
-#  define INT_DSP_MAILBOX1     INT_1610_DSP_MAILBOX1
-#endif
-
-static struct resource mbox_resources[] = {
-       {
-               .start          = OMAP16XX_MAILBOX_BASE,
-               .end            = OMAP16XX_MAILBOX_BASE + OMAP1_MBOX_SIZE,
-               .flags          = IORESOURCE_MEM,
-       },
-       {
-               .start          = INT_DSP_MAILBOX1,
-               .flags          = IORESOURCE_IRQ,
-               .name           = "dsp",
-       },
-};
-
-static struct platform_device mbox_device = {
-       .name           = "omap-mailbox",
-       .id             = -1,
-       .num_resources  = ARRAY_SIZE(mbox_resources),
-       .resource       = mbox_resources,
-};
-
-static inline void omap_init_mbox(void)
-{
-       platform_device_register(&mbox_device);
-}
-#else
 static inline void omap_init_mbox(void) { }
-#endif
 
 /*-------------------------------------------------------------------------*/
 
@@ -229,42 +193,7 @@ static inline void omap_init_spi100k(void)
 
 /*-------------------------------------------------------------------------*/
 
-#if defined(CONFIG_OMAP_STI)
-
-#define OMAP1_STI_BASE         0xfffea000
-#define OMAP1_STI_CHANNEL_BASE (OMAP1_STI_BASE + 0x400)
-
-static struct resource sti_resources[] = {
-       {
-               .start          = OMAP1_STI_BASE,
-               .end            = OMAP1_STI_BASE + SZ_1K - 1,
-               .flags          = IORESOURCE_MEM,
-       },
-       {
-               .start          = OMAP1_STI_CHANNEL_BASE,
-               .end            = OMAP1_STI_CHANNEL_BASE + SZ_1K - 1,
-               .flags          = IORESOURCE_MEM,
-       },
-       {
-               .start          = INT_1610_STI,
-               .flags          = IORESOURCE_IRQ,
-       }
-};
-
-static struct platform_device sti_device = {
-       .name           = "sti",
-       .id             = -1,
-       .num_resources  = ARRAY_SIZE(sti_resources),
-       .resource       = sti_resources,
-};
-
-static inline void omap_init_sti(void)
-{
-       platform_device_register(&sti_device);
-}
-#else
 static inline void omap_init_sti(void) {}
-#endif
 
 /*-------------------------------------------------------------------------*/
 

diff --git a/arch/arm/mach-omap1/include/mach/debug-macro.S b/arch/arm/mach-omap1/include/mach/debug-macro.S
index e8a8cf36b7f0fa28c952989258645eb9ee89e7cf..671408eb4ab42f8d0128f125c546a8b2405bc9d0 100644 (file)
--- a/arch/arm/mach-omap1/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap1/include/mach/debug-macro.S
@@ -33,7 +33,7 @@ omap_uart_virt:       .word   0x0
                /* Use omap_uart_phys/virt if already configured */
 9:             mrc     p15, 0, \rx, c1, c0
                tst     \rx, #1                 @ MMU enabled?
-               ldreq   \rx, =omap_uart_phys    @ physical base address
+               ldreq   \rx, =__virt_to_phys(omap_uart_phys)    @ physical base address
                ldrne   \rx, =omap_uart_virt    @ virtual base
                ldr     \rx, [\rx, #0]
                cmp     \rx, #0                 @ is port configured?
@@ -68,11 +68,15 @@ omap_uart_virt:     .word   0x0
 
                /* Store both phys and virt address for the uart */
 98:            add     \rx, \rx, #0xff000000   @ phys base
-               ldr     \tmp, =omap_uart_phys
+               mrc     p15, 0, \tmp, c1, c0
+               tst     \tmp, #1                @ MMU enabled?
+               ldreq   \tmp, =__virt_to_phys(omap_uart_phys)
+               ldrne   \tmp, =omap_uart_phys
                str     \rx, [\tmp, #0]
                sub     \rx, \rx, #0xff000000   @ phys base
                add     \rx, \rx, #0xfe000000   @ virt base
-               ldr     \tmp, =omap_uart_virt
+               ldreq   \tmp, =__virt_to_phys(omap_uart_virt)
+               ldrne   \tmp, =omap_uart_virt
                str     \rx, [\tmp, #0]
                b       9b
 99:

diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index d9b8d82530ae165bf18ab272c49ff61a069ae298..0ce3fec2d257c2b6183a4b426608e56679ff556c 100644 (file)
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -22,7 +22,6 @@
 
 extern void omap_check_revision(void);
 extern void omap_sram_init(void);
-extern void omapfb_reserve_sdram(void);
 
 /*
  * The machine specific code may provide the extra mapping besides the
@@ -122,7 +121,6 @@ void __init omap1_map_common_io(void)
 #endif
 
        omap_sram_init();
-       omapfb_reserve_sdram();
 }
 
 /*

diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index e9bdff192f8261d39a7cac0a7ad351970b24d633..b3a796a6da03579b1704960b18a65ea540382784 100644 (file)
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -23,7 +23,6 @@
 #include <plat/mux.h>
 #include <plat/cpu.h>
 #include <plat/mcbsp.h>
-#include <plat/dsp_common.h>
 
 #define DPS_RSTCT2_PER_EN      (1 << 0)
 #define DSP_RSTCT2_WD_PER_EN   (1 << 1)
@@ -46,7 +45,6 @@ static void omap1_mcbsp_request(unsigned int id)
                                clk_enable(api_clk);
                                clk_enable(dsp_clk);
 
-                               omap_dsp_request_mem();
                                /*
                                 * DSP external peripheral reset
                                 * FIXME: This should be moved to dsp code
@@ -62,7 +60,6 @@ static void omap1_mcbsp_free(unsigned int id)
 {
        if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
                if (--dsp_use == 0) {
-                       omap_dsp_release_mem();
                        if (!IS_ERR(api_clk)) {
                                clk_disable(api_clk);
                                clk_put(api_clk);

diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
index 84341377232db2ac2706cc5494b2aad7ab0ab34d..7835add0034478309f5790f2cd0cde6e0cfa7bc8 100644 (file)
--- a/arch/arm/mach-omap1/mux.c
+++ b/arch/arm/mach-omap1/mux.c
@@ -70,6 +70,10 @@ MUX_CFG_7XX("SPI_7XX_3",           6,   13,    4,   12,   1, 0)
 MUX_CFG_7XX("SPI_7XX_4",           6,   17,    4,   16,   1, 0)
 MUX_CFG_7XX("SPI_7XX_5",           8,   25,    0,   24,   0, 0)
 MUX_CFG_7XX("SPI_7XX_6",           9,    5,    0,    4,   0, 0)
+
+/* UART pins */
+MUX_CFG_7XX("UART_7XX_1",          3,   21,    0,   20,   0, 0)
+MUX_CFG_7XX("UART_7XX_2",          8,    1,    6,    0,   0, 0)
 };
 #define OMAP7XX_PINS_SZ                ARRAY_SIZE(omap7xx_pins)
 #else
@@ -440,7 +444,7 @@ int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
        }
 #endif
 
-#ifdef CONFIG_OMAP_MUX_ERRORS
+#ifdef CONFIG_OMAP_MUX_WARNINGS
        return warn ? -ETXTBSY : 0;
 #else
        return 0;

diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c
index 349de90194e30cc05bd654d19c8e3c935b6a7c95..b78d0749f13d9bd4a80c8dd250ac531123c869ad 100644 (file)
--- a/arch/arm/mach-omap1/serial.c
+++ b/arch/arm/mach-omap1/serial.c
@@ -122,6 +122,13 @@ void __init omap_serial_init(void)
 
        for (i = 0; i < ARRAY_SIZE(serial_platform_data) - 1; i++) {
 
+               /* Don't look at UARTs higher than 2 for omap7xx */
+               if (cpu_is_omap7xx() && i > 1) {
+                       serial_platform_data[i].membase = NULL;
+                       serial_platform_data[i].mapbase = 0;
+                       continue;
+               }
+
                /* Static mapping, never released */
                serial_platform_data[i].membase =
                        ioremap(serial_platform_data[i].mapbase, SZ_2K);

diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c
new file mode 100644 (file)
index 0000000..19de03b
--- /dev/null
+++ b/arch/arm/mach-omap1/usb.c
@@ -0,0 +1,530 @@
+/*
+ * Platform level USB initialization for FS USB OTG controller on omap1 and 24xx
+ *
+ * Copyright (C) 2004 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <asm/irq.h>
+
+#include <plat/mux.h>
+#include <plat/usb.h>
+
+/* These routines should handle the standard chip-specific modes
+ * for usb0/1/2 ports, covering basic mux and transceiver setup.
+ *
+ * Some board-*.c files will need to set up additional mux options,
+ * like for suspend handling, vbus sensing, GPIOs, and the D+ pullup.
+ */
+
+/* TESTED ON:
+ *  - 1611B H2 (with usb1 mini-AB) using standard Mini-B or OTG cables
+ *  - 5912 OSK OHCI (with usb0 standard-A), standard A-to-B cables
+ *  - 5912 OSK UDC, with *nonstandard* A-to-A cable
+ *  - 1510 Innovator UDC with bundled usb0 cable
+ *  - 1510 Innovator OHCI with bundled usb1/usb2 cable
+ *  - 1510 Innovator OHCI with custom usb0 cable, feeding 5V VBUS
+ *  - 1710 custom development board using alternate pin group
+ *  - 1710 H3 (with usb1 mini-AB) using standard Mini-B or OTG cables
+ */
+
+#define INT_USB_IRQ_GEN                IH2_BASE + 20
+#define INT_USB_IRQ_NISO       IH2_BASE + 30
+#define INT_USB_IRQ_ISO                IH2_BASE + 29
+#define INT_USB_IRQ_HGEN       INT_USB_HHC_1
+#define INT_USB_IRQ_OTG                IH2_BASE + 8
+
+#ifdef CONFIG_USB_GADGET_OMAP
+
+static struct resource udc_resources[] = {
+       /* order is significant! */
+       {               /* registers */
+               .start          = UDC_BASE,
+               .end            = UDC_BASE + 0xff,
+               .flags          = IORESOURCE_MEM,
+       }, {            /* general IRQ */
+               .start          = INT_USB_IRQ_GEN,
+               .flags          = IORESOURCE_IRQ,
+       }, {            /* PIO IRQ */
+               .start          = INT_USB_IRQ_NISO,
+               .flags          = IORESOURCE_IRQ,
+       }, {            /* SOF IRQ */
+               .start          = INT_USB_IRQ_ISO,
+               .flags          = IORESOURCE_IRQ,
+       },
+};
+
+static u64 udc_dmamask = ~(u32)0;
+
+static struct platform_device udc_device = {
+       .name           = "omap_udc",
+       .id             = -1,
+       .dev = {
+               .dma_mask               = &udc_dmamask,
+               .coherent_dma_mask      = 0xffffffff,
+       },
+       .num_resources  = ARRAY_SIZE(udc_resources),
+       .resource       = udc_resources,
+};
+
+static inline void udc_device_init(struct omap_usb_config *pdata)
+{
+       /* IRQ numbers for omap7xx */
+       if(cpu_is_omap7xx()) {
+               udc_resources[1].start = INT_7XX_USB_GENI;
+               udc_resources[2].start = INT_7XX_USB_NON_ISO;
+               udc_resources[3].start = INT_7XX_USB_ISO;
+       }
+       pdata->udc_device = &udc_device;
+}
+
+#else
+
+static inline void udc_device_init(struct omap_usb_config *pdata)
+{
+}
+
+#endif
+
+#if    defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+
+/* The dmamask must be set for OHCI to work */
+static u64 ohci_dmamask = ~(u32)0;
+
+static struct resource ohci_resources[] = {
+       {
+               .start  = OMAP_OHCI_BASE,
+               .end    = OMAP_OHCI_BASE + 0xff,
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .start  = INT_USB_IRQ_HGEN,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device ohci_device = {
+       .name                   = "ohci",
+       .id                     = -1,
+       .dev = {
+               .dma_mask               = &ohci_dmamask,
+               .coherent_dma_mask      = 0xffffffff,
+       },
+       .num_resources  = ARRAY_SIZE(ohci_resources),
+       .resource               = ohci_resources,
+};
+
+static inline void ohci_device_init(struct omap_usb_config *pdata)
+{
+       if (cpu_is_omap7xx())
+               ohci_resources[1].start = INT_7XX_USB_HHC_1;
+       pdata->ohci_device = &ohci_device;
+}
+
+#else
+
+static inline void ohci_device_init(struct omap_usb_config *pdata)
+{
+}
+
+#endif
+
+#if    defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG)
+
+static struct resource otg_resources[] = {
+       /* order is significant! */
+       {
+               .start          = OTG_BASE,
+               .end            = OTG_BASE + 0xff,
+               .flags          = IORESOURCE_MEM,
+       }, {
+               .start          = INT_USB_IRQ_OTG,
+               .flags          = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device otg_device = {
+       .name           = "omap_otg",
+       .id             = -1,
+       .num_resources  = ARRAY_SIZE(otg_resources),
+       .resource       = otg_resources,
+};
+
+static inline void otg_device_init(struct omap_usb_config *pdata)
+{
+       if (cpu_is_omap7xx())
+               otg_resources[1].start = INT_7XX_USB_OTG;
+       pdata->otg_device = &otg_device;
+}
+
+#else
+
+static inline void otg_device_init(struct omap_usb_config *pdata)
+{
+}
+
+#endif
+
+u32 __init omap1_usb0_init(unsigned nwires, unsigned is_device)
+{
+       u32     syscon1 = 0;
+
+       if (nwires == 0) {
+               if (!cpu_is_omap15xx()) {
+                       u32 l;
+
+                       /* pulldown D+/D- */
+                       l = omap_readl(USB_TRANSCEIVER_CTRL);
+                       l &= ~(3 << 1);
+                       omap_writel(l, USB_TRANSCEIVER_CTRL);
+               }
+               return 0;
+       }
+
+       if (is_device) {
+               if (cpu_is_omap7xx()) {
+                       omap_cfg_reg(AA17_7XX_USB_DM);
+                       omap_cfg_reg(W16_7XX_USB_PU_EN);
+                       omap_cfg_reg(W17_7XX_USB_VBUSI);
+                       omap_cfg_reg(W18_7XX_USB_DMCK_OUT);
+                       omap_cfg_reg(W19_7XX_USB_DCRST);
+               } else
+                       omap_cfg_reg(W4_USB_PUEN);
+       }
+
+       if (nwires == 2) {
+               u32 l;
+
+               // omap_cfg_reg(P9_USB_DP);
+               // omap_cfg_reg(R8_USB_DM);
+
+               if (cpu_is_omap15xx()) {
+                       /* This works on 1510-Innovator */
+                       return 0;
+               }
+
+               /* NOTES:
+                *  - peripheral should configure VBUS detection!
+                *  - only peripherals may use the internal D+/D- pulldowns
+                *  - OTG support on this port not yet written
+                */
+
+               /* Don't do this for omap7xx -- it causes USB to not work correctly */
+               if (!cpu_is_omap7xx()) {
+                       l = omap_readl(USB_TRANSCEIVER_CTRL);
+                       l &= ~(7 << 4);
+                       if (!is_device)
+                               l |= (3 << 1);
+                       omap_writel(l, USB_TRANSCEIVER_CTRL);
+               }
+
+               return 3 << 16;
+       }
+
+       /* alternate pin config, external transceiver */
+       if (cpu_is_omap15xx()) {
+               printk(KERN_ERR "no usb0 alt pin config on 15xx\n");
+               return 0;
+       }
+
+       omap_cfg_reg(V6_USB0_TXD);
+       omap_cfg_reg(W9_USB0_TXEN);
+       omap_cfg_reg(W5_USB0_SE0);
+       if (nwires != 3)
+               omap_cfg_reg(Y5_USB0_RCV);
+
+       /* NOTE:  SPEED and SUSP aren't configured here.  OTG hosts
+        * may be able to use I2C requests to set those bits along
+        * with VBUS switching and overcurrent detection.
+        */
+
+       if (nwires != 6) {
+               u32 l;
+
+               l = omap_readl(USB_TRANSCEIVER_CTRL);
+               l &= ~CONF_USB2_UNI_R;
+               omap_writel(l, USB_TRANSCEIVER_CTRL);
+       }
+
+       switch (nwires) {
+       case 3:
+               syscon1 = 2;
+               break;
+       case 4:
+               syscon1 = 1;
+               break;
+       case 6:
+               syscon1 = 3;
+               {
+                       u32 l;
+
+                       omap_cfg_reg(AA9_USB0_VP);
+                       omap_cfg_reg(R9_USB0_VM);
+                       l = omap_readl(USB_TRANSCEIVER_CTRL);
+                       l |= CONF_USB2_UNI_R;
+                       omap_writel(l, USB_TRANSCEIVER_CTRL);
+               }
+               break;
+       default:
+               printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
+                       0, nwires);
+       }
+
+       return syscon1 << 16;
+}
+
+u32 __init omap1_usb1_init(unsigned nwires)
+{
+       u32     syscon1 = 0;
+
+       if (!cpu_is_omap15xx() && nwires != 6) {
+               u32 l;
+
+               l = omap_readl(USB_TRANSCEIVER_CTRL);
+               l &= ~CONF_USB1_UNI_R;
+               omap_writel(l, USB_TRANSCEIVER_CTRL);
+       }
+       if (nwires == 0)
+               return 0;
+
+       /* external transceiver */
+       omap_cfg_reg(USB1_TXD);
+       omap_cfg_reg(USB1_TXEN);
+       if (nwires != 3)
+               omap_cfg_reg(USB1_RCV);
+
+       if (cpu_is_omap15xx()) {
+               omap_cfg_reg(USB1_SEO);
+               omap_cfg_reg(USB1_SPEED);
+               // SUSP
+       } else if (cpu_is_omap1610() || cpu_is_omap5912()) {
+               omap_cfg_reg(W13_1610_USB1_SE0);
+               omap_cfg_reg(R13_1610_USB1_SPEED);
+               // SUSP
+       } else if (cpu_is_omap1710()) {
+               omap_cfg_reg(R13_1710_USB1_SE0);
+               // SUSP
+       } else {
+               pr_debug("usb%d cpu unrecognized\n", 1);
+               return 0;
+       }
+
+       switch (nwires) {
+       case 2:
+               goto bad;
+       case 3:
+               syscon1 = 2;
+               break;
+       case 4:
+               syscon1 = 1;
+               break;
+       case 6:
+               syscon1 = 3;
+               omap_cfg_reg(USB1_VP);
+               omap_cfg_reg(USB1_VM);
+               if (!cpu_is_omap15xx()) {
+                       u32 l;
+
+                       l = omap_readl(USB_TRANSCEIVER_CTRL);
+                       l |= CONF_USB1_UNI_R;
+                       omap_writel(l, USB_TRANSCEIVER_CTRL);
+               }
+               break;
+       default:
+bad:
+               printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
+                       1, nwires);
+       }
+
+       return syscon1 << 20;
+}
+
+u32 __init omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
+{
+       u32     syscon1 = 0;
+
+       /* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */
+       if (alt_pingroup || nwires == 0)
+               return 0;
+
+       if (!cpu_is_omap15xx() && nwires != 6) {
+               u32 l;
+
+               l = omap_readl(USB_TRANSCEIVER_CTRL);
+               l &= ~CONF_USB2_UNI_R;
+               omap_writel(l, USB_TRANSCEIVER_CTRL);
+       }
+
+       /* external transceiver */
+       if (cpu_is_omap15xx()) {
+               omap_cfg_reg(USB2_TXD);
+               omap_cfg_reg(USB2_TXEN);
+               omap_cfg_reg(USB2_SEO);
+               if (nwires != 3)
+                       omap_cfg_reg(USB2_RCV);
+               /* there is no USB2_SPEED */
+       } else if (cpu_is_omap16xx()) {
+               omap_cfg_reg(V6_USB2_TXD);
+               omap_cfg_reg(W9_USB2_TXEN);
+               omap_cfg_reg(W5_USB2_SE0);
+               if (nwires != 3)
+                       omap_cfg_reg(Y5_USB2_RCV);
+               // FIXME omap_cfg_reg(USB2_SPEED);
+       } else {
+               pr_debug("usb%d cpu unrecognized\n", 1);
+               return 0;
+       }
+
+       // omap_cfg_reg(USB2_SUSP);
+
+       switch (nwires) {
+       case 2:
+               goto bad;
+       case 3:
+               syscon1 = 2;
+               break;
+       case 4:
+               syscon1 = 1;
+               break;
+       case 5:
+               goto bad;
+       case 6:
+               syscon1 = 3;
+               if (cpu_is_omap15xx()) {
+                       omap_cfg_reg(USB2_VP);
+                       omap_cfg_reg(USB2_VM);
+               } else {
+                       u32 l;
+
+                       omap_cfg_reg(AA9_USB2_VP);
+                       omap_cfg_reg(R9_USB2_VM);
+                       l = omap_readl(USB_TRANSCEIVER_CTRL);
+                       l |= CONF_USB2_UNI_R;
+                       omap_writel(l, USB_TRANSCEIVER_CTRL);
+               }
+               break;
+       default:
+bad:
+               printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
+                       2, nwires);
+       }
+
+       return syscon1 << 24;
+}
+
+#ifdef CONFIG_ARCH_OMAP15XX
+
+/* ULPD_DPLL_CTRL */
+#define DPLL_IOB               (1 << 13)
+#define DPLL_PLL_ENABLE                (1 << 4)
+#define DPLL_LOCK              (1 << 0)
+
+/* ULPD_APLL_CTRL */
+#define APLL_NDPLL_SWITCH      (1 << 0)
+
+static void __init omap_1510_usb_init(struct omap_usb_config *config)
+{
+       unsigned int val;
+       u16 w;
+
+       config->usb0_init(config->pins[0], is_usb0_device(config));
+       config->usb1_init(config->pins[1]);
+       config->usb2_init(config->pins[2], 0);
+
+       val = omap_readl(MOD_CONF_CTRL_0) & ~(0x3f << 1);
+       val |= (config->hmc_mode << 1);
+       omap_writel(val, MOD_CONF_CTRL_0);
+
+       printk("USB: hmc %d", config->hmc_mode);
+       if (config->pins[0])
+               printk(", usb0 %d wires%s", config->pins[0],
+                       is_usb0_device(config) ? " (dev)" : "");
+       if (config->pins[1])
+               printk(", usb1 %d wires", config->pins[1]);
+       if (config->pins[2])
+               printk(", usb2 %d wires", config->pins[2]);
+       printk("\n");
+
+       /* use DPLL for 48 MHz function clock */
+       pr_debug("APLL %04x DPLL %04x REQ %04x\n", omap_readw(ULPD_APLL_CTRL),
+                       omap_readw(ULPD_DPLL_CTRL), omap_readw(ULPD_SOFT_REQ));
+
+       w = omap_readw(ULPD_APLL_CTRL);
+       w &= ~APLL_NDPLL_SWITCH;
+       omap_writew(w, ULPD_APLL_CTRL);
+
+       w = omap_readw(ULPD_DPLL_CTRL);
+       w |= DPLL_IOB | DPLL_PLL_ENABLE;
+       omap_writew(w, ULPD_DPLL_CTRL);
+
+       w = omap_readw(ULPD_SOFT_REQ);
+       w |= SOFT_UDC_REQ | SOFT_DPLL_REQ;
+       omap_writew(w, ULPD_SOFT_REQ);
+
+       while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK))
+               cpu_relax();
+
+#ifdef CONFIG_USB_GADGET_OMAP
+       if (config->register_dev) {
+               int status;
+
+               udc_device.dev.platform_data = config;
+               status = platform_device_register(&udc_device);
+               if (status)
+                       pr_debug("can't register UDC device, %d\n", status);
+               /* udc driver gates 48MHz by D+ pullup */
+       }
+#endif
+
+#if    defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+       if (config->register_host) {
+               int status;
+
+               ohci_device.dev.platform_data = config;
+               status = platform_device_register(&ohci_device);
+               if (status)
+                       pr_debug("can't register OHCI device, %d\n", status);
+               /* hcd explicitly gates 48MHz */
+       }
+#endif
+}
+
+#else
+static inline void omap_1510_usb_init(struct omap_usb_config *config) {}
+#endif
+
+void __init omap1_usb_init(struct omap_usb_config *pdata)
+{
+       pdata->usb0_init = omap1_usb0_init;
+       pdata->usb1_init = omap1_usb1_init;
+       pdata->usb2_init = omap1_usb2_init;
+       udc_device_init(pdata);
+       ohci_device_init(pdata);
+       otg_device_init(pdata);
+
+       if (cpu_is_omap7xx() || cpu_is_omap16xx())
+               omap_otg_init(pdata);
+       else if (cpu_is_omap15xx())
+               omap_1510_usb_init(pdata);
+       else
+               printk(KERN_ERR "USB: No init for your chip yet\n");
+}

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index b31b6f1231227dd66b38b691a8b63c4e775963c9..b48bacf0a7aa96c9b6892c80efb94183019efe53 100644 (file)
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -1,22 +1,77 @@
+if ARCH_OMAP2PLUS
+
+menu "TI OMAP2/3/4 Specific Features"
+
+config ARCH_OMAP2PLUS_TYPICAL
+       bool "Typical OMAP configuration"
+       default y
+       select AEABI
+       select REGULATOR
+       select PM
+       select PM_RUNTIME
+       select VFP
+       select NEON if ARCH_OMAP3 || ARCH_OMAP4
+       select SERIAL_8250
+       select SERIAL_CORE_CONSOLE
+       select SERIAL_8250_CONSOLE
+       select I2C
+       select I2C_OMAP
+       select MFD
+       select MENELAUS if ARCH_OMAP2
+       select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
+       select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
+       help
+         Compile a kernel suitable for booting most boards
+
+config ARCH_OMAP2
+       bool "TI OMAP2"
+       depends on ARCH_OMAP2PLUS
+       default y
+       select CPU_V6
+
+config ARCH_OMAP3
+       bool "TI OMAP3"
+       depends on ARCH_OMAP2PLUS
+       default y
+       select CPU_V7
+       select USB_ARCH_HAS_EHCI
+       select ARM_L1_CACHE_SHIFT_6
+
+config ARCH_OMAP4
+       bool "TI OMAP4"
+       default y
+       depends on ARCH_OMAP2PLUS
+       select CPU_V7
+       select ARM_GIC
+
 comment "OMAP Core Type"
        depends on ARCH_OMAP2
 
 config ARCH_OMAP2420
        bool "OMAP2420 support"
        depends on ARCH_OMAP2
+       default y
        select OMAP_DM_TIMER
        select ARCH_OMAP_OTG
 
 config ARCH_OMAP2430
        bool "OMAP2430 support"
        depends on ARCH_OMAP2
+       default y
        select ARCH_OMAP_OTG
 
 config ARCH_OMAP3430
        bool "OMAP3430 support"
        depends on ARCH_OMAP3
+       default y
        select ARCH_OMAP_OTG
 
+config OMAP_PACKAGE_ZAF
+       bool
+
+config OMAP_PACKAGE_ZAC
+       bool
+
 config OMAP_PACKAGE_CBC
        bool
 
@@ -35,6 +90,7 @@ comment "OMAP Board Type"
 config MACH_OMAP_GENERIC
        bool "Generic OMAP board"
        depends on ARCH_OMAP2
+       default y
 
 config MACH_OMAP2_TUSB6010
        bool
@@ -44,60 +100,75 @@ config MACH_OMAP2_TUSB6010
 config MACH_OMAP_H4
        bool "OMAP 2420 H4 board"
        depends on ARCH_OMAP2
+       default y
+       select OMAP_PACKAGE_ZAF
        select OMAP_DEBUG_DEVICES
 
 config MACH_OMAP_APOLLON
        bool "OMAP 2420 Apollon board"
        depends on ARCH_OMAP2
+       default y
+       select OMAP_PACKAGE_ZAC
 
 config MACH_OMAP_2430SDP
        bool "OMAP 2430 SDP board"
        depends on ARCH_OMAP2
+       default y
+       select OMAP_PACKAGE_ZAC
 
 config MACH_OMAP3_BEAGLE
        bool "OMAP3 BEAGLE board"
        depends on ARCH_OMAP3
+       default y
        select OMAP_PACKAGE_CBB
 
 config MACH_DEVKIT8000
        bool "DEVKIT8000 board"
        depends on ARCH_OMAP3
+       default y
        select OMAP_PACKAGE_CUS
        select OMAP_MUX
 
 config MACH_OMAP_LDP
        bool "OMAP3 LDP board"
        depends on ARCH_OMAP3
+       default y
        select OMAP_PACKAGE_CBB
 
 config MACH_OVERO
        bool "Gumstix Overo board"
        depends on ARCH_OMAP3
+       default y
        select OMAP_PACKAGE_CBB
 
 config MACH_OMAP3EVM
        bool "OMAP 3530 EVM board"
        depends on ARCH_OMAP3
+       default y
        select OMAP_PACKAGE_CBB
 
 config MACH_OMAP3517EVM
        bool "OMAP3517/ AM3517 EVM board"
        depends on ARCH_OMAP3
+       default y
        select OMAP_PACKAGE_CBB
 
 config MACH_OMAP3_PANDORA
        bool "OMAP3 Pandora"
        depends on ARCH_OMAP3
+       default y
        select OMAP_PACKAGE_CBB
 
 config MACH_OMAP3_TOUCHBOOK
        bool "OMAP3 Touch Book"
        depends on ARCH_OMAP3
+       default y
        select BACKLIGHT_CLASS_DEVICE
 
 config MACH_OMAP_3430SDP
        bool "OMAP 3430 SDP board"
        depends on ARCH_OMAP3
+       default y
        select OMAP_PACKAGE_CBB
 
 config MACH_NOKIA_N800
@@ -112,6 +183,8 @@ config MACH_NOKIA_N810_WIMAX
 config MACH_NOKIA_N8X0
        bool "Nokia N800/N810"
        depends on ARCH_OMAP2420
+       default y
+       select OMAP_PACKAGE_ZAC
        select MACH_NOKIA_N800
        select MACH_NOKIA_N810
        select MACH_NOKIA_N810_WIMAX
@@ -119,42 +192,55 @@ config MACH_NOKIA_N8X0
 config MACH_NOKIA_RX51
        bool "Nokia RX-51 board"
        depends on ARCH_OMAP3
+       default y
        select OMAP_PACKAGE_CBB
 
 config MACH_OMAP_ZOOM2
        bool "OMAP3 Zoom2 board"
        depends on ARCH_OMAP3
+       default y
        select OMAP_PACKAGE_CBB
 
 config MACH_OMAP_ZOOM3
        bool "OMAP3630 Zoom3 board"
        depends on ARCH_OMAP3
+       default y
        select OMAP_PACKAGE_CBP
 
 config MACH_CM_T35
        bool "CompuLab CM-T35 module"
        depends on ARCH_OMAP3
+       default y
        select OMAP_PACKAGE_CUS
        select OMAP_MUX
 
 config MACH_IGEP0020
        bool "IGEP v2 board"
        depends on ARCH_OMAP3
+       default y
        select OMAP_PACKAGE_CBB
 
 config MACH_SBC3530
        bool "OMAP3 SBC STALKER board"
        depends on ARCH_OMAP3
+       default y
        select OMAP_PACKAGE_CUS
        select OMAP_MUX
 
 config MACH_OMAP_3630SDP
        bool "OMAP3630 SDP board"
        depends on ARCH_OMAP3
+       default y
        select OMAP_PACKAGE_CBP
 
 config MACH_OMAP_4430SDP
        bool "OMAP 4430 SDP board"
+       default y
+       depends on ARCH_OMAP4
+
+config MACH_OMAP4_PANDA
+       bool "OMAP4 Panda Board"
+       default y
        depends on ARCH_OMAP4
 
 config OMAP3_EMU
@@ -176,3 +262,6 @@ config OMAP3_SDRC_AC_TIMING
          wish to say no.  Selecting yes without understanding what is
          going on could result in system crashes;
 
+endmenu
+
+endif

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index ea52b034e9635708b93f869a81b2c40a1f9dd644..63b2d8859c3c291af8e8af729f63d8302ad4915e 100644 (file)
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,7 +3,7 @@
 #
 
 # Common support
-obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o
+obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o
 
 omap-2-3-common                                = irq.o sdrc.o
 hwmod-common                           = omap_hwmod.o \
@@ -15,13 +15,14 @@ clock-common                                = clock.o clock_common_data.o \
 
 obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(hwmod-common)
 obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(hwmod-common)
-obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common)
+obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) $(hwmod-common)
 
 obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
 
 # SMP support ONLY available for OMAP4
 obj-$(CONFIG_SMP)                      += omap-smp.o omap-headsmp.o
 obj-$(CONFIG_LOCAL_TIMERS)             += timer-mpu.o
+obj-$(CONFIG_HOTPLUG_CPU)              += omap-hotplug.o
 obj-$(CONFIG_ARCH_OMAP4)               += omap44xx-smc.o omap4-common.o
 
 AFLAGS_omap44xx-smc.o                  :=-Wa,-march=armv7-a
@@ -36,6 +37,8 @@ AFLAGS_sram243x.o                     :=-Wa,-march=armv6
 AFLAGS_sram34xx.o                      :=-Wa,-march=armv7-a
 
 # Pin multiplexing
+obj-$(CONFIG_ARCH_OMAP2420)            += mux2420.o
+obj-$(CONFIG_ARCH_OMAP2430)            += mux2430.o
 obj-$(CONFIG_ARCH_OMAP3)               += mux34xx.o
 
 # SMS/SDRC
@@ -47,6 +50,7 @@ ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_ARCH_OMAP2)               += pm24xx.o
 obj-$(CONFIG_ARCH_OMAP2)               += sleep24xx.o
 obj-$(CONFIG_ARCH_OMAP3)               += pm34xx.o sleep34xx.o cpuidle34xx.o
+obj-$(CONFIG_ARCH_OMAP4)               += pm44xx.o
 obj-$(CONFIG_PM_DEBUG)                 += pm-debug.o
 
 AFLAGS_sleep24xx.o                     :=-Wa,-march=armv6
@@ -89,7 +93,10 @@ obj-$(CONFIG_OMAP3_EMU)                      += emu.o
 obj-$(CONFIG_OMAP_MBOX_FWK)            += mailbox_mach.o
 mailbox_mach-objs                      := mailbox.o
 
-obj-$(CONFIG_OMAP_IOMMU)               := iommu2.o omap-iommu.o
+obj-$(CONFIG_OMAP_IOMMU)               += iommu2.o
+
+iommu-$(CONFIG_OMAP_IOMMU)             := omap-iommu.o
+obj-y                                  += $(iommu-m) $(iommu-y)
 
 i2c-omap-$(CONFIG_I2C_OMAP)            := i2c.o
 obj-y                                  += $(i2c-omap-m) $(i2c-omap-y)
@@ -105,6 +112,7 @@ obj-$(CONFIG_MACH_OMAP3_BEAGLE)             += board-omap3beagle.o \
 obj-$(CONFIG_MACH_DEVKIT8000)          += board-devkit8000.o \
                                            hsmmc.o
 obj-$(CONFIG_MACH_OMAP_LDP)            += board-ldp.o \
+                                          board-flash.o \
                                           hsmmc.o
 obj-$(CONFIG_MACH_OVERO)               += board-overo.o \
                                           hsmmc.o
@@ -114,7 +122,7 @@ obj-$(CONFIG_MACH_OMAP3_PANDORA)    += board-omap3pandora.o \
                                           hsmmc.o
 obj-$(CONFIG_MACH_OMAP_3430SDP)                += board-3430sdp.o \
                                           hsmmc.o \
-                                          board-sdp-flash.o
+                                          board-flash.o
 obj-$(CONFIG_MACH_NOKIA_N8X0)          += board-n8x0.o
 obj-$(CONFIG_MACH_NOKIA_RX51)          += board-rx51.o \
                                           board-rx51-sdram.o \
@@ -123,14 +131,17 @@ obj-$(CONFIG_MACH_NOKIA_RX51)             += board-rx51.o \
                                           hsmmc.o
 obj-$(CONFIG_MACH_OMAP_ZOOM2)          += board-zoom2.o \
                                           board-zoom-peripherals.o \
+                                          board-flash.o \
                                           hsmmc.o \
                                           board-zoom-debugboard.o
 obj-$(CONFIG_MACH_OMAP_ZOOM3)          += board-zoom3.o \
                                           board-zoom-peripherals.o \
+                                          board-flash.o \
                                           hsmmc.o \
                                           board-zoom-debugboard.o
 obj-$(CONFIG_MACH_OMAP_3630SDP)                += board-3630sdp.o \
                                           board-zoom-peripherals.o \
+                                          board-flash.o \
                                           hsmmc.o
 obj-$(CONFIG_MACH_CM_T35)              += board-cm-t35.o \
                                           hsmmc.o
@@ -140,12 +151,16 @@ obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK)        += board-omap3touchbook.o \
                                           hsmmc.o
 obj-$(CONFIG_MACH_OMAP_4430SDP)                += board-4430sdp.o \
                                           hsmmc.o
+obj-$(CONFIG_MACH_OMAP4_PANDA)         += board-omap4panda.o \
+                                          hsmmc.o
 
 obj-$(CONFIG_MACH_OMAP3517EVM)         += board-am3517evm.o
 
 obj-$(CONFIG_MACH_SBC3530)             += board-omap3stalker.o \
                                           hsmmc.o
 # Platform specific device init code
+usbfs-$(CONFIG_ARCH_OMAP_OTG)          := usb-fs.o
+obj-y                                  += $(usbfs-m) $(usbfs-y)
 obj-y                                  += usb-musb.o
 obj-$(CONFIG_MACH_OMAP2_TUSB6010)      += usb-tusb6010.o
 obj-y                                  += usb-ehci.o

diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index a11a575745e44c5bcab1d1fd7cc202afeedd06ea..8538e4131d27670de9b7f0c4a2a32c075f6cf27b 100644 (file)
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -31,13 +31,13 @@
 #include <asm/mach/map.h>
 
 #include <mach/gpio.h>
-#include <plat/mux.h>
 #include <plat/board.h>
 #include <plat/common.h>
 #include <plat/gpmc.h>
 #include <plat/usb.h>
 #include <plat/gpmc-smc91x.h>
 
+#include "mux.h"
 #include "hsmmc.h"
 
 #define SDP2430_CS0_BASE       0x04000000
@@ -122,11 +122,7 @@ static struct omap_smc91x_platform_data board_smc91x_data = {
 
 static void __init board_smc91x_init(void)
 {
-       if (omap_rev() > OMAP3430_REV_ES1_0)
-               board_smc91x_data.gpio_irq = 6;
-       else
-               board_smc91x_data.gpio_irq = 29;
-
+       omap_mux_init_gpio(149, OMAP_PIN_INPUT);
        gpmc_smc91x_init(&board_smc91x_data);
 }
 
@@ -217,17 +213,30 @@ static struct omap_usb_config sdp2430_usb_config __initdata = {
        .pins[0]        = 3,
 };
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+       { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux      NULL
+#endif
+
 static void __init omap_2430sdp_init(void)
 {
        int ret;
 
+       omap2430_mux_init(board_mux, OMAP_PACKAGE_ZAC);
+
        omap2430_i2c_init();
 
        platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));
        omap_serial_init();
        omap2_hsmmc_init(mmc);
-       omap_usb_init(&sdp2430_usb_config);
+       omap2_usbfs_init(&sdp2430_usb_config);
+
+       omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP);
        usb_musb_init(&musb_board_data);
+
        board_smc91x_init();
 
        /* Turn off secondary LCD backlight */
@@ -248,6 +257,7 @@ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
        .boot_params    = 0x80000100,
        .map_io         = omap_2430sdp_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = omap_2430sdp_init_irq,
        .init_machine   = omap_2430sdp_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index f474a80b886733582af7f3dba04929ce02cd561b..67b95b5f1a2f62d8270a92a5a5cf1d7bcee57b0e 100644 (file)
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -41,7 +41,7 @@
 #include <plat/control.h>
 #include <plat/gpmc-smc91x.h>
 
-#include <mach/board-sdp.h>
+#include <mach/board-flash.h>
 
 #include "mux.h"
 #include "sdram-qimonda-hyb18m512160af-6.h"
@@ -667,6 +667,18 @@ static struct omap_board_mux board_mux[] __initdata = {
 #define board_mux      NULL
 #endif
 
+/*
+ * SDP3430 V2 Board CS organization
+ * Different from SDP3430 V1. Now 4 switches used to specify CS
+ *
+ * See also the Switch S8 settings in the comments.
+ */
+static char chip_sel_3430[][GPMC_CS_NUM] = {
+       {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */
+       {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */
+       {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */
+};
+
 static struct mtd_partition sdp_nor_partitions[] = {
        /* bootloader (U-Boot, etc) in first sector */
        {
@@ -797,24 +809,19 @@ static void __init omap_3430sdp_init(void)
        omap_serial_init();
        usb_musb_init(&musb_board_data);
        board_smc91x_init();
-       sdp_flash_init(sdp_flash_partitions);
+       board_flash_init(sdp_flash_partitions, chip_sel_3430);
        sdp3430_display_init();
        enable_board_wakeup_source();
        usb_ehci_init(&ehci_pdata);
 }
 
-static void __init omap_3430sdp_map_io(void)
-{
-       omap2_set_globals_343x();
-       omap34xx_map_common_io();
-}
-
 MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
        /* Maintainer: Syed Khasim - Texas Instruments Inc */
        .phys_io        = 0x48000000,
        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
        .boot_params    = 0x80000100,
-       .map_io         = omap_3430sdp_map_io,
+       .map_io         = omap3_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = omap_3430sdp_init_irq,
        .init_machine   = omap_3430sdp_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index 504d2bd222fe35ec02bb277f5f87d6af6f18e5e8..b359c3f7bb399b9608ddc315226f263ae76d8ec0 100644 (file)
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -18,10 +18,10 @@
 #include <plat/common.h>
 #include <plat/board.h>
 #include <plat/gpmc-smc91x.h>
-#include <plat/mux.h>
 #include <plat/usb.h>
 
 #include <mach/board-zoom.h>
+#include <mach/board-flash.h>
 
 #include "mux.h"
 #include "sdram-hynix-h8mbx00u0mer-0em.h"
@@ -66,12 +66,6 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
        .reset_gpio_port[2]  = -EINVAL
 };
 
-static void __init omap_sdp_map_io(void)
-{
-       omap2_set_globals_36xx();
-       omap34xx_map_common_io();
-}
-
 static struct omap_board_config_kernel sdp_config[] __initdata = {
 };
 
@@ -93,12 +87,131 @@ static struct omap_board_mux board_mux[] __initdata = {
 #define board_mux      NULL
 #endif
 
+/*
+ * SDP3630 CS organization
+ * See also the Switch S8 settings in the comments.
+ */
+static char chip_sel_sdp[][GPMC_CS_NUM] = {
+       {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */
+       {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */
+       {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */
+};
+
+static struct mtd_partition sdp_nor_partitions[] = {
+       /* bootloader (U-Boot, etc) in first sector */
+       {
+               .name           = "Bootloader-NOR",
+               .offset         = 0,
+               .size           = SZ_256K,
+               .mask_flags     = MTD_WRITEABLE, /* force read-only */
+       },
+       /* bootloader params in the next sector */
+       {
+               .name           = "Params-NOR",
+               .offset         = MTDPART_OFS_APPEND,
+               .size           = SZ_256K,
+               .mask_flags     = 0,
+       },
+       /* kernel */
+       {
+               .name           = "Kernel-NOR",
+               .offset         = MTDPART_OFS_APPEND,
+               .size           = SZ_2M,
+               .mask_flags     = 0
+       },
+       /* file system */
+       {
+               .name           = "Filesystem-NOR",
+               .offset         = MTDPART_OFS_APPEND,
+               .size           = MTDPART_SIZ_FULL,
+               .mask_flags     = 0
+       }
+};
+
+static struct mtd_partition sdp_onenand_partitions[] = {
+       {
+               .name           = "X-Loader-OneNAND",
+               .offset         = 0,
+               .size           = 4 * (64 * 2048),
+               .mask_flags     = MTD_WRITEABLE  /* force read-only */
+       },
+       {
+               .name           = "U-Boot-OneNAND",
+               .offset         = MTDPART_OFS_APPEND,
+               .size           = 2 * (64 * 2048),
+               .mask_flags     = MTD_WRITEABLE  /* force read-only */
+       },
+       {
+               .name           = "U-Boot Environment-OneNAND",
+               .offset         = MTDPART_OFS_APPEND,
+               .size           = 1 * (64 * 2048),
+       },
+       {
+               .name           = "Kernel-OneNAND",
+               .offset         = MTDPART_OFS_APPEND,
+               .size           = 16 * (64 * 2048),
+       },
+       {
+               .name           = "File System-OneNAND",
+               .offset         = MTDPART_OFS_APPEND,
+               .size           = MTDPART_SIZ_FULL,
+       },
+};
+
+static struct mtd_partition sdp_nand_partitions[] = {
+       /* All the partition sizes are listed in terms of NAND block size */
+       {
+               .name           = "X-Loader-NAND",
+               .offset         = 0,
+               .size           = 4 * (64 * 2048),
+               .mask_flags     = MTD_WRITEABLE,        /* force read-only */
+       },
+       {
+               .name           = "U-Boot-NAND",
+               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x80000 */
+               .size           = 10 * (64 * 2048),
+               .mask_flags     = MTD_WRITEABLE,        /* force read-only */
+       },
+       {
+               .name           = "Boot Env-NAND",
+
+               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x1c0000 */
+               .size           = 6 * (64 * 2048),
+       },
+       {
+               .name           = "Kernel-NAND",
+               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x280000 */
+               .size           = 40 * (64 * 2048),
+       },
+       {
+               .name           = "File System - NAND",
+               .size           = MTDPART_SIZ_FULL,
+               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x780000 */
+       },
+};
+
+static struct flash_partitions sdp_flash_partitions[] = {
+       {
+               .parts = sdp_nor_partitions,
+               .nr_parts = ARRAY_SIZE(sdp_nor_partitions),
+       },
+       {
+               .parts = sdp_onenand_partitions,
+               .nr_parts = ARRAY_SIZE(sdp_onenand_partitions),
+       },
+       {
+               .parts = sdp_nand_partitions,
+               .nr_parts = ARRAY_SIZE(sdp_nand_partitions),
+       },
+};
+
 static void __init omap_sdp_init(void)
 {
        omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
        omap_serial_init();
        zoom_peripherals_init();
        board_smc91x_init();
+       board_flash_init(sdp_flash_partitions, chip_sel_sdp);
        enable_board_wakeup_source();
        usb_ehci_init(&ehci_pdata);
 }
@@ -107,7 +220,8 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
        .phys_io        = 0x48000000,
        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
        .boot_params    = 0x80000100,
-       .map_io         = omap_sdp_map_io,
+       .map_io         = omap3_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = omap_sdp_init_irq,
        .init_machine   = omap_sdp_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index e4a5d66b83b8bbb5e8f1701bbba5a94f825b9703..9447644774c234435667a548e409bb0b4df76163 100644 (file)
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -21,6 +21,7 @@
 #include <linux/spi/spi.h>
 #include <linux/i2c/twl.h>
 #include <linux/regulator/machine.h>
+#include <linux/leds.h>
 
 #include <mach/hardware.h>
 #include <mach/omap4-common.h>
@@ -40,6 +41,54 @@
 #define ETH_KS8851_POWER_ON            48
 #define ETH_KS8851_QUART               138
 
+static struct gpio_led sdp4430_gpio_leds[] = {
+       {
+               .name   = "omap4:green:debug0",
+               .gpio   = 61,
+       },
+       {
+               .name   = "omap4:green:debug1",
+               .gpio   = 30,
+       },
+       {
+               .name   = "omap4:green:debug2",
+               .gpio   = 7,
+       },
+       {
+               .name   = "omap4:green:debug3",
+               .gpio   = 8,
+       },
+       {
+               .name   = "omap4:green:debug4",
+               .gpio   = 50,
+       },
+       {
+               .name   = "omap4:blue:user",
+               .gpio   = 169,
+       },
+       {
+               .name   = "omap4:red:user",
+               .gpio   = 170,
+       },
+       {
+               .name   = "omap4:green:user",
+               .gpio   = 139,
+       },
+
+};
+
+static struct gpio_led_platform_data sdp4430_led_data = {
+       .leds   = sdp4430_gpio_leds,
+       .num_leds       = ARRAY_SIZE(sdp4430_gpio_leds),
+};
+
+static struct platform_device sdp4430_leds_gpio = {
+       .name   = "leds-gpio",
+       .id     = -1,
+       .dev    = {
+               .platform_data = &sdp4430_led_data,
+       },
+};
 static struct spi_board_info sdp4430_spi_board_info[] __initdata = {
        {
                .modalias               = "ks8851",
@@ -112,6 +161,7 @@ static struct platform_device sdp4430_lcd_device = {
 
 static struct platform_device *sdp4430_devices[] __initdata = {
        &sdp4430_lcd_device,
+       &sdp4430_leds_gpio,
 };
 
 static struct omap_lcd_config sdp4430_lcd_config __initdata = {
@@ -156,14 +206,16 @@ static struct omap2_hsmmc_info mmc[] = {
        {}      /* Terminator */
 };
 
-static struct regulator_consumer_supply sdp4430_vmmc_supply[] = {
+static struct regulator_consumer_supply sdp4430_vaux_supply[] = {
        {
                .supply = "vmmc",
-               .dev_name = "mmci-omap-hs.0",
+               .dev_name = "mmci-omap-hs.1",
        },
+};
+static struct regulator_consumer_supply sdp4430_vmmc_supply[] = {
        {
                .supply = "vmmc",
-               .dev_name = "mmci-omap-hs.1",
+               .dev_name = "mmci-omap-hs.0",
        },
 };
 
@@ -210,6 +262,8 @@ static struct regulator_init_data sdp4430_vaux1 = {
                                        | REGULATOR_CHANGE_MODE
                                        | REGULATOR_CHANGE_STATUS,
        },
+       .num_consumer_supplies  = 1,
+       .consumer_supplies      = sdp4430_vaux_supply,
 };
 
 static struct regulator_init_data sdp4430_vaux2 = {
@@ -250,7 +304,7 @@ static struct regulator_init_data sdp4430_vmmc = {
                                        | REGULATOR_CHANGE_MODE
                                        | REGULATOR_CHANGE_STATUS,
        },
-       .num_consumer_supplies  = 2,
+       .num_consumer_supplies  = 1,
        .consumer_supplies      = sdp4430_vmmc_supply,
 };
 
@@ -353,6 +407,11 @@ static struct i2c_board_info __initdata sdp4430_i2c_boardinfo[] = {
                .platform_data = &sdp4430_twldata,
        },
 };
+static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = {
+       {
+               I2C_BOARD_INFO("tmp105", 0x48),
+       },
+};
 static int __init omap4_i2c_init(void)
 {
        /*
@@ -362,7 +421,8 @@ static int __init omap4_i2c_init(void)
        omap_register_i2c_bus(1, 400, sdp4430_i2c_boardinfo,
                        ARRAY_SIZE(sdp4430_i2c_boardinfo));
        omap_register_i2c_bus(2, 400, NULL, 0);
-       omap_register_i2c_bus(3, 400, NULL, 0);
+       omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
+                               ARRAY_SIZE(sdp4430_i2c_3_boardinfo));
        omap_register_i2c_bus(4, 400, NULL, 0);
        return 0;
 }
@@ -402,6 +462,7 @@ MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
        .boot_params    = 0x80000100,
        .map_io         = omap_4430sdp_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = omap_4430sdp_init_irq,
        .init_machine   = omap_4430sdp_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index af383a8769432fd108bc48efedf5e893e93f60fe..4d0f58592864972429c0a19fb3d5e2ff9ecc0d27 100644 (file)
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -461,17 +461,12 @@ static void __init am3517_evm_init(void)
        am3517_evm_ethernet_init(&am3517_evm_emac_pdata);
 }
 
-static void __init am3517_evm_map_io(void)
-{
-       omap2_set_globals_343x();
-       omap34xx_map_common_io();
-}
-
 MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
        .phys_io        = 0x48000000,
        .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
        .boot_params    = 0x80000100,
-       .map_io         = am3517_evm_map_io,
+       .map_io         = omap3_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = am3517_evm_init_irq,
        .init_machine   = am3517_evm_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index aa69fb999748af3698a6950f9549a59c8260f5a7..c6421a72514a2a4e776aab63a2e1107434c3ffc2 100644 (file)
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -35,13 +35,14 @@
 
 #include <mach/gpio.h>
 #include <plat/led.h>
-#include <plat/mux.h>
 #include <plat/usb.h>
 #include <plat/board.h>
 #include <plat/common.h>
 #include <plat/gpmc.h>
 #include <plat/control.h>
 
+#include "mux.h"
+
 /* LED & Switch macros */
 #define LED0_GPIO13            13
 #define LED1_GPIO14            14
@@ -244,7 +245,7 @@ static inline void __init apollon_init_smc91x(void)
        apollon_smc91x_resources[0].end   = base + 0x30f;
        udelay(100);
 
-       omap_cfg_reg(W4__24XX_GPIO74);
+       omap_mux_init_gpio(74, 0);
        if (gpio_request(APOLLON_ETHR_GPIO_IRQ, "SMC91x irq") < 0) {
                printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
                        APOLLON_ETHR_GPIO_IRQ);
@@ -286,15 +287,15 @@ static void __init omap_apollon_init_irq(void)
 static void __init apollon_led_init(void)
 {
        /* LED0 - AA10 */
-       omap_cfg_reg(AA10_242X_GPIO13);
+       omap_mux_init_signal("vlynq_clk.gpio_13", 0);
        gpio_request(LED0_GPIO13, "LED0");
        gpio_direction_output(LED0_GPIO13, 0);
        /* LED1  - AA6 */
-       omap_cfg_reg(AA6_242X_GPIO14);
+       omap_mux_init_signal("vlynq_rx1.gpio_14", 0);
        gpio_request(LED1_GPIO14, "LED1");
        gpio_direction_output(LED1_GPIO14, 0);
        /* LED2  - AA4 */
-       omap_cfg_reg(AA4_242X_GPIO15);
+       omap_mux_init_signal("vlynq_rx0.gpio_15", 0);
        gpio_request(LED2_GPIO15, "LED2");
        gpio_direction_output(LED2_GPIO15, 0);
 }
@@ -303,22 +304,35 @@ static void __init apollon_usb_init(void)
 {
        /* USB device */
        /* DEVICE_SUSPEND */
-       omap_cfg_reg(P21_242X_GPIO12);
+       omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0);
        gpio_request(12, "USB suspend");
        gpio_direction_output(12, 0);
-       omap_usb_init(&apollon_usb_config);
+       omap2_usbfs_init(&apollon_usb_config);
 }
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+       { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux      NULL
+#endif
+
 static void __init omap_apollon_init(void)
 {
        u32 v;
 
+       omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC);
+
        apollon_led_init();
        apollon_flash_init();
        apollon_usb_init();
 
        /* REVISIT: where's the correct place */
-       omap_cfg_reg(W19_24XX_SYS_NIRQ);
+       omap_mux_init_signal("sys_nirq", OMAP_PULL_ENA | OMAP_PULL_UP);
+
+       /* LCD PWR_EN */
+       omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP);
 
        /* Use Interal loop-back in MMC/SDIO Module Input Clock selection */
        v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
@@ -346,6 +360,7 @@ MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
        .boot_params    = 0x80000100,
        .map_io         = omap_apollon_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = omap_apollon_init_irq,
        .init_machine   = omap_apollon_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index e679a2cc86c3061031923123c21e4189bf028e8a..e10bc109415c4d3793b89b3e6e6ac1580311645a 100644 (file)
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -61,8 +61,6 @@
 #define SB_T35_SMSC911X_GPIO   65
 
 #define NAND_BLOCK_SIZE                SZ_128K
-#define GPMC_CS0_BASE          0x60
-#define GPMC_CS0_BASE_ADDR     (OMAP34XX_GPMC_VIRT + GPMC_CS0_BASE)
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 #include <linux/smsc911x.h>
@@ -223,28 +221,12 @@ static struct omap_nand_platform_data cm_t35_nand_data = {
        .nr_parts               = ARRAY_SIZE(cm_t35_nand_partitions),
        .dma_channel            = -1,   /* disable DMA in OMAP NAND driver */
        .cs                     = 0,
-       .gpmc_cs_baseaddr       = (void __iomem *)GPMC_CS0_BASE_ADDR,
-       .gpmc_baseaddr          = (void __iomem *)OMAP34XX_GPMC_VIRT,
 
 };
 
-static struct resource cm_t35_nand_resource = {
-       .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device cm_t35_nand_device = {
-       .name           = "omap2-nand",
-       .id             = -1,
-       .num_resources  = 1,
-       .resource       = &cm_t35_nand_resource,
-       .dev            = {
-               .platform_data  = &cm_t35_nand_data,
-       },
-};
-
 static void __init cm_t35_init_nand(void)
 {
-       if (platform_device_register(&cm_t35_nand_device) < 0)
+       if (gpmc_nand_init(&cm_t35_nand_data) < 0)
                pr_err("CM-T35: Unable to register NAND device\n");
 }
 #else
@@ -708,12 +690,6 @@ static void __init cm_t35_init_irq(void)
        omap_gpio_init();
 }
 
-static void __init cm_t35_map_io(void)
-{
-       omap2_set_globals_343x();
-       omap34xx_map_common_io();
-}
-
 static struct omap_board_mux board_mux[] __initdata = {
        /* nCS and IRQ for CM-T35 ethernet */
        OMAP3_MUX(GPMC_NCS5, OMAP_MUX_MODE0),
@@ -836,7 +812,8 @@ MACHINE_START(CM_T35, "Compulab CM-T35")
        .phys_io        = 0x48000000,
        .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
        .boot_params    = 0x80000100,
-       .map_io         = cm_t35_map_io,
+       .map_io         = omap3_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = cm_t35_init_irq,
        .init_machine   = cm_t35_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 77022b58881670fc38bf3c88840a4b925ae0ff03..a07086d6a0b26b6cb7d7fbe7d810ea330bcdae28 100644 (file)
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -33,6 +33,7 @@
 #include <linux/i2c/twl.h>
 
 #include <mach/hardware.h>
+#include <mach/id.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -58,9 +59,6 @@
 #include "mux.h"
 #include "hsmmc.h"
 
-#define GPMC_CS0_BASE  0x60
-#define GPMC_CS_SIZE   0x30
-
 #define NAND_BLOCK_SIZE                SZ_128K
 
 #define OMAP_DM9000_GPIO_IRQ   25
@@ -104,20 +102,6 @@ static struct omap_nand_platform_data devkit8000_nand_data = {
        .dma_channel    = -1,           /* disable DMA in OMAP NAND driver */
 };
 
-static struct resource devkit8000_nand_resource = {
-       .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device devkit8000_nand_device = {
-       .name           = "omap2-nand",
-       .id             = -1,
-       .dev            = {
-               .platform_data  = &devkit8000_nand_data,
-       },
-       .num_resources  = 1,
-       .resource       = &devkit8000_nand_resource,
-};
-
 static struct omap2_hsmmc_info mmc[] = {
        {
                .mmc            = 1,
@@ -126,54 +110,50 @@ static struct omap2_hsmmc_info mmc[] = {
        },
        {}      /* Terminator */
 };
-static struct omap_board_config_kernel devkit8000_config[] __initdata = {
-};
 
 static int devkit8000_panel_enable_lcd(struct omap_dss_device *dssdev)
 {
        twl_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80, REG_GPIODATADIR1);
        twl_i2c_write_u8(TWL4030_MODULE_LED, 0x0, 0x0);
 
+       if (gpio_is_valid(dssdev->reset_gpio))
+               gpio_set_value(dssdev->reset_gpio, 1);
        return 0;
 }
 
 static void devkit8000_panel_disable_lcd(struct omap_dss_device *dssdev)
 {
+       if (gpio_is_valid(dssdev->reset_gpio))
+               gpio_set_value(dssdev->reset_gpio, 0);
 }
+
 static int devkit8000_panel_enable_dvi(struct omap_dss_device *dssdev)
 {
+       if (gpio_is_valid(dssdev->reset_gpio))
+               gpio_set_value(dssdev->reset_gpio, 1);
        return 0;
 }
 
 static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev)
 {
+       if (gpio_is_valid(dssdev->reset_gpio))
+               gpio_set_value(dssdev->reset_gpio, 0);
 }
 
-static int devkit8000_panel_enable_tv(struct omap_dss_device *dssdev)
-{
+static struct regulator_consumer_supply devkit8000_vmmc1_supply =
+       REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0");
 
-       return 0;
-}
-
-static void devkit8000_panel_disable_tv(struct omap_dss_device *dssdev)
-{
-}
-
-
-static struct regulator_consumer_supply devkit8000_vmmc1_supply = {
-       .supply                 = "vmmc",
-};
-
-static struct regulator_consumer_supply devkit8000_vsim_supply = {
-       .supply                 = "vmmc_aux",
-};
 
+/* ads7846 on SPI */
+static struct regulator_consumer_supply devkit8000_vio_supply =
+       REGULATOR_SUPPLY("vcc", "spi2.0");
 
 static struct omap_dss_device devkit8000_lcd_device = {
        .name                   = "lcd",
-       .driver_name            = "innolux_at_panel",
+       .driver_name            = "generic_panel",
        .type                   = OMAP_DISPLAY_TYPE_DPI,
        .phy.dpi.data_lines     = 24,
+       .reset_gpio             = -EINVAL, /* will be replaced */
        .platform_enable        = devkit8000_panel_enable_lcd,
        .platform_disable       = devkit8000_panel_disable_lcd,
 };
@@ -182,6 +162,7 @@ static struct omap_dss_device devkit8000_dvi_device = {
        .driver_name            = "generic_panel",
        .type                   = OMAP_DISPLAY_TYPE_DPI,
        .phy.dpi.data_lines     = 24,
+       .reset_gpio             = -EINVAL, /* will be replaced */
        .platform_enable        = devkit8000_panel_enable_dvi,
        .platform_disable       = devkit8000_panel_disable_dvi,
 };
@@ -191,8 +172,6 @@ static struct omap_dss_device devkit8000_tv_device = {
        .driver_name            = "venc",
        .type                   = OMAP_DISPLAY_TYPE_VENC,
        .phy.venc.type          = OMAP_DSS_VENC_TYPE_SVIDEO,
-       .platform_enable        = devkit8000_panel_enable_tv,
-       .platform_disable       = devkit8000_panel_disable_tv,
 };
 
 
@@ -216,10 +195,8 @@ static struct platform_device devkit8000_dss_device = {
        },
 };
 
-static struct regulator_consumer_supply devkit8000_vdda_dac_supply = {
-       .supply = "vdda_dac",
-       .dev    = &devkit8000_dss_device.dev,
-};
+static struct regulator_consumer_supply devkit8000_vdda_dac_supply =
+       REGULATOR_SUPPLY("vdda_dac", "omapdss");
 
 static int board_keymap[] = {
        KEY(0, 0, KEY_1),
@@ -266,7 +243,21 @@ static int devkit8000_twl_gpio_setup(struct device *dev,
 
        /* link regulators to MMC adapters */
        devkit8000_vmmc1_supply.dev = mmc[0].dev;
-       devkit8000_vsim_supply.dev = mmc[0].dev;
+
+       /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
+       gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
+
+        /* gpio + 1 is "LCD_PWREN" (out, active high) */
+       devkit8000_lcd_device.reset_gpio = gpio + 1;
+       gpio_request(devkit8000_lcd_device.reset_gpio, "LCD_PWREN");
+       /* Disable until needed */
+       gpio_direction_output(devkit8000_lcd_device.reset_gpio, 0);
+
+       /* gpio + 7 is "DVI_PD" (out, active low) */
+       devkit8000_dvi_device.reset_gpio = gpio + 7;
+       gpio_request(devkit8000_dvi_device.reset_gpio, "DVI PowerDown");
+       /* Disable until needed */
+       gpio_direction_output(devkit8000_dvi_device.reset_gpio, 0);
 
        return 0;
 }
@@ -282,16 +273,8 @@ static struct twl4030_gpio_platform_data devkit8000_gpio_data = {
        .setup          = devkit8000_twl_gpio_setup,
 };
 
-static struct regulator_consumer_supply devkit8000_vpll2_supplies[] = {
-       {
-       .supply         = "vdvi",
-       .dev            = &devkit8000_lcd_device.dev,
-       },
-       {
-       .supply         = "vdds_dsi",
-       .dev            = &devkit8000_dss_device.dev,
-       }
-};
+static struct regulator_consumer_supply devkit8000_vpll1_supply =
+       REGULATOR_SUPPLY("vdds_dsi", "omapdss");
 
 /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
 static struct regulator_init_data devkit8000_vmmc1 = {
@@ -308,21 +291,6 @@ static struct regulator_init_data devkit8000_vmmc1 = {
        .consumer_supplies      = &devkit8000_vmmc1_supply,
 };
 
-/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
-static struct regulator_init_data devkit8000_vsim = {
-       .constraints = {
-               .min_uV                 = 1800000,
-               .max_uV                 = 3000000,
-               .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                       | REGULATOR_MODE_STANDBY,
-               .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
-                                       | REGULATOR_CHANGE_MODE
-                                       | REGULATOR_CHANGE_STATUS,
-       },
-       .num_consumer_supplies  = 1,
-       .consumer_supplies      = &devkit8000_vsim_supply,
-};
-
 /* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
 static struct regulator_init_data devkit8000_vdac = {
        .constraints = {
@@ -337,10 +305,9 @@ static struct regulator_init_data devkit8000_vdac = {
        .consumer_supplies      = &devkit8000_vdda_dac_supply,
 };
 
-/* VPLL2 for digital video outputs */
-static struct regulator_init_data devkit8000_vpll2 = {
+/* VPLL1 for digital video outputs */
+static struct regulator_init_data devkit8000_vpll1 = {
        .constraints = {
-               .name                   = "VDVI",
                .min_uV                 = 1800000,
                .max_uV                 = 1800000,
                .valid_modes_mask       = REGULATOR_MODE_NORMAL
@@ -348,8 +315,23 @@ static struct regulator_init_data devkit8000_vpll2 = {
                .valid_ops_mask         = REGULATOR_CHANGE_MODE
                                        | REGULATOR_CHANGE_STATUS,
        },
-       .num_consumer_supplies  = ARRAY_SIZE(devkit8000_vpll2_supplies),
-       .consumer_supplies      = devkit8000_vpll2_supplies,
+       .num_consumer_supplies  = 1,
+       .consumer_supplies      = &devkit8000_vpll1_supply,
+};
+
+/* VAUX4 for ads7846 and nubs */
+static struct regulator_init_data devkit8000_vio = {
+       .constraints = {
+               .min_uV                 = 1800000,
+               .max_uV                 = 1800000,
+               .apply_uV               = true,
+               .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                       | REGULATOR_MODE_STANDBY,
+               .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                       | REGULATOR_CHANGE_STATUS,
+       },
+       .num_consumer_supplies  = 1,
+       .consumer_supplies      = &devkit8000_vio_supply,
 };
 
 static struct twl4030_usb_data devkit8000_usb_data = {
@@ -374,15 +356,15 @@ static struct twl4030_platform_data devkit8000_twldata = {
        .gpio           = &devkit8000_gpio_data,
        .codec          = &devkit8000_codec_data,
        .vmmc1          = &devkit8000_vmmc1,
-       .vsim           = &devkit8000_vsim,
        .vdac           = &devkit8000_vdac,
-       .vpll2          = &devkit8000_vpll2,
+       .vpll1          = &devkit8000_vpll1,
+       .vio            = &devkit8000_vio,
        .keypad         = &devkit8000_kp_data,
 };
 
 static struct i2c_board_info __initdata devkit8000_i2c_boardinfo[] = {
        {
-               I2C_BOARD_INFO("twl4030", 0x48),
+               I2C_BOARD_INFO("tps65930", 0x48),
                .flags = I2C_CLIENT_WAKE,
                .irq = INT_34XX_SYS_NIRQ,
                .platform_data = &devkit8000_twldata,
@@ -464,8 +446,6 @@ static struct platform_device keys_gpio = {
 
 static void __init devkit8000_init_irq(void)
 {
-       omap_board_config = devkit8000_config;
-       omap_board_config_size = ARRAY_SIZE(devkit8000_config);
        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
                             mt46h32m32lf6_sdrc_params);
        omap_init_irq();
@@ -560,6 +540,9 @@ static struct platform_device omap_dm9000_dev = {
 
 static void __init omap_dm9000_init(void)
 {
+       unsigned char *eth_addr = omap_dm9000_platdata.dev_addr;
+       struct omap_die_id odi;
+
        if (gpio_request(OMAP_DM9000_GPIO_IRQ, "dm9000 irq") < 0) {
                printk(KERN_ERR "Failed to request GPIO%d for dm9000 IRQ\n",
                        OMAP_DM9000_GPIO_IRQ);
@@ -567,6 +550,16 @@ static void __init omap_dm9000_init(void)
                }
 
        gpio_direction_input(OMAP_DM9000_GPIO_IRQ);
+
+       /* init the mac address using DIE id */
+       omap_get_die_id(&odi);
+
+       eth_addr[0] = 0x02; /* locally administered */
+       eth_addr[1] = odi.id_1 & 0xff;
+       eth_addr[2] = (odi.id_0 & 0xff000000) >> 24;
+       eth_addr[3] = (odi.id_0 & 0x00ff0000) >> 16;
+       eth_addr[4] = (odi.id_0 & 0x0000ff00) >> 8;
+       eth_addr[5] = (odi.id_0 & 0x000000ff);
 }
 
 static struct platform_device *devkit8000_devices[] __initdata = {
@@ -581,8 +574,6 @@ static void __init devkit8000_flash_init(void)
        u8 cs = 0;
        u8 nandcs = GPMC_CS_NUM + 1;
 
-       u32 gpmc_base_add = OMAP34XX_GPMC_VIRT;
-
        /* find out the chip-select on which NAND exists */
        while (cs < GPMC_CS_NUM) {
                u32 ret = 0;
@@ -604,13 +595,9 @@ static void __init devkit8000_flash_init(void)
 
        if (nandcs < GPMC_CS_NUM) {
                devkit8000_nand_data.cs = nandcs;
-               devkit8000_nand_data.gpmc_cs_baseaddr = (void *)
-                       (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE);
-               devkit8000_nand_data.gpmc_baseaddr = (void *)
-                       (gpmc_base_add);
 
                printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
-               if (platform_device_register(&devkit8000_nand_device) < 0)
+               if (gpmc_nand_init(&devkit8000_nand_data) < 0)
                        printk(KERN_ERR "Unable to register NAND device\n");
        }
 }
@@ -797,8 +784,6 @@ static void __init devkit8000_init(void)
        devkit8000_i2c_init();
        platform_add_devices(devkit8000_devices,
                        ARRAY_SIZE(devkit8000_devices));
-       omap_board_config = devkit8000_config;
-       omap_board_config_size = ARRAY_SIZE(devkit8000_config);
 
        spi_register_board_info(devkit8000_spi_board_info,
        ARRAY_SIZE(devkit8000_spi_board_info));
@@ -814,17 +799,12 @@ static void __init devkit8000_init(void)
        omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
 }
 
-static void __init devkit8000_map_io(void)
-{
-       omap2_set_globals_343x();
-       omap34xx_map_common_io();
-}
-
 MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
        .phys_io        = 0x48000000,
        .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
        .boot_params    = 0x80000100,
-       .map_io         = devkit8000_map_io,
+       .map_io         = omap3_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = devkit8000_init_irq,
        .init_machine   = devkit8000_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap2/board-sdp-flash.c b/arch/arm/mach-omap2/board-flash.c
similarity index 66%
rename from arch/arm/mach-omap2/board-sdp-flash.c
rename to arch/arm/mach-omap2/board-flash.c
index 2d026328e3852ec5dff0ad3be63a8f38a9c4b013..ac834aa7abf61f0713957c9f98061e8045a99767 100644 (file)
--- a/arch/arm/mach-omap2/board-sdp-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -21,7 +21,7 @@
 #include <plat/nand.h>
 #include <plat/onenand.h>
 #include <plat/tc.h>
-#include <mach/board-sdp.h>
+#include <mach/board-flash.h>
 
 #define REG_FPGA_REV                   0x10
 #define REG_FPGA_DIP_SWITCH_INPUT2     0x60
@@ -29,72 +29,53 @@
 
 #define DEBUG_BASE             0x08000000 /* debug board */
 
-#define PDC_NOR                1
-#define PDC_NAND       2
-#define PDC_ONENAND    3
-#define DBG_MPDB       4
-
 /* various memory sizes */
 #define FLASH_SIZE_SDPV1       SZ_64M  /* NOR flash (64 Meg aligned) */
 #define FLASH_SIZE_SDPV2       SZ_128M /* NOR flash (256 Meg aligned) */
 
-/*
- * SDP3430 V2 Board CS organization
- * Different from SDP3430 V1. Now 4 switches used to specify CS
- *
- * See also the Switch S8 settings in the comments.
- *
- * REVISIT: Add support for 2430 SDP
- */
-static const unsigned char chip_sel_sdp[][GPMC_CS_NUM] = {
-       {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */
-       {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */
-       {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */
-};
-
-static struct physmap_flash_data sdp_nor_data = {
+static struct physmap_flash_data board_nor_data = {
        .width          = 2,
 };
 
-static struct resource sdp_nor_resource = {
+static struct resource board_nor_resource = {
        .flags          = IORESOURCE_MEM,
 };
 
-static struct platform_device sdp_nor_device = {
+static struct platform_device board_nor_device = {
        .name           = "physmap-flash",
        .id             = 0,
        .dev            = {
-                       .platform_data = &sdp_nor_data,
+                       .platform_data = &board_nor_data,
        },
        .num_resources  = 1,
-       .resource       = &sdp_nor_resource,
+       .resource       = &board_nor_resource,
 };
 
 static void
-__init board_nor_init(struct flash_partitions sdp_nor_parts, u8 cs)
+__init board_nor_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
 {
        int err;
 
-       sdp_nor_data.parts      = sdp_nor_parts.parts;
-       sdp_nor_data.nr_parts   = sdp_nor_parts.nr_parts;
+       board_nor_data.parts    = nor_parts;
+       board_nor_data.nr_parts = nr_parts;
 
        /* Configure start address and size of NOR device */
        if (omap_rev() >= OMAP3430_REV_ES1_0) {
                err = gpmc_cs_request(cs, FLASH_SIZE_SDPV2 - 1,
-                               (unsigned long *)&sdp_nor_resource.start);
-               sdp_nor_resource.end = sdp_nor_resource.start
+                               (unsigned long *)&board_nor_resource.start);
+               board_nor_resource.end = board_nor_resource.start
                                        + FLASH_SIZE_SDPV2 - 1;
        } else {
                err = gpmc_cs_request(cs, FLASH_SIZE_SDPV1 - 1,
-                               (unsigned long *)&sdp_nor_resource.start);
-               sdp_nor_resource.end = sdp_nor_resource.start
+                               (unsigned long *)&board_nor_resource.start);
+               board_nor_resource.end = board_nor_resource.start
                                        + FLASH_SIZE_SDPV1 - 1;
        }
        if (err < 0) {
                printk(KERN_ERR "NOR: Can't request GPMC CS\n");
                return;
        }
-       if (platform_device_register(&sdp_nor_device) < 0)
+       if (platform_device_register(&board_nor_device) < 0)
                printk(KERN_ERR "Unable to register NOR device\n");
 }
 
@@ -105,17 +86,18 @@ static struct omap_onenand_platform_data board_onenand_data = {
 };
 
 static void
-__init board_onenand_init(struct flash_partitions sdp_onenand_parts, u8 cs)
+__init board_onenand_init(struct mtd_partition *onenand_parts,
+                               u8 nr_parts, u8 cs)
 {
        board_onenand_data.cs           = cs;
-       board_onenand_data.parts        = sdp_onenand_parts.parts;
-       board_onenand_data.nr_parts     = sdp_onenand_parts.nr_parts;
+       board_onenand_data.parts        = onenand_parts;
+       board_onenand_data.nr_parts     = nr_parts;
 
        gpmc_onenand_init(&board_onenand_data);
 }
 #else
 static void
-__init board_onenand_init(struct flash_partitions sdp_onenand_parts, u8 cs)
+__init board_onenand_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
 {
 }
 #endif /* CONFIG_MTD_ONENAND_OMAP2 || CONFIG_MTD_ONENAND_OMAP2_MODULE */
@@ -147,7 +129,7 @@ static struct gpmc_timings nand_timings = {
        .wr_data_mux_bus = 0,
 };
 
-static struct omap_nand_platform_data sdp_nand_data = {
+static struct omap_nand_platform_data board_nand_data = {
        .nand_setup     = NULL,
        .gpmc_t         = &nand_timings,
        .dma_channel    = -1,           /* disable DMA in OMAP NAND driver */
@@ -155,23 +137,18 @@ static struct omap_nand_platform_data sdp_nand_data = {
        .devsize        = 0,    /* '0' for 8-bit, '1' for 16-bit device */
 };
 
-static void
-__init board_nand_init(struct flash_partitions sdp_nand_parts, u8 cs)
+void
+__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs)
 {
-       sdp_nand_data.cs                = cs;
-       sdp_nand_data.parts             = sdp_nand_parts.parts;
-       sdp_nand_data.nr_parts          = sdp_nand_parts.nr_parts;
+       board_nand_data.cs              = cs;
+       board_nand_data.parts           = nand_parts;
+       board_nand_data.nr_parts                = nr_parts;
 
-       sdp_nand_data.gpmc_cs_baseaddr  = (void *)(OMAP34XX_GPMC_VIRT +
-                                                       GPMC_CS0_BASE +
-                                                       cs * GPMC_CS_SIZE);
-       sdp_nand_data.gpmc_baseaddr      = (void *) (OMAP34XX_GPMC_VIRT);
-
-       gpmc_nand_init(&sdp_nand_data);
+       gpmc_nand_init(&board_nand_data);
 }
 #else
-static void
-__init board_nand_init(struct flash_partitions sdp_nand_parts, u8 cs)
+void
+__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs)
 {
 }
 #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
@@ -215,7 +192,8 @@ unmap:
  *
  * @return - void.
  */
-void __init sdp_flash_init(struct flash_partitions sdp_partition_info[])
+void board_flash_init(struct flash_partitions partition_info[],
+                                       char chip_sel_board[][GPMC_CS_NUM])
 {
        u8              cs = 0;
        u8              norcs = GPMC_CS_NUM + 1;
@@ -232,7 +210,7 @@ void __init sdp_flash_init(struct flash_partitions sdp_partition_info[])
                printk(KERN_ERR "%s: Invalid chip select: %d\n", __func__, cs);
                return;
        }
-       config_sel = (unsigned char *)(chip_sel_sdp[idx]);
+       config_sel = (unsigned char *)(chip_sel_board[idx]);
 
        while (cs < GPMC_CS_NUM) {
                switch (config_sel[cs]) {
@@ -256,17 +234,20 @@ void __init sdp_flash_init(struct flash_partitions sdp_partition_info[])
                printk(KERN_INFO "NOR: Unable to find configuration "
                                "in GPMC\n");
        else
-               board_nor_init(sdp_partition_info[0], norcs);
+               board_nor_init(partition_info[0].parts,
+                               partition_info[0].nr_parts, norcs);
 
        if (onenandcs > GPMC_CS_NUM)
                printk(KERN_INFO "OneNAND: Unable to find configuration "
                                "in GPMC\n");
        else
-               board_onenand_init(sdp_partition_info[1], onenandcs);
+               board_onenand_init(partition_info[1].parts,
+                                       partition_info[1].nr_parts, onenandcs);
 
        if (nandcs > GPMC_CS_NUM)
                printk(KERN_INFO "NAND: Unable to find configuration "
                                "in GPMC\n");
        else
-               board_nand_init(sdp_partition_info[2], nandcs);
+               board_nand_init(partition_info[2].parts,
+                               partition_info[2].nr_parts, nandcs);
 }

diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 16cc06860670ed7cf22c4a6e1d991d6e76fe3b89..3482b99e8c8653c4e72240d263692a436674afdc 100644 (file)
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -26,7 +26,6 @@
 #include <asm/mach/map.h>
 
 #include <mach/gpio.h>
-#include <plat/mux.h>
 #include <plat/usb.h>
 #include <plat/board.h>
 #include <plat/common.h>
@@ -59,6 +58,7 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
        .boot_params    = 0x80000100,
        .map_io         = omap_generic_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = omap_generic_init_irq,
        .init_machine   = omap_generic_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 0665f2c8dc8e894a1e949baf2a273e7bef104159..e09bd686389f32dc385da26db744efbecc7fe5a7 100644 (file)
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -33,7 +33,6 @@
 
 #include <plat/control.h>
 #include <mach/gpio.h>
-#include <plat/mux.h>
 #include <plat/usb.h>
 #include <plat/board.h>
 #include <plat/common.h>
@@ -42,6 +41,8 @@
 #include <plat/dma.h>
 #include <plat/gpmc.h>
 
+#include "mux.h"
+
 #define H4_FLASH_CS    0
 #define H4_SMC91X_CS   1
 
@@ -246,7 +247,7 @@ static inline void __init h4_init_debug(void)
 
        udelay(100);
 
-       omap_cfg_reg(M15_24XX_GPIO92);
+       omap_mux_init_gpio(92, 0);
        if (debug_card_init(cs_mem_base, H4_ETHR_GPIO_IRQ) < 0)
                gpmc_cs_free(eth_cs);
 
@@ -272,27 +273,6 @@ static struct omap_lcd_config h4_lcd_config __initdata = {
 };
 
 static struct omap_usb_config h4_usb_config __initdata = {
-#ifdef CONFIG_MACH_OMAP2_H4_USB1
-       /* NOTE:  usb1 could also be used with 3 wire signaling */
-       .pins[1]        = 4,
-#endif
-
-#ifdef CONFIG_MACH_OMAP_H4_OTG
-       /* S1.10 ON -- USB OTG port
-        * usb0 switched to Mini-AB port and isp1301 transceiver;
-        * S2.POS3 = OFF, S2.POS4 = ON ... to allow battery charging
-        */
-       .otg            = 1,
-       .pins[0]        = 4,
-#ifdef CONFIG_USB_GADGET_OMAP
-       /* use OTG cable, or standard A-to-MiniB */
-       .hmc_mode       = 0x14, /* 0:dev/otg 1:host 2:disable */
-#elif  defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-       /* use OTG cable, or NONSTANDARD (B-to-MiniB) */
-       .hmc_mode       = 0x11, /* 0:host 1:host 2:disable */
-#endif /* XX */
-
-#else
        /* S1.10 OFF -- usb "download port"
         * usb0 switched to Mini-B port and isp1105 transceiver;
         * S2.POS3 = ON, S2.POS4 = OFF ... to enable battery charging
@@ -301,7 +281,6 @@ static struct omap_usb_config h4_usb_config __initdata = {
        .pins[0]        = 3,
 /*     .hmc_mode       = 0x14,*/       /* 0:dev 1:host 2:disable */
        .hmc_mode       = 0x00,         /* 0:dev|otg 1:disable 2:disable */
-#endif
 };
 
 static struct omap_board_config_kernel h4_config[] = {
@@ -338,31 +317,54 @@ static struct i2c_board_info __initdata h4_i2c_board_info[] = {
        },
 };
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+       { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux      NULL
+#endif
+
 static void __init omap_h4_init(void)
 {
+       omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAF);
+
        /*
         * Make sure the serial ports are muxed on at this point.
         * You have to mux them off in device drivers later on
         * if not needed.
         */
-#if defined(CONFIG_OMAP_IR) || defined(CONFIG_OMAP_IR_MODULE)
-       omap_cfg_reg(K15_24XX_UART3_TX);
-       omap_cfg_reg(K14_24XX_UART3_RX);
-#endif
 
 #if defined(CONFIG_KEYBOARD_OMAP) || defined(CONFIG_KEYBOARD_OMAP_MODULE)
+       omap_mux_init_gpio(88, OMAP_PULL_ENA | OMAP_PULL_UP);
+       omap_mux_init_gpio(89, OMAP_PULL_ENA | OMAP_PULL_UP);
+       omap_mux_init_gpio(124, OMAP_PULL_ENA | OMAP_PULL_UP);
+       omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP);
        if (omap_has_menelaus()) {
+               omap_mux_init_signal("sdrc_a14.gpio0",
+                       OMAP_PULL_ENA | OMAP_PULL_UP);
+               omap_mux_init_signal("vlynq_rx0.gpio_15", 0);
+               omap_mux_init_signal("gpio_98", 0);
                row_gpios[5] = 0;
                col_gpios[2] = 15;
                col_gpios[6] = 18;
+       } else {
+               omap_mux_init_signal("gpio_96", OMAP_PULL_ENA | OMAP_PULL_UP);
+               omap_mux_init_signal("gpio_100", 0);
+               omap_mux_init_signal("gpio_98", 0);
        }
+       omap_mux_init_signal("gpio_90", 0);
+       omap_mux_init_signal("gpio_91", 0);
+       omap_mux_init_signal("gpio_36", 0);
+       omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0);
+       omap_mux_init_signal("gpio_97", 0);
 #endif
 
        i2c_register_board_info(1, h4_i2c_board_info,
                        ARRAY_SIZE(h4_i2c_board_info));
 
        platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices));
-       omap_usb_init(&h4_usb_config);
+       omap2_usbfs_init(&h4_usb_config);
        omap_serial_init();
 }
 
@@ -378,6 +380,7 @@ MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
        .boot_params    = 0x80000100,
        .map_io         = omap_h4_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = omap_h4_init_irq,
        .init_machine   = omap_h4_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index d55c57b761a988e3bb62cc2adeb999709861db2c..175f043397612df6bc764a668338789d301e69c2 100644 (file)
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -532,17 +532,12 @@ static void __init igep2_init(void)
                pr_warning("IGEP v2: Could not obtain gpio GPIO_WIFI_NRESET\n");
 }
 
-static void __init igep2_map_io(void)
-{
-       omap2_set_globals_343x();
-       omap34xx_map_common_io();
-}
-
 MACHINE_START(IGEP0020, "IGEP v2 board")
        .phys_io        = 0x48000000,
        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
        .boot_params    = 0x80000100,
-       .map_io         = igep2_map_io,
+       .map_io         = omap3_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = igep2_init_irq,
        .init_machine   = igep2_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index fefd7e6e97796a9ede0ce8076de96f9ee437fb9d..00d9b13b01c5938e0118ced2a8801595dede232f 100644 (file)
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -38,6 +38,7 @@
 #include <plat/board.h>
 #include <plat/common.h>
 #include <plat/gpmc.h>
+#include <mach/board-zoom.h>
 
 #include <asm/delay.h>
 #include <plat/control.h>
@@ -388,6 +389,38 @@ static struct omap_musb_board_data musb_board_data = {
        .power                  = 100,
 };
 
+static struct mtd_partition ldp_nand_partitions[] = {
+       /* All the partition sizes are listed in terms of NAND block size */
+       {
+               .name           = "X-Loader-NAND",
+               .offset         = 0,
+               .size           = 4 * (64 * 2048),      /* 512KB, 0x80000 */
+               .mask_flags     = MTD_WRITEABLE,        /* force read-only */
+       },
+       {
+               .name           = "U-Boot-NAND",
+               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x80000 */
+               .size           = 10 * (64 * 2048),     /* 1.25MB, 0x140000 */
+               .mask_flags     = MTD_WRITEABLE,        /* force read-only */
+       },
+       {
+               .name           = "Boot Env-NAND",
+               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x1c0000 */
+               .size           = 2 * (64 * 2048),      /* 256KB, 0x40000 */
+       },
+       {
+               .name           = "Kernel-NAND",
+               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x0200000*/
+               .size           = 240 * (64 * 2048),    /* 30M, 0x1E00000 */
+       },
+       {
+               .name           = "File System - NAND",
+               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x2000000 */
+               .size           = MTDPART_SIZ_FULL,     /* 96MB, 0x6000000 */
+       },
+
+};
+
 static void __init omap_ldp_init(void)
 {
        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
@@ -400,23 +433,20 @@ static void __init omap_ldp_init(void)
        ads7846_dev_init();
        omap_serial_init();
        usb_musb_init(&musb_board_data);
+       board_nand_init(ldp_nand_partitions,
+               ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS);
 
        omap2_hsmmc_init(mmc);
        /* link regulators to MMC adapters */
        ldp_vmmc1_supply.dev = mmc[0].dev;
 }
 
-static void __init omap_ldp_map_io(void)
-{
-       omap2_set_globals_343x();
-       omap34xx_map_common_io();
-}
-
 MACHINE_START(OMAP_LDP, "OMAP LDP board")
        .phys_io        = 0x48000000,
        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
        .boot_params    = 0x80000100,
-       .map_io         = omap_ldp_map_io,
+       .map_io         = omap3_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = omap_ldp_init_irq,
        .init_machine   = omap_ldp_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 3ccc34ebdcc79c11e021b4c80e9fca550bfea037..a3e2b49aa39f001046c0994b09c64aa14cd10581 100644 (file)
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -33,6 +33,8 @@
 #include <plat/mmc.h>
 #include <plat/serial.h>
 
+#include "mux.h"
+
 static int slot1_cover_open;
 static int slot2_cover_open;
 static struct device *mmc_device;
@@ -649,8 +651,17 @@ static void __init n8x0_init_irq(void)
        omap_gpio_init();
 }
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+       { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux      NULL
+#endif
+
 static void __init n8x0_init_machine(void)
 {
+       omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC);
        /* FIXME: add n810 spi devices */
        spi_register_board_info(n800_spi_board_info,
                                ARRAY_SIZE(n800_spi_board_info));
@@ -667,6 +678,7 @@ MACHINE_START(NOKIA_N800, "Nokia N800")
        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
        .boot_params    = 0x80000100,
        .map_io         = n8x0_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = n8x0_init_irq,
        .init_machine   = n8x0_init_machine,
        .timer          = &omap_timer,
@@ -677,6 +689,7 @@ MACHINE_START(NOKIA_N810, "Nokia N810")
        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
        .boot_params    = 0x80000100,
        .map_io         = n8x0_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = n8x0_init_irq,
        .init_machine   = n8x0_init_machine,
        .timer          = &omap_timer,
@@ -687,6 +700,7 @@ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
        .boot_params    = 0x80000100,
        .map_io         = n8x0_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = n8x0_init_irq,
        .init_machine   = n8x0_init_machine,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 69b154cdc75dcaa2c46d0a33434cfc7c379fd1fc..87969c7df652885ff6210519f3043cb7bb4f055e 100644 (file)
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -48,9 +48,6 @@
 #include "mux.h"
 #include "hsmmc.h"
 
-#define GPMC_CS0_BASE  0x60
-#define GPMC_CS_SIZE   0x30
-
 #define NAND_BLOCK_SIZE                SZ_128K
 
 static struct mtd_partition omap3beagle_nand_partitions[] = {
@@ -93,20 +90,6 @@ static struct omap_nand_platform_data omap3beagle_nand_data = {
        .dev_ready      = NULL,
 };
 
-static struct resource omap3beagle_nand_resource = {
-       .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device omap3beagle_nand_device = {
-       .name           = "omap2-nand",
-       .id             = -1,
-       .dev            = {
-               .platform_data  = &omap3beagle_nand_data,
-       },
-       .num_resources  = 1,
-       .resource       = &omap3beagle_nand_resource,
-};
-
 /* DSS */
 
 static int beagle_enable_dvi(struct omap_dss_device *dssdev)
@@ -424,8 +407,6 @@ static void __init omap3beagle_flash_init(void)
        u8 cs = 0;
        u8 nandcs = GPMC_CS_NUM + 1;
 
-       u32 gpmc_base_add = OMAP34XX_GPMC_VIRT;
-
        /* find out the chip-select on which NAND exists */
        while (cs < GPMC_CS_NUM) {
                u32 ret = 0;
@@ -447,12 +428,9 @@ static void __init omap3beagle_flash_init(void)
 
        if (nandcs < GPMC_CS_NUM) {
                omap3beagle_nand_data.cs = nandcs;
-               omap3beagle_nand_data.gpmc_cs_baseaddr = (void *)
-                       (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE);
-               omap3beagle_nand_data.gpmc_baseaddr = (void *) (gpmc_base_add);
 
                printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
-               if (platform_device_register(&omap3beagle_nand_device) < 0)
+               if (gpmc_nand_init(&omap3beagle_nand_data) < 0)
                        printk(KERN_ERR "Unable to register NAND device\n");
        }
 }
@@ -507,18 +485,13 @@ static void __init omap3_beagle_init(void)
        beagle_display_init();
 }
 
-static void __init omap3_beagle_map_io(void)
-{
-       omap2_set_globals_343x();
-       omap34xx_map_common_io();
-}
-
 MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
        /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */
        .phys_io        = 0x48000000,
        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
        .boot_params    = 0x80000100,
-       .map_io         = omap3_beagle_map_io,
+       .map_io         = omap3_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = omap3_beagle_init_irq,
        .init_machine   = omap3_beagle_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index b952610138121862368aab2296ef30552bdc5528..6494dbdfc391567bfe3d1c209de0d4d2ad34c5b5 100644 (file)
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -715,18 +715,13 @@ static void __init omap3_evm_init(void)
        omap3_evm_display_init();
 }
 
-static void __init omap3_evm_map_io(void)
-{
-       omap2_set_globals_343x();
-       omap34xx_map_common_io();
-}
-
 MACHINE_START(OMAP3EVM, "OMAP3 EVM")
        /* Maintainer: Syed Mohammed Khasim - Texas Instruments */
        .phys_io        = 0x48000000,
        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
        .boot_params    = 0x80000100,
-       .map_io         = omap3_evm_map_io,
+       .map_io         = omap3_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = omap3_evm_init_irq,
        .init_machine   = omap3_evm_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index db06dc910ba755c6988cc11155c3f047dff3c792..55836fa3506014a20329ffad3d8eda0df722d3d3 100644 (file)
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -25,6 +25,9 @@
 #include <linux/spi/ads7846.h>
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
+#include <linux/spi/wl12xx.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/nand.h>
 #include <linux/leds.h>
 #include <linux/input.h>
 #include <linux/input/matrix_keypad.h>
@@ -41,15 +44,49 @@
 #include <plat/mcspi.h>
 #include <plat/usb.h>
 #include <plat/display.h>
+#include <plat/nand.h>
 
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "hsmmc.h"
 
+#define PANDORA_WIFI_IRQ_GPIO          21
+#define PANDORA_WIFI_NRESET_GPIO       23
 #define OMAP3_PANDORA_TS_GPIO          94
 
-/* hardware debounce: (value + 1) * 31us */
-#define GPIO_DEBOUNCE_TIME             127
+#define NAND_BLOCK_SIZE                        SZ_128K
+
+static struct mtd_partition omap3pandora_nand_partitions[] = {
+       {
+               .name           = "xloader",
+               .offset         = 0,
+               .size           = 4 * NAND_BLOCK_SIZE,
+               .mask_flags     = MTD_WRITEABLE
+       }, {
+               .name           = "uboot",
+               .offset         = MTDPART_OFS_APPEND,
+               .size           = 15 * NAND_BLOCK_SIZE,
+       }, {
+               .name           = "uboot-env",
+               .offset         = MTDPART_OFS_APPEND,
+               .size           = 1 * NAND_BLOCK_SIZE,
+       }, {
+               .name           = "boot",
+               .offset         = MTDPART_OFS_APPEND,
+               .size           = 80 * NAND_BLOCK_SIZE,
+       }, {
+               .name           = "rootfs",
+               .offset         = MTDPART_OFS_APPEND,
+               .size           = MTDPART_SIZ_FULL,
+       },
+};
+
+static struct omap_nand_platform_data pandora_nand_data = {
+       .cs             = 0,
+       .devsize        = 1,    /* '0' for 8-bit, '1' for 16-bit device */
+       .parts          = omap3pandora_nand_partitions,
+       .nr_parts       = ARRAY_SIZE(omap3pandora_nand_partitions),
+};
 
 static struct gpio_led pandora_gpio_leds[] = {
        {
@@ -88,6 +125,7 @@ static struct platform_device pandora_leds_gpio = {
        .type           = ev_type,                              \
        .code           = ev_code,                              \
        .active_low     = act_low,                              \
+       .debounce_interval = 4,                                 \
        .desc           = "btn " descr,                         \
 }
 
@@ -99,14 +137,14 @@ static struct gpio_keys_button pandora_gpio_keys[] = {
        GPIO_BUTTON_LOW(103,    KEY_DOWN,       "down"),
        GPIO_BUTTON_LOW(96,     KEY_LEFT,       "left"),
        GPIO_BUTTON_LOW(98,     KEY_RIGHT,      "right"),
-       GPIO_BUTTON_LOW(109,    KEY_KP1,        "game 1"),
-       GPIO_BUTTON_LOW(111,    KEY_KP2,        "game 2"),
-       GPIO_BUTTON_LOW(106,    KEY_KP3,        "game 3"),
-       GPIO_BUTTON_LOW(101,    KEY_KP4,        "game 4"),
-       GPIO_BUTTON_LOW(102,    BTN_TL,         "l"),
-       GPIO_BUTTON_LOW(97,     BTN_TL2,        "l2"),
-       GPIO_BUTTON_LOW(105,    BTN_TR,         "r"),
-       GPIO_BUTTON_LOW(107,    BTN_TR2,        "r2"),
+       GPIO_BUTTON_LOW(109,    KEY_PAGEUP,     "game 1"),
+       GPIO_BUTTON_LOW(111,    KEY_END,        "game 2"),
+       GPIO_BUTTON_LOW(106,    KEY_PAGEDOWN,   "game 3"),
+       GPIO_BUTTON_LOW(101,    KEY_HOME,       "game 4"),
+       GPIO_BUTTON_LOW(102,    KEY_RIGHTSHIFT, "l"),
+       GPIO_BUTTON_LOW(97,     KEY_KPPLUS,     "l2"),
+       GPIO_BUTTON_LOW(105,    KEY_RIGHTCTRL,  "r"),
+       GPIO_BUTTON_LOW(107,    KEY_KPMINUS,    "r2"),
        GPIO_BUTTON_LOW(104,    KEY_LEFTCTRL,   "ctrl"),
        GPIO_BUTTON_LOW(99,     KEY_MENU,       "menu"),
        GPIO_BUTTON_LOW(176,    KEY_COFFEE,     "hold"),
@@ -127,14 +165,7 @@ static struct platform_device pandora_keys_gpio = {
        },
 };
 
-static void __init pandora_keys_gpio_init(void)
-{
-       /* set debounce time for GPIO banks 4 and 6 */
-       gpio_set_debounce(32 * 3, GPIO_DEBOUNCE_TIME);
-       gpio_set_debounce(32 * 5, GPIO_DEBOUNCE_TIME);
-}
-
-static int board_keymap[] = {
+static const uint32_t board_keymap[] = {
        /* row, col, code */
        KEY(0, 0, KEY_9),
        KEY(0, 1, KEY_8),
@@ -255,12 +286,33 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = {
 static int omap3pandora_twl_gpio_setup(struct device *dev,
                unsigned gpio, unsigned ngpio)
 {
+       int ret, gpio_32khz;
+
        /* gpio + {0,1} is "mmc{0,1}_cd" (input/IRQ) */
        omap3pandora_mmc[0].gpio_cd = gpio + 0;
        omap3pandora_mmc[1].gpio_cd = gpio + 1;
        omap2_hsmmc_init(omap3pandora_mmc);
 
+       /* gpio + 13 drives 32kHz buffer for wifi module */
+       gpio_32khz = gpio + 13;
+       ret = gpio_request(gpio_32khz, "wifi 32kHz");
+       if (ret < 0) {
+               pr_err("Cannot get GPIO line %d, ret=%d\n", gpio_32khz, ret);
+               goto fail;
+       }
+
+       ret = gpio_direction_output(gpio_32khz, 1);
+       if (ret < 0) {
+               pr_err("Cannot set GPIO line %d, ret=%d\n", gpio_32khz, ret);
+               goto fail_direction;
+       }
+
        return 0;
+
+fail_direction:
+       gpio_free(gpio_32khz);
+fail:
+       return -ENODEV;
 }
 
 static struct twl4030_gpio_platform_data omap3pandora_gpio_data = {
@@ -539,10 +591,67 @@ static void __init omap3pandora_init_irq(void)
        omap_gpio_init();
 }
 
+static void pandora_wl1251_set_power(bool enable)
+{
+       /*
+        * Keep power always on until wl1251_sdio driver learns to re-init
+        * the chip after powering it down and back up.
+        */
+}
+
+static struct wl12xx_platform_data pandora_wl1251_pdata = {
+       .set_power      = pandora_wl1251_set_power,
+       .use_eeprom     = true,
+};
+
+static struct platform_device pandora_wl1251_data = {
+       .name           = "wl1251_data",
+       .id             = -1,
+       .dev            = {
+               .platform_data  = &pandora_wl1251_pdata,
+       },
+};
+
+static void pandora_wl1251_init(void)
+{
+       int ret;
+
+       ret = gpio_request(PANDORA_WIFI_IRQ_GPIO, "wl1251 irq");
+       if (ret < 0)
+               goto fail;
+
+       ret = gpio_direction_input(PANDORA_WIFI_IRQ_GPIO);
+       if (ret < 0)
+               goto fail_irq;
+
+       pandora_wl1251_pdata.irq = gpio_to_irq(PANDORA_WIFI_IRQ_GPIO);
+       if (pandora_wl1251_pdata.irq < 0)
+               goto fail_irq;
+
+       ret = gpio_request(PANDORA_WIFI_NRESET_GPIO, "wl1251 nreset");
+       if (ret < 0)
+               goto fail_irq;
+
+       /* start powered so that it probes with MMC subsystem */
+       ret = gpio_direction_output(PANDORA_WIFI_NRESET_GPIO, 1);
+       if (ret < 0)
+               goto fail_nreset;
+
+       return;
+
+fail_nreset:
+       gpio_free(PANDORA_WIFI_NRESET_GPIO);
+fail_irq:
+       gpio_free(PANDORA_WIFI_IRQ_GPIO);
+fail:
+       printk(KERN_ERR "wl1251 board initialisation failed\n");
+}
+
 static struct platform_device *omap3pandora_devices[] __initdata = {
        &pandora_leds_gpio,
        &pandora_keys_gpio,
        &pandora_dss_device,
+       &pandora_wl1251_data,
 };
 
 static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
@@ -575,6 +684,7 @@ static void __init omap3pandora_init(void)
 {
        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
        omap3pandora_i2c_init();
+       pandora_wl1251_init();
        platform_add_devices(omap3pandora_devices,
                        ARRAY_SIZE(omap3pandora_devices));
        omap_serial_init();
@@ -582,25 +692,20 @@ static void __init omap3pandora_init(void)
                        ARRAY_SIZE(omap3pandora_spi_board_info));
        omap3pandora_ads7846_init();
        usb_ehci_init(&ehci_pdata);
-       pandora_keys_gpio_init();
        usb_musb_init(&musb_board_data);
+       gpmc_nand_init(&pandora_nand_data);
 
        /* Ensure SDRC pins are mux'd for self-refresh */
        omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
        omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
 }
 
-static void __init omap3pandora_map_io(void)
-{
-       omap2_set_globals_343x();
-       omap34xx_map_common_io();
-}
-
 MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
        .phys_io        = 0x48000000,
        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
        .boot_params    = 0x80000100,
-       .map_io         = omap3pandora_map_io,
+       .map_io         = omap3_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = omap3pandora_init_irq,
        .init_machine   = omap3pandora_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index a04cffd691c55995812365aa78c373e7950d0b2c..bcd01d278c656f0b09a742a31370e5e278b1fb9e 100644 (file)
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -652,18 +652,12 @@ static void __init omap3_stalker_init(void)
        omap_mux_init_signal("sdr_cke1", OMAP_PIN_OUTPUT);
 }
 
-static void __init omap3_stalker_map_io(void)
-{
-       omap2_set_globals_343x();
-       omap34xx_map_common_io();
-}
-
 MACHINE_START(SBC3530, "OMAP3 STALKER")
        /* Maintainer: Jason Lam -lzg@ema-tech.com */
        .phys_io                = 0x48000000,
        .io_pg_offst            = ((0xfa000000) >> 18) & 0xfffc,
        .boot_params            = 0x80000100,
-       .map_io                 = omap3_stalker_map_io,
+       .map_io                 = omap3_map_io,
        .init_irq               = omap3_stalker_init_irq,
        .init_machine           = omap3_stalker_init,
        .timer                  = &omap_timer,

diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 2f5f8233dd5b8857bcfddb29d178f802fbd1271f..663c62d271e8bfa0fcdec35bd9f03333ac0af87c 100644 (file)
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -54,9 +54,6 @@
 
 #include <asm/setup.h>
 
-#define GPMC_CS0_BASE  0x60
-#define GPMC_CS_SIZE   0x30
-
 #define NAND_BLOCK_SIZE                SZ_128K
 
 #define OMAP3_AC_GPIO          136
@@ -106,20 +103,6 @@ static struct omap_nand_platform_data omap3touchbook_nand_data = {
        .dev_ready      = NULL,
 };
 
-static struct resource omap3touchbook_nand_resource = {
-       .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device omap3touchbook_nand_device = {
-       .name           = "omap2-nand",
-       .id             = -1,
-       .dev            = {
-               .platform_data  = &omap3touchbook_nand_data,
-       },
-       .num_resources  = 1,
-       .resource       = &omap3touchbook_nand_resource,
-};
-
 #include "sdram-micron-mt46h32m32lf-6.h"
 
 static struct omap2_hsmmc_info mmc[] = {
@@ -458,8 +441,6 @@ static void __init omap3touchbook_flash_init(void)
        u8 cs = 0;
        u8 nandcs = GPMC_CS_NUM + 1;
 
-       u32 gpmc_base_add = OMAP34XX_GPMC_VIRT;
-
        /* find out the chip-select on which NAND exists */
        while (cs < GPMC_CS_NUM) {
                u32 ret = 0;
@@ -481,13 +462,9 @@ static void __init omap3touchbook_flash_init(void)
 
        if (nandcs < GPMC_CS_NUM) {
                omap3touchbook_nand_data.cs = nandcs;
-               omap3touchbook_nand_data.gpmc_cs_baseaddr = (void *)
-                       (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE);
-               omap3touchbook_nand_data.gpmc_baseaddr =
-                                               (void *) (gpmc_base_add);
 
                printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
-               if (platform_device_register(&omap3touchbook_nand_device) < 0)
+               if (gpmc_nand_init(&omap3touchbook_nand_data) < 0)
                        printk(KERN_ERR "Unable to register NAND device\n");
        }
 }
@@ -559,18 +536,13 @@ static void __init omap3_touchbook_init(void)
        omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
 }
 
-static void __init omap3_touchbook_map_io(void)
-{
-       omap2_set_globals_343x();
-       omap34xx_map_common_io();
-}
-
 MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
        /* Maintainer: Gregoire Gentil - http://www.alwaysinnovating.com */
        .phys_io        = 0x48000000,
        .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
        .boot_params    = 0x80000100,
-       .map_io         = omap3_touchbook_map_io,
+       .map_io         = omap3_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = omap3_touchbook_init_irq,
        .init_machine   = omap3_touchbook_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
new file mode 100644 (file)
index 0000000..c03d1d5
--- /dev/null
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -0,0 +1,304 @@
+/*
+ * Board support file for OMAP4430 based PandaBoard.
+ *
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * Author: David Anders <x0132446@ti.com>
+ *
+ * Based on mach-omap2/board-4430sdp.c
+ *
+ * Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * Based on mach-omap2/board-3430sdp.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/usb/otg.h>
+#include <linux/i2c/twl.h>
+#include <linux/regulator/machine.h>
+
+#include <mach/hardware.h>
+#include <mach/omap4-common.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <plat/board.h>
+#include <plat/common.h>
+#include <plat/control.h>
+#include <plat/timer-gp.h>
+#include <plat/usb.h>
+#include <plat/mmc.h>
+#include "hsmmc.h"
+
+
+static void __init omap4_panda_init_irq(void)
+{
+       omap2_init_common_hw(NULL, NULL);
+       gic_init_irq();
+       omap_gpio_init();
+}
+
+static struct omap_musb_board_data musb_board_data = {
+       .interface_type         = MUSB_INTERFACE_UTMI,
+       .mode                   = MUSB_PERIPHERAL,
+       .power                  = 100,
+};
+
+static struct omap2_hsmmc_info mmc[] = {
+       {
+               .mmc            = 1,
+               .wires          = 8,
+               .gpio_wp        = -EINVAL,
+       },
+       {}      /* Terminator */
+};
+
+static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = {
+       {
+               .supply = "vmmc",
+               .dev_name = "mmci-omap-hs.0",
+       },
+       {
+               .supply = "vmmc",
+               .dev_name = "mmci-omap-hs.1",
+       },
+};
+
+static int omap4_twl6030_hsmmc_late_init(struct device *dev)
+{
+       int ret = 0;
+       struct platform_device *pdev = container_of(dev,
+                               struct platform_device, dev);
+       struct omap_mmc_platform_data *pdata = dev->platform_data;
+
+       /* Setting MMC1 Card detect Irq */
+       if (pdev->id == 0)
+               pdata->slots[0].card_detect_irq = TWL6030_IRQ_BASE +
+                                               MMCDETECT_INTR_OFFSET;
+       return ret;
+}
+
+static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
+{
+       struct omap_mmc_platform_data *pdata = dev->platform_data;
+
+       pdata->init =   omap4_twl6030_hsmmc_late_init;
+}
+
+static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
+{
+       struct omap2_hsmmc_info *c;
+
+       omap2_hsmmc_init(controllers);
+       for (c = controllers; c->mmc; c++)
+               omap4_twl6030_hsmmc_set_late_init(c->dev);
+
+       return 0;
+}
+
+static struct regulator_init_data omap4_panda_vaux1 = {
+       .constraints = {
+               .min_uV                 = 1000000,
+               .max_uV                 = 3000000,
+               .apply_uV               = true,
+               .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                       | REGULATOR_MODE_STANDBY,
+               .valid_ops_mask  = REGULATOR_CHANGE_VOLTAGE
+                                       | REGULATOR_CHANGE_MODE
+                                       | REGULATOR_CHANGE_STATUS,
+       },
+};
+
+static struct regulator_init_data omap4_panda_vaux2 = {
+       .constraints = {
+               .min_uV                 = 1200000,
+               .max_uV                 = 2800000,
+               .apply_uV               = true,
+               .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                       | REGULATOR_MODE_STANDBY,
+               .valid_ops_mask  = REGULATOR_CHANGE_VOLTAGE
+                                       | REGULATOR_CHANGE_MODE
+                                       | REGULATOR_CHANGE_STATUS,
+       },
+};
+
+static struct regulator_init_data omap4_panda_vaux3 = {
+       .constraints = {
+               .min_uV                 = 1000000,
+               .max_uV                 = 3000000,
+               .apply_uV               = true,
+               .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                       | REGULATOR_MODE_STANDBY,
+               .valid_ops_mask  = REGULATOR_CHANGE_VOLTAGE
+                                       | REGULATOR_CHANGE_MODE
+                                       | REGULATOR_CHANGE_STATUS,
+       },
+};
+
+/* VMMC1 for MMC1 card */
+static struct regulator_init_data omap4_panda_vmmc = {
+       .constraints = {
+               .min_uV                 = 1200000,
+               .max_uV                 = 3000000,
+               .apply_uV               = true,
+               .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                       | REGULATOR_MODE_STANDBY,
+               .valid_ops_mask  = REGULATOR_CHANGE_VOLTAGE
+                                       | REGULATOR_CHANGE_MODE
+                                       | REGULATOR_CHANGE_STATUS,
+       },
+       .num_consumer_supplies  = 2,
+       .consumer_supplies      = omap4_panda_vmmc_supply,
+};
+
+static struct regulator_init_data omap4_panda_vpp = {
+       .constraints = {
+               .min_uV                 = 1800000,
+               .max_uV                 = 2500000,
+               .apply_uV               = true,
+               .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                       | REGULATOR_MODE_STANDBY,
+               .valid_ops_mask  = REGULATOR_CHANGE_VOLTAGE
+                                       | REGULATOR_CHANGE_MODE
+                                       | REGULATOR_CHANGE_STATUS,
+       },
+};
+
+static struct regulator_init_data omap4_panda_vusim = {
+       .constraints = {
+               .min_uV                 = 1200000,
+               .max_uV                 = 2900000,
+               .apply_uV               = true,
+               .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                       | REGULATOR_MODE_STANDBY,
+               .valid_ops_mask  = REGULATOR_CHANGE_VOLTAGE
+                                       | REGULATOR_CHANGE_MODE
+                                       | REGULATOR_CHANGE_STATUS,
+       },
+};
+
+static struct regulator_init_data omap4_panda_vana = {
+       .constraints = {
+               .min_uV                 = 2100000,
+               .max_uV                 = 2100000,
+               .apply_uV               = true,
+               .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                       | REGULATOR_MODE_STANDBY,
+               .valid_ops_mask  = REGULATOR_CHANGE_MODE
+                                       | REGULATOR_CHANGE_STATUS,
+       },
+};
+
+static struct regulator_init_data omap4_panda_vcxio = {
+       .constraints = {
+               .min_uV                 = 1800000,
+               .max_uV                 = 1800000,
+               .apply_uV               = true,
+               .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                       | REGULATOR_MODE_STANDBY,
+               .valid_ops_mask  = REGULATOR_CHANGE_MODE
+                                       | REGULATOR_CHANGE_STATUS,
+       },
+};
+
+static struct regulator_init_data omap4_panda_vdac = {
+       .constraints = {
+               .min_uV                 = 1800000,
+               .max_uV                 = 1800000,
+               .apply_uV               = true,
+               .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                       | REGULATOR_MODE_STANDBY,
+               .valid_ops_mask  = REGULATOR_CHANGE_MODE
+                                       | REGULATOR_CHANGE_STATUS,
+       },
+};
+
+static struct regulator_init_data omap4_panda_vusb = {
+       .constraints = {
+               .min_uV                 = 3300000,
+               .max_uV                 = 3300000,
+               .apply_uV               = true,
+               .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                       | REGULATOR_MODE_STANDBY,
+               .valid_ops_mask  =      REGULATOR_CHANGE_MODE
+                                       | REGULATOR_CHANGE_STATUS,
+       },
+};
+
+static struct twl4030_platform_data omap4_panda_twldata = {
+       .irq_base       = TWL6030_IRQ_BASE,
+       .irq_end        = TWL6030_IRQ_END,
+
+       /* Regulators */
+       .vmmc           = &omap4_panda_vmmc,
+       .vpp            = &omap4_panda_vpp,
+       .vusim          = &omap4_panda_vusim,
+       .vana           = &omap4_panda_vana,
+       .vcxio          = &omap4_panda_vcxio,
+       .vdac           = &omap4_panda_vdac,
+       .vusb           = &omap4_panda_vusb,
+       .vaux1          = &omap4_panda_vaux1,
+       .vaux2          = &omap4_panda_vaux2,
+       .vaux3          = &omap4_panda_vaux3,
+};
+
+static struct i2c_board_info __initdata omap4_panda_i2c_boardinfo[] = {
+       {
+               I2C_BOARD_INFO("twl6030", 0x48),
+               .flags = I2C_CLIENT_WAKE,
+               .irq = OMAP44XX_IRQ_SYS_1N,
+               .platform_data = &omap4_panda_twldata,
+       },
+};
+static int __init omap4_panda_i2c_init(void)
+{
+       /*
+        * Phoenix Audio IC needs I2C1 to
+        * start with 400 KHz or less
+        */
+       omap_register_i2c_bus(1, 400, omap4_panda_i2c_boardinfo,
+                       ARRAY_SIZE(omap4_panda_i2c_boardinfo));
+       omap_register_i2c_bus(2, 400, NULL, 0);
+       omap_register_i2c_bus(3, 400, NULL, 0);
+       omap_register_i2c_bus(4, 400, NULL, 0);
+       return 0;
+}
+static void __init omap4_panda_init(void)
+{
+       int status;
+
+       omap4_panda_i2c_init();
+       omap_serial_init();
+       omap4_twl6030_hsmmc_init(mmc);
+       /* OMAP4 Panda uses internal transceiver so register nop transceiver */
+       usb_nop_xceiv_register();
+       /* FIXME: allow multi-omap to boot until musb is updated for omap4 */
+       if (!cpu_is_omap44xx())
+               usb_musb_init(&musb_board_data);
+}
+
+static void __init omap4_panda_map_io(void)
+{
+       omap2_set_globals_443x();
+       omap44xx_map_common_io();
+}
+
+MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
+       /* Maintainer: David Anders - Texas Instruments Inc */
+       .phys_io        = 0x48000000,
+       .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
+       .boot_params    = 0x80000100,
+       .map_io         = omap4_panda_map_io,
+       .init_irq       = omap4_panda_init_irq,
+       .init_machine   = omap4_panda_init,
+       .timer          = &omap_timer,
+MACHINE_END

diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 79ac41400c218039193ab8a3384805d74953797a..4c484361835063d17de2df8fe27c7fb28be7984f 100644 (file)
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -58,8 +58,6 @@
 #define OVERO_GPIO_USBH_NRESET 183
 
 #define NAND_BLOCK_SIZE SZ_128K
-#define GPMC_CS0_BASE  0x60
-#define GPMC_CS_SIZE   0x30
 
 #define OVERO_SMSC911X_CS      5
 #define OVERO_SMSC911X_GPIO    176
@@ -166,9 +164,26 @@ static struct platform_device overo_smsc911x_device = {
        },
 };
 
+static struct platform_device overo_smsc911x2_device = {
+       .name           = "smsc911x",
+       .id             = 1,
+       .num_resources  = ARRAY_SIZE(overo_smsc911x2_resources),
+       .resource       = overo_smsc911x2_resources,
+       .dev            = {
+               .platform_data = &overo_smsc911x_config,
+       },
+};
+
+static struct platform_device *smsc911x_devices[] = {
+       &overo_smsc911x_device,
+       &overo_smsc911x2_device,
+};
+
 static inline void __init overo_init_smsc911x(void)
 {
-       unsigned long cs_mem_base;
+       unsigned long cs_mem_base, cs_mem_base2;
+
+       /* set up first smsc911x chip */
 
        if (gpmc_cs_request(OVERO_SMSC911X_CS, SZ_16M, &cs_mem_base) < 0) {
                printk(KERN_ERR "Failed request for GPMC mem for smsc911x\n");
@@ -189,7 +204,28 @@ static inline void __init overo_init_smsc911x(void)
        overo_smsc911x_resources[1].start = OMAP_GPIO_IRQ(OVERO_SMSC911X_GPIO);
        overo_smsc911x_resources[1].end   = 0;
 
-       platform_device_register(&overo_smsc911x_device);
+       /* set up second smsc911x chip */
+
+       if (gpmc_cs_request(OVERO_SMSC911X2_CS, SZ_16M, &cs_mem_base2) < 0) {
+               printk(KERN_ERR "Failed request for GPMC mem for smsc911x2\n");
+               return;
+       }
+
+       overo_smsc911x2_resources[0].start = cs_mem_base2 + 0x0;
+       overo_smsc911x2_resources[0].end   = cs_mem_base2 + 0xff;
+
+       if ((gpio_request(OVERO_SMSC911X2_GPIO, "SMSC911X2 IRQ") == 0) &&
+           (gpio_direction_input(OVERO_SMSC911X2_GPIO) == 0)) {
+               gpio_export(OVERO_SMSC911X2_GPIO, 0);
+       } else {
+               printk(KERN_ERR "could not obtain gpio for SMSC911X2 IRQ\n");
+               return;
+       }
+
+       overo_smsc911x2_resources[1].start = OMAP_GPIO_IRQ(OVERO_SMSC911X2_GPIO);
+       overo_smsc911x2_resources[1].end   = 0;
+
+       platform_add_devices(smsc911x_devices, ARRAY_SIZE(smsc911x_devices));
 }
 
 #else
@@ -231,28 +267,11 @@ static struct omap_nand_platform_data overo_nand_data = {
        .dma_channel = -1,      /* disable DMA in OMAP NAND driver */
 };
 
-static struct resource overo_nand_resource = {
-       .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device overo_nand_device = {
-       .name           = "omap2-nand",
-       .id             = -1,
-       .dev            = {
-               .platform_data  = &overo_nand_data,
-       },
-       .num_resources  = 1,
-       .resource       = &overo_nand_resource,
-};
-
-
 static void __init overo_flash_init(void)
 {
        u8 cs = 0;
        u8 nandcs = GPMC_CS_NUM + 1;
 
-       u32 gpmc_base_add = OMAP34XX_GPMC_VIRT;
-
        /* find out the chip-select on which NAND exists */
        while (cs < GPMC_CS_NUM) {
                u32 ret = 0;
@@ -274,12 +293,9 @@ static void __init overo_flash_init(void)
 
        if (nandcs < GPMC_CS_NUM) {
                overo_nand_data.cs = nandcs;
-               overo_nand_data.gpmc_cs_baseaddr = (void *)
-                       (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE);
-               overo_nand_data.gpmc_baseaddr = (void *) (gpmc_base_add);
 
                printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
-               if (platform_device_register(&overo_nand_device) < 0)
+               if (gpmc_nand_init(&overo_nand_data) < 0)
                        printk(KERN_ERR "Unable to register NAND device\n");
        }
 }
@@ -484,17 +500,12 @@ static void __init overo_init(void)
                                        "OVERO_GPIO_USBH_CPEN\n");
 }
 
-static void __init overo_map_io(void)
-{
-       omap2_set_globals_343x();
-       omap34xx_map_common_io();
-}
-
 MACHINE_START(OVERO, "Gumstix Overo")
        .phys_io        = 0x48000000,
        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
        .boot_params    = 0x80000100,
-       .map_io         = overo_map_io,
+       .map_io         = omap3_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = overo_init_irq,
        .init_machine   = overo_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 03483920ed6e0b12fa007c3438d3ea4401f8ec7f..9a5eb87425fcf91dc3164acf3b1386e38e655be7 100644 (file)
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -25,7 +25,6 @@
 #include <linux/mmc/host.h>
 
 #include <plat/mcspi.h>
-#include <plat/mux.h>
 #include <plat/board.h>
 #include <plat/common.h>
 #include <plat/dma.h>
@@ -33,6 +32,11 @@
 #include <plat/onenand.h>
 #include <plat/gpmc-smc91x.h>
 
+#include <sound/tlv320aic3x.h>
+#include <sound/tpa6130a2-plat.h>
+
+#include <../drivers/staging/iio/light/tsl2563.h>
+
 #include "mux.h"
 #include "hsmmc.h"
 
@@ -51,6 +55,12 @@ enum {
 
 static struct wl12xx_platform_data wl1251_pdata;
 
+#if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE)
+static struct tsl2563_platform_data rx51_tsl2563_platform_data = {
+       .cover_comp_gain = 16,
+};
+#endif
+
 static struct omap2_mcspi_device_config wl1251_mcspi_config = {
        .turbo_mode     = 0,
        .single_channel = 1,
@@ -311,48 +321,29 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
        {}      /* Terminator */
 };
 
-static struct regulator_consumer_supply rx51_vmmc1_supply = {
-       .supply   = "vmmc",
-       .dev_name = "mmci-omap-hs.0",
-};
+static struct regulator_consumer_supply rx51_vmmc1_supply =
+       REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0");
 
-static struct regulator_consumer_supply rx51_vaux3_supply = {
-       .supply   = "vmmc",
-       .dev_name = "mmci-omap-hs.1",
-};
+static struct regulator_consumer_supply rx51_vaux3_supply =
+       REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1");
 
-static struct regulator_consumer_supply rx51_vsim_supply = {
-       .supply   = "vmmc_aux",
-       .dev_name = "mmci-omap-hs.1",
-};
+static struct regulator_consumer_supply rx51_vsim_supply =
+       REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1");
 
 static struct regulator_consumer_supply rx51_vmmc2_supplies[] = {
        /* tlv320aic3x analog supplies */
-       {
-               .supply         = "AVDD",
-               .dev_name       = "2-0018",
-       },
-       {
-               .supply         = "DRVDD",
-               .dev_name       = "2-0018",
-       },
+       REGULATOR_SUPPLY("AVDD", "2-0018"),
+       REGULATOR_SUPPLY("DRVDD", "2-0018"),
+       /* tpa6130a2 */
+       REGULATOR_SUPPLY("Vdd", "2-0060"),
        /* Keep vmmc as last item. It is not iterated for newer boards */
-       {
-               .supply         = "vmmc",
-               .dev_name       = "mmci-omap-hs.1",
-       },
+       REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"),
 };
 
 static struct regulator_consumer_supply rx51_vio_supplies[] = {
        /* tlv320aic3x digital supplies */
-       {
-               .supply         = "IOVDD",
-               .dev_name       = "2-0018"
-       },
-       {
-               .supply         = "DVDD",
-               .dev_name       = "2-0018"
-       },
+       REGULATOR_SUPPLY("IOVDD", "2-0018"),
+       REGULATOR_SUPPLY("DVDD", "2-0018"),
 };
 
 #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
@@ -373,6 +364,7 @@ static struct regulator_init_data rx51_vaux1 = {
                .name                   = "V28",
                .min_uV                 = 2800000,
                .max_uV                 = 2800000,
+               .always_on              = true, /* due battery cover sensor */
                .valid_modes_mask       = REGULATOR_MODE_NORMAL
                                        | REGULATOR_MODE_STANDBY,
                .valid_ops_mask         = REGULATOR_CHANGE_MODE
@@ -718,6 +710,15 @@ static struct twl4030_platform_data rx51_twldata __initdata = {
        .vio                    = &rx51_vio,
 };
 
+static struct aic3x_pdata rx51_aic3x_data __initdata = {
+       .gpio_reset             = 60,
+};
+
+static struct tpa6130a2_platform_data rx51_tpa6130a2_data __initdata = {
+       .id                     = TPA6130A2,
+       .power_gpio             = 98,
+};
+
 static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_1[] = {
        {
                I2C_BOARD_INFO("twl5030", 0x48),
@@ -730,7 +731,18 @@ static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_1[] = {
 static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = {
        {
                I2C_BOARD_INFO("tlv320aic3x", 0x18),
+               .platform_data = &rx51_aic3x_data,
+       },
+#if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE)
+       {
+               I2C_BOARD_INFO("tsl2563", 0x29),
+               .platform_data = &rx51_tsl2563_platform_data,
        },
+#endif
+       {
+               I2C_BOARD_INFO("tpa6130a2", 0x60),
+               .platform_data = &rx51_tpa6130a2_data,
+       }
 };
 
 static int __init rx51_i2c_init(void)

diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c
index b743a4f426492ca8fcc8a851ac7d526b4d2f6409..5a1005ba9815541777641f6ed7b446273c123e59 100644 (file)
--- a/arch/arm/mach-omap2/board-rx51-video.c
+++ b/arch/arm/mach-omap2/board-rx51-video.c
@@ -16,7 +16,6 @@
 #include <linux/mm.h>
 
 #include <asm/mach-types.h>
-#include <plat/mux.h>
 #include <plat/display.h>
 #include <plat/vram.h>
 #include <plat/mcspi.h>

diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 1b86b5bb87a219bc89d3703131c2d70c28181d04..a58e8cb1a7fc9abf639225bed3fa5de8cc3187c9 100644 (file)
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -143,7 +143,7 @@ static void __init rx51_init(void)
 
 static void __init rx51_map_io(void)
 {
-       omap2_set_globals_343x();
+       omap2_set_globals_3xxx();
        rx51_video_mem_init();
        omap34xx_map_common_io();
 }
@@ -154,6 +154,7 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
        .boot_params    = 0x80000100,
        .map_io         = rx51_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = rx51_init_irq,
        .init_machine   = rx51_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c
index 803ef14cbf2d64ca3218e56ce4e48572088fe67f..3ad9ecf7f5e2b32d2361ae1df84aaa54b63013f8 100644 (file)
--- a/arch/arm/mach-omap2/board-zoom2.c
+++ b/arch/arm/mach-omap2/board-zoom2.c
@@ -71,30 +71,81 @@ static struct twl4030_platform_data zoom2_twldata = {
 
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
+       /* WLAN IRQ - GPIO 162 */
+       OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
+       /* WLAN POWER ENABLE - GPIO 101 */
+       OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+       /* WLAN SDIO: MMC3 CMD */
+       OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP),
+       /* WLAN SDIO: MMC3 CLK */
+       OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
+       /* WLAN SDIO: MMC3 DAT[0-3] */
+       OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
+       OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
+       OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
+       OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
        { .reg_offset = OMAP_MUX_TERMINATOR },
 };
 #else
 #define board_mux      NULL
 #endif
 
+static struct mtd_partition zoom_nand_partitions[] = {
+       /* All the partition sizes are listed in terms of NAND block size */
+       {
+               .name           = "X-Loader-NAND",
+               .offset         = 0,
+               .size           = 4 * (64 * 2048),      /* 512KB, 0x80000 */
+               .mask_flags     = MTD_WRITEABLE,        /* force read-only */
+       },
+       {
+               .name           = "U-Boot-NAND",
+               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x80000 */
+               .size           = 10 * (64 * 2048),     /* 1.25MB, 0x140000 */
+               .mask_flags     = MTD_WRITEABLE,        /* force read-only */
+       },
+       {
+               .name           = "Boot Env-NAND",
+               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x1c0000 */
+               .size           = 2 * (64 * 2048),      /* 256KB, 0x40000 */
+       },
+       {
+               .name           = "Kernel-NAND",
+               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x0200000*/
+               .size           = 240 * (64 * 2048),    /* 30M, 0x1E00000 */
+       },
+       {
+               .name           = "system",
+               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x2000000 */
+               .size           = 3328 * (64 * 2048),   /* 416M, 0x1A000000 */
+       },
+       {
+               .name           = "userdata",
+               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x1C000000*/
+               .size           = 256 * (64 * 2048),    /* 32M, 0x2000000 */
+       },
+       {
+               .name           = "cache",
+               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x1E000000*/
+               .size           = 256 * (64 * 2048),    /* 32M, 0x2000000 */
+       },
+};
+
 static void __init omap_zoom2_init(void)
 {
        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
        zoom_peripherals_init();
+       board_nand_init(zoom_nand_partitions,
+                       ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS);
        zoom_debugboard_init();
 }
 
-static void __init omap_zoom2_map_io(void)
-{
-       omap2_set_globals_343x();
-       omap34xx_map_common_io();
-}
-
 MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
        .phys_io        = ZOOM_UART_BASE,
        .io_pg_offst    = (ZOOM_UART_VIRT >> 18) & 0xfffc,
        .boot_params    = 0x80000100,
-       .map_io         = omap_zoom2_map_io,
+       .map_io         = omap3_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = omap_zoom2_init_irq,
        .init_machine   = omap_zoom2_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom3.c
index 33147042485f5f505c7a0906f2b0d94e02a9f460..6ca0b8341615efcbe628648bfe478bf9c1e91b35 100644 (file)
--- a/arch/arm/mach-omap2/board-zoom3.c
+++ b/arch/arm/mach-omap2/board-zoom3.c
@@ -25,15 +25,50 @@
 #include "mux.h"
 #include "sdram-hynix-h8mbx00u0mer-0em.h"
 
-static void __init omap_zoom_map_io(void)
-{
-       omap2_set_globals_36xx();
-       omap34xx_map_common_io();
-}
-
 static struct omap_board_config_kernel zoom_config[] __initdata = {
 };
 
+static struct mtd_partition zoom_nand_partitions[] = {
+       /* All the partition sizes are listed in terms of NAND block size */
+       {
+               .name           = "X-Loader-NAND",
+               .offset         = 0,
+               .size           = 4 * (64 * 2048),      /* 512KB, 0x80000 */
+               .mask_flags     = MTD_WRITEABLE,        /* force read-only */
+       },
+       {
+               .name           = "U-Boot-NAND",
+               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x80000 */
+               .size           = 10 * (64 * 2048),     /* 1.25MB, 0x140000 */
+               .mask_flags     = MTD_WRITEABLE,        /* force read-only */
+       },
+       {
+               .name           = "Boot Env-NAND",
+               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x1c0000 */
+               .size           = 2 * (64 * 2048),      /* 256KB, 0x40000 */
+       },
+       {
+               .name           = "Kernel-NAND",
+               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x0200000*/
+               .size           = 240 * (64 * 2048),    /* 30M, 0x1E00000 */
+       },
+       {
+               .name           = "system",
+               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x2000000 */
+               .size           = 3328 * (64 * 2048),   /* 416M, 0x1A000000 */
+       },
+       {
+               .name           = "userdata",
+               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x1C000000*/
+               .size           = 256 * (64 * 2048),    /* 32M, 0x2000000 */
+       },
+       {
+               .name           = "cache",
+               .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x1E000000*/
+               .size           = 256 * (64 * 2048),    /* 32M, 0x2000000 */
+       },
+};
+
 static void __init omap_zoom_init_irq(void)
 {
        omap_board_config = zoom_config;
@@ -46,6 +81,19 @@ static void __init omap_zoom_init_irq(void)
 
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
+       /* WLAN IRQ - GPIO 162 */
+       OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
+       /* WLAN POWER ENABLE - GPIO 101 */
+       OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+       /* WLAN SDIO: MMC3 CMD */
+       OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP),
+       /* WLAN SDIO: MMC3 CLK */
+       OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
+       /* WLAN SDIO: MMC3 DAT[0-3] */
+       OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
+       OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
+       OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
+       OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
        { .reg_offset = OMAP_MUX_TERMINATOR },
 };
 #else
@@ -66,6 +114,8 @@ static void __init omap_zoom_init(void)
 {
        omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
        zoom_peripherals_init();
+       board_nand_init(zoom_nand_partitions,
+                        ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS);
        zoom_debugboard_init();
 
        omap_mux_init_gpio(64, OMAP_PIN_OUTPUT);
@@ -76,7 +126,8 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
        .phys_io        = ZOOM_UART_BASE,
        .io_pg_offst    = (ZOOM_UART_VIRT >> 18) & 0xfffc,
        .boot_params    = 0x80000100,
-       .map_io         = omap_zoom_map_io,
+       .map_io         = omap3_map_io,
+       .reserve        = omap_reserve,
        .init_irq       = omap_zoom_init_irq,
        .init_machine   = omap_zoom_init,
        .timer          = &omap_timer,

diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 41b155acfca7cf2605202f78ffbe45a84ebf594a..138646deac8932210cc6168ab647444908c92b85 100644 (file)
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -1408,7 +1408,7 @@ static struct clk ts_fck = {
 
 static struct clk usbtll_fck = {
        .name           = "usbtll_fck",
-       .ops            = &clkops_omap2_dflt,
+       .ops            = &clkops_omap2_dflt_wait,
        .parent         = &dpll5_m2_ck,
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
        .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
@@ -3166,6 +3166,10 @@ static struct clk uart4_ick_am35xx = {
        .recalc         = &followparent_recalc,
 };
 
+static struct clk dummy_apb_pclk = {
+       .name           = "apb_pclk",
+       .ops            = &clkops_null,
+};
 
 /*
  * clkdev
@@ -3173,6 +3177,7 @@ static struct clk uart4_ick_am35xx = {
 
 /* XXX At some point we should rename this file to clock3xxx_data.c */
 static struct omap_clk omap3xxx_clks[] = {
+       CLK(NULL,       "apb_pclk",     &dummy_apb_pclk,        CK_3XXX),
        CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_3XXX),
        CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_3XXX),
        CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_3XXX),

diff --git a/arch/arm/mach-omap2/cm.c b/arch/arm/mach-omap2/cm.c
index 2d83565d2be29b8d0be4ea06f4208aaf593378bb..721c3b66740acd1475793c6ee4029c65e8db3815 100644 (file)
--- a/arch/arm/mach-omap2/cm.c
+++ b/arch/arm/mach-omap2/cm.c
@@ -50,15 +50,15 @@ int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
 
        cm_idlest_reg = cm_idlest_offs[idlest_id - 1];
 
+       mask = 1 << idlest_shift;
+
        if (cpu_is_omap24xx())
-               ena = idlest_shift;
+               ena = mask;
        else if (cpu_is_omap34xx())
                ena = 0;
        else
                BUG();
 
-       mask = 1 << idlest_shift;
-
        /* XXX should be OMAP2 CM */
        omap_test_timeout(((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
                          MAX_MODULE_READY_TIME, i);

diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 44902405fb63370c115290d7a27a3608d14ed3f9..2dbb265bedd4e914c6ceac472dbe9a0b8bddbf0b 100644 (file)
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -25,7 +25,6 @@
 #include <plat/control.h>
 #include <plat/tc.h>
 #include <plat/board.h>
-#include <plat/mux.h>
 #include <mach/gpio.h>
 #include <plat/mmc.h>
 #include <plat/dma.h>
@@ -234,64 +233,7 @@ static inline void omap_init_mbox(void)
 static inline void omap_init_mbox(void) { }
 #endif /* CONFIG_OMAP_MBOX_FWK */
 
-#if defined(CONFIG_OMAP_STI)
-
-#if defined(CONFIG_ARCH_OMAP2)
-
-#define OMAP2_STI_BASE         0x48068000
-#define OMAP2_STI_CHANNEL_BASE 0x54000000
-#define OMAP2_STI_IRQ          4
-
-static struct resource sti_resources[] = {
-       {
-               .start          = OMAP2_STI_BASE,
-               .end            = OMAP2_STI_BASE + 0x7ff,
-               .flags          = IORESOURCE_MEM,
-       },
-       {
-               .start          = OMAP2_STI_CHANNEL_BASE,
-               .end            = OMAP2_STI_CHANNEL_BASE + SZ_64K - 1,
-               .flags          = IORESOURCE_MEM,
-       },
-       {
-               .start          = OMAP2_STI_IRQ,
-               .flags          = IORESOURCE_IRQ,
-       }
-};
-#elif defined(CONFIG_ARCH_OMAP3)
-
-#define OMAP3_SDTI_BASE                0x54500000
-#define OMAP3_SDTI_CHANNEL_BASE        0x54600000
-
-static struct resource sti_resources[] = {
-       {
-               .start          = OMAP3_SDTI_BASE,
-               .end            = OMAP3_SDTI_BASE + 0xFFF,
-               .flags          = IORESOURCE_MEM,
-       },
-       {
-               .start          = OMAP3_SDTI_CHANNEL_BASE,
-               .end            = OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1,
-               .flags          = IORESOURCE_MEM,
-       }
-};
-
-#endif
-
-static struct platform_device sti_device = {
-       .name           = "sti",
-       .id             = -1,
-       .num_resources  = ARRAY_SIZE(sti_resources),
-       .resource       = sti_resources,
-};
-
-static inline void omap_init_sti(void)
-{
-       platform_device_register(&sti_device);
-}
-#else
 static inline void omap_init_sti(void) {}
-#endif
 
 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
 
@@ -676,19 +618,19 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
                                        OMAP_PIN_INPUT_PULLUP);
 
        if (cpu_is_omap2420() && controller_nr == 0) {
-               omap_cfg_reg(H18_24XX_MMC_CMD);
-               omap_cfg_reg(H15_24XX_MMC_CLKI);
-               omap_cfg_reg(G19_24XX_MMC_CLKO);
-               omap_cfg_reg(F20_24XX_MMC_DAT0);
-               omap_cfg_reg(F19_24XX_MMC_DAT_DIR0);
-               omap_cfg_reg(G18_24XX_MMC_CMD_DIR);
+               omap_mux_init_signal("sdmmc_cmd", 0);
+               omap_mux_init_signal("sdmmc_clki", 0);
+               omap_mux_init_signal("sdmmc_clko", 0);
+               omap_mux_init_signal("sdmmc_dat0", 0);
+               omap_mux_init_signal("sdmmc_dat_dir0", 0);
+               omap_mux_init_signal("sdmmc_cmd_dir", 0);
                if (mmc_controller->slots[0].wires == 4) {
-                       omap_cfg_reg(H14_24XX_MMC_DAT1);
-                       omap_cfg_reg(E19_24XX_MMC_DAT2);
-                       omap_cfg_reg(D19_24XX_MMC_DAT3);
-                       omap_cfg_reg(E20_24XX_MMC_DAT_DIR1);
-                       omap_cfg_reg(F18_24XX_MMC_DAT_DIR2);
-                       omap_cfg_reg(E18_24XX_MMC_DAT_DIR3);
+                       omap_mux_init_signal("sdmmc_dat1", 0);
+                       omap_mux_init_signal("sdmmc_dat2", 0);
+                       omap_mux_init_signal("sdmmc_dat3", 0);
+                       omap_mux_init_signal("sdmmc_dat_dir1", 0);
+                       omap_mux_init_signal("sdmmc_dat_dir2", 0);
+                       omap_mux_init_signal("sdmmc_dat_dir3", 0);
                }
 
                /*

diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index e57fb29ff855b484e5339abfbb563259c7390140..72220960192750473128ae3c6fd165e84e7161aa 100644 (file)
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -19,8 +19,6 @@
 #include <plat/board.h>
 #include <plat/gpmc.h>
 
-#define WR_RD_PIN_MONITORING   0x00600000
-
 static struct omap_nand_platform_data *gpmc_nand_data;
 
 static struct resource gpmc_nand_resource = {
@@ -71,10 +69,10 @@ static int omap2_nand_gpmc_retime(void)
        t.wr_cycle  = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle);
 
        /* Configure GPMC */
-       gpmc_cs_write_reg(gpmc_nand_data->cs, GPMC_CS_CONFIG1,
-                       GPMC_CONFIG1_DEVICESIZE(gpmc_nand_data->devsize) |
-                       GPMC_CONFIG1_DEVICETYPE_NAND);
-
+       gpmc_cs_configure(gpmc_nand_data->cs,
+                               GPMC_CONFIG_DEV_SIZE, gpmc_nand_data->devsize);
+       gpmc_cs_configure(gpmc_nand_data->cs,
+                       GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND);
        err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
        if (err)
                return err;
@@ -82,27 +80,13 @@ static int omap2_nand_gpmc_retime(void)
        return 0;
 }
 
-static int gpmc_nand_setup(void)
-{
-       struct device *dev = &gpmc_nand_device.dev;
-
-       /* Set timings in GPMC */
-       if (omap2_nand_gpmc_retime() < 0) {
-               dev_err(dev, "Unable to set gpmc timings\n");
-               return -EINVAL;
-       }
-
-       return 0;
-}
-
 int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data)
 {
-       unsigned int val;
        int err = 0;
        struct device *dev = &gpmc_nand_device.dev;
 
        gpmc_nand_data = _nand_data;
-       gpmc_nand_data->nand_setup = gpmc_nand_setup;
+       gpmc_nand_data->nand_setup = omap2_nand_gpmc_retime;
        gpmc_nand_device.dev.platform_data = gpmc_nand_data;
 
        err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
@@ -112,19 +96,16 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data)
                return err;
        }
 
-       err = gpmc_nand_setup();
+        /* Set timings in GPMC */
+       err = omap2_nand_gpmc_retime();
        if (err < 0) {
-               dev_err(dev, "NAND platform setup failed: %d\n", err);
+               dev_err(dev, "Unable to set gpmc timings: %d\n", err);
                return err;
        }
 
        /* Enable RD PIN Monitoring Reg */
        if (gpmc_nand_data->dev_ready) {
-               val  = gpmc_cs_read_reg(gpmc_nand_data->cs,
-                                                GPMC_CS_CONFIG1);
-               val |= WR_RD_PIN_MONITORING;
-               gpmc_cs_write_reg(gpmc_nand_data->cs,
-                                               GPMC_CS_CONFIG1, val);
+               gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1);
        }
 
        err = platform_device_register(&gpmc_nand_device);

diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 5bc3ca03551c23656e7d46732b5ccfe495e1a72a..f46933bc9373495c3094b6b98d7ebe12b0768238 100644 (file)
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -46,8 +46,9 @@
 #define GPMC_ECC_CONFIG                0x1f4
 #define GPMC_ECC_CONTROL       0x1f8
 #define GPMC_ECC_SIZE_CONFIG   0x1fc
+#define GPMC_ECC1_RESULT        0x200
 
-#define GPMC_CS0               0x60
+#define GPMC_CS0_OFFSET                0x60
 #define GPMC_CS_SIZE           0x30
 
 #define GPMC_MEM_START         0x00000000
@@ -92,7 +93,8 @@ struct omap3_gpmc_regs {
 static struct resource gpmc_mem_root;
 static struct resource gpmc_cs_mem[GPMC_CS_NUM];
 static DEFINE_SPINLOCK(gpmc_mem_lock);
-static unsigned                gpmc_cs_map;
+static unsigned int gpmc_cs_map;       /* flag for cs which are initialized */
+static int gpmc_ecc_used = -EINVAL;    /* cs using ecc engine */
 
 static void __iomem *gpmc_base;
 
@@ -108,11 +110,27 @@ static u32 gpmc_read_reg(int idx)
        return __raw_readl(gpmc_base + idx);
 }
 
+static void gpmc_cs_write_byte(int cs, int idx, u8 val)
+{
+       void __iomem *reg_addr;
+
+       reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
+       __raw_writeb(val, reg_addr);
+}
+
+static u8 gpmc_cs_read_byte(int cs, int idx)
+{
+       void __iomem *reg_addr;
+
+       reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
+       return __raw_readb(reg_addr);
+}
+
 void gpmc_cs_write_reg(int cs, int idx, u32 val)
 {
        void __iomem *reg_addr;
 
-       reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
+       reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
        __raw_writel(val, reg_addr);
 }
 
@@ -120,7 +138,7 @@ u32 gpmc_cs_read_reg(int cs, int idx)
 {
        void __iomem *reg_addr;
 
-       reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
+       reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
        return __raw_readl(reg_addr);
 }
 
@@ -418,9 +436,158 @@ void gpmc_cs_free(int cs)
 }
 EXPORT_SYMBOL(gpmc_cs_free);
 
+/**
+ * gpmc_read_status - read access request to get the different gpmc status
+ * @cmd: command type
+ * @return status
+ */
+int gpmc_read_status(int cmd)
+{
+       int     status = -EINVAL;
+       u32     regval = 0;
+
+       switch (cmd) {
+       case GPMC_GET_IRQ_STATUS:
+               status = gpmc_read_reg(GPMC_IRQSTATUS);
+               break;
+
+       case GPMC_PREFETCH_FIFO_CNT:
+               regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
+               status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval);
+               break;
+
+       case GPMC_PREFETCH_COUNT:
+               regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
+               status = GPMC_PREFETCH_STATUS_COUNT(regval);
+               break;
+
+       case GPMC_STATUS_BUFFER:
+               regval = gpmc_read_reg(GPMC_STATUS);
+               /* 1 : buffer is available to write */
+               status = regval & GPMC_STATUS_BUFF_EMPTY;
+               break;
+
+       default:
+               printk(KERN_ERR "gpmc_read_status: Not supported\n");
+       }
+       return status;
+}
+EXPORT_SYMBOL(gpmc_read_status);
+
+/**
+ * gpmc_cs_configure - write request to configure gpmc
+ * @cs: chip select number
+ * @cmd: command type
+ * @wval: value to write
+ * @return status of the operation
+ */
+int gpmc_cs_configure(int cs, int cmd, int wval)
+{
+       int err = 0;
+       u32 regval = 0;
+
+       switch (cmd) {
+       case GPMC_SET_IRQ_STATUS:
+               gpmc_write_reg(GPMC_IRQSTATUS, wval);
+               break;
+
+       case GPMC_CONFIG_WP:
+               regval = gpmc_read_reg(GPMC_CONFIG);
+               if (wval)
+                       regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
+               else
+                       regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
+               gpmc_write_reg(GPMC_CONFIG, regval);
+               break;
+
+       case GPMC_CONFIG_RDY_BSY:
+               regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
+               if (wval)
+                       regval |= WR_RD_PIN_MONITORING;
+               else
+                       regval &= ~WR_RD_PIN_MONITORING;
+               gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
+               break;
+
+       case GPMC_CONFIG_DEV_SIZE:
+               regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
+               regval |= GPMC_CONFIG1_DEVICESIZE(wval);
+               gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
+               break;
+
+       case GPMC_CONFIG_DEV_TYPE:
+               regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
+               regval |= GPMC_CONFIG1_DEVICETYPE(wval);
+               if (wval == GPMC_DEVICETYPE_NOR)
+                       regval |= GPMC_CONFIG1_MUXADDDATA;
+               gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
+               break;
+
+       default:
+               printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
+               err = -EINVAL;
+       }
+
+       return err;
+}
+EXPORT_SYMBOL(gpmc_cs_configure);
+
+/**
+ * gpmc_nand_read - nand specific read access request
+ * @cs: chip select number
+ * @cmd: command type
+ */
+int gpmc_nand_read(int cs, int cmd)
+{
+       int rval = -EINVAL;
+
+       switch (cmd) {
+       case GPMC_NAND_DATA:
+               rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA);
+               break;
+
+       default:
+               printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n");
+       }
+       return rval;
+}
+EXPORT_SYMBOL(gpmc_nand_read);
+
+/**
+ * gpmc_nand_write - nand specific write request
+ * @cs: chip select number
+ * @cmd: command type
+ * @wval: value to write
+ */
+int gpmc_nand_write(int cs, int cmd, int wval)
+{
+       int err = 0;
+
+       switch (cmd) {
+       case GPMC_NAND_COMMAND:
+               gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval);
+               break;
+
+       case GPMC_NAND_ADDRESS:
+               gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval);
+               break;
+
+       case GPMC_NAND_DATA:
+               gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval);
+
+       default:
+               printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n");
+               err = -EINVAL;
+       }
+       return err;
+}
+EXPORT_SYMBOL(gpmc_nand_write);
+
+
+
 /**
  * gpmc_prefetch_enable - configures and starts prefetch transfer
- * @cs: nand cs (chip select) number
+ * @cs: cs (chip select) number
  * @dma_mode: dma mode enable (1) or disable (0)
  * @u32_count: number of bytes to be transferred
  * @is_write: prefetch read(0) or write post(1) mode
@@ -428,7 +595,6 @@ EXPORT_SYMBOL(gpmc_cs_free);
 int gpmc_prefetch_enable(int cs, int dma_mode,
                                unsigned int u32_count, int is_write)
 {
-       uint32_t prefetch_config1;
 
        if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
                /* Set the amount of bytes to be prefetched */
@@ -437,17 +603,17 @@ int gpmc_prefetch_enable(int cs, int dma_mode,
                /* Set dma/mpu mode, the prefetch read / post write and
                 * enable the engine. Set which cs is has requested for.
                 */
-               prefetch_config1 = ((cs << CS_NUM_SHIFT) |
+               gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
                                        PREFETCH_FIFOTHRESHOLD |
                                        ENABLE_PREFETCH |
                                        (dma_mode << DMA_MPU_MODE) |
-                                       (0x1 & is_write));
-               gpmc_write_reg(GPMC_PREFETCH_CONFIG1, prefetch_config1);
+                                       (0x1 & is_write)));
+
+               /*  Start the prefetch engine */
+               gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
        } else {
                return -EBUSY;
        }
-       /*  Start the prefetch engine */
-       gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
 
        return 0;
 }
@@ -456,24 +622,24 @@ EXPORT_SYMBOL(gpmc_prefetch_enable);
 /**
  * gpmc_prefetch_reset - disables and stops the prefetch engine
  */
-void gpmc_prefetch_reset(void)
+int gpmc_prefetch_reset(int cs)
 {
+       u32 config1;
+
+       /* check if the same module/cs is trying to reset */
+       config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
+       if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs)
+               return -EINVAL;
+
        /* Stop the PFPW engine */
        gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
 
        /* Reset/disable the PFPW engine */
        gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
-}
-EXPORT_SYMBOL(gpmc_prefetch_reset);
 
-/**
- * gpmc_prefetch_status - reads prefetch status of engine
- */
-int  gpmc_prefetch_status(void)
-{
-       return gpmc_read_reg(GPMC_PREFETCH_STATUS);
+       return 0;
 }
-EXPORT_SYMBOL(gpmc_prefetch_status);
+EXPORT_SYMBOL(gpmc_prefetch_reset);
 
 static void __init gpmc_mem_init(void)
 {
@@ -615,3 +781,79 @@ void omap3_gpmc_restore_context(void)
        }
 }
 #endif /* CONFIG_ARCH_OMAP3 */
+
+/**
+ * gpmc_enable_hwecc - enable hardware ecc functionality
+ * @cs: chip select number
+ * @mode: read/write mode
+ * @dev_width: device bus width(1 for x16, 0 for x8)
+ * @ecc_size: bytes for which ECC will be generated
+ */
+int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
+{
+       unsigned int val;
+
+       /* check if ecc module is in used */
+       if (gpmc_ecc_used != -EINVAL)
+               return -EINVAL;
+
+       gpmc_ecc_used = cs;
+
+       /* clear ecc and enable bits */
+       val = ((0x00000001<<8) | 0x00000001);
+       gpmc_write_reg(GPMC_ECC_CONTROL, val);
+
+       /* program ecc and result sizes */
+       val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F));
+       gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, val);
+
+       switch (mode) {
+       case GPMC_ECC_READ:
+               gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
+               break;
+       case GPMC_ECC_READSYN:
+                gpmc_write_reg(GPMC_ECC_CONTROL, 0x100);
+               break;
+       case GPMC_ECC_WRITE:
+               gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
+               break;
+       default:
+               printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode);
+               break;
+       }
+
+       /* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
+       val = (dev_width << 7) | (cs << 1) | (0x1);
+       gpmc_write_reg(GPMC_ECC_CONFIG, val);
+       return 0;
+}
+
+/**
+ * gpmc_calculate_ecc - generate non-inverted ecc bytes
+ * @cs: chip select number
+ * @dat: data pointer over which ecc is computed
+ * @ecc_code: ecc code buffer
+ *
+ * Using non-inverted ECC is considered ugly since writing a blank
+ * page (padding) will clear the ECC bytes. This is not a problem as long
+ * no one is trying to write data on the seemingly unused page. Reading
+ * an erased page will produce an ECC mismatch between generated and read
+ * ECC bytes that has to be dealt with separately.
+ */
+int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
+{
+       unsigned int val = 0x0;
+
+       if (gpmc_ecc_used != cs)
+               return -EINVAL;
+
+       /* read ecc result */
+       val = gpmc_read_reg(GPMC_ECC1_RESULT);
+       *ecc_code++ = val;          /* P128e, ..., P1e */
+       *ecc_code++ = val >> 16;    /* P128o, ..., P1o */
+       /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
+       *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
+
+       gpmc_ecc_used = -EINVAL;
+       return 0;
+}

diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
index 7951ae1447ee3c0ad64930f81ff577701d2f2b15..79c478c4cb1cc0696b62cb0e23ca53596588d14f 100644 (file)
--- a/arch/arm/mach-omap2/i2c.c
+++ b/arch/arm/mach-omap2/i2c.c
@@ -21,32 +21,19 @@
 
 #include <plat/cpu.h>
 #include <plat/i2c.h>
-#include <plat/mux.h>
 
 #include "mux.h"
 
 void __init omap2_i2c_mux_pins(int bus_id)
 {
-       if (cpu_is_omap24xx()) {
-               const int omap24xx_pins[][2] = {
-                       { M19_24XX_I2C1_SCL, L15_24XX_I2C1_SDA },
-                       { J15_24XX_I2C2_SCL, H19_24XX_I2C2_SDA },
-               };
-               int scl, sda;
-
-               scl = omap24xx_pins[bus_id - 1][0];
-               sda = omap24xx_pins[bus_id - 1][1];
-               omap_cfg_reg(sda);
-               omap_cfg_reg(scl);
-       }
+       char mux_name[sizeof("i2c2_scl.i2c2_scl")];
 
        /* First I2C bus is not muxable */
-       if (cpu_is_omap34xx() && bus_id > 1) {
-               char mux_name[sizeof("i2c2_scl.i2c2_scl")];
+       if (bus_id == 1)
+               return;
 
-               sprintf(mux_name, "i2c%i_scl.i2c%i_scl", bus_id, bus_id);
-               omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
-               sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id);
-               omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
-       }
+       sprintf(mux_name, "i2c%i_scl.i2c%i_scl", bus_id, bus_id);
+       omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
+       sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id);
+       omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
 }

diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 37b8a1a4adf869c8ee18e17beb419ddec9eb5981..e8256a2ed8e782dd56a7bfa674b98886a9f63e71 100644 (file)
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -25,6 +25,8 @@
 #include <plat/control.h>
 #include <plat/cpu.h>
 
+#include <mach/id.h>
+
 static struct omap_chip_id omap_chip;
 static unsigned int omap_revision;
 
@@ -102,30 +104,36 @@ static struct omap_id omap_ids[] __initdata = {
 static void __iomem *tap_base;
 static u16 tap_prod_id;
 
-void __init omap24xx_check_revision(void)
+void omap_get_die_id(struct omap_die_id *odi)
+{
+       odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
+       odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
+       odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
+       odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
+}
+
+static void __init omap24xx_check_revision(void)
 {
        int i, j;
        u32 idcode, prod_id;
        u16 hawkeye;
        u8  dev_type, rev;
+       struct omap_die_id odi;
 
        idcode = read_tap_reg(OMAP_TAP_IDCODE);
        prod_id = read_tap_reg(tap_prod_id);
        hawkeye = (idcode >> 12) & 0xffff;
        rev = (idcode >> 28) & 0x0f;
        dev_type = (prod_id >> 16) & 0x0f;
+       omap_get_die_id(&odi);
 
        pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
                 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
-       pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n",
-                read_tap_reg(OMAP_TAP_DIE_ID_0));
+       pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
        pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
-                read_tap_reg(OMAP_TAP_DIE_ID_1),
-                (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
-       pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n",
-                read_tap_reg(OMAP_TAP_DIE_ID_2));
-       pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n",
-                read_tap_reg(OMAP_TAP_DIE_ID_3));
+                odi.id_1, (odi.id_1 >> 28) & 0xf);
+       pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
+       pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
        pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
                 prod_id, dev_type);
 
@@ -164,7 +172,7 @@ void __init omap24xx_check_revision(void)
                omap3_features |= OMAP3_HAS_ ##feat;                    \
        }
 
-void __init omap3_check_features(void)
+static void __init omap3_check_features(void)
 {
        u32 status;
 
@@ -179,6 +187,8 @@ void __init omap3_check_features(void)
        OMAP3_CHECK_FEATURE(status, ISP);
        if (cpu_is_omap3630())
                omap3_features |= OMAP3_HAS_192MHZ_CLK;
+       if (!cpu_is_omap3505() && !cpu_is_omap3517())
+               omap3_features |= OMAP3_HAS_IO_WAKEUP;
 
        /*
         * TODO: Get additional info (where applicable)
@@ -186,7 +196,7 @@ void __init omap3_check_features(void)
         */
 }
 
-void __init omap3_check_revision(void)
+static void __init omap3_check_revision(void)
 {
        u32 cpuid, idcode;
        u16 hawkeye;
@@ -259,15 +269,31 @@ void __init omap3_check_revision(void)
                omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
                break;
        case 0xb891:
-       /* FALLTHROUGH */
+               /* Handle 36xx devices */
+               omap_chip.oc |= CHIP_IS_OMAP3630ES1;
+
+               switch(rev) {
+               case 0: /* Take care of early samples */
+                       omap_revision = OMAP3630_REV_ES1_0;
+                       break;
+               case 1:
+                       omap_revision = OMAP3630_REV_ES1_1;
+                       omap_chip.oc |= CHIP_IS_OMAP3630ES1_1;
+                       break;
+               case 2:
+               default:
+                       omap_revision =  OMAP3630_REV_ES1_2;
+                       omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
+                       break;
+               }
        default:
                /* Unknown default to latest silicon rev as default*/
-               omap_revision = OMAP3630_REV_ES1_0;
-               omap_chip.oc |= CHIP_IS_OMAP3630ES1;
+               omap_revision =  OMAP3630_REV_ES1_2;
+               omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
        }
 }
 
-void __init omap4_check_revision(void)
+static void __init omap4_check_revision(void)
 {
        u32 idcode;
        u16 hawkeye;
@@ -297,7 +323,7 @@ void __init omap4_check_revision(void)
        if (omap3_has_ ##feat())                \
                printk(#feat" ");
 
-void __init omap3_cpuinfo(void)
+static void __init omap3_cpuinfo(void)
 {
        u8 rev = GET_OMAP_REVISION();
        char cpu_name[16], cpu_rev[16];
@@ -339,6 +365,12 @@ void __init omap3_cpuinfo(void)
        case OMAP_REVBITS_00:
                strcpy(cpu_rev, "1.0");
                break;
+       case OMAP_REVBITS_01:
+               strcpy(cpu_rev, "1.1");
+               break;
+       case OMAP_REVBITS_02:
+               strcpy(cpu_rev, "1.2");
+               break;
        case OMAP_REVBITS_10:
                strcpy(cpu_rev, "2.0");
                break;

diff --git a/arch/arm/mach-omap2/include/mach/board-sdp.h b/arch/arm/mach-omap2/include/mach/board-flash.h
similarity index 71%
rename from arch/arm/mach-omap2/include/mach/board-sdp.h
rename to arch/arm/mach-omap2/include/mach/board-flash.h
index 465169c0908afb4e1fd3126e496b8f57e404ad8b..b2242ae2bb6fbea09dce14ad7103dd03b5394978 100644 (file)
--- a/arch/arm/mach-omap2/include/mach/board-sdp.h
+++ b/arch/arm/mach-omap2/include/mach/board-flash.h
@@ -12,10 +12,17 @@
  */
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+#include <plat/gpmc.h>
+
+#define PDC_NOR                1
+#define PDC_NAND       2
+#define PDC_ONENAND    3
+#define DBG_MPDB       4
 
 struct flash_partitions {
        struct mtd_partition *parts;
        int nr_parts;
 };
 
-extern void sdp_flash_init(struct flash_partitions []);
+extern void board_flash_init(struct flash_partitions [],
+                               char chip_sel[][GPMC_CS_NUM]);

diff --git a/arch/arm/mach-omap2/include/mach/board-zoom.h b/arch/arm/mach-omap2/include/mach/board-zoom.h
index c93b29e21b78afd28258bf6dc8fde504811d3fee..3af69d2c3dcde626a6f74cdff393cc3be7926201 100644 (file)
--- a/arch/arm/mach-omap2/include/mach/board-zoom.h
+++ b/arch/arm/mach-omap2/include/mach/board-zoom.h
@@ -1,5 +1,11 @@
 /*
  * Defines for zoom boards
  */
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#define ZOOM_NAND_CS    0
+
+extern void __init board_nand_init(struct mtd_partition *, u8 nr_parts, u8 cs);
 extern int __init zoom_debugboard_init(void);
 extern void __init zoom_peripherals_init(void);

diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index 35b24409a0c827a85e3c4e821f7c966d2602462e..09331bbbda52b66e267756b58cf8294472a010bb 100644 (file)
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -36,7 +36,7 @@ omap_uart_lsr:        .word   0
                /* Use omap_uart_phys/virt if already configured */
 10:            mrc     p15, 0, \rx, c1, c0
                tst     \rx, #1                 @ MMU enabled?
-               ldreq   \rx, =omap_uart_phys    @ physical base address
+               ldreq   \rx, =__virt_to_phys(omap_uart_phys)    @ physical base address
                ldrne   \rx, =omap_uart_virt    @ virtual base address
                ldr     \rx, [\rx, #0]
                cmp     \rx, #0                 @ is port configured?
@@ -89,26 +89,36 @@ omap_uart_lsr:      .word   0
 44:            mov     \rx, #UART_OFFSET(OMAP4_UART4_BASE)
                b       98f
 95:            ldr     \rx, =ZOOM_UART_BASE
-               ldr     \tmp, =omap_uart_phys
+               mrc     p15, 0, \tmp, c1, c0
+               tst     \tmp, #1                @ MMU enabled?
+               ldreq   \tmp, =__virt_to_phys(omap_uart_phys)
+               ldrne   \tmp, =omap_uart_phys
                str     \rx, [\tmp, #0]
                ldr     \rx, =ZOOM_UART_VIRT
-               ldr     \tmp, =omap_uart_virt
+               ldreq   \tmp, =__virt_to_phys(omap_uart_virt)
+               ldrne   \tmp, =omap_uart_virt
                str     \rx, [\tmp, #0]
                mov     \rx, #(UART_LSR << ZOOM_PORT_SHIFT)
-               ldr     \tmp, =omap_uart_lsr
+               ldreq   \tmp, =__virt_to_phys(omap_uart_lsr)
+               ldrne   \tmp, =omap_uart_lsr
                str     \rx, [\tmp, #0]
                b       10b
 
                /* Store both phys and virt address for the uart */
 98:            add     \rx, \rx, #0x48000000   @ phys base
-               ldr     \tmp, =omap_uart_phys
+               mrc     p15, 0, \tmp, c1, c0
+               tst     \tmp, #1                @ MMU enabled?
+               ldreq   \tmp, =__virt_to_phys(omap_uart_phys)
+               ldrne   \tmp, =omap_uart_phys
                str     \rx, [\tmp, #0]
                sub     \rx, \rx, #0x48000000   @ phys base
                add     \rx, \rx, #0xfa000000   @ virt base
-               ldr     \tmp, =omap_uart_virt
+               ldreq   \tmp, =__virt_to_phys(omap_uart_virt)
+               ldrne   \tmp, =omap_uart_virt
                str     \rx, [\tmp, #0]
                mov     \rx, #(UART_LSR << OMAP_PORT_SHIFT)
-               ldr     \tmp, =omap_uart_lsr
+               ldreq   \tmp, =__virt_to_phys(omap_uart_lsr)
+               ldrne   \tmp, =omap_uart_lsr
                str     \rx, [\tmp, #0]
 
                b       10b
@@ -120,7 +130,10 @@ omap_uart_lsr:     .word   0
                .endm
 
                .macro  busyuart,rd,rx
-1001:          ldr     \rd, =omap_uart_lsr
+1001:          mrc     p15, 0, \rd, c1, c0
+               tst     \rd, #1         @ MMU enabled?
+               ldreq   \rd, =__virt_to_phys(omap_uart_lsr)
+               ldrne   \rd, =omap_uart_lsr
                ldr     \rd, [\rd, #0]
                ldrb    \rd, [\rx, \rd]
                and     \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE)

diff --git a/arch/arm/mach-omap2/include/mach/id.h b/arch/arm/mach-omap2/include/mach/id.h
new file mode 100644 (file)
index 0000000..02ed3aa
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/id.h
@@ -0,0 +1,22 @@
+/*
+ * OMAP2 CPU identification code
+ *
+ * Copyright (C) 2010 Kan-Ru Chen <kanru@0xlab.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef OMAP2_ARCH_ID_H
+#define OMAP2_ARCH_ID_H
+
+struct omap_die_id {
+       u32 id_0;
+       u32 id_1;
+       u32 id_2;
+       u32 id_3;
+};
+
+void omap_get_die_id(struct omap_die_id *odi);
+
+#endif

diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h
index 423af3a6dd31489ee72bee8cf30ad1b5506b41b4..2744dfee1ff4875cad6e6b2faac9a292020e2065 100644 (file)
--- a/arch/arm/mach-omap2/include/mach/omap4-common.h
+++ b/arch/arm/mach-omap2/include/mach/omap4-common.h
@@ -13,6 +13,13 @@
 #ifndef OMAP_ARCH_OMAP4_COMMON_H
 #define OMAP_ARCH_OMAP4_COMMON_H
 
+/*
+ * wfi used in low power code. Directly opcode is used instead
+ * of instruction to avoid mulit-omap build break
+ */
+#define do_wfi()                       \
+               __asm__ __volatile__ (".word    0xe320f003" : : : "memory")
+
 #ifdef CONFIG_CACHE_L2X0
 extern void __iomem *l2cache_base;
 #endif

diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 3cfb425ea67e86585f66e1595b29e2c28b4d31ea..b9ea70bce5635d431ef2651058bd72b0619420df 100644 (file)
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -28,12 +28,10 @@
 
 #include <asm/mach/map.h>
 
-#include <plat/mux.h>
 #include <plat/sram.h>
 #include <plat/sdrc.h>
 #include <plat/gpmc.h>
 #include <plat/serial.h>
-#include <plat/vram.h>
 
 #include "clock2xxx.h"
 #include "clock3xxx.h"
@@ -45,6 +43,7 @@
 
 #include <plat/clockdomain.h>
 #include "clockdomains.h"
+
 #include <plat/omap_hwmod.h>
 
 /*
@@ -241,8 +240,6 @@ static void __init _omap2_map_common_io(void)
 
        omap2_check_revision();
        omap_sram_init();
-       omapfb_reserve_sdram();
-       omap_vram_reserve_sdram();
 }
 
 #ifdef CONFIG_ARCH_OMAP2420
@@ -316,6 +313,8 @@ static int __init _omap2_init_reprogram_sdrc(void)
 void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
                                 struct omap_sdrc_params *sdrc_cs1)
 {
+       u8 skip_setup_idle = 0;
+
        pwrdm_init(powerdomains_omap);
        clkdm_init(clockdomains_omap, clkdm_autodeps);
        if (cpu_is_omap242x())
@@ -324,7 +323,6 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
                omap2430_hwmod_init();
        else if (cpu_is_omap34xx())
                omap3xxx_hwmod_init();
-       omap2_mux_init();
        /* The OPP tables have to be registered before a clk init */
        omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
 
@@ -340,9 +338,13 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
                pr_err("Could not init clock framework - unknown CPU\n");
 
        omap_serial_early_init();
+
+#ifndef CONFIG_PM_RUNTIME
+       skip_setup_idle = 1;
+#endif
        if (cpu_is_omap24xx() || cpu_is_omap34xx())   /* FIXME: OMAP4 */
-               omap_hwmod_late_init();
-       omap_pm_if_init();
+               omap_hwmod_late_init(skip_setup_idle);
+
        if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
                omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
                _omap2_init_reprogram_sdrc();

diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
index e82da680d908915ead83a2018f9d9e2b11042b8b..14ee686b64923c94f89303eb2ed2dfd1a8971838 100644 (file)
--- a/arch/arm/mach-omap2/iommu2.c
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -44,9 +44,13 @@
 #define MMU_IRQ_EMUMISS                (1 << 2)
 #define MMU_IRQ_TRANSLATIONFAULT       (1 << 1)
 #define MMU_IRQ_TLBMISS                (1 << 0)
-#define MMU_IRQ_MASK   \
-       (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_EMUMISS | \
-        MMU_IRQ_TRANSLATIONFAULT)
+
+#define __MMU_IRQ_FAULT                \
+       (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
+#define MMU_IRQ_MASK           \
+       (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
+#define MMU_IRQ_TWL_MASK       (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
+#define MMU_IRQ_TLB_MISS_MASK  (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)
 
 /* MMU_CNTL */
 #define MMU_CNTL_SHIFT         1
@@ -61,6 +65,26 @@
         ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 :    \
         ((pgsz) == MMU_CAM_PGSZ_4K)  ? 0xfffff000 : 0)
 
+
+static void __iommu_set_twl(struct iommu *obj, bool on)
+{
+       u32 l = iommu_read_reg(obj, MMU_CNTL);
+
+       if (on)
+               iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
+       else
+               iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
+
+       l &= ~MMU_CNTL_MASK;
+       if (on)
+               l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
+       else
+               l |= (MMU_CNTL_MMU_EN);
+
+       iommu_write_reg(obj, l, MMU_CNTL);
+}
+
+
 static int omap2_iommu_enable(struct iommu *obj)
 {
        u32 l, pa;
@@ -96,13 +120,9 @@ static int omap2_iommu_enable(struct iommu *obj)
        l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE);
        iommu_write_reg(obj, l, MMU_SYSCONFIG);
 
-       iommu_write_reg(obj, MMU_IRQ_MASK, MMU_IRQENABLE);
        iommu_write_reg(obj, pa, MMU_TTB);
 
-       l = iommu_read_reg(obj, MMU_CNTL);
-       l &= ~MMU_CNTL_MASK;
-       l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
-       iommu_write_reg(obj, l, MMU_CNTL);
+       __iommu_set_twl(obj, true);
 
        return 0;
 }
@@ -118,6 +138,11 @@ static void omap2_iommu_disable(struct iommu *obj)
        dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
 }
 
+static void omap2_iommu_set_twl(struct iommu *obj, bool on)
+{
+       __iommu_set_twl(obj, false);
+}
+
 static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
 {
        int i;
@@ -147,7 +172,7 @@ static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
        printk("\n");
 
        iommu_write_reg(obj, stat, MMU_IRQSTATUS);
-       omap2_iommu_disable(obj);
+
        return stat;
 }
 
@@ -300,6 +325,7 @@ static const struct iommu_functions omap2_iommu_ops = {
 
        .enable         = omap2_iommu_enable,
        .disable        = omap2_iommu_disable,
+       .set_twl        = omap2_iommu_set_twl,
        .fault_isr      = omap2_iommu_fault_isr,
 
        .tlb_read_cr    = omap2_tlb_read_cr,

diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index c29337074ad37be754264c44add9ff84ee93b110..87aa4c9597cc031cca2e16f4679fa6db18705714 100644 (file)
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -20,17 +20,18 @@
 
 #include <mach/irqs.h>
 #include <plat/dma.h>
-#include <plat/mux.h>
 #include <plat/cpu.h>
 #include <plat/mcbsp.h>
 
+#include "mux.h"
+
 static void omap2_mcbsp2_mux_setup(void)
 {
-       omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
-       omap_cfg_reg(R14_24XX_MCBSP2_FSX);
-       omap_cfg_reg(W15_24XX_MCBSP2_DR);
-       omap_cfg_reg(V15_24XX_MCBSP2_DX);
-       omap_cfg_reg(V14_24XX_GPIO117);
+       omap_mux_init_signal("eac_ac_sclk.mcbsp2_clkx", OMAP_PULL_ENA);
+       omap_mux_init_signal("eac_ac_fs.mcbsp2_fsx", OMAP_PULL_ENA);
+       omap_mux_init_signal("eac_ac_din.mcbsp2_dr", OMAP_PULL_ENA);
+       omap_mux_init_signal("eac_ac_dout.mcbsp2_dx", OMAP_PULL_ENA);
+       omap_mux_init_gpio(117, OMAP_PULL_ENA);
        /*
         * TODO: Need to add MUX settings for OMAP 2430 SDP
         */

diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 8b3d26935a39423c927b73287d1f60fec31ee996..ab403b2ed26befb6058309e26e3b75688eb46905 100644 (file)
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -37,12 +37,12 @@
 #include <asm/system.h>
 
 #include <plat/control.h>
-#include <plat/mux.h>
 
 #include "mux.h"
 
 #define OMAP_MUX_BASE_OFFSET           0x30    /* Offset from CTRL_BASE */
 #define OMAP_MUX_BASE_SZ               0x5ca
+#define MUXABLE_GPIO_MODE3             BIT(0)
 
 struct omap_mux_entry {
        struct omap_mux         mux;
@@ -51,6 +51,7 @@ struct omap_mux_entry {
 
 static unsigned long mux_phys;
 static void __iomem *mux_base;
+static u8 omap_mux_flags;
 
 u16 omap_mux_read(u16 reg)
 {
@@ -76,301 +77,6 @@ void omap_mux_write_array(struct omap_board_mux *board_mux)
        }
 }
 
-#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_OMAP_MUX)
-
-static struct omap_mux_cfg arch_mux_cfg;
-
-/* NOTE: See mux.h for the enumeration */
-
-static struct pin_config __initdata_or_module omap24xx_pins[] = {
-/*
- *     description                     mux     mux     pull    pull    debug
- *                                     offset  mode    ena     type
- */
-
-/* 24xx I2C */
-MUX_CFG_24XX("M19_24XX_I2C1_SCL",      0x111,  0,      0,      0,      1)
-MUX_CFG_24XX("L15_24XX_I2C1_SDA",      0x112,  0,      0,      0,      1)
-MUX_CFG_24XX("J15_24XX_I2C2_SCL",      0x113,  0,      0,      1,      1)
-MUX_CFG_24XX("H19_24XX_I2C2_SDA",      0x114,  0,      0,      0,      1)
-
-/* Menelaus interrupt */
-MUX_CFG_24XX("W19_24XX_SYS_NIRQ",      0x12c,  0,      1,      1,      1)
-
-/* 24xx clocks */
-MUX_CFG_24XX("W14_24XX_SYS_CLKOUT",    0x137,  0,      1,      1,      1)
-
-/* 24xx GPMC chipselects, wait pin monitoring */
-MUX_CFG_24XX("E2_GPMC_NCS2",           0x08e,  0,      1,      1,      1)
-MUX_CFG_24XX("L2_GPMC_NCS7",           0x093,  0,      1,      1,      1)
-MUX_CFG_24XX("L3_GPMC_WAIT0",          0x09a,  0,      1,      1,      1)
-MUX_CFG_24XX("N7_GPMC_WAIT1",          0x09b,  0,      1,      1,      1)
-MUX_CFG_24XX("M1_GPMC_WAIT2",          0x09c,  0,      1,      1,      1)
-MUX_CFG_24XX("P1_GPMC_WAIT3",          0x09d,  0,      1,      1,      1)
-
-/* 24xx McBSP */
-MUX_CFG_24XX("Y15_24XX_MCBSP2_CLKX",   0x124,  1,      1,      0,      1)
-MUX_CFG_24XX("R14_24XX_MCBSP2_FSX",    0x125,  1,      1,      0,      1)
-MUX_CFG_24XX("W15_24XX_MCBSP2_DR",     0x126,  1,      1,      0,      1)
-MUX_CFG_24XX("V15_24XX_MCBSP2_DX",     0x127,  1,      1,      0,      1)
-
-/* 24xx GPIO */
-MUX_CFG_24XX("M21_242X_GPIO11",                0x0c9,  3,      1,      1,      1)
-MUX_CFG_24XX("P21_242X_GPIO12",                0x0ca,  3,      0,      0,      1)
-MUX_CFG_24XX("AA10_242X_GPIO13",       0x0e5,  3,      0,      0,      1)
-MUX_CFG_24XX("AA6_242X_GPIO14",                0x0e6,  3,      0,      0,      1)
-MUX_CFG_24XX("AA4_242X_GPIO15",                0x0e7,  3,      0,      0,      1)
-MUX_CFG_24XX("Y11_242X_GPIO16",                0x0e8,  3,      0,      0,      1)
-MUX_CFG_24XX("AA12_242X_GPIO17",       0x0e9,  3,      0,      0,      1)
-MUX_CFG_24XX("AA8_242X_GPIO58",                0x0ea,  3,      0,      0,      1)
-MUX_CFG_24XX("Y20_24XX_GPIO60",                0x12c,  3,      0,      0,      1)
-MUX_CFG_24XX("W4__24XX_GPIO74",                0x0f2,  3,      0,      0,      1)
-MUX_CFG_24XX("N15_24XX_GPIO85",                0x103,  3,      0,      0,      1)
-MUX_CFG_24XX("M15_24XX_GPIO92",                0x10a,  3,      0,      0,      1)
-MUX_CFG_24XX("P20_24XX_GPIO93",                0x10b,  3,      0,      0,      1)
-MUX_CFG_24XX("P18_24XX_GPIO95",                0x10d,  3,      0,      0,      1)
-MUX_CFG_24XX("M18_24XX_GPIO96",                0x10e,  3,      0,      0,      1)
-MUX_CFG_24XX("L14_24XX_GPIO97",                0x10f,  3,      0,      0,      1)
-MUX_CFG_24XX("J15_24XX_GPIO99",                0x113,  3,      1,      1,      1)
-MUX_CFG_24XX("V14_24XX_GPIO117",       0x128,  3,      1,      0,      1)
-MUX_CFG_24XX("P14_24XX_GPIO125",       0x140,  3,      1,      1,      1)
-
-/* 242x DBG GPIO */
-MUX_CFG_24XX("V4_242X_GPIO49",         0xd3,   3,      0,      0,      1)
-MUX_CFG_24XX("W2_242X_GPIO50",         0xd4,   3,      0,      0,      1)
-MUX_CFG_24XX("U4_242X_GPIO51",         0xd5,   3,      0,      0,      1)
-MUX_CFG_24XX("V3_242X_GPIO52",         0xd6,   3,      0,      0,      1)
-MUX_CFG_24XX("V2_242X_GPIO53",         0xd7,   3,      0,      0,      1)
-MUX_CFG_24XX("V6_242X_GPIO53",         0xcf,   3,      0,      0,      1)
-MUX_CFG_24XX("T4_242X_GPIO54",         0xd8,   3,      0,      0,      1)
-MUX_CFG_24XX("Y4_242X_GPIO54",         0xd0,   3,      0,      0,      1)
-MUX_CFG_24XX("T3_242X_GPIO55",         0xd9,   3,      0,      0,      1)
-MUX_CFG_24XX("U2_242X_GPIO56",         0xda,   3,      0,      0,      1)
-
-/* 24xx external DMA requests */
-MUX_CFG_24XX("AA10_242X_DMAREQ0",      0x0e5,  2,      0,      0,      1)
-MUX_CFG_24XX("AA6_242X_DMAREQ1",       0x0e6,  2,      0,      0,      1)
-MUX_CFG_24XX("E4_242X_DMAREQ2",                0x074,  2,      0,      0,      1)
-MUX_CFG_24XX("G4_242X_DMAREQ3",                0x073,  2,      0,      0,      1)
-MUX_CFG_24XX("D3_242X_DMAREQ4",                0x072,  2,      0,      0,      1)
-MUX_CFG_24XX("E3_242X_DMAREQ5",                0x071,  2,      0,      0,      1)
-
-/* UART3 */
-MUX_CFG_24XX("K15_24XX_UART3_TX",      0x118,  0,      0,      0,      1)
-MUX_CFG_24XX("K14_24XX_UART3_RX",      0x119,  0,      0,      0,      1)
-
-/* MMC/SDIO */
-MUX_CFG_24XX("G19_24XX_MMC_CLKO",      0x0f3,  0,      0,      0,      1)
-MUX_CFG_24XX("H18_24XX_MMC_CMD",       0x0f4,  0,      0,      0,      1)
-MUX_CFG_24XX("F20_24XX_MMC_DAT0",      0x0f5,  0,      0,      0,      1)
-MUX_CFG_24XX("H14_24XX_MMC_DAT1",      0x0f6,  0,      0,      0,      1)
-MUX_CFG_24XX("E19_24XX_MMC_DAT2",      0x0f7,  0,      0,      0,      1)
-MUX_CFG_24XX("D19_24XX_MMC_DAT3",      0x0f8,  0,      0,      0,      1)
-MUX_CFG_24XX("F19_24XX_MMC_DAT_DIR0",  0x0f9,  0,      0,      0,      1)
-MUX_CFG_24XX("E20_24XX_MMC_DAT_DIR1",  0x0fa,  0,      0,      0,      1)
-MUX_CFG_24XX("F18_24XX_MMC_DAT_DIR2",  0x0fb,  0,      0,      0,      1)
-MUX_CFG_24XX("E18_24XX_MMC_DAT_DIR3",  0x0fc,  0,      0,      0,      1)
-MUX_CFG_24XX("G18_24XX_MMC_CMD_DIR",   0x0fd,  0,      0,      0,      1)
-MUX_CFG_24XX("H15_24XX_MMC_CLKI",      0x0fe,  0,      0,      0,      1)
-
-/* Full speed USB */
-MUX_CFG_24XX("J20_24XX_USB0_PUEN",     0x11d,  0,      0,      0,      1)
-MUX_CFG_24XX("J19_24XX_USB0_VP",       0x11e,  0,      0,      0,      1)
-MUX_CFG_24XX("K20_24XX_USB0_VM",       0x11f,  0,      0,      0,      1)
-MUX_CFG_24XX("J18_24XX_USB0_RCV",      0x120,  0,      0,      0,      1)
-MUX_CFG_24XX("K19_24XX_USB0_TXEN",     0x121,  0,      0,      0,      1)
-MUX_CFG_24XX("J14_24XX_USB0_SE0",      0x122,  0,      0,      0,      1)
-MUX_CFG_24XX("K18_24XX_USB0_DAT",      0x123,  0,      0,      0,      1)
-
-MUX_CFG_24XX("N14_24XX_USB1_SE0",      0x0ed,  2,      0,      0,      1)
-MUX_CFG_24XX("W12_24XX_USB1_SE0",      0x0dd,  3,      0,      0,      1)
-MUX_CFG_24XX("P15_24XX_USB1_DAT",      0x0ee,  2,      0,      0,      1)
-MUX_CFG_24XX("R13_24XX_USB1_DAT",      0x0e0,  3,      0,      0,      1)
-MUX_CFG_24XX("W20_24XX_USB1_TXEN",     0x0ec,  2,      0,      0,      1)
-MUX_CFG_24XX("P13_24XX_USB1_TXEN",     0x0df,  3,      0,      0,      1)
-MUX_CFG_24XX("V19_24XX_USB1_RCV",      0x0eb,  2,      0,      0,      1)
-MUX_CFG_24XX("V12_24XX_USB1_RCV",      0x0de,  3,      0,      0,      1)
-
-MUX_CFG_24XX("AA10_24XX_USB2_SE0",     0x0e5,  2,      0,      0,      1)
-MUX_CFG_24XX("Y11_24XX_USB2_DAT",      0x0e8,  2,      0,      0,      1)
-MUX_CFG_24XX("AA12_24XX_USB2_TXEN",    0x0e9,  2,      0,      0,      1)
-MUX_CFG_24XX("AA6_24XX_USB2_RCV",      0x0e6,  2,      0,      0,      1)
-MUX_CFG_24XX("AA4_24XX_USB2_TLLSE0",   0x0e7,  2,      0,      0,      1)
-
-/* Keypad GPIO*/
-MUX_CFG_24XX("T19_24XX_KBR0",          0x106,  3,      1,      1,      1)
-MUX_CFG_24XX("R19_24XX_KBR1",          0x107,  3,      1,      1,      1)
-MUX_CFG_24XX("V18_24XX_KBR2",          0x139,  3,      1,      1,      1)
-MUX_CFG_24XX("M21_24XX_KBR3",          0xc9,   3,      1,      1,      1)
-MUX_CFG_24XX("E5__24XX_KBR4",          0x138,  3,      1,      1,      1)
-MUX_CFG_24XX("M18_24XX_KBR5",          0x10e,  3,      1,      1,      1)
-MUX_CFG_24XX("R20_24XX_KBC0",          0x108,  3,      0,      0,      1)
-MUX_CFG_24XX("M14_24XX_KBC1",          0x109,  3,      0,      0,      1)
-MUX_CFG_24XX("H19_24XX_KBC2",          0x114,  3,      0,      0,      1)
-MUX_CFG_24XX("V17_24XX_KBC3",          0x135,  3,      0,      0,      1)
-MUX_CFG_24XX("P21_24XX_KBC4",          0xca,   3,      0,      0,      1)
-MUX_CFG_24XX("L14_24XX_KBC5",          0x10f,  3,      0,      0,      1)
-MUX_CFG_24XX("N19_24XX_KBC6",          0x110,  3,      0,      0,      1)
-
-/* 24xx Menelaus Keypad GPIO */
-MUX_CFG_24XX("B3__24XX_KBR5",          0x30,   3,      1,      1,      1)
-MUX_CFG_24XX("AA4_24XX_KBC2",          0xe7,   3,      0,      0,      1)
-MUX_CFG_24XX("B13_24XX_KBC6",          0x110,  3,      0,      0,      1)
-
-/* 2430 USB */
-MUX_CFG_24XX("AD9_2430_USB0_PUEN",     0x133,  4,      0,      0,      1)
-MUX_CFG_24XX("Y11_2430_USB0_VP",       0x134,  4,      0,      0,      1)
-MUX_CFG_24XX("AD7_2430_USB0_VM",       0x135,  4,      0,      0,      1)
-MUX_CFG_24XX("AE7_2430_USB0_RCV",      0x136,  4,      0,      0,      1)
-MUX_CFG_24XX("AD4_2430_USB0_TXEN",     0x137,  4,      0,      0,      1)
-MUX_CFG_24XX("AF9_2430_USB0_SE0",      0x138,  4,      0,      0,      1)
-MUX_CFG_24XX("AE6_2430_USB0_DAT",      0x139,  4,      0,      0,      1)
-MUX_CFG_24XX("AD24_2430_USB1_SE0",     0x107,  2,      0,      0,      1)
-MUX_CFG_24XX("AB24_2430_USB1_RCV",     0x108,  2,      0,      0,      1)
-MUX_CFG_24XX("Y25_2430_USB1_TXEN",     0x109,  2,      0,      0,      1)
-MUX_CFG_24XX("AA26_2430_USB1_DAT",     0x10A,  2,      0,      0,      1)
-
-/* 2430 HS-USB */
-MUX_CFG_24XX("AD9_2430_USB0HS_DATA3",  0x133,  0,      0,      0,      1)
-MUX_CFG_24XX("Y11_2430_USB0HS_DATA4",  0x134,  0,      0,      0,      1)
-MUX_CFG_24XX("AD7_2430_USB0HS_DATA5",  0x135,  0,      0,      0,      1)
-MUX_CFG_24XX("AE7_2430_USB0HS_DATA6",  0x136,  0,      0,      0,      1)
-MUX_CFG_24XX("AD4_2430_USB0HS_DATA2",  0x137,  0,      0,      0,      1)
-MUX_CFG_24XX("AF9_2430_USB0HS_DATA0",  0x138,  0,      0,      0,      1)
-MUX_CFG_24XX("AE6_2430_USB0HS_DATA1",  0x139,  0,      0,      0,      1)
-MUX_CFG_24XX("AE8_2430_USB0HS_CLK",    0x13A,  0,      0,      0,      1)
-MUX_CFG_24XX("AD8_2430_USB0HS_DIR",    0x13B,  0,      0,      0,      1)
-MUX_CFG_24XX("AE5_2430_USB0HS_STP",    0x13c,  0,      1,      1,      1)
-MUX_CFG_24XX("AE9_2430_USB0HS_NXT",    0x13D,  0,      0,      0,      1)
-MUX_CFG_24XX("AC7_2430_USB0HS_DATA7",  0x13E,  0,      0,      0,      1)
-
-/* 2430 McBSP */
-MUX_CFG_24XX("AD6_2430_MCBSP_CLKS",    0x011E, 0,      0,      0,      1)
-
-MUX_CFG_24XX("AB2_2430_MCBSP1_CLKR",   0x011A, 0,      0,      0,      1)
-MUX_CFG_24XX("AD5_2430_MCBSP1_FSR",    0x011B, 0,      0,      0,      1)
-MUX_CFG_24XX("AA1_2430_MCBSP1_DX",     0x011C, 0,      0,      0,      1)
-MUX_CFG_24XX("AF3_2430_MCBSP1_DR",     0x011D, 0,      0,      0,      1)
-MUX_CFG_24XX("AB3_2430_MCBSP1_FSX",    0x011F, 0,      0,      0,      1)
-MUX_CFG_24XX("Y9_2430_MCBSP1_CLKX",    0x0120, 0,      0,      0,      1)
-
-MUX_CFG_24XX("AC10_2430_MCBSP2_FSX",   0x012E, 1,      0,      0,      1)
-MUX_CFG_24XX("AD16_2430_MCBSP2_CLX",   0x012F, 1,      0,      0,      1)
-MUX_CFG_24XX("AE13_2430_MCBSP2_DX",    0x0130, 1,      0,      0,      1)
-MUX_CFG_24XX("AD13_2430_MCBSP2_DR",    0x0131, 1,      0,      0,      1)
-MUX_CFG_24XX("AC10_2430_MCBSP2_FSX_OFF",0x012E,        0,      0,      0,      1)
-MUX_CFG_24XX("AD16_2430_MCBSP2_CLX_OFF",0x012F,        0,      0,      0,      1)
-MUX_CFG_24XX("AE13_2430_MCBSP2_DX_OFF",        0x0130, 0,      0,      0,      1)
-MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF",        0x0131, 0,      0,      0,      1)
-
-MUX_CFG_24XX("AC9_2430_MCBSP3_CLKX",   0x0103, 0,      0,      0,      1)
-MUX_CFG_24XX("AE4_2430_MCBSP3_FSX",    0x0104, 0,      0,      0,      1)
-MUX_CFG_24XX("AE2_2430_MCBSP3_DR",     0x0105, 0,      0,      0,      1)
-MUX_CFG_24XX("AF4_2430_MCBSP3_DX",     0x0106, 0,      0,      0,      1)
-
-MUX_CFG_24XX("N3_2430_MCBSP4_CLKX",    0x010B, 1,      0,      0,      1)
-MUX_CFG_24XX("AD23_2430_MCBSP4_DR",    0x010C, 1,      0,      0,      1)
-MUX_CFG_24XX("AB25_2430_MCBSP4_DX",    0x010D, 1,      0,      0,      1)
-MUX_CFG_24XX("AC25_2430_MCBSP4_FSX",   0x010E, 1,      0,      0,      1)
-
-MUX_CFG_24XX("AE16_2430_MCBSP5_CLKX",  0x00ED, 1,      0,      0,      1)
-MUX_CFG_24XX("AF12_2430_MCBSP5_FSX",   0x00ED, 1,      0,      0,      1)
-MUX_CFG_24XX("K7_2430_MCBSP5_DX",      0x00EF, 1,      0,      0,      1)
-MUX_CFG_24XX("M1_2430_MCBSP5_DR",      0x00F0, 1,      0,      0,      1)
-
-/* 2430 MCSPI1 */
-MUX_CFG_24XX("Y18_2430_MCSPI1_CLK",    0x010F, 0,      0,      0,      1)
-MUX_CFG_24XX("AD15_2430_MCSPI1_SIMO",  0x0110, 0,      0,      0,      1)
-MUX_CFG_24XX("AE17_2430_MCSPI1_SOMI",  0x0111, 0,      0,      0,      1)
-MUX_CFG_24XX("U1_2430_MCSPI1_CS0",     0x0112, 0,      0,      0,      1)
-
-/* Touchscreen GPIO */
-MUX_CFG_24XX("AF19_2430_GPIO_85",      0x0113, 3,      0,      0,      1)
-
-};
-
-#define OMAP24XX_PINS_SZ       ARRAY_SIZE(omap24xx_pins)
-
-#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
-
-static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 reg)
-{
-       u16 orig;
-       u8 warn = 0, debug = 0;
-
-       orig = omap_mux_read(cfg->mux_reg - OMAP_MUX_BASE_OFFSET);
-
-#ifdef CONFIG_OMAP_MUX_DEBUG
-       debug = cfg->debug;
-#endif
-       warn = (orig != reg);
-       if (debug || warn)
-               printk(KERN_WARNING
-                       "MUX: setup %s (0x%p): 0x%04x -> 0x%04x\n",
-                       cfg->name, omap_ctrl_base_get() + cfg->mux_reg,
-                       orig, reg);
-}
-#else
-#define omap2_cfg_debug(x, y)  do {} while (0)
-#endif
-
-static int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
-{
-       static DEFINE_SPINLOCK(mux_spin_lock);
-       unsigned long flags;
-       u8 reg = 0;
-
-       spin_lock_irqsave(&mux_spin_lock, flags);
-       reg |= cfg->mask & 0x7;
-       if (cfg->pull_val)
-               reg |= OMAP2_PULL_ENA;
-       if (cfg->pu_pd_val)
-               reg |= OMAP2_PULL_UP;
-       omap2_cfg_debug(cfg, reg);
-       omap_mux_write(reg, cfg->mux_reg - OMAP_MUX_BASE_OFFSET);
-       spin_unlock_irqrestore(&mux_spin_lock, flags);
-
-       return 0;
-}
-
-int __init omap2_mux_init(void)
-{
-       u32 mux_pbase;
-
-       if (cpu_is_omap2420())
-               mux_pbase = OMAP2420_CTRL_BASE + OMAP_MUX_BASE_OFFSET;
-       else if (cpu_is_omap2430())
-               mux_pbase = OMAP243X_CTRL_BASE + OMAP_MUX_BASE_OFFSET;
-       else
-               return -ENODEV;
-
-       mux_base = ioremap(mux_pbase, OMAP_MUX_BASE_SZ);
-       if (!mux_base) {
-               printk(KERN_ERR "mux: Could not ioremap\n");
-               return -ENODEV;
-       }
-
-       if (cpu_is_omap24xx()) {
-               arch_mux_cfg.pins       = omap24xx_pins;
-               arch_mux_cfg.size       = OMAP24XX_PINS_SZ;
-               arch_mux_cfg.cfg_reg    = omap24xx_cfg_reg;
-
-               return omap_mux_register(&arch_mux_cfg);
-       }
-
-       return 0;
-}
-
-#else
-int __init omap2_mux_init(void)
-{
-       return 0;
-}
-#endif /* CONFIG_OMAP_MUX */
-
-/*----------------------------------------------------------------------------*/
-
-#ifdef CONFIG_ARCH_OMAP3
 static LIST_HEAD(muxmodes);
 static DEFINE_MUTEX(muxmode_mutex);
 
@@ -381,6 +87,9 @@ static char *omap_mux_options;
 int __init omap_mux_init_gpio(int gpio, int val)
 {
        struct omap_mux_entry *e;
+       struct omap_mux *gpio_mux;
+       u16 old_mode;
+       u16 mux_mode;
        int found = 0;
 
        if (!gpio)
@@ -389,31 +98,33 @@ int __init omap_mux_init_gpio(int gpio, int val)
        list_for_each_entry(e, &muxmodes, node) {
                struct omap_mux *m = &e->mux;
                if (gpio == m->gpio) {
-                       u16 old_mode;
-                       u16 mux_mode;
-
-                       old_mode = omap_mux_read(m->reg_offset);
-                       mux_mode = val & ~(OMAP_MUX_NR_MODES - 1);
-                       mux_mode |= OMAP_MUX_MODE4;
-                       printk(KERN_DEBUG "mux: Setting signal "
-                               "%s.gpio%i 0x%04x -> 0x%04x\n",
-                               m->muxnames[0], gpio, old_mode, mux_mode);
-                       omap_mux_write(mux_mode, m->reg_offset);
+                       gpio_mux = m;
                        found++;
                }
        }
 
-       if (found == 1)
-               return 0;
+       if (found == 0) {
+               printk(KERN_ERR "mux: Could not set gpio%i\n", gpio);
+               return -ENODEV;
+       }
 
        if (found > 1) {
-               printk(KERN_ERR "mux: Multiple gpio paths for gpio%i\n", gpio);
+               printk(KERN_INFO "mux: Multiple gpio paths (%d) for gpio%i\n",
+                               found, gpio);
                return -EINVAL;
        }
 
-       printk(KERN_ERR "mux: Could not set gpio%i\n", gpio);
+       old_mode = omap_mux_read(gpio_mux->reg_offset);
+       mux_mode = val & ~(OMAP_MUX_NR_MODES - 1);
+       if (omap_mux_flags & MUXABLE_GPIO_MODE3)
+               mux_mode |= OMAP_MUX_MODE3;
+       else
+               mux_mode |= OMAP_MUX_MODE4;
+       printk(KERN_DEBUG "mux: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n",
+                       gpio_mux->muxnames[0], gpio, old_mode, mux_mode);
+       omap_mux_write(mux_mode, gpio_mux->reg_offset);
 
-       return -ENODEV;
+       return 0;
 }
 
 int __init omap_mux_init_signal(char *muxname, int val)
@@ -1032,6 +743,9 @@ int __init omap_mux_init(u32 mux_pbase, u32 mux_size,
                return -ENODEV;
        }
 
+       if (cpu_is_omap24xx())
+               omap_mux_flags = MUXABLE_GPIO_MODE3;
+
        omap_mux_init_package(superset, package_subset, package_balls);
        omap_mux_init_list(superset);
        omap_mux_init_signals(board_mux);
@@ -1039,5 +753,3 @@ int __init omap_mux_init(u32 mux_pbase, u32 mux_size,
        return 0;
 }
 
-#endif /* CONFIG_ARCH_OMAP3 */
-

diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index 480abc56e605b2140590c7556c46ff15bb31892f..a8e040c2c7e9817aa67115b0e52860dd81653369 100644 (file)
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -7,6 +7,8 @@
  * published by the Free Software Foundation.
  */
 
+#include "mux2420.h"
+#include "mux2430.h"
 #include "mux34xx.h"
 
 #define OMAP_MUX_TERMINATOR    0xffff
@@ -56,10 +58,12 @@
 
 /* Flags for omap_mux_init */
 #define OMAP_PACKAGE_MASK              0xffff
-#define OMAP_PACKAGE_CBP               4               /* 515-pin 0.40 0.50 */
-#define OMAP_PACKAGE_CUS               3               /* 423-pin 0.65 */
-#define OMAP_PACKAGE_CBB               2               /* 515-pin 0.40 0.50 */
-#define OMAP_PACKAGE_CBC               1               /* 515-pin 0.50 0.65 */
+#define OMAP_PACKAGE_CBP               6               /* 515-pin 0.40 0.50 */
+#define OMAP_PACKAGE_CUS               5               /* 423-pin 0.65 */
+#define OMAP_PACKAGE_CBB               4               /* 515-pin 0.40 0.50 */
+#define OMAP_PACKAGE_CBC               3               /* 515-pin 0.50 0.65 */
+#define OMAP_PACKAGE_ZAC               2               /* 24xx 447-pin POP */
+#define OMAP_PACKAGE_ZAF               1               /* 2420 447-pin SIP */
 
 
 #define OMAP_MUX_NR_MODES      8                       /* Available modes */
@@ -102,7 +106,7 @@ struct omap_board_mux {
        u16     value;
 };
 
-#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_ARCH_OMAP3)
+#if defined(CONFIG_OMAP_MUX)
 
 /**
  * omap_mux_init_gpio - initialize a signal based on the GPIO number
@@ -170,6 +174,20 @@ void omap_mux_write(u16 val, u16 mux_offset);
  */
 void omap_mux_write_array(struct omap_board_mux *board_mux);
 
+/**
+ * omap2420_mux_init() - initialize mux system with board specific set
+ * @board_mux:         Board specific mux table
+ * @flags:             OMAP package type used for the board
+ */
+int omap2420_mux_init(struct omap_board_mux *board_mux, int flags);
+
+/**
+ * omap2430_mux_init() - initialize mux system with board specific set
+ * @board_mux:         Board specific mux table
+ * @flags:             OMAP package type used for the board
+ */
+int omap2430_mux_init(struct omap_board_mux *board_mux, int flags);
+
 /**
  * omap3_mux_init() - initialize mux system with board specific set
  * @board_mux:         Board specific mux table

diff --git a/arch/arm/mach-omap2/mux2420.c b/arch/arm/mach-omap2/mux2420.c
new file mode 100644 (file)
index 0000000..fdb04a7
--- /dev/null
+++ b/arch/arm/mach-omap2/mux2420.c
@@ -0,0 +1,688 @@
+/*
+ * Copyright (C) 2010 Nokia
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include "mux.h"
+
+#ifdef CONFIG_OMAP_MUX
+
+#define _OMAP2420_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)              \
+{                                                                      \
+       .reg_offset     = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET),     \
+       .gpio           = (g),                                          \
+       .muxnames       = { m0, m1, m2, m3, m4, m5, m6, m7 },           \
+}
+
+#else
+
+#define _OMAP2420_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)              \
+{                                                                      \
+       .reg_offset     = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET),     \
+       .gpio           = (g),                                          \
+}
+
+#endif
+
+#define _OMAP2420_BALLENTRY(M0, bb, bt)                                        \
+{                                                                      \
+       .reg_offset     = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET),     \
+       .balls          = { bb, bt },                                   \
+}
+
+/*
+ * Superset of all mux modes for omap2420
+ */
+static struct omap_mux __initdata omap2420_muxmodes[] = {
+       _OMAP2420_MUXENTRY(CAM_D0, 54,
+               "cam_d0", "hw_dbg2", "sti_dout", "gpio_54",
+               NULL, NULL, "etk_d2", NULL),
+       _OMAP2420_MUXENTRY(CAM_D1, 53,
+               "cam_d1", "hw_dbg3", "sti_din", "gpio_53",
+               NULL, NULL, "etk_d3", NULL),
+       _OMAP2420_MUXENTRY(CAM_D2, 52,
+               "cam_d2", "hw_dbg4", "mcbsp1_clkx", "gpio_52",
+               NULL, NULL, "etk_d4", NULL),
+       _OMAP2420_MUXENTRY(CAM_D3, 51,
+               "cam_d3", "hw_dbg5", "mcbsp1_dr", "gpio_51",
+               NULL, NULL, "etk_d5", NULL),
+       _OMAP2420_MUXENTRY(CAM_D4, 50,
+               "cam_d4", "hw_dbg6", "mcbsp1_fsr", "gpio_50",
+               NULL, NULL, "etk_d6", NULL),
+       _OMAP2420_MUXENTRY(CAM_D5, 49,
+               "cam_d5", "hw_dbg7", "mcbsp1_clkr", "gpio_49",
+               NULL, NULL, "etk_d7", NULL),
+       _OMAP2420_MUXENTRY(CAM_D6, 0,
+               "cam_d6", "hw_dbg8", NULL, NULL,
+               NULL, NULL, "etk_d8", NULL),
+       _OMAP2420_MUXENTRY(CAM_D7, 0,
+               "cam_d7", "hw_dbg9", NULL, NULL,
+               NULL, NULL, "etk_d9", NULL),
+       _OMAP2420_MUXENTRY(CAM_D8, 54,
+               "cam_d8", "hw_dbg10", NULL, "gpio_54",
+               NULL, NULL, "etk_d10", NULL),
+       _OMAP2420_MUXENTRY(CAM_D9, 53,
+               "cam_d9", "hw_dbg11", NULL, "gpio_53",
+               NULL, NULL, "etk_d11", NULL),
+       _OMAP2420_MUXENTRY(CAM_HS, 55,
+               "cam_hs", "hw_dbg1", "mcbsp1_dx", "gpio_55",
+               NULL, NULL, "etk_d1", NULL),
+       _OMAP2420_MUXENTRY(CAM_LCLK, 57,
+               "cam_lclk", NULL, "mcbsp_clks", "gpio_57",
+               NULL, NULL, "etk_c1", NULL),
+       _OMAP2420_MUXENTRY(CAM_VS, 56,
+               "cam_vs", "hw_dbg0", "mcbsp1_fsx", "gpio_56",
+               NULL, NULL, "etk_d0", NULL),
+       _OMAP2420_MUXENTRY(CAM_XCLK, 0,
+               "cam_xclk", NULL, "sti_clk", NULL,
+               NULL, NULL, "etk_c2", NULL),
+       _OMAP2420_MUXENTRY(DSS_ACBIAS, 48,
+               "dss_acbias", NULL, "mcbsp2_fsx", "gpio_48",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(DSS_DATA10, 40,
+               "dss_data10", NULL, NULL, "gpio_40",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(DSS_DATA11, 41,
+               "dss_data11", NULL, NULL, "gpio_41",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(DSS_DATA12, 42,
+               "dss_data12", NULL, NULL, "gpio_42",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(DSS_DATA13, 43,
+               "dss_data13", NULL, NULL, "gpio_43",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(DSS_DATA14, 44,
+               "dss_data14", NULL, NULL, "gpio_44",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(DSS_DATA15, 45,
+               "dss_data15", NULL, NULL, "gpio_45",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(DSS_DATA16, 46,
+               "dss_data16", NULL, NULL, "gpio_46",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(DSS_DATA17, 47,
+               "dss_data17", NULL, NULL, "gpio_47",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(DSS_DATA8, 38,
+               "dss_data8", NULL, NULL, "gpio_38",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(DSS_DATA9, 39,
+               "dss_data9", NULL, NULL, "gpio_39",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(EAC_AC_DIN, 115,
+               "eac_ac_din", "mcbsp2_dr", NULL, "gpio_115",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(EAC_AC_DOUT, 116,
+               "eac_ac_dout", "mcbsp2_dx", NULL, "gpio_116",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(EAC_AC_FS, 114,
+               "eac_ac_fs", "mcbsp2_fsx", NULL, "gpio_114",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(EAC_AC_MCLK, 117,
+               "eac_ac_mclk", NULL, NULL, "gpio_117",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(EAC_AC_RST, 118,
+               "eac_ac_rst", "eac_bt_din", NULL, "gpio_118",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(EAC_AC_SCLK, 113,
+               "eac_ac_sclk", "mcbsp2_clkx", NULL, "gpio_113",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(EAC_BT_DIN, 73,
+               "eac_bt_din", NULL, NULL, "gpio_73",
+               NULL, NULL, "etk_d9", NULL),
+       _OMAP2420_MUXENTRY(EAC_BT_DOUT, 74,
+               "eac_bt_dout", NULL, "sti_clk", "gpio_74",
+               NULL, NULL, "etk_d8", NULL),
+       _OMAP2420_MUXENTRY(EAC_BT_FS, 72,
+               "eac_bt_fs", NULL, NULL, "gpio_72",
+               NULL, NULL, "etk_d10", NULL),
+       _OMAP2420_MUXENTRY(EAC_BT_SCLK, 71,
+               "eac_bt_sclk", NULL, NULL, "gpio_71",
+               NULL, NULL, "etk_d11", NULL),
+       _OMAP2420_MUXENTRY(GPIO_119, 119,
+               "gpio_119", NULL, "sti_din", "gpio_119",
+               NULL, "sys_boot0", "etk_d12", NULL),
+       _OMAP2420_MUXENTRY(GPIO_120, 120,
+               "gpio_120", NULL, "sti_dout", "gpio_120",
+               "cam_d9", "sys_boot1", "etk_d13", NULL),
+       _OMAP2420_MUXENTRY(GPIO_121, 121,
+               "gpio_121", NULL, NULL, "gpio_121",
+               "jtag_emu2", "sys_boot2", "etk_d14", NULL),
+       _OMAP2420_MUXENTRY(GPIO_122, 122,
+               "gpio_122", NULL, NULL, "gpio_122",
+               "jtag_emu3", "sys_boot3", "etk_d15", NULL),
+       _OMAP2420_MUXENTRY(GPIO_124, 124,
+               "gpio_124", NULL, NULL, "gpio_124",
+               NULL, "sys_boot5", NULL, NULL),
+       _OMAP2420_MUXENTRY(GPIO_125, 125,
+               "gpio_125", "sys_jtagsel1", "sys_jtagsel2", "gpio_125",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPIO_36, 36,
+               "gpio_36", NULL, NULL, "gpio_36",
+               NULL, "sys_boot4", NULL, NULL),
+       _OMAP2420_MUXENTRY(GPIO_62, 62,
+               "gpio_62", "uart1_rx", "usb1_dat", "gpio_62",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPIO_6, 6,
+               "gpio_6", "tv_detpulse", NULL, "gpio_6",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_A10, 3,
+               "gpmc_a10", NULL, "sys_ndmareq5", "gpio_3",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_A1, 12,
+               "gpmc_a1", "dss_data18", NULL, "gpio_12",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_A2, 11,
+               "gpmc_a2", "dss_data19", NULL, "gpio_11",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_A3, 10,
+               "gpmc_a3", "dss_data20", NULL, "gpio_10",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_A4, 9,
+               "gpmc_a4", "dss_data21", NULL, "gpio_9",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_A5, 8,
+               "gpmc_a5", "dss_data22", NULL, "gpio_8",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_A6, 7,
+               "gpmc_a6", "dss_data23", NULL, "gpio_7",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_A7, 6,
+               "gpmc_a7", NULL, "sys_ndmareq2", "gpio_6",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_A8, 5,
+               "gpmc_a8", NULL, "sys_ndmareq3", "gpio_5",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_A9, 4,
+               "gpmc_a9", NULL, "sys_ndmareq4", "gpio_4",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_CLK, 21,
+               "gpmc_clk", NULL, NULL, "gpio_21",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_D10, 18,
+               "gpmc_d10", "ssi2_rdy_rx", NULL, "gpio_18",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_D11, 17,
+               "gpmc_d11", "ssi2_flag_rx", NULL, "gpio_17",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_D12, 16,
+               "gpmc_d12", "ssi2_dat_rx", NULL, "gpio_16",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_D13, 15,
+               "gpmc_d13", "ssi2_rdy_tx", NULL, "gpio_15",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_D14, 14,
+               "gpmc_d14", "ssi2_flag_tx", NULL, "gpio_14",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_D15, 13,
+               "gpmc_d15", "ssi2_dat_tx", NULL, "gpio_13",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_D8, 20,
+               "gpmc_d8", NULL, NULL, "gpio_20",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_D9, 19,
+               "gpmc_d9", "ssi2_wake", NULL, "gpio_19",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_NBE0, 29,
+               "gpmc_nbe0", NULL, NULL, "gpio_29",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_NBE1, 30,
+               "gpmc_nbe1", NULL, NULL, "gpio_30",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_NCS1, 22,
+               "gpmc_ncs1", NULL, NULL, "gpio_22",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_NCS2, 23,
+               "gpmc_ncs2", NULL, NULL, "gpio_23",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_NCS3, 24,
+               "gpmc_ncs3", "gpmc_io_dir", NULL, "gpio_24",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_NCS4, 25,
+               "gpmc_ncs4", NULL, NULL, "gpio_25",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_NCS5, 26,
+               "gpmc_ncs5", NULL, NULL, "gpio_26",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_NCS6, 27,
+               "gpmc_ncs6", NULL, NULL, "gpio_27",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_NCS7, 28,
+               "gpmc_ncs7", "gpmc_io_dir", "gpio_28", NULL,
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_NWP, 31,
+               "gpmc_nwp", NULL, NULL, "gpio_31",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_WAIT1, 33,
+               "gpmc_wait1", NULL, NULL, "gpio_33",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_WAIT2, 34,
+               "gpmc_wait2", NULL, NULL, "gpio_34",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(GPMC_WAIT3, 35,
+               "gpmc_wait3", NULL, NULL, "gpio_35",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(HDQ_SIO, 101,
+               "hdq_sio", "usb2_tllse0", "sys_altclk", "gpio_101",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(I2C2_SCL, 99,
+               "i2c2_scl", NULL, "gpt9_pwm_evt", "gpio_99",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(I2C2_SDA, 100,
+               "i2c2_sda", NULL, "spi2_ncs1", "gpio_100",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(JTAG_EMU0, 127,
+               "jtag_emu0", NULL, NULL, "gpio_127",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(JTAG_EMU1, 126,
+               "jtag_emu1", NULL, NULL, "gpio_126",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(MCBSP1_CLKR, 92,
+               "mcbsp1_clkr", "ssi2_dat_tx", "vlynq_tx1", "gpio_92",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(MCBSP1_CLKX, 98,
+               "mcbsp1_clkx", "ssi2_wake", "vlynq_nla", "gpio_98",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(MCBSP1_DR, 95,
+               "mcbsp1_dr", "ssi2_dat_rx", "vlynq_rx1", "gpio_95",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(MCBSP1_DX, 94,
+               "mcbsp1_dx", "ssi2_rdy_tx", "vlynq_clk", "gpio_94",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(MCBSP1_FSR, 93,
+               "mcbsp1_fsr", "ssi2_flag_tx", "vlynq_tx0", "gpio_93",
+               "spi2_ncs1", NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(MCBSP1_FSX, 97,
+               "mcbsp1_fsx", "ssi2_rdy_rx", NULL, "gpio_97",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(MCBSP2_CLKX, 12,
+               "mcbsp2_clkx", NULL, "dss_data23", "gpio_12",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(MCBSP2_DR, 11,
+               "mcbsp2_dr", NULL, "dss_data22", "gpio_11",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(MCBSP_CLKS, 96,
+               "mcbsp_clks", "ssi2_flag_rx", "vlynq_rx0", "gpio_96",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(MMC_CLKI, 59,
+               "sdmmc_clki", "ms_clki", NULL, "gpio_59",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(MMC_CLKO, 0,
+               "sdmmc_clko", "ms_clko", NULL, NULL,
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(MMC_CMD_DIR, 8,
+               "sdmmc_cmd_dir", NULL, NULL, "gpio_8",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(MMC_CMD, 0,
+               "sdmmc_cmd", "ms_bs", NULL, NULL,
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(MMC_DAT_DIR0, 7,
+               "sdmmc_dat_dir0", "ms_dat0_dir", NULL, "gpio_7",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(MMC_DAT0, 0,
+               "sdmmc_dat0", "ms_dat0", NULL, NULL,
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(MMC_DAT_DIR1, 78,
+               "sdmmc_dat_dir1", "ms_datu_dir", "uart2_rts", "gpio_78",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(MMC_DAT1, 75,
+               "sdmmc_dat1", "ms_dat1", NULL, "gpio_75",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(MMC_DAT_DIR2, 79,
+               "sdmmc_dat_dir2", "ms_datu_dir", "uart2_tx", "gpio_79",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(MMC_DAT2, 76,
+               "sdmmc_dat2", "ms_dat2", "uart2_cts", "gpio_76",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(MMC_DAT_DIR3, 80,
+               "sdmmc_dat_dir3", "ms_datu_dir", "uart2_rx", "gpio_80",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(MMC_DAT3, 77,
+               "sdmmc_dat3", "ms_dat3", NULL, "gpio_77",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(SDRC_A12, 2,
+               "sdrc_a12", NULL, NULL, "gpio_2",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(SDRC_A13, 1,
+               "sdrc_a13", NULL, NULL, "gpio_1",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(SDRC_A14, 0,
+               "sdrc_a14", NULL, NULL, "gpio_0",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(SDRC_CKE1, 38,
+               "sdrc_cke1", NULL, NULL, "gpio_38",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(SDRC_NCS1, 37,
+               "sdrc_ncs1", NULL, NULL, "gpio_37",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(SPI1_CLK, 81,
+               "spi1_clk", NULL, NULL, "gpio_81",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(SPI1_NCS0, 84,
+               "spi1_ncs0", NULL, NULL, "gpio_84",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(SPI1_NCS1, 85,
+               "spi1_ncs1", NULL, NULL, "gpio_85",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(SPI1_NCS2, 86,
+               "spi1_ncs2", NULL, NULL, "gpio_86",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(SPI1_NCS3, 87,
+               "spi1_ncs3", NULL, NULL, "gpio_87",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(SPI1_SIMO, 82,
+               "spi1_simo", NULL, NULL, "gpio_82",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(SPI1_SOMI, 83,
+               "spi1_somi", NULL, NULL, "gpio_83",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(SPI2_CLK, 88,
+               "spi2_clk", NULL, NULL, "gpio_88",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(SPI2_NCS0, 91,
+               "spi2_ncs0", "gpt12_pwm_evt", NULL, "gpio_91",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(SPI2_SIMO, 89,
+               "spi2_simo", "gpt10_pwm_evt", NULL, "gpio_89",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(SPI2_SOMI, 90,
+               "spi2_somi", "gpt11_pwm_evt", NULL, "gpio_90",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(SSI1_DAT_RX, 63,
+               "ssi1_dat_rx", "eac_md_sclk", NULL, "gpio_63",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(SSI1_DAT_TX, 59,
+               "ssi1_dat_tx", "uart1_tx", "usb1_se0", "gpio_59",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(SSI1_FLAG_RX, 64,
+               "ssi1_flag_rx", "eac_md_din", NULL, "gpio_64",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(SSI1_FLAG_TX, 25,
+               "ssi1_flag_tx", "uart1_rts", "usb1_rcv", "gpio_25",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(SSI1_RDY_RX, 65,
+               "ssi1_rdy_rx", "eac_md_dout", NULL, "gpio_65",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(SSI1_RDY_TX, 61,
+               "ssi1_rdy_tx", "uart1_cts", "usb1_txen", "gpio_61",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(SSI1_WAKE, 66,
+               "ssi1_wake", "eac_md_fs", NULL, "gpio_66",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(SYS_CLKOUT, 123,
+               "sys_clkout", NULL, NULL, "gpio_123",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(SYS_CLKREQ, 52,
+               "sys_clkreq", NULL, NULL, "gpio_52",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(SYS_NIRQ, 60,
+               "sys_nirq", NULL, NULL, "gpio_60",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(UART1_CTS, 32,
+               "uart1_cts", NULL, "dss_data18", "gpio_32",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(UART1_RTS, 8,
+               "uart1_rts", NULL, "dss_data19", "gpio_8",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(UART1_RX, 10,
+               "uart1_rx", NULL, "dss_data21", "gpio_10",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(UART1_TX, 9,
+               "uart1_tx", NULL, "dss_data20", "gpio_9",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(UART2_CTS, 67,
+               "uart2_cts", "usb1_rcv", "gpt9_pwm_evt", "gpio_67",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(UART2_RTS, 68,
+               "uart2_rts", "usb1_txen", "gpt10_pwm_evt", "gpio_68",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(UART2_RX, 70,
+               "uart2_rx", "usb1_dat", "gpt12_pwm_evt", "gpio_70",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(UART2_TX, 69,
+               "uart2_tx", "usb1_se0", "gpt11_pwm_evt", "gpio_69",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(UART3_CTS_RCTX, 102,
+               "uart3_cts_rctx", "uart3_rx_irrx", NULL, "gpio_102",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(UART3_RTS_SD, 103,
+               "uart3_rts_sd", "uart3_tx_irtx", NULL, "gpio_103",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(UART3_RX_IRRX, 105,
+               "uart3_rx_irrx", NULL, NULL, "gpio_105",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(UART3_TX_IRTX, 104,
+               "uart3_tx_irtx", "uart3_cts_rctx", NULL, "gpio_104",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(USB0_DAT, 112,
+               "usb0_dat", "uart3_rx_irrx", "uart2_rx", "gpio_112",
+               "uart2_tx", NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(USB0_PUEN, 106,
+               "usb0_puen", "mcbsp2_dx", NULL, "gpio_106",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(USB0_RCV, 109,
+               "usb0_rcv", "mcbsp2_fsx", NULL, "gpio_109",
+               "uart2_cts", NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(USB0_SE0, 111,
+               "usb0_se0", "uart3_tx_irtx", "uart2_tx", "gpio_111",
+               "uart2_rx", NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(USB0_TXEN, 110,
+               "usb0_txen", "uart3_cts_rctx", "uart2_cts", "gpio_110",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(USB0_VM, 108,
+               "usb0_vm", "mcbsp2_clkx", NULL, "gpio_108",
+               "uart2_rx", NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(USB0_VP, 107,
+               "usb0_vp", "mcbsp2_dr", NULL, "gpio_107",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(VLYNQ_CLK, 13,
+               "vlynq_clk", "usb2_se0", "sys_ndmareq0", "gpio_13",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(VLYNQ_NLA, 58,
+               "vlynq_nla", NULL, NULL, "gpio_58",
+               "cam_d6", NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(VLYNQ_RX0, 15,
+               "vlynq_rx0", "usb2_tllse0", NULL, "gpio_15",
+               "cam_d7", NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(VLYNQ_RX1, 14,
+               "vlynq_rx1", "usb2_rcv", "sys_ndmareq1", "gpio_14",
+               "cam_d8", NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(VLYNQ_TX0, 17,
+               "vlynq_tx0", "usb2_txen", NULL, "gpio_17",
+               NULL, NULL, NULL, NULL),
+       _OMAP2420_MUXENTRY(VLYNQ_TX1, 16,
+               "vlynq_tx1", "usb2_dat", "sys_clkout2", "gpio_16",
+               NULL, NULL, NULL, NULL),
+       { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+/*
+ * Balls for 447-pin POP package
+ */
+#ifdef CONFIG_DEBUG_FS
+struct omap_ball __initdata omap2420_pop_ball[] = {
+       _OMAP2420_BALLENTRY(CAM_D0, "y4", NULL),
+       _OMAP2420_BALLENTRY(CAM_D1, "y3", NULL),
+       _OMAP2420_BALLENTRY(CAM_D2, "u7", NULL),
+       _OMAP2420_BALLENTRY(CAM_D3, "ab3", NULL),
+       _OMAP2420_BALLENTRY(CAM_D4, "v2", NULL),
+       _OMAP2420_BALLENTRY(CAM_D5, "ad3", NULL),
+       _OMAP2420_BALLENTRY(CAM_D6, "aa4", NULL),
+       _OMAP2420_BALLENTRY(CAM_D7, "ab4", NULL),
+       _OMAP2420_BALLENTRY(CAM_D8, "ac6", NULL),
+       _OMAP2420_BALLENTRY(CAM_D9, "ac7", NULL),
+       _OMAP2420_BALLENTRY(CAM_HS, "v4", NULL),
+       _OMAP2420_BALLENTRY(CAM_LCLK, "ad6", NULL),
+       _OMAP2420_BALLENTRY(CAM_VS, "p7", NULL),
+       _OMAP2420_BALLENTRY(CAM_XCLK, "w4", NULL),
+       _OMAP2420_BALLENTRY(DSS_ACBIAS, "ae8", NULL),
+       _OMAP2420_BALLENTRY(DSS_DATA10, "ac12", NULL),
+       _OMAP2420_BALLENTRY(DSS_DATA11, "ae11", NULL),
+       _OMAP2420_BALLENTRY(DSS_DATA12, "ae13", NULL),
+       _OMAP2420_BALLENTRY(DSS_DATA13, "ad13", NULL),
+       _OMAP2420_BALLENTRY(DSS_DATA14, "ac13", NULL),
+       _OMAP2420_BALLENTRY(DSS_DATA15, "y12", NULL),
+       _OMAP2420_BALLENTRY(DSS_DATA16, "ad14", NULL),
+       _OMAP2420_BALLENTRY(DSS_DATA17, "y13", NULL),
+       _OMAP2420_BALLENTRY(DSS_DATA8, "ad11", NULL),
+       _OMAP2420_BALLENTRY(DSS_DATA9, "ad12", NULL),
+       _OMAP2420_BALLENTRY(EAC_AC_DIN, "ad19", NULL),
+       _OMAP2420_BALLENTRY(EAC_AC_DOUT, "af22", NULL),
+       _OMAP2420_BALLENTRY(EAC_AC_FS, "ad16", NULL),
+       _OMAP2420_BALLENTRY(EAC_AC_MCLK, "y17", NULL),
+       _OMAP2420_BALLENTRY(EAC_AC_RST, "ae22", NULL),
+       _OMAP2420_BALLENTRY(EAC_AC_SCLK, "ac18", NULL),
+       _OMAP2420_BALLENTRY(EAC_BT_DIN, "u8", NULL),
+       _OMAP2420_BALLENTRY(EAC_BT_DOUT, "ad5", NULL),
+       _OMAP2420_BALLENTRY(EAC_BT_FS, "w7", NULL),
+       _OMAP2420_BALLENTRY(EAC_BT_SCLK, "ad4", NULL),
+       _OMAP2420_BALLENTRY(GPIO_119, "af6", NULL),
+       _OMAP2420_BALLENTRY(GPIO_120, "af4", NULL),
+       _OMAP2420_BALLENTRY(GPIO_121, "ae6", NULL),
+       _OMAP2420_BALLENTRY(GPIO_122, "w3", NULL),
+       _OMAP2420_BALLENTRY(GPIO_124, "y19", NULL),
+       _OMAP2420_BALLENTRY(GPIO_125, "ae24", NULL),
+       _OMAP2420_BALLENTRY(GPIO_36, "y18", NULL),
+       _OMAP2420_BALLENTRY(GPIO_6, "d6", NULL),
+       _OMAP2420_BALLENTRY(GPIO_62, "ad18", NULL),
+       _OMAP2420_BALLENTRY(GPMC_A1, "m8", NULL),
+       _OMAP2420_BALLENTRY(GPMC_A10, "d5", NULL),
+       _OMAP2420_BALLENTRY(GPMC_A2, "w9", NULL),
+       _OMAP2420_BALLENTRY(GPMC_A3, "af10", NULL),
+       _OMAP2420_BALLENTRY(GPMC_A4, "w8", NULL),
+       _OMAP2420_BALLENTRY(GPMC_A5, "ae16", NULL),
+       _OMAP2420_BALLENTRY(GPMC_A6, "af9", NULL),
+       _OMAP2420_BALLENTRY(GPMC_A7, "e4", NULL),
+       _OMAP2420_BALLENTRY(GPMC_A8, "j7", NULL),
+       _OMAP2420_BALLENTRY(GPMC_A9, "ae18", NULL),
+       _OMAP2420_BALLENTRY(GPMC_CLK, "p1", "l1"),
+       _OMAP2420_BALLENTRY(GPMC_D10, "t1", "n1"),
+       _OMAP2420_BALLENTRY(GPMC_D11, "u2", "p2"),
+       _OMAP2420_BALLENTRY(GPMC_D12, "u1", "p1"),
+       _OMAP2420_BALLENTRY(GPMC_D13, "p2", "m1"),
+       _OMAP2420_BALLENTRY(GPMC_D14, "h2", "j2"),
+       _OMAP2420_BALLENTRY(GPMC_D15, "h1", "k2"),
+       _OMAP2420_BALLENTRY(GPMC_D8, "v1", "r1"),
+       _OMAP2420_BALLENTRY(GPMC_D9, "y1", "t1"),
+       _OMAP2420_BALLENTRY(GPMC_NBE0, "af12", "aa10"),
+       _OMAP2420_BALLENTRY(GPMC_NBE1, "u3", NULL),
+       _OMAP2420_BALLENTRY(GPMC_NCS1, "af14", "w1"),
+       _OMAP2420_BALLENTRY(GPMC_NCS2, "g4", NULL),
+       _OMAP2420_BALLENTRY(GPMC_NCS3, "t8", NULL),
+       _OMAP2420_BALLENTRY(GPMC_NCS4, "h8", NULL),
+       _OMAP2420_BALLENTRY(GPMC_NCS5, "k3", NULL),
+       _OMAP2420_BALLENTRY(GPMC_NCS6, "m7", NULL),
+       _OMAP2420_BALLENTRY(GPMC_NCS7, "p3", NULL),
+       _OMAP2420_BALLENTRY(GPMC_NWP, "ae15", "y5"),
+       _OMAP2420_BALLENTRY(GPMC_WAIT1, "ae20", "y8"),
+       _OMAP2420_BALLENTRY(GPMC_WAIT2, "n2", NULL),
+       _OMAP2420_BALLENTRY(GPMC_WAIT3, "t4", NULL),
+       _OMAP2420_BALLENTRY(HDQ_SIO, "t23", NULL),
+       _OMAP2420_BALLENTRY(I2C2_SCL, "l2", NULL),
+       _OMAP2420_BALLENTRY(I2C2_SDA, "k19", NULL),
+       _OMAP2420_BALLENTRY(JTAG_EMU0, "n24", NULL),
+       _OMAP2420_BALLENTRY(JTAG_EMU1, "ac22", NULL),
+       _OMAP2420_BALLENTRY(MCBSP1_CLKR, "y24", NULL),
+       _OMAP2420_BALLENTRY(MCBSP1_CLKX, "t19", NULL),
+       _OMAP2420_BALLENTRY(MCBSP1_DR, "u23", NULL),
+       _OMAP2420_BALLENTRY(MCBSP1_DX, "r24", NULL),
+       _OMAP2420_BALLENTRY(MCBSP1_FSR, "r20", NULL),
+       _OMAP2420_BALLENTRY(MCBSP1_FSX, "r23", NULL),
+       _OMAP2420_BALLENTRY(MCBSP2_CLKX, "t24", NULL),
+       _OMAP2420_BALLENTRY(MCBSP2_DR, "p20", NULL),
+       _OMAP2420_BALLENTRY(MCBSP_CLKS, "p23", NULL),
+       _OMAP2420_BALLENTRY(MMC_CLKI, "c23", NULL),
+       _OMAP2420_BALLENTRY(MMC_CLKO, "h23", NULL),
+       _OMAP2420_BALLENTRY(MMC_CMD, "j23", NULL),
+       _OMAP2420_BALLENTRY(MMC_CMD_DIR, "j24", NULL),
+       _OMAP2420_BALLENTRY(MMC_DAT0, "h17", NULL),
+       _OMAP2420_BALLENTRY(MMC_DAT_DIR0, "f23", NULL),
+       _OMAP2420_BALLENTRY(MMC_DAT1, "g19", NULL),
+       _OMAP2420_BALLENTRY(MMC_DAT_DIR1, "d23", NULL),
+       _OMAP2420_BALLENTRY(MMC_DAT2, "h20", NULL),
+       _OMAP2420_BALLENTRY(MMC_DAT_DIR2, "g23", NULL),
+       _OMAP2420_BALLENTRY(MMC_DAT3, "d24", NULL),
+       _OMAP2420_BALLENTRY(MMC_DAT_DIR3, "e23", NULL),
+       _OMAP2420_BALLENTRY(SDRC_A12, "w26", "r21"),
+       _OMAP2420_BALLENTRY(SDRC_A13, "w25", "aa15"),
+       _OMAP2420_BALLENTRY(SDRC_A14, "aa26", "y12"),
+       _OMAP2420_BALLENTRY(SDRC_CKE1, "ae25", "y13"),
+       _OMAP2420_BALLENTRY(SDRC_NCS1, "y25", "t20"),
+       _OMAP2420_BALLENTRY(SPI1_CLK, "y23", NULL),
+       _OMAP2420_BALLENTRY(SPI1_NCS0, "w24", NULL),
+       _OMAP2420_BALLENTRY(SPI1_NCS1, "w23", NULL),
+       _OMAP2420_BALLENTRY(SPI1_NCS2, "v23", NULL),
+       _OMAP2420_BALLENTRY(SPI1_NCS3, "u20", NULL),
+       _OMAP2420_BALLENTRY(SPI1_SIMO, "h10", NULL),
+       _OMAP2420_BALLENTRY(SPI1_SOMI, "v19", NULL),
+       _OMAP2420_BALLENTRY(SPI2_CLK, "v24", NULL),
+       _OMAP2420_BALLENTRY(SPI2_NCS0, "aa24", NULL),
+       _OMAP2420_BALLENTRY(SPI2_SIMO, "u24", NULL),
+       _OMAP2420_BALLENTRY(SPI2_SOMI, "v25", NULL),
+       _OMAP2420_BALLENTRY(SSI1_DAT_RX, "w15", NULL),
+       _OMAP2420_BALLENTRY(SSI1_DAT_TX, "w13", NULL),
+       _OMAP2420_BALLENTRY(SSI1_FLAG_RX, "af11", NULL),
+       _OMAP2420_BALLENTRY(SSI1_FLAG_TX, "ac15", NULL),
+       _OMAP2420_BALLENTRY(SSI1_RDY_RX, "ac16", NULL),
+       _OMAP2420_BALLENTRY(SSI1_RDY_TX, "af15", NULL),
+       _OMAP2420_BALLENTRY(SSI1_WAKE, "ad15", NULL),
+       _OMAP2420_BALLENTRY(SYS_CLKOUT, "ae19", NULL),
+       _OMAP2420_BALLENTRY(SYS_CLKREQ, "ad20", NULL),
+       _OMAP2420_BALLENTRY(SYS_NIRQ, "y20", NULL),
+       _OMAP2420_BALLENTRY(UART1_CTS, "g20", NULL),
+       _OMAP2420_BALLENTRY(UART1_RTS, "k20", NULL),
+       _OMAP2420_BALLENTRY(UART1_RX, "t20", NULL),
+       _OMAP2420_BALLENTRY(UART1_TX, "h12", NULL),
+       _OMAP2420_BALLENTRY(UART2_CTS, "ac24", NULL),
+       _OMAP2420_BALLENTRY(UART2_RTS, "w20", NULL),
+       _OMAP2420_BALLENTRY(UART2_RX, "ad24", NULL),
+       _OMAP2420_BALLENTRY(UART2_TX, "ab24", NULL),
+       _OMAP2420_BALLENTRY(UART3_CTS_RCTX, "k24", NULL),
+       _OMAP2420_BALLENTRY(UART3_RTS_SD, "m20", NULL),
+       _OMAP2420_BALLENTRY(UART3_RX_IRRX, "h24", NULL),
+       _OMAP2420_BALLENTRY(UART3_TX_IRTX, "g24", NULL),
+       _OMAP2420_BALLENTRY(USB0_DAT, "j25", NULL),
+       _OMAP2420_BALLENTRY(USB0_PUEN, "l23", NULL),
+       _OMAP2420_BALLENTRY(USB0_RCV, "k23", NULL),
+       _OMAP2420_BALLENTRY(USB0_SE0, "l24", NULL),
+       _OMAP2420_BALLENTRY(USB0_TXEN, "m24", NULL),
+       _OMAP2420_BALLENTRY(USB0_VM, "n23", NULL),
+       _OMAP2420_BALLENTRY(USB0_VP, "m23", NULL),
+       _OMAP2420_BALLENTRY(VLYNQ_CLK, "w12", NULL),
+       _OMAP2420_BALLENTRY(VLYNQ_NLA, "ae10", NULL),
+       _OMAP2420_BALLENTRY(VLYNQ_RX0, "ad7", NULL),
+       _OMAP2420_BALLENTRY(VLYNQ_RX1, "w10", NULL),
+       _OMAP2420_BALLENTRY(VLYNQ_TX0, "y15", NULL),
+       _OMAP2420_BALLENTRY(VLYNQ_TX1, "w14", NULL),
+       { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap2420_pop_ball       NULL
+#endif
+
+int __init omap2420_mux_init(struct omap_board_mux *board_subset, int flags)
+{
+       struct omap_ball *package_balls = NULL;
+
+       switch (flags & OMAP_PACKAGE_MASK) {
+       case OMAP_PACKAGE_ZAC:
+               package_balls = omap2420_pop_ball;
+               break;
+       case OMAP_PACKAGE_ZAF:
+               /* REVISIT: Please add data */
+       default:
+               pr_warning("mux: No ball data available for omap2420 package\n");
+       }
+
+       return omap_mux_init(OMAP2420_CONTROL_PADCONF_MUX_PBASE,
+                            OMAP2420_CONTROL_PADCONF_MUX_SIZE,
+                               omap2420_muxmodes, NULL, board_subset,
+                               package_balls);
+}

diff --git a/arch/arm/mach-omap2/mux2420.h b/arch/arm/mach-omap2/mux2420.h
new file mode 100644 (file)
index 0000000..0f555aa
--- /dev/null
+++ b/arch/arm/mach-omap2/mux2420.h
@@ -0,0 +1,282 @@
+/*
+ * Copyright (C) 2009 Nokia
+ * Copyright (C) 2009 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define OMAP2420_CONTROL_PADCONF_MUX_PBASE                     0x48000030LU
+
+#define OMAP2420_MUX(mode0, mux_value)                                 \
+{                                                                      \
+       .reg_offset     = (OMAP2420_CONTROL_PADCONF_##mode0##_OFFSET),  \
+       .value          = (mux_value),                                  \
+}
+
+/*
+ * OMAP2420 CONTROL_PADCONF* register offsets for pin-muxing
+ *
+ * Extracted from the TRM.  Add 0x48000030 to these values to get the
+ * absolute addresses.  The name in the macro is the mode-0 name of
+ * the pin.  NOTE: These registers are 8-bits wide.
+ */
+#define OMAP2420_CONTROL_PADCONF_SDRC_A14_OFFSET                       0x000
+#define OMAP2420_CONTROL_PADCONF_SDRC_A13_OFFSET                       0x001
+#define OMAP2420_CONTROL_PADCONF_SDRC_A12_OFFSET                       0x002
+#define OMAP2420_CONTROL_PADCONF_SDRC_BA1_OFFSET                       0x003
+#define OMAP2420_CONTROL_PADCONF_SDRC_BA0_OFFSET                       0x004
+#define OMAP2420_CONTROL_PADCONF_SDRC_A11_OFFSET                       0x005
+#define OMAP2420_CONTROL_PADCONF_SDRC_A10_OFFSET                       0x006
+#define OMAP2420_CONTROL_PADCONF_SDRC_A9_OFFSET                                0x007
+#define OMAP2420_CONTROL_PADCONF_SDRC_A8_OFFSET                                0x008
+#define OMAP2420_CONTROL_PADCONF_SDRC_A7_OFFSET                                0x009
+#define OMAP2420_CONTROL_PADCONF_SDRC_A6_OFFSET                                0x00a
+#define OMAP2420_CONTROL_PADCONF_SDRC_A5_OFFSET                                0x00b
+#define OMAP2420_CONTROL_PADCONF_SDRC_A4_OFFSET                                0x00c
+#define OMAP2420_CONTROL_PADCONF_SDRC_A3_OFFSET                                0x00d
+#define OMAP2420_CONTROL_PADCONF_SDRC_A2_OFFSET                                0x00e
+#define OMAP2420_CONTROL_PADCONF_SDRC_A1_OFFSET                                0x00f
+#define OMAP2420_CONTROL_PADCONF_SDRC_A0_OFFSET                                0x010
+#define OMAP2420_CONTROL_PADCONF_SDRC_D31_OFFSET                       0x021
+#define OMAP2420_CONTROL_PADCONF_SDRC_D30_OFFSET                       0x022
+#define OMAP2420_CONTROL_PADCONF_SDRC_D29_OFFSET                       0x023
+#define OMAP2420_CONTROL_PADCONF_SDRC_D28_OFFSET                       0x024
+#define OMAP2420_CONTROL_PADCONF_SDRC_D27_OFFSET                       0x025
+#define OMAP2420_CONTROL_PADCONF_SDRC_D26_OFFSET                       0x026
+#define OMAP2420_CONTROL_PADCONF_SDRC_D25_OFFSET                       0x027
+#define OMAP2420_CONTROL_PADCONF_SDRC_D24_OFFSET                       0x028
+#define OMAP2420_CONTROL_PADCONF_SDRC_D23_OFFSET                       0x029
+#define OMAP2420_CONTROL_PADCONF_SDRC_D22_OFFSET                       0x02a
+#define OMAP2420_CONTROL_PADCONF_SDRC_D21_OFFSET                       0x02b
+#define OMAP2420_CONTROL_PADCONF_SDRC_D20_OFFSET                       0x02c
+#define OMAP2420_CONTROL_PADCONF_SDRC_D19_OFFSET                       0x02d
+#define OMAP2420_CONTROL_PADCONF_SDRC_D18_OFFSET                       0x02e
+#define OMAP2420_CONTROL_PADCONF_SDRC_D17_OFFSET                       0x02f
+#define OMAP2420_CONTROL_PADCONF_SDRC_D16_OFFSET                       0x030
+#define OMAP2420_CONTROL_PADCONF_SDRC_D15_OFFSET                       0x031
+#define OMAP2420_CONTROL_PADCONF_SDRC_D14_OFFSET                       0x032
+#define OMAP2420_CONTROL_PADCONF_SDRC_D13_OFFSET                       0x033
+#define OMAP2420_CONTROL_PADCONF_SDRC_D12_OFFSET                       0x034
+#define OMAP2420_CONTROL_PADCONF_SDRC_D11_OFFSET                       0x035
+#define OMAP2420_CONTROL_PADCONF_SDRC_D10_OFFSET                       0x036
+#define OMAP2420_CONTROL_PADCONF_SDRC_D9_OFFSET                                0x037
+#define OMAP2420_CONTROL_PADCONF_SDRC_D8_OFFSET                                0x038
+#define OMAP2420_CONTROL_PADCONF_SDRC_D7_OFFSET                                0x039
+#define OMAP2420_CONTROL_PADCONF_SDRC_D6_OFFSET                                0x03a
+#define OMAP2420_CONTROL_PADCONF_SDRC_D5_OFFSET                                0x03b
+#define OMAP2420_CONTROL_PADCONF_SDRC_D4_OFFSET                                0x03c
+#define OMAP2420_CONTROL_PADCONF_SDRC_D3_OFFSET                                0x03d
+#define OMAP2420_CONTROL_PADCONF_SDRC_D2_OFFSET                                0x03e
+#define OMAP2420_CONTROL_PADCONF_SDRC_D1_OFFSET                                0x03f
+#define OMAP2420_CONTROL_PADCONF_SDRC_D0_OFFSET                                0x040
+#define OMAP2420_CONTROL_PADCONF_GPMC_A10_OFFSET                       0x041
+#define OMAP2420_CONTROL_PADCONF_GPMC_A9_OFFSET                                0x042
+#define OMAP2420_CONTROL_PADCONF_GPMC_A8_OFFSET                                0x043
+#define OMAP2420_CONTROL_PADCONF_GPMC_A7_OFFSET                                0x044
+#define OMAP2420_CONTROL_PADCONF_GPMC_A6_OFFSET                                0x045
+#define OMAP2420_CONTROL_PADCONF_GPMC_A5_OFFSET                                0x046
+#define OMAP2420_CONTROL_PADCONF_GPMC_A4_OFFSET                                0x047
+#define OMAP2420_CONTROL_PADCONF_GPMC_A3_OFFSET                                0x048
+#define OMAP2420_CONTROL_PADCONF_GPMC_A2_OFFSET                                0x049
+#define OMAP2420_CONTROL_PADCONF_GPMC_A1_OFFSET                                0x04a
+#define OMAP2420_CONTROL_PADCONF_GPMC_D15_OFFSET                       0x04b
+#define OMAP2420_CONTROL_PADCONF_GPMC_D14_OFFSET                       0x04c
+#define OMAP2420_CONTROL_PADCONF_GPMC_D13_OFFSET                       0x04d
+#define OMAP2420_CONTROL_PADCONF_GPMC_D12_OFFSET                       0x04e
+#define OMAP2420_CONTROL_PADCONF_GPMC_D11_OFFSET                       0x04f
+#define OMAP2420_CONTROL_PADCONF_GPMC_D10_OFFSET                       0x050
+#define OMAP2420_CONTROL_PADCONF_GPMC_D9_OFFSET                                0x051
+#define OMAP2420_CONTROL_PADCONF_GPMC_D8_OFFSET                                0x052
+#define OMAP2420_CONTROL_PADCONF_GPMC_D7_OFFSET                                0x053
+#define OMAP2420_CONTROL_PADCONF_GPMC_D6_OFFSET                                0x054
+#define OMAP2420_CONTROL_PADCONF_GPMC_D5_OFFSET                                0x055
+#define OMAP2420_CONTROL_PADCONF_GPMC_D4_OFFSET                                0x056
+#define OMAP2420_CONTROL_PADCONF_GPMC_D3_OFFSET                                0x057
+#define OMAP2420_CONTROL_PADCONF_GPMC_D2_OFFSET                                0x058
+#define OMAP2420_CONTROL_PADCONF_GPMC_D1_OFFSET                                0x059
+#define OMAP2420_CONTROL_PADCONF_GPMC_D0_OFFSET                                0x05a
+#define OMAP2420_CONTROL_PADCONF_GPMC_CLK_OFFSET                       0x05b
+#define OMAP2420_CONTROL_PADCONF_GPMC_NCS0_OFFSET                      0x05c
+#define OMAP2420_CONTROL_PADCONF_GPMC_NCS1_OFFSET                      0x05d
+#define OMAP2420_CONTROL_PADCONF_GPMC_NCS2_OFFSET                      0x05e
+#define OMAP2420_CONTROL_PADCONF_GPMC_NCS3_OFFSET                      0x05f
+#define OMAP2420_CONTROL_PADCONF_GPMC_NCS4_OFFSET                      0x060
+#define OMAP2420_CONTROL_PADCONF_GPMC_NCS5_OFFSET                      0x061
+#define OMAP2420_CONTROL_PADCONF_GPMC_NCS6_OFFSET                      0x062
+#define OMAP2420_CONTROL_PADCONF_GPMC_NCS7_OFFSET                      0x063
+#define OMAP2420_CONTROL_PADCONF_GPMC_NALE_ALE_OFFSET                  0x064
+#define OMAP2420_CONTROL_PADCONF_GPMC_NOE_OFFSET                       0x065
+#define OMAP2420_CONTROL_PADCONF_GPMC_NWE_OFFSET                       0x066
+#define OMAP2420_CONTROL_PADCONF_GPMC_NBE0_OFFSET                      0x067
+#define OMAP2420_CONTROL_PADCONF_GPMC_NBE1_OFFSET                      0x068
+#define OMAP2420_CONTROL_PADCONF_GPMC_NWP_OFFSET                       0x069
+#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT0_OFFSET                     0x06a
+#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT1_OFFSET                     0x06b
+#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT2_OFFSET                     0x06c
+#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT3_OFFSET                     0x06d
+#define OMAP2420_CONTROL_PADCONF_SDRC_CLK_OFFSET                       0x06e
+#define OMAP2420_CONTROL_PADCONF_SDRC_NCLK_OFFSET                      0x06f
+#define OMAP2420_CONTROL_PADCONF_SDRC_NCS0_OFFSET                      0x070
+#define OMAP2420_CONTROL_PADCONF_SDRC_NCS1_OFFSET                      0x071
+#define OMAP2420_CONTROL_PADCONF_SDRC_CKE0_OFFSET                      0x072
+#define OMAP2420_CONTROL_PADCONF_SDRC_CKE1_OFFSET                      0x073
+#define OMAP2420_CONTROL_PADCONF_SDRC_NRAS_OFFSET                      0x074
+#define OMAP2420_CONTROL_PADCONF_SDRC_NCAS_OFFSET                      0x075
+#define OMAP2420_CONTROL_PADCONF_SDRC_NWE_OFFSET                       0x076
+#define OMAP2420_CONTROL_PADCONF_SDRC_DM0_OFFSET                       0x077
+#define OMAP2420_CONTROL_PADCONF_SDRC_DM1_OFFSET                       0x078
+#define OMAP2420_CONTROL_PADCONF_SDRC_DM2_OFFSET                       0x079
+#define OMAP2420_CONTROL_PADCONF_SDRC_DM3_OFFSET                       0x07a
+#define OMAP2420_CONTROL_PADCONF_SDRC_DQS0_OFFSET                      0x07f
+#define OMAP2420_CONTROL_PADCONF_SDRC_DQS1_OFFSET                      0x080
+#define OMAP2420_CONTROL_PADCONF_SDRC_DQS2_OFFSET                      0x081
+#define OMAP2420_CONTROL_PADCONF_SDRC_DQS3_OFFSET                      0x082
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA0_OFFSET                      0x083
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA1_OFFSET                      0x084
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA2_OFFSET                      0x085
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA3_OFFSET                      0x086
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA4_OFFSET                      0x087
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA5_OFFSET                      0x088
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA6_OFFSET                      0x089
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA7_OFFSET                      0x08a
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA8_OFFSET                      0x08b
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA9_OFFSET                      0x08c
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA10_OFFSET                     0x08d
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA11_OFFSET                     0x08e
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA12_OFFSET                     0x08f
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA13_OFFSET                     0x090
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA14_OFFSET                     0x091
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA15_OFFSET                     0x092
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA16_OFFSET                     0x093
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA17_OFFSET                     0x094
+#define OMAP2420_CONTROL_PADCONF_UART1_CTS_OFFSET                      0x095
+#define OMAP2420_CONTROL_PADCONF_UART1_RTS_OFFSET                      0x096
+#define OMAP2420_CONTROL_PADCONF_UART1_TX_OFFSET                       0x097
+#define OMAP2420_CONTROL_PADCONF_UART1_RX_OFFSET                       0x098
+#define OMAP2420_CONTROL_PADCONF_MCBSP2_DR_OFFSET                      0x099
+#define OMAP2420_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET                    0x09a
+#define OMAP2420_CONTROL_PADCONF_DSS_PCL_OFFSET                                0x09b
+#define OMAP2420_CONTROL_PADCONF_DSS_VSYNC_OFFSET                      0x09c
+#define OMAP2420_CONTROL_PADCONF_DSS_HSYNC_OFFSET                      0x09d
+#define OMAP2420_CONTROL_PADCONF_DSS_ACBIAS_OFFSET                     0x09e
+#define OMAP2420_CONTROL_PADCONF_CAM_D9_OFFSET                         0x09f
+#define OMAP2420_CONTROL_PADCONF_CAM_D8_OFFSET                         0x0a0
+#define OMAP2420_CONTROL_PADCONF_CAM_D7_OFFSET                         0x0a1
+#define OMAP2420_CONTROL_PADCONF_CAM_D6_OFFSET                         0x0a2
+#define OMAP2420_CONTROL_PADCONF_CAM_D5_OFFSET                         0x0a3
+#define OMAP2420_CONTROL_PADCONF_CAM_D4_OFFSET                         0x0a4
+#define OMAP2420_CONTROL_PADCONF_CAM_D3_OFFSET                         0x0a5
+#define OMAP2420_CONTROL_PADCONF_CAM_D2_OFFSET                         0x0a6
+#define OMAP2420_CONTROL_PADCONF_CAM_D1_OFFSET                         0x0a7
+#define OMAP2420_CONTROL_PADCONF_CAM_D0_OFFSET                         0x0a8
+#define OMAP2420_CONTROL_PADCONF_CAM_HS_OFFSET                         0x0a9
+#define OMAP2420_CONTROL_PADCONF_CAM_VS_OFFSET                         0x0aa
+#define OMAP2420_CONTROL_PADCONF_CAM_LCLK_OFFSET                       0x0ab
+#define OMAP2420_CONTROL_PADCONF_CAM_XCLK_OFFSET                       0x0ac
+#define OMAP2420_CONTROL_PADCONF_SSI1_DAT_TX_OFFSET                    0x0ad
+#define OMAP2420_CONTROL_PADCONF_SSI1_FLAG_TX_OFFSET                   0x0ae
+#define OMAP2420_CONTROL_PADCONF_SSI1_RDY_TX_OFFSET                    0x0af
+#define OMAP2420_CONTROL_PADCONF_GPIO_62_OFFSET                                0x0b0
+#define OMAP2420_CONTROL_PADCONF_SSI1_DAT_RX_OFFSET                    0x0b1
+#define OMAP2420_CONTROL_PADCONF_SSI1_FLAG_RX_OFFSET                   0x0b2
+#define OMAP2420_CONTROL_PADCONF_SSI1_RDY_RX_OFFSET                    0x0b3
+#define OMAP2420_CONTROL_PADCONF_SSI1_WAKE_OFFSET                      0x0b4
+#define OMAP2420_CONTROL_PADCONF_VLYNQ_CLK_OFFSET                      0x0b5
+#define OMAP2420_CONTROL_PADCONF_VLYNQ_RX1_OFFSET                      0x0b6
+#define OMAP2420_CONTROL_PADCONF_VLYNQ_RX0_OFFSET                      0x0b7
+#define OMAP2420_CONTROL_PADCONF_VLYNQ_TX1_OFFSET                      0x0b8
+#define OMAP2420_CONTROL_PADCONF_VLYNQ_TX0_OFFSET                      0x0b9
+#define OMAP2420_CONTROL_PADCONF_VLYNQ_NLA_OFFSET                      0x0ba
+#define OMAP2420_CONTROL_PADCONF_UART2_CTS_OFFSET                      0x0bb
+#define OMAP2420_CONTROL_PADCONF_UART2_RTS_OFFSET                      0x0bc
+#define OMAP2420_CONTROL_PADCONF_UART2_TX_OFFSET                       0x0bd
+#define OMAP2420_CONTROL_PADCONF_UART2_RX_OFFSET                       0x0be
+#define OMAP2420_CONTROL_PADCONF_EAC_BT_SCLK_OFFSET                    0x0bf
+#define OMAP2420_CONTROL_PADCONF_EAC_BT_FS_OFFSET                      0x0c0
+#define OMAP2420_CONTROL_PADCONF_EAC_BT_DIN_OFFSET                     0x0c1
+#define OMAP2420_CONTROL_PADCONF_EAC_BT_DOUT_OFFSET                    0x0c2
+#define OMAP2420_CONTROL_PADCONF_MMC_CLKO_OFFSET                       0x0c3
+#define OMAP2420_CONTROL_PADCONF_MMC_CMD_OFFSET                                0x0c4
+#define OMAP2420_CONTROL_PADCONF_MMC_DAT0_OFFSET                       0x0c5
+#define OMAP2420_CONTROL_PADCONF_MMC_DAT1_OFFSET                       0x0c6
+#define OMAP2420_CONTROL_PADCONF_MMC_DAT2_OFFSET                       0x0c7
+#define OMAP2420_CONTROL_PADCONF_MMC_DAT3_OFFSET                       0x0c8
+#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR0_OFFSET                   0x0c9
+#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR1_OFFSET                   0x0ca
+#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR2_OFFSET                   0x0cb
+#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR3_OFFSET                   0x0cc
+#define OMAP2420_CONTROL_PADCONF_MMC_CMD_DIR_OFFSET                    0x0cd
+#define OMAP2420_CONTROL_PADCONF_MMC_CLKI_OFFSET                       0x0ce
+#define OMAP2420_CONTROL_PADCONF_SPI1_CLK_OFFSET                       0x0cf
+#define OMAP2420_CONTROL_PADCONF_SPI1_SIMO_OFFSET                      0x0d0
+#define OMAP2420_CONTROL_PADCONF_SPI1_SOMI_OFFSET                      0x0d1
+#define OMAP2420_CONTROL_PADCONF_SPI1_NCS0_OFFSET                      0x0d2
+#define OMAP2420_CONTROL_PADCONF_SPI1_NCS1_OFFSET                      0x0d3
+#define OMAP2420_CONTROL_PADCONF_SPI1_NCS2_OFFSET                      0x0d4
+#define OMAP2420_CONTROL_PADCONF_SPI1_NCS3_OFFSET                      0x0d5
+#define OMAP2420_CONTROL_PADCONF_SPI2_CLK_OFFSET                       0x0d6
+#define OMAP2420_CONTROL_PADCONF_SPI2_SIMO_OFFSET                      0x0d7
+#define OMAP2420_CONTROL_PADCONF_SPI2_SOMI_OFFSET                      0x0d8
+#define OMAP2420_CONTROL_PADCONF_SPI2_NCS0_OFFSET                      0x0d9
+#define OMAP2420_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET                    0x0da
+#define OMAP2420_CONTROL_PADCONF_MCBSP1_FSR_OFFSET                     0x0db
+#define OMAP2420_CONTROL_PADCONF_MCBSP1_DX_OFFSET                      0x0dc
+#define OMAP2420_CONTROL_PADCONF_MCBSP1_DR_OFFSET                      0x0dd
+#define OMAP2420_CONTROL_PADCONF_MCBSP_CLKS_OFFSET                     0x0de
+#define OMAP2420_CONTROL_PADCONF_MCBSP1_FSX_OFFSET                     0x0df
+#define OMAP2420_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET                    0x0e0
+#define OMAP2420_CONTROL_PADCONF_I2C1_SCL_OFFSET                       0x0e1
+#define OMAP2420_CONTROL_PADCONF_I2C1_SDA_OFFSET                       0x0e2
+#define OMAP2420_CONTROL_PADCONF_I2C2_SCL_OFFSET                       0x0e3
+#define OMAP2420_CONTROL_PADCONF_I2C2_SDA_OFFSET                       0x0e4
+#define OMAP2420_CONTROL_PADCONF_HDQ_SIO_OFFSET                                0x0e5
+#define OMAP2420_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET                 0x0e6
+#define OMAP2420_CONTROL_PADCONF_UART3_RTS_SD_OFFSET                   0x0e7
+#define OMAP2420_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET                  0x0e8
+#define OMAP2420_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET                  0x0e9
+#define OMAP2420_CONTROL_PADCONF_TV_CVBS_OFFSET                                0x0ea
+#define OMAP2420_CONTROL_PADCONF_TV_VREF_OFFSET                                0x0eb
+#define OMAP2420_CONTROL_PADCONF_TV_RREF_OFFSET                                0x0ec
+#define OMAP2420_CONTROL_PADCONF_USB0_PUEN_OFFSET                      0x0ed
+#define OMAP2420_CONTROL_PADCONF_USB0_VP_OFFSET                                0x0ee
+#define OMAP2420_CONTROL_PADCONF_USB0_VM_OFFSET                                0x0ef
+#define OMAP2420_CONTROL_PADCONF_USB0_RCV_OFFSET                       0x0f0
+#define OMAP2420_CONTROL_PADCONF_USB0_TXEN_OFFSET                      0x0f1
+#define OMAP2420_CONTROL_PADCONF_USB0_SE0_OFFSET                       0x0f2
+#define OMAP2420_CONTROL_PADCONF_USB0_DAT_OFFSET                       0x0f3
+#define OMAP2420_CONTROL_PADCONF_EAC_AC_SCLK_OFFSET                    0x0f4
+#define OMAP2420_CONTROL_PADCONF_EAC_AC_FS_OFFSET                      0x0f5
+#define OMAP2420_CONTROL_PADCONF_EAC_AC_DIN_OFFSET                     0x0f6
+#define OMAP2420_CONTROL_PADCONF_EAC_AC_DOUT_OFFSET                    0x0f7
+#define OMAP2420_CONTROL_PADCONF_EAC_AC_MCLK_OFFSET                    0x0f8
+#define OMAP2420_CONTROL_PADCONF_EAC_AC_RST_OFFSET                     0x0f9
+#define OMAP2420_CONTROL_PADCONF_SYS_NRESPWRON_OFFSET                  0x0fa
+#define OMAP2420_CONTROL_PADCONF_SYS_NRESWARM_OFFSET                   0x0fb
+#define OMAP2420_CONTROL_PADCONF_SYS_NIRQ_OFFSET                       0x0fc
+#define OMAP2420_CONTROL_PADCONF_SYS_NV_OFFSET                         0x0fd
+#define OMAP2420_CONTROL_PADCONF_GPIO_119_OFFSET                       0x0fe
+#define OMAP2420_CONTROL_PADCONF_GPIO_120_OFFSET                       0x0ff
+#define OMAP2420_CONTROL_PADCONF_GPIO_121_OFFSET                       0x100
+#define OMAP2420_CONTROL_PADCONF_GPIO_122_OFFSET                       0x101
+#define OMAP2420_CONTROL_PADCONF_SYS_32K_OFFSET                                0x102
+#define OMAP2420_CONTROL_PADCONF_SYS_XTALIN_OFFSET                     0x103
+#define OMAP2420_CONTROL_PADCONF_SYS_XTALOUT_OFFSET                    0x104
+#define OMAP2420_CONTROL_PADCONF_GPIO_36_OFFSET                                0x105
+#define OMAP2420_CONTROL_PADCONF_SYS_CLKREQ_OFFSET                     0x106
+#define OMAP2420_CONTROL_PADCONF_SYS_CLKOUT_OFFSET                     0x107
+#define OMAP2420_CONTROL_PADCONF_GPIO_6_OFFSET                         0x108
+#define OMAP2420_CONTROL_PADCONF_GPIO_124_OFFSET                       0x109
+#define OMAP2420_CONTROL_PADCONF_GPIO_125_OFFSET                       0x10a
+#define OMAP2420_CONTROL_PADCONF_JTAG_EMU1_OFFSET                      0x10b
+#define OMAP2420_CONTROL_PADCONF_JTAG_EMU0_OFFSET                      0x10c
+#define OMAP2420_CONTROL_PADCONF_JTAG_NTRST_OFFSET                     0x10d
+#define OMAP2420_CONTROL_PADCONF_JTAG_TCK_OFFSET                       0x10e
+#define OMAP2420_CONTROL_PADCONF_JTAG_RTCK_OFFSET                      0x10f
+#define OMAP2420_CONTROL_PADCONF_JTAG_TMS_OFFSET                       0x110
+#define OMAP2420_CONTROL_PADCONF_JTAG_TDI_OFFSET                       0x111
+#define OMAP2420_CONTROL_PADCONF_JTAG_TDO_OFFSET                       0x112
+
+#define OMAP2420_CONTROL_PADCONF_MUX_SIZE                      \
+               (OMAP2420_CONTROL_PADCONF_JTAG_TDO_OFFSET + 0x1)

diff --git a/arch/arm/mach-omap2/mux2430.c b/arch/arm/mach-omap2/mux2430.c
new file mode 100644 (file)
index 0000000..7dcaaa8
--- /dev/null
+++ b/arch/arm/mach-omap2/mux2430.c
@@ -0,0 +1,791 @@
+/*
+ * Copyright (C) 2010 Nokia
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include "mux.h"
+
+#ifdef CONFIG_OMAP_MUX
+
+#define _OMAP2430_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)              \
+{                                                                      \
+       .reg_offset     = (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET),     \
+       .gpio           = (g),                                          \
+       .muxnames       = { m0, m1, m2, m3, m4, m5, m6, m7 },           \
+}
+
+#else
+
+#define _OMAP2430_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)              \
+{                                                                      \
+       .reg_offset     = (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET),     \
+       .gpio           = (g),                                          \
+}
+
+#endif
+
+#define _OMAP2430_BALLENTRY(M0, bb, bt)                                        \
+{                                                                      \
+       .reg_offset     = (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET),     \
+       .balls          = { bb, bt },                                   \
+}
+
+/*
+ * Superset of all mux modes for omap2430
+ */
+static struct omap_mux __initdata omap2430_muxmodes[] = {
+       _OMAP2430_MUXENTRY(CAM_D0, 133,
+               "cam_d0", "hw_dbg0", "sti_dout", "gpio_133",
+               NULL, NULL, "etk_d2", "safe_mode"),
+       _OMAP2430_MUXENTRY(CAM_D10, 146,
+               "cam_d10", NULL, NULL, "gpio_146",
+               NULL, NULL, "etk_d12", "safe_mode"),
+       _OMAP2430_MUXENTRY(CAM_D11, 145,
+               "cam_d11", NULL, NULL, "gpio_145",
+               NULL, NULL, "etk_d13", "safe_mode"),
+       _OMAP2430_MUXENTRY(CAM_D1, 132,
+               "cam_d1", "hw_dbg1", "sti_din", "gpio_132",
+               NULL, NULL, "etk_d3", "safe_mode"),
+       _OMAP2430_MUXENTRY(CAM_D2, 129,
+               "cam_d2", "hw_dbg2", "mcbsp1_clkx", "gpio_129",
+               NULL, NULL, "etk_d4", "safe_mode"),
+       _OMAP2430_MUXENTRY(CAM_D3, 128,
+               "cam_d3", "hw_dbg3", "mcbsp1_dr", "gpio_128",
+               NULL, NULL, "etk_d5", "safe_mode"),
+       _OMAP2430_MUXENTRY(CAM_D4, 143,
+               "cam_d4", "hw_dbg4", "mcbsp1_fsr", "gpio_143",
+               NULL, NULL, "etk_d6", "safe_mode"),
+       _OMAP2430_MUXENTRY(CAM_D5, 112,
+               "cam_d5", "hw_dbg5", "mcbsp1_clkr", "gpio_112",
+               NULL, NULL, "etk_d7", "safe_mode"),
+       _OMAP2430_MUXENTRY(CAM_D6, 137,
+               "cam_d6", "hw_dbg6", NULL, "gpio_137",
+               NULL, NULL, "etk_d8", "safe_mode"),
+       _OMAP2430_MUXENTRY(CAM_D7, 136,
+               "cam_d7", "hw_dbg7", NULL, "gpio_136",
+               NULL, NULL, "etk_d9", "safe_mode"),
+       _OMAP2430_MUXENTRY(CAM_D8, 135,
+               "cam_d8", "hw_dbg8", NULL, "gpio_135",
+               NULL, NULL, "etk_d10", "safe_mode"),
+       _OMAP2430_MUXENTRY(CAM_D9, 134,
+               "cam_d9", "hw_dbg9", NULL, "gpio_134",
+               NULL, NULL, "etk_d11", "safe_mode"),
+       _OMAP2430_MUXENTRY(CAM_HS, 11,
+               "cam_hs", "hw_dbg10", "mcbsp1_dx", "gpio_11",
+               NULL, NULL, "etk_d1", "safe_mode"),
+       _OMAP2430_MUXENTRY(CAM_LCLK, 0,
+               "cam_lclk", NULL, "mcbsp_clks", NULL,
+               NULL, NULL, "etk_c1", "safe_mode"),
+       _OMAP2430_MUXENTRY(CAM_VS, 12,
+               "cam_vs", "hw_dbg11", "mcbsp1_fsx", "gpio_12",
+               NULL, NULL, "etk_d0", "safe_mode"),
+       _OMAP2430_MUXENTRY(CAM_XCLK, 0,
+               "cam_xclk", NULL, "sti_clk", NULL,
+               NULL, NULL, "etk_c2", NULL),
+       _OMAP2430_MUXENTRY(DSS_ACBIAS, 48,
+               "dss_acbias", NULL, "mcbsp2_fsx", "gpio_48",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(DSS_DATA0, 40,
+               "dss_data0", "uart1_cts", NULL, "gpio_40",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(DSS_DATA10, 128,
+               "dss_data10", "sdi_data1n", NULL, "gpio_128",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(DSS_DATA11, 129,
+               "dss_data11", "sdi_data1p", NULL, "gpio_129",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(DSS_DATA12, 130,
+               "dss_data12", "sdi_data2n", NULL, "gpio_130",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(DSS_DATA13, 131,
+               "dss_data13", "sdi_data2p", NULL, "gpio_131",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(DSS_DATA14, 132,
+               "dss_data14", "sdi_data3n", NULL, "gpio_132",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(DSS_DATA15, 133,
+               "dss_data15", "sdi_data3p", NULL, "gpio_133",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(DSS_DATA16, 46,
+               "dss_data16", NULL, NULL, "gpio_46",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(DSS_DATA17, 47,
+               "dss_data17", NULL, NULL, "gpio_47",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(DSS_DATA1, 41,
+               "dss_data1", "uart1_rts", NULL, "gpio_41",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(DSS_DATA2, 42,
+               "dss_data2", "uart1_tx", NULL, "gpio_42",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(DSS_DATA3, 43,
+               "dss_data3", "uart1_rx", NULL, "gpio_43",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(DSS_DATA4, 44,
+               "dss_data4", "uart3_rx_irrx", NULL, "gpio_44",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(DSS_DATA5, 45,
+               "dss_data5", "uart3_tx_irtx", NULL, "gpio_45",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(DSS_DATA6, 144,
+               "dss_data6", NULL, NULL, "gpio_144",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(DSS_DATA7, 147,
+               "dss_data7", NULL, NULL, "gpio_147",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(DSS_DATA8, 38,
+               "dss_data8", NULL, NULL, "gpio_38",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(DSS_DATA9, 39,
+               "dss_data9", NULL, NULL, "gpio_39",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(DSS_HSYNC, 110,
+               "dss_hsync", NULL, NULL, "gpio_110",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_113, 113,
+               "gpio_113", "mcbsp2_clkx", NULL, "gpio_113",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_114, 114,
+               "gpio_114", "mcbsp2_fsx", NULL, "gpio_114",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_115, 115,
+               "gpio_115", "mcbsp2_dr", NULL, "gpio_115",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_116, 116,
+               "gpio_116", "mcbsp2_dx", NULL, "gpio_116",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_128, 128,
+               "gpio_128", NULL, "sti_din", "gpio_128",
+               NULL, "sys_boot0", NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_129, 129,
+               "gpio_129", NULL, "sti_dout", "gpio_129",
+               NULL, "sys_boot1", NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_130, 130,
+               "gpio_130", NULL, NULL, "gpio_130",
+               "jtag_emu2", "sys_boot2", NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_131, 131,
+               "gpio_131", NULL, NULL, "gpio_131",
+               "jtag_emu3", "sys_boot3", NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_132, 132,
+               "gpio_132", NULL, NULL, "gpio_132",
+               NULL, "sys_boot4", NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_133, 133,
+               "gpio_133", NULL, NULL, "gpio_133",
+               NULL, "sys_boot5", NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_134, 134,
+               "gpio_134", "ccp_datn", NULL, "gpio_134",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_135, 135,
+               "gpio_135", "ccp_datp", NULL, "gpio_135",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_136, 136,
+               "gpio_136", "ccp_clkn", NULL, "gpio_136",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_137, 137,
+               "gpio_137", "ccp_clkp", NULL, "gpio_137",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_138, 138,
+               "gpio_138", "spi3_clk", NULL, "gpio_138",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_139, 139,
+               "gpio_139", "spi3_cs0", "sys_ndmareq3", "gpio_139",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_140, 140,
+               "gpio_140", "spi3_simo", "sys_ndmareq4", "gpio_140",
+               NULL, NULL, "etk_d14", "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_141, 141,
+               "gpio_141", "spi3_somi", NULL, "gpio_141",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_142, 142,
+               "gpio_142", "spi3_cs1", "sys_ndmareq2", "gpio_142",
+               NULL, NULL, "etk_d15", "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_148, 148,
+               "gpio_148", "mcbsp5_fsx", NULL, "gpio_148",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_149, 149,
+               "gpio_149", "mcbsp5_dx", NULL, "gpio_149",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_150, 150,
+               "gpio_150", "mcbsp5_dr", NULL, "gpio_150",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_151, 151,
+               "gpio_151", "sys_pwrok", NULL, "gpio_151",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_152, 152,
+               "gpio_152", "uart1_cts", "sys_ndmareq1", "gpio_152",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_153, 153,
+               "gpio_153", "uart1_rx", "sys_ndmareq0", "gpio_153",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_154, 154,
+               "gpio_154", "mcbsp5_clkx", NULL, "gpio_154",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_63, 63,
+               "gpio_63", "mcbsp4_clkx", NULL, "gpio_63",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_78, 78,
+               "gpio_78", NULL, "uart2_rts", "gpio_78",
+               "uart3_rts_sd", NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_79, 79,
+               "gpio_79", "secure_indicator", "uart2_tx", "gpio_79",
+               "uart3_tx_irtx", NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_7, 7,
+               "gpio_7", NULL, "uart2_cts", "gpio_7",
+               "uart3_cts_rctx", NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPIO_80, 80,
+               "gpio_80", NULL, "uart2_rx", "gpio_80",
+               "uart3_rx_irrx", NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_A10, 3,
+               "gpmc_a10", NULL, "sys_ndmareq0", "gpio_3",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_A1, 31,
+               "gpmc_a1", NULL, NULL, "gpio_31",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_A2, 30,
+               "gpmc_a2", NULL, NULL, "gpio_30",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_A3, 29,
+               "gpmc_a3", NULL, NULL, "gpio_29",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_A4, 49,
+               "gpmc_a4", NULL, NULL, "gpio_49",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_A5, 53,
+               "gpmc_a5", NULL, NULL, "gpio_53",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_A6, 52,
+               "gpmc_a6", NULL, NULL, "gpio_52",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_A7, 6,
+               "gpmc_a7", NULL, NULL, "gpio_6",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_A8, 5,
+               "gpmc_a8", NULL, NULL, "gpio_5",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_A9, 4,
+               "gpmc_a9", NULL, "sys_ndmareq1", "gpio_4",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_CLK, 21,
+               "gpmc_clk", NULL, NULL, "gpio_21",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_D10, 18,
+               "gpmc_d10", NULL, NULL, "gpio_18",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_D11, 57,
+               "gpmc_d11", NULL, NULL, "gpio_57",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_D12, 77,
+               "gpmc_d12", NULL, NULL, "gpio_77",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_D13, 76,
+               "gpmc_d13", NULL, NULL, "gpio_76",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_D14, 55,
+               "gpmc_d14", NULL, NULL, "gpio_55",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_D15, 54,
+               "gpmc_d15", NULL, NULL, "gpio_54",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_D8, 20,
+               "gpmc_d8", NULL, NULL, "gpio_20",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_D9, 19,
+               "gpmc_d9", NULL, NULL, "gpio_19",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_NCS1, 22,
+               "gpmc_ncs1", NULL, NULL, "gpio_22",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_NCS2, 23,
+               "gpmc_ncs2", NULL, NULL, "gpio_23",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_NCS3, 24,
+               "gpmc_ncs3", "gpmc_io_dir", NULL, "gpio_24",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_NCS4, 25,
+               "gpmc_ncs4", NULL, NULL, "gpio_25",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_NCS5, 26,
+               "gpmc_ncs5", NULL, NULL, "gpio_26",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_NCS6, 27,
+               "gpmc_ncs6", NULL, NULL, "gpio_27",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_NCS7, 28,
+               "gpmc_ncs7", "gpmc_io_dir", NULL, "gpio_28",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_WAIT1, 33,
+               "gpmc_wait1", NULL, NULL, "gpio_33",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_WAIT2, 34,
+               "gpmc_wait2", NULL, NULL, "gpio_34",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(GPMC_WAIT3, 35,
+               "gpmc_wait3", NULL, NULL, "gpio_35",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(HDQ_SIO, 101,
+               "hdq_sio", "usb2_tllse0", "sys_altclk", "gpio_101",
+               "uart3_rx_irrx", NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(I2C1_SCL, 50,
+               "i2c1_scl", NULL, NULL, "gpio_50",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(I2C1_SDA, 51,
+               "i2c1_sda", NULL, NULL, "gpio_51",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(I2C2_SCL, 99,
+               "i2c2_scl", NULL, NULL, "gpio_99",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(I2C2_SDA, 100,
+               "i2c2_sda", NULL, NULL, "gpio_100",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(JTAG_EMU0, 127,
+               "jtag_emu0", "secure_indicator", NULL, "gpio_127",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(JTAG_EMU1, 126,
+               "jtag_emu1", NULL, NULL, "gpio_126",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(MCBSP1_CLKR, 92,
+               "mcbsp1_clkr", "ssi2_dat_tx", NULL, "gpio_92",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(MCBSP1_CLKX, 98,
+               "mcbsp1_clkx", "ssi2_wake", NULL, "gpio_98",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(MCBSP1_DR, 95,
+               "mcbsp1_dr", "ssi2_dat_rx", NULL, "gpio_95",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(MCBSP1_DX, 94,
+               "mcbsp1_dx", "ssi2_rdy_tx", NULL, "gpio_94",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(MCBSP1_FSR, 93,
+               "mcbsp1_fsr", "ssi2_flag_tx", NULL, "gpio_93",
+               "spi2_cs1", NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(MCBSP1_FSX, 97,
+               "mcbsp1_fsx", "ssi2_rdy_rx", NULL, "gpio_97",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(MCBSP2_CLKX, 147,
+               "mcbsp2_clkx", "sdi_clkp", "dss_data23", "gpio_147",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(MCBSP2_DR, 144,
+               "mcbsp2_dr", "sdi_clkn", "dss_data22", "gpio_144",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(MCBSP3_CLKX, 71,
+               "mcbsp3_clkx", NULL, NULL, "gpio_71",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(MCBSP3_DR, 73,
+               "mcbsp3_dr", NULL, NULL, "gpio_73",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(MCBSP3_DX, 74,
+               "mcbsp3_dx", NULL, "sti_clk", "gpio_74",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(MCBSP3_FSX, 72,
+               "mcbsp3_fsx", NULL, NULL, "gpio_72",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(MCBSP_CLKS, 96,
+               "mcbsp_clks", "ssi2_flag_rx", NULL, "gpio_96",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SDMMC1_CLKO, 0,
+               "sdmmc1_clko", "ms_clko", NULL, NULL,
+               NULL, "hw_dbg9", "hw_dbg3", "safe_mode"),
+       _OMAP2430_MUXENTRY(SDMMC1_CMD, 0,
+               "sdmmc1_cmd", "ms_bs", NULL, NULL,
+               NULL, "hw_dbg8", "hw_dbg2", "safe_mode"),
+       _OMAP2430_MUXENTRY(SDMMC1_DAT0, 0,
+               "sdmmc1_dat0", "ms_dat0", NULL, NULL,
+               NULL, "hw_dbg7", "hw_dbg1", "safe_mode"),
+       _OMAP2430_MUXENTRY(SDMMC1_DAT1, 75,
+               "sdmmc1_dat1", "ms_dat1", NULL, "gpio_75",
+               NULL, "hw_dbg6", "hw_dbg0", "safe_mode"),
+       _OMAP2430_MUXENTRY(SDMMC1_DAT2, 0,
+               "sdmmc1_dat2", "ms_dat2", NULL, NULL,
+               NULL, "hw_dbg5", "hw_dbg10", "safe_mode"),
+       _OMAP2430_MUXENTRY(SDMMC1_DAT3, 0,
+               "sdmmc1_dat3", "ms_dat3", NULL, NULL,
+               NULL, "hw_dbg4", "hw_dbg11", "safe_mode"),
+       _OMAP2430_MUXENTRY(SDMMC2_CLKO, 13,
+               "sdmmc2_clko", NULL, NULL, "gpio_13",
+               NULL, "spi3_clk", NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SDMMC2_CMD, 15,
+               "sdmmc2_cmd", "usb2_rcv", NULL, "gpio_15",
+               NULL, "spi3_simo", NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SDMMC2_DAT0, 16,
+               "sdmmc2_dat0", "usb2_tllse0", NULL, "gpio_16",
+               NULL, "spi3_somi", NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SDMMC2_DAT1, 58,
+               "sdmmc2_dat1", "usb2_txen", NULL, "gpio_58",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SDMMC2_DAT2, 17,
+               "sdmmc2_dat2", "usb2_dat", NULL, "gpio_17",
+               NULL, "spi3_cs1", NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SDMMC2_DAT3, 14,
+               "sdmmc2_dat3", "usb2_se0", NULL, "gpio_14",
+               NULL, "spi3_cs0", NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SDRC_A12, 2,
+               "sdrc_a12", NULL, NULL, "gpio_2",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SDRC_A13, 1,
+               "sdrc_a13", NULL, NULL, "gpio_1",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SDRC_A14, 0,
+               "sdrc_a14", NULL, NULL, "gpio_0",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SDRC_CKE1, 36,
+               "sdrc_cke1", NULL, NULL, "gpio_36",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SDRC_NCS1, 37,
+               "sdrc_ncs1", NULL, NULL, "gpio_37",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SPI1_CLK, 81,
+               "spi1_clk", NULL, NULL, "gpio_81",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SPI1_CS0, 84,
+               "spi1_cs0", NULL, NULL, "gpio_84",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SPI1_CS1, 85,
+               "spi1_cs1", NULL, NULL, "gpio_85",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SPI1_CS2, 86,
+               "spi1_cs2", NULL, NULL, "gpio_86",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SPI1_CS3, 87,
+               "spi1_cs3", "spi2_cs1", NULL, "gpio_87",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SPI1_SIMO, 82,
+               "spi1_simo", NULL, NULL, "gpio_82",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SPI1_SOMI, 83,
+               "spi1_somi", NULL, NULL, "gpio_83",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SPI2_CLK, 88,
+               "spi2_clk", "gpt9_pwm_evt", NULL, "gpio_88",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SPI2_CS0, 91,
+               "spi2_cs0", "gpt12_pwm_evt", NULL, "gpio_91",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SPI2_SIMO, 89,
+               "spi2_simo", "gpt10_pwm_evt", NULL, "gpio_89",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SPI2_SOMI, 90,
+               "spi2_somi", "gpt11_pwm_evt", NULL, "gpio_90",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SSI1_DAT_RX, 62,
+               "ssi1_dat_rx", "uart1_rx", "usb1_dat", "gpio_62",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SSI1_DAT_TX, 59,
+               "ssi1_dat_tx", "uart1_tx", "usb1_se0", "gpio_59",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SSI1_FLAG_RX, 64,
+               "ssi1_flag_rx", "mcbsp4_dr", NULL, "gpio_64",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SSI1_FLAG_TX, 60,
+               "ssi1_flag_tx", "uart1_rts", "usb1_rcv", "gpio_60",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SSI1_RDY_RX, 65,
+               "ssi1_rdy_rx", "mcbsp4_dx", NULL, "gpio_65",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SSI1_RDY_TX, 61,
+               "ssi1_rdy_tx", "uart1_cts", "usb1_txen", "gpio_61",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SSI1_WAKE, 66,
+               "ssi1_wake", "mcbsp4_fsx", NULL, "gpio_66",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SYS_CLKOUT, 111,
+               "sys_clkout", NULL, NULL, "gpio_111",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SYS_DRM_MSECURE, 118,
+               "sys_drm_msecure", NULL, "sys_ndmareq6", "gpio_118",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SYS_NIRQ0, 56,
+               "sys_nirq0", NULL, NULL, "gpio_56",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(SYS_NIRQ1, 125,
+               "sys_nirq1", NULL, "sys_ndmareq5", "gpio_125",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(UART1_CTS, 32,
+               "uart1_cts", "sdi_vsync", "dss_data18", "gpio_32",
+               "mcbsp5_clkx", NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(UART1_RTS, 8,
+               "uart1_rts", "sdi_hsync", "dss_data19", "gpio_8",
+               "mcbsp5_fsx", NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(UART1_RX, 10,
+               "uart1_rx", "sdi_stp", "dss_data21", "gpio_10",
+               "mcbsp5_dr", NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(UART1_TX, 9,
+               "uart1_tx", "sdi_den", "dss_data20", "gpio_9",
+               "mcbsp5_dx", NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(UART2_CTS, 67,
+               "uart2_cts", "usb1_rcv", "gpt9_pwm_evt", "gpio_67",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(UART2_RTS, 68,
+               "uart2_rts", "usb1_txen", "gpt10_pwm_evt", "gpio_68",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(UART2_RX, 70,
+               "uart2_rx", "usb1_dat", "gpt12_pwm_evt", "gpio_70",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(UART2_TX, 69,
+               "uart2_tx", "usb1_se0", "gpt11_pwm_evt", "gpio_69",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(UART3_CTS_RCTX, 102,
+               "uart3_cts_rctx", "uart3_rx_irrx", NULL, "gpio_102",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(UART3_RTS_SD, 103,
+               "uart3_rts_sd", "uart3_tx_irtx", NULL, "gpio_103",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(UART3_RX_IRRX, 105,
+               "uart3_rx_irrx", NULL, NULL, "gpio_105",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(UART3_TX_IRTX, 104,
+               "uart3_tx_irtx", "uart3_cts_rctx", NULL, "gpio_104",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(USB0HS_CLK, 120,
+               "usb0hs_clk", NULL, NULL, "gpio_120",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(USB0HS_DATA0, 0,
+               "usb0hs_data0", "uart3_tx_irtx", NULL, NULL,
+               "usb0_txen", NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(USB0HS_DATA1, 0,
+               "usb0hs_data1", "uart3_rx_irrx", NULL, NULL,
+               "usb0_dat", NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(USB0HS_DATA2, 0,
+               "usb0hs_data2", "uart3_rts_sd", NULL, NULL,
+               "usb0_se0", NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(USB0HS_DATA3, 106,
+               "usb0hs_data3", NULL, "uart3_cts_rctx", "gpio_106",
+               "usb0_puen", NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(USB0HS_DATA4, 107,
+               "usb0hs_data4", "mcbsp2_dr", NULL, "gpio_107",
+               "usb0_vp", NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(USB0HS_DATA5, 108,
+               "usb0hs_data5", "mcbsp2_dx", NULL, "gpio_108",
+               "usb0_vm", NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(USB0HS_DATA6, 109,
+               "usb0hs_data6", "mcbsp2_fsx", NULL, "gpio_109",
+               "usb0_rcv", NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(USB0HS_DATA7, 124,
+               "usb0hs_data7", "mcbsp2_clkx", NULL, "gpio_124",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(USB0HS_DIR, 121,
+               "usb0hs_dir", NULL, NULL, "gpio_121",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(USB0HS_NXT, 123,
+               "usb0hs_nxt", NULL, NULL, "gpio_123",
+               NULL, NULL, NULL, "safe_mode"),
+       _OMAP2430_MUXENTRY(USB0HS_STP, 122,
+               "usb0hs_stp", NULL, NULL, "gpio_122",
+               NULL, NULL, NULL, "safe_mode"),
+       { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+/*
+ * Balls for POP package
+ * 447-pin s-PBGA Package, 0.00mm Ball Pitch (Bottom)
+ */
+#ifdef CONFIG_DEBUG_FS
+struct omap_ball __initdata omap2430_pop_ball[] = {
+       _OMAP2430_BALLENTRY(CAM_D0, "t8", NULL),
+       _OMAP2430_BALLENTRY(CAM_D1, "t4", NULL),
+       _OMAP2430_BALLENTRY(CAM_D10, "r4", NULL),
+       _OMAP2430_BALLENTRY(CAM_D11, "w3", NULL),
+       _OMAP2430_BALLENTRY(CAM_D2, "r2", NULL),
+       _OMAP2430_BALLENTRY(CAM_D3, "u3", NULL),
+       _OMAP2430_BALLENTRY(CAM_D4, "u2", NULL),
+       _OMAP2430_BALLENTRY(CAM_D5, "v1", NULL),
+       _OMAP2430_BALLENTRY(CAM_D6, "t3", NULL),
+       _OMAP2430_BALLENTRY(CAM_D7, "r3", NULL),
+       _OMAP2430_BALLENTRY(CAM_D8, "u7", NULL),
+       _OMAP2430_BALLENTRY(CAM_D9, "t7", NULL),
+       _OMAP2430_BALLENTRY(CAM_HS, "p2", NULL),
+       _OMAP2430_BALLENTRY(CAM_LCLK, "r7", NULL),
+       _OMAP2430_BALLENTRY(CAM_VS, "n2", NULL),
+       _OMAP2430_BALLENTRY(CAM_XCLK, "p3", NULL),
+       _OMAP2430_BALLENTRY(DSS_ACBIAS, "y3", NULL),
+       _OMAP2430_BALLENTRY(DSS_DATA0, "v8", NULL),
+       _OMAP2430_BALLENTRY(DSS_DATA1, "w1", NULL),
+       _OMAP2430_BALLENTRY(DSS_DATA10, "k25", NULL),
+       _OMAP2430_BALLENTRY(DSS_DATA11, "j25", NULL),
+       _OMAP2430_BALLENTRY(DSS_DATA12, "k24", NULL),
+       _OMAP2430_BALLENTRY(DSS_DATA13, "j24", NULL),
+       _OMAP2430_BALLENTRY(DSS_DATA14, "h25", NULL),
+       _OMAP2430_BALLENTRY(DSS_DATA15, "g25", NULL),
+       _OMAP2430_BALLENTRY(DSS_DATA16, "ac3", NULL),
+       _OMAP2430_BALLENTRY(DSS_DATA17, "y7", NULL),
+       _OMAP2430_BALLENTRY(DSS_DATA2, "u8", NULL),
+       _OMAP2430_BALLENTRY(DSS_DATA3, "u4", NULL),
+       _OMAP2430_BALLENTRY(DSS_DATA4, "v3", NULL),
+       _OMAP2430_BALLENTRY(DSS_DATA5, "aa4", NULL),
+       _OMAP2430_BALLENTRY(DSS_DATA6, "w8", NULL),
+       _OMAP2430_BALLENTRY(DSS_DATA7, "y1", NULL),
+       _OMAP2430_BALLENTRY(DSS_DATA8, "aa2", NULL),
+       _OMAP2430_BALLENTRY(DSS_DATA9, "ab4", NULL),
+       _OMAP2430_BALLENTRY(DSS_HSYNC, "v2", NULL),
+       _OMAP2430_BALLENTRY(GPIO_113, "ad16", NULL),
+       _OMAP2430_BALLENTRY(GPIO_114, "ac10", NULL),
+       _OMAP2430_BALLENTRY(GPIO_115, "ad13", NULL),
+       _OMAP2430_BALLENTRY(GPIO_116, "ae15", NULL),
+       _OMAP2430_BALLENTRY(GPIO_128, "p1", NULL),
+       _OMAP2430_BALLENTRY(GPIO_129, "r1", NULL),
+       _OMAP2430_BALLENTRY(GPIO_130, "p7", NULL),
+       _OMAP2430_BALLENTRY(GPIO_131, "l8", NULL),
+       _OMAP2430_BALLENTRY(GPIO_132, "w24", NULL),
+       _OMAP2430_BALLENTRY(GPIO_133, "aa24", NULL),
+       _OMAP2430_BALLENTRY(GPIO_134, "ae12", NULL),
+       _OMAP2430_BALLENTRY(GPIO_135, "ae11", NULL),
+       _OMAP2430_BALLENTRY(GPIO_136, "ad12", NULL),
+       _OMAP2430_BALLENTRY(GPIO_137, "ad11", NULL),
+       _OMAP2430_BALLENTRY(GPIO_138, "y12", NULL),
+       _OMAP2430_BALLENTRY(GPIO_139, "ad17", NULL),
+       _OMAP2430_BALLENTRY(GPIO_140, "l7", NULL),
+       _OMAP2430_BALLENTRY(GPIO_141, "ac24", NULL),
+       _OMAP2430_BALLENTRY(GPIO_142, "m3", NULL),
+       _OMAP2430_BALLENTRY(GPIO_148, "af12", NULL),
+       _OMAP2430_BALLENTRY(GPIO_149, "k7", NULL),
+       _OMAP2430_BALLENTRY(GPIO_150, "m1", NULL),
+       _OMAP2430_BALLENTRY(GPIO_151, "ad14", NULL),
+       _OMAP2430_BALLENTRY(GPIO_152, "ad18", NULL),
+       _OMAP2430_BALLENTRY(GPIO_153, "u24", NULL),
+       _OMAP2430_BALLENTRY(GPIO_154, "ae16", NULL),
+       _OMAP2430_BALLENTRY(GPIO_63, "n3", NULL),
+       _OMAP2430_BALLENTRY(GPIO_7, "ac23", NULL),
+       _OMAP2430_BALLENTRY(GPIO_78, "ad10", NULL),
+       _OMAP2430_BALLENTRY(GPIO_79, "ae10", NULL),
+       _OMAP2430_BALLENTRY(GPIO_80, "ae13", NULL),
+       _OMAP2430_BALLENTRY(GPMC_A1, "a9", NULL),
+       _OMAP2430_BALLENTRY(GPMC_A10, "g12", NULL),
+       _OMAP2430_BALLENTRY(GPMC_A2, "b8", NULL),
+       _OMAP2430_BALLENTRY(GPMC_A3, "g10", NULL),
+       _OMAP2430_BALLENTRY(GPMC_A4, "g11", NULL),
+       _OMAP2430_BALLENTRY(GPMC_A5, "a10", NULL),
+       _OMAP2430_BALLENTRY(GPMC_A6, "g13", NULL),
+       _OMAP2430_BALLENTRY(GPMC_A7, "a6", NULL),
+       _OMAP2430_BALLENTRY(GPMC_A8, "h1", NULL),
+       _OMAP2430_BALLENTRY(GPMC_A9, "c8", NULL),
+       _OMAP2430_BALLENTRY(GPMC_CLK, "n1", "l1"),
+       _OMAP2430_BALLENTRY(GPMC_D10, "d1", "n1"),
+       _OMAP2430_BALLENTRY(GPMC_D11, "d2", "p2"),
+       _OMAP2430_BALLENTRY(GPMC_D12, "e1", "p1"),
+       _OMAP2430_BALLENTRY(GPMC_D13, "e3", "m1"),
+       _OMAP2430_BALLENTRY(GPMC_D14, "c7", "j2"),
+       _OMAP2430_BALLENTRY(GPMC_D15, "f3", "k2"),
+       _OMAP2430_BALLENTRY(GPMC_D8, "e2", "r1"),
+       _OMAP2430_BALLENTRY(GPMC_D9, "ab1", "t1"),
+       _OMAP2430_BALLENTRY(GPMC_NCS1, "ac1", "w1"),
+       _OMAP2430_BALLENTRY(GPMC_NCS2, "c6", NULL),
+       _OMAP2430_BALLENTRY(GPMC_NCS3, "b9", NULL),
+       _OMAP2430_BALLENTRY(GPMC_NCS4, "b4", NULL),
+       _OMAP2430_BALLENTRY(GPMC_NCS5, "a4", NULL),
+       _OMAP2430_BALLENTRY(GPMC_NCS6, "f1", NULL),
+       _OMAP2430_BALLENTRY(GPMC_NCS7, "a7", NULL),
+       _OMAP2430_BALLENTRY(GPMC_WAIT1, "j1", "y8"),
+       _OMAP2430_BALLENTRY(GPMC_WAIT2, "b7", NULL),
+       _OMAP2430_BALLENTRY(GPMC_WAIT3, "g14", NULL),
+       _OMAP2430_BALLENTRY(HDQ_SIO, "h20", NULL),
+       _OMAP2430_BALLENTRY(I2C1_SCL, "y17", NULL),
+       _OMAP2430_BALLENTRY(I2C1_SDA, "ac19", NULL),
+       _OMAP2430_BALLENTRY(I2C2_SCL, "n7", NULL),
+       _OMAP2430_BALLENTRY(I2C2_SDA, "m4", NULL),
+       _OMAP2430_BALLENTRY(JTAG_EMU0, "e25", NULL),
+       _OMAP2430_BALLENTRY(JTAG_EMU1, "e24", NULL),
+       _OMAP2430_BALLENTRY(MCBSP1_CLKR, "ab2", NULL),
+       _OMAP2430_BALLENTRY(MCBSP1_CLKX, "y9", NULL),
+       _OMAP2430_BALLENTRY(MCBSP1_DR, "af3", NULL),
+       _OMAP2430_BALLENTRY(MCBSP1_DX, "aa1", NULL),
+       _OMAP2430_BALLENTRY(MCBSP1_FSR, "ad5", NULL),
+       _OMAP2430_BALLENTRY(MCBSP1_FSX, "ab3", NULL),
+       _OMAP2430_BALLENTRY(MCBSP2_CLKX, "j26", NULL),
+       _OMAP2430_BALLENTRY(MCBSP2_DR, "k26", NULL),
+       _OMAP2430_BALLENTRY(MCBSP3_CLKX, "ac9", NULL),
+       _OMAP2430_BALLENTRY(MCBSP3_DR, "ae2", NULL),
+       _OMAP2430_BALLENTRY(MCBSP3_DX, "af4", NULL),
+       _OMAP2430_BALLENTRY(MCBSP3_FSX, "ae4", NULL),
+       _OMAP2430_BALLENTRY(MCBSP_CLKS, "ad6", NULL),
+       _OMAP2430_BALLENTRY(SDMMC1_CLKO, "n23", NULL),
+       _OMAP2430_BALLENTRY(SDMMC1_CMD, "l23", NULL),
+       _OMAP2430_BALLENTRY(SDMMC1_DAT0, "m24", NULL),
+       _OMAP2430_BALLENTRY(SDMMC1_DAT1, "p23", NULL),
+       _OMAP2430_BALLENTRY(SDMMC1_DAT2, "t20", NULL),
+       _OMAP2430_BALLENTRY(SDMMC1_DAT3, "r20", NULL),
+       _OMAP2430_BALLENTRY(SDMMC2_CLKO, "v26", NULL),
+       _OMAP2430_BALLENTRY(SDMMC2_CMD, "w20", NULL),
+       _OMAP2430_BALLENTRY(SDMMC2_DAT0, "v23", NULL),
+       _OMAP2430_BALLENTRY(SDMMC2_DAT1, "y24", NULL),
+       _OMAP2430_BALLENTRY(SDMMC2_DAT2, "v25", NULL),
+       _OMAP2430_BALLENTRY(SDMMC2_DAT3, "v24", NULL),
+       _OMAP2430_BALLENTRY(SDRC_A12, "w26", "r21"),
+       _OMAP2430_BALLENTRY(SDRC_A13, "af20", "aa15"),
+       _OMAP2430_BALLENTRY(SDRC_A14, "af16", "y12"),
+       _OMAP2430_BALLENTRY(SDRC_CKE1, "af15", "y13"),
+       _OMAP2430_BALLENTRY(SDRC_NCS1, "aa25", "t20"),
+       _OMAP2430_BALLENTRY(SPI1_CLK, "y18", NULL),
+       _OMAP2430_BALLENTRY(SPI1_CS0, "u1", NULL),
+       _OMAP2430_BALLENTRY(SPI1_CS1, "af19", NULL),
+       _OMAP2430_BALLENTRY(SPI1_CS2, "ae19", NULL),
+       _OMAP2430_BALLENTRY(SPI1_CS3, "h24", NULL),
+       _OMAP2430_BALLENTRY(SPI1_SIMO, "ad15", NULL),
+       _OMAP2430_BALLENTRY(SPI1_SOMI, "ae17", NULL),
+       _OMAP2430_BALLENTRY(SPI2_CLK, "y20", NULL),
+       _OMAP2430_BALLENTRY(SPI2_CS0, "y19", NULL),
+       _OMAP2430_BALLENTRY(SPI2_SIMO, "ac20", NULL),
+       _OMAP2430_BALLENTRY(SPI2_SOMI, "ad19", NULL),
+       _OMAP2430_BALLENTRY(SSI1_DAT_RX, "aa26", NULL),
+       _OMAP2430_BALLENTRY(SSI1_DAT_TX, "ad24", NULL),
+       _OMAP2430_BALLENTRY(SSI1_FLAG_RX, "ad23", NULL),
+       _OMAP2430_BALLENTRY(SSI1_FLAG_TX, "ab24", NULL),
+       _OMAP2430_BALLENTRY(SSI1_RDY_RX, "ab25", NULL),
+       _OMAP2430_BALLENTRY(SSI1_RDY_TX, "y25", NULL),
+       _OMAP2430_BALLENTRY(SSI1_WAKE, "ac25", NULL),
+       _OMAP2430_BALLENTRY(SYS_CLKOUT, "r25", NULL),
+       _OMAP2430_BALLENTRY(SYS_DRM_MSECURE, "ae3", NULL),
+       _OMAP2430_BALLENTRY(SYS_NIRQ0, "w25", NULL),
+       _OMAP2430_BALLENTRY(SYS_NIRQ1, "ad21", NULL),
+       _OMAP2430_BALLENTRY(UART1_CTS, "p24", NULL),
+       _OMAP2430_BALLENTRY(UART1_RTS, "p25", NULL),
+       _OMAP2430_BALLENTRY(UART1_RX, "n24", NULL),
+       _OMAP2430_BALLENTRY(UART1_TX, "r24", NULL),
+       _OMAP2430_BALLENTRY(UART2_CTS, "u25", NULL),
+       _OMAP2430_BALLENTRY(UART2_RTS, "t23", NULL),
+       _OMAP2430_BALLENTRY(UART2_RX, "t24", NULL),
+       _OMAP2430_BALLENTRY(UART2_TX, "u20", NULL),
+       _OMAP2430_BALLENTRY(UART3_CTS_RCTX, "m2", NULL),
+       _OMAP2430_BALLENTRY(UART3_RTS_SD, "k2", NULL),
+       _OMAP2430_BALLENTRY(UART3_RX_IRRX, "l3", NULL),
+       _OMAP2430_BALLENTRY(UART3_TX_IRTX, "l2", NULL),
+       _OMAP2430_BALLENTRY(USB0HS_CLK, "ae8", NULL),
+       _OMAP2430_BALLENTRY(USB0HS_DATA0, "ad4", NULL),
+       _OMAP2430_BALLENTRY(USB0HS_DATA1, "ae6", NULL),
+       _OMAP2430_BALLENTRY(USB0HS_DATA2, "af9", NULL),
+       _OMAP2430_BALLENTRY(USB0HS_DATA3, "ad9", NULL),
+       _OMAP2430_BALLENTRY(USB0HS_DATA4, "y11", NULL),
+       _OMAP2430_BALLENTRY(USB0HS_DATA5, "ad7", NULL),
+       _OMAP2430_BALLENTRY(USB0HS_DATA6, "ae7", NULL),
+       _OMAP2430_BALLENTRY(USB0HS_DATA7, "ac7", NULL),
+       _OMAP2430_BALLENTRY(USB0HS_DIR, "ad8", NULL),
+       _OMAP2430_BALLENTRY(USB0HS_NXT, "ae9", NULL),
+       _OMAP2430_BALLENTRY(USB0HS_STP, "ae5", NULL),
+       { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap2430_pop_ball       NULL
+#endif
+
+int __init omap2430_mux_init(struct omap_board_mux *board_subset, int flags)
+{
+       struct omap_ball *package_balls = NULL;
+
+       switch (flags & OMAP_PACKAGE_MASK) {
+       case OMAP_PACKAGE_ZAC:
+               package_balls = omap2430_pop_ball;
+               break;
+       default:
+               pr_warning("mux: No ball data available for omap2420 package\n");
+       }
+
+       return omap_mux_init(OMAP2430_CONTROL_PADCONF_MUX_PBASE,
+                            OMAP2430_CONTROL_PADCONF_MUX_SIZE,
+                               omap2430_muxmodes, NULL, board_subset,
+                               package_balls);
+}

diff --git a/arch/arm/mach-omap2/mux2430.h b/arch/arm/mach-omap2/mux2430.h
new file mode 100644 (file)
index 0000000..adbea0d
--- /dev/null
+++ b/arch/arm/mach-omap2/mux2430.h
@@ -0,0 +1,370 @@
+/*
+ * Copyright (C) 2009 Nokia
+ * Copyright (C) 2009 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define OMAP2430_CONTROL_PADCONF_MUX_PBASE                     0x49002030LU
+
+#define OMAP2430_MUX(mode0, mux_value)                                 \
+{                                                                      \
+       .reg_offset     = (OMAP2430_CONTROL_PADCONF_##mode0##_OFFSET),  \
+       .value          = (mux_value),                                  \
+}
+
+/*
+ * OMAP2430 CONTROL_PADCONF* register offsets for pin-muxing
+ *
+ * Extracted from the TRM.  Add 0x49002030 to these values to get the
+ * absolute addresses.  The name in the macro is the mode-0 name of
+ * the pin.  NOTE: These registers are 8-bits wide.
+ *
+ * Note that these defines use SDMMC instead of MMC for compability
+ * with signal names used in 3630.
+ */
+#define OMAP2430_CONTROL_PADCONF_GPMC_CLK_OFFSET               0x000
+#define OMAP2430_CONTROL_PADCONF_GPMC_NCS0_OFFSET              0x001
+#define OMAP2430_CONTROL_PADCONF_GPMC_NCS1_OFFSET              0x002
+#define OMAP2430_CONTROL_PADCONF_GPMC_NCS2_OFFSET              0x003
+#define OMAP2430_CONTROL_PADCONF_GPMC_NCS3_OFFSET              0x004
+#define OMAP2430_CONTROL_PADCONF_GPMC_NCS4_OFFSET              0x005
+#define OMAP2430_CONTROL_PADCONF_GPMC_NCS5_OFFSET              0x006
+#define OMAP2430_CONTROL_PADCONF_GPMC_NCS6_OFFSET              0x007
+#define OMAP2430_CONTROL_PADCONF_GPMC_NCS7_OFFSET              0x008
+#define OMAP2430_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET          0x009
+#define OMAP2430_CONTROL_PADCONF_GPMC_NOE_NRE_OFFSET           0x00a
+#define OMAP2430_CONTROL_PADCONF_GPMC_NWE_OFFSET               0x00b
+#define OMAP2430_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET          0x00c
+#define OMAP2430_CONTROL_PADCONF_GPMC_NBE1_OFFSET              0x00d
+#define OMAP2430_CONTROL_PADCONF_GPMC_NWP_OFFSET               0x00e
+#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT0_OFFSET             0x00f
+#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT1_OFFSET             0x010
+#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT2_OFFSET             0x011
+#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT3_OFFSET             0x012
+#define OMAP2430_CONTROL_PADCONF_SDRC_CLK_OFFSET               0x013
+#define OMAP2430_CONTROL_PADCONF_SDRC_NCLK_OFFSET              0x014
+#define OMAP2430_CONTROL_PADCONF_SDRC_NCS0_OFFSET              0x015
+#define OMAP2430_CONTROL_PADCONF_SDRC_NCS1_OFFSET              0x016
+#define OMAP2430_CONTROL_PADCONF_SDRC_CKE0_OFFSET              0x017
+#define OMAP2430_CONTROL_PADCONF_SDRC_CKE1_OFFSET              0x018
+#define OMAP2430_CONTROL_PADCONF_SDRC_NRAS_OFFSET              0x019
+#define OMAP2430_CONTROL_PADCONF_SDRC_NCAS_OFFSET              0x01a
+#define OMAP2430_CONTROL_PADCONF_SDRC_NWE_OFFSET               0x01b
+#define OMAP2430_CONTROL_PADCONF_SDRC_DM0_OFFSET               0x01c
+#define OMAP2430_CONTROL_PADCONF_SDRC_DM1_OFFSET               0x01d
+#define OMAP2430_CONTROL_PADCONF_SDRC_DM2_OFFSET               0x01e
+#define OMAP2430_CONTROL_PADCONF_SDRC_DM3_OFFSET               0x01f
+#define OMAP2430_CONTROL_PADCONF_SDRC_DQS0_OFFSET              0x020
+#define OMAP2430_CONTROL_PADCONF_SDRC_DQS1_OFFSET              0x021
+#define OMAP2430_CONTROL_PADCONF_SDRC_DQS2_OFFSET              0x022
+#define OMAP2430_CONTROL_PADCONF_SDRC_DQS3_OFFSET              0x023
+#define OMAP2430_CONTROL_PADCONF_SDRC_A14_OFFSET               0x024
+#define OMAP2430_CONTROL_PADCONF_SDRC_A13_OFFSET               0x025
+#define OMAP2430_CONTROL_PADCONF_SDRC_A12_OFFSET               0x026
+#define OMAP2430_CONTROL_PADCONF_SDRC_BA1_OFFSET               0x027
+#define OMAP2430_CONTROL_PADCONF_SDRC_BA0_OFFSET               0x028
+#define OMAP2430_CONTROL_PADCONF_SDRC_A11_OFFSET               0x029
+#define OMAP2430_CONTROL_PADCONF_SDRC_A10_OFFSET               0x02a
+#define OMAP2430_CONTROL_PADCONF_SDRC_A9_OFFSET                        0x02b
+#define OMAP2430_CONTROL_PADCONF_SDRC_A8_OFFSET                        0x02c
+#define OMAP2430_CONTROL_PADCONF_SDRC_A7_OFFSET                        0x02d
+#define OMAP2430_CONTROL_PADCONF_SDRC_A6_OFFSET                        0x02e
+#define OMAP2430_CONTROL_PADCONF_SDRC_A5_OFFSET                        0x02f
+#define OMAP2430_CONTROL_PADCONF_SDRC_A4_OFFSET                        0x030
+#define OMAP2430_CONTROL_PADCONF_SDRC_A3_OFFSET                        0x031
+#define OMAP2430_CONTROL_PADCONF_SDRC_A2_OFFSET                        0x032
+#define OMAP2430_CONTROL_PADCONF_SDRC_A1_OFFSET                        0x033
+#define OMAP2430_CONTROL_PADCONF_SDRC_A0_OFFSET                        0x034
+#define OMAP2430_CONTROL_PADCONF_SDRC_D31_OFFSET               0x035
+#define OMAP2430_CONTROL_PADCONF_SDRC_D30_OFFSET               0x036
+#define OMAP2430_CONTROL_PADCONF_SDRC_D29_OFFSET               0x037
+#define OMAP2430_CONTROL_PADCONF_SDRC_D28_OFFSET               0x038
+#define OMAP2430_CONTROL_PADCONF_SDRC_D27_OFFSET               0x039
+#define OMAP2430_CONTROL_PADCONF_SDRC_D26_OFFSET               0x03a
+#define OMAP2430_CONTROL_PADCONF_SDRC_D25_OFFSET               0x03b
+#define OMAP2430_CONTROL_PADCONF_SDRC_D24_OFFSET               0x03c
+#define OMAP2430_CONTROL_PADCONF_SDRC_D23_OFFSET               0x03d
+#define OMAP2430_CONTROL_PADCONF_SDRC_D22_OFFSET               0x03e
+#define OMAP2430_CONTROL_PADCONF_SDRC_D21_OFFSET               0x03f
+#define OMAP2430_CONTROL_PADCONF_SDRC_D20_OFFSET               0x040
+#define OMAP2430_CONTROL_PADCONF_SDRC_D19_OFFSET               0x041
+#define OMAP2430_CONTROL_PADCONF_SDRC_D18_OFFSET               0x042
+#define OMAP2430_CONTROL_PADCONF_SDRC_D17_OFFSET               0x043
+#define OMAP2430_CONTROL_PADCONF_SDRC_D16_OFFSET               0x044
+#define OMAP2430_CONTROL_PADCONF_SDRC_D15_OFFSET               0x045
+#define OMAP2430_CONTROL_PADCONF_SDRC_D14_OFFSET               0x046
+#define OMAP2430_CONTROL_PADCONF_SDRC_D13_OFFSET               0x047
+#define OMAP2430_CONTROL_PADCONF_SDRC_D12_OFFSET               0x048
+#define OMAP2430_CONTROL_PADCONF_SDRC_D11_OFFSET               0x049
+#define OMAP2430_CONTROL_PADCONF_SDRC_D10_OFFSET               0x04a
+#define OMAP2430_CONTROL_PADCONF_SDRC_D9_OFFSET                        0x04b
+#define OMAP2430_CONTROL_PADCONF_SDRC_D8_OFFSET                        0x04c
+#define OMAP2430_CONTROL_PADCONF_SDRC_D7_OFFSET                        0x04d
+#define OMAP2430_CONTROL_PADCONF_SDRC_D6_OFFSET                        0x04e
+#define OMAP2430_CONTROL_PADCONF_SDRC_D5_OFFSET                        0x04f
+#define OMAP2430_CONTROL_PADCONF_SDRC_D4_OFFSET                        0x050
+#define OMAP2430_CONTROL_PADCONF_SDRC_D3_OFFSET                        0x051
+#define OMAP2430_CONTROL_PADCONF_SDRC_D2_OFFSET                        0x052
+#define OMAP2430_CONTROL_PADCONF_SDRC_D1_OFFSET                        0x053
+#define OMAP2430_CONTROL_PADCONF_SDRC_D0_OFFSET                        0x054
+#define OMAP2430_CONTROL_PADCONF_GPMC_A10_OFFSET               0x055
+#define OMAP2430_CONTROL_PADCONF_GPMC_A9_OFFSET                        0x056
+#define OMAP2430_CONTROL_PADCONF_GPMC_A8_OFFSET                        0x057
+#define OMAP2430_CONTROL_PADCONF_GPMC_A7_OFFSET                        0x058
+#define OMAP2430_CONTROL_PADCONF_GPMC_A6_OFFSET                        0x059
+#define OMAP2430_CONTROL_PADCONF_GPMC_A5_OFFSET                        0x05a
+#define OMAP2430_CONTROL_PADCONF_GPMC_A4_OFFSET                        0x05b
+#define OMAP2430_CONTROL_PADCONF_GPMC_A3_OFFSET                        0x05c
+#define OMAP2430_CONTROL_PADCONF_GPMC_A2_OFFSET                        0x05d
+#define OMAP2430_CONTROL_PADCONF_GPMC_A1_OFFSET                        0x05e
+#define OMAP2430_CONTROL_PADCONF_GPMC_D15_OFFSET               0x05f
+#define OMAP2430_CONTROL_PADCONF_GPMC_D14_OFFSET               0x060
+#define OMAP2430_CONTROL_PADCONF_GPMC_D13_OFFSET               0x061
+#define OMAP2430_CONTROL_PADCONF_GPMC_D12_OFFSET               0x062
+#define OMAP2430_CONTROL_PADCONF_GPMC_D11_OFFSET               0x063
+#define OMAP2430_CONTROL_PADCONF_GPMC_D10_OFFSET               0x064
+#define OMAP2430_CONTROL_PADCONF_GPMC_D9_OFFSET                        0x065
+#define OMAP2430_CONTROL_PADCONF_GPMC_D8_OFFSET                        0x066
+#define OMAP2430_CONTROL_PADCONF_GPMC_D7_OFFSET                        0x067
+#define OMAP2430_CONTROL_PADCONF_GPMC_D6_OFFSET                        0x068
+#define OMAP2430_CONTROL_PADCONF_GPMC_D5_OFFSET                        0x069
+#define OMAP2430_CONTROL_PADCONF_GPMC_D4_OFFSET                        0x06a
+#define OMAP2430_CONTROL_PADCONF_GPMC_D3_OFFSET                        0x06b
+#define OMAP2430_CONTROL_PADCONF_GPMC_D2_OFFSET                        0x06c
+#define OMAP2430_CONTROL_PADCONF_GPMC_D1_OFFSET                        0x06d
+#define OMAP2430_CONTROL_PADCONF_GPMC_D0_OFFSET                        0x06e
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA0_OFFSET              0x06f
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA1_OFFSET              0x070
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA2_OFFSET              0x071
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA3_OFFSET              0x072
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA4_OFFSET              0x073
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA5_OFFSET              0x074
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA6_OFFSET              0x075
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA7_OFFSET              0x076
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA8_OFFSET              0x077
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA9_OFFSET              0x078
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA10_OFFSET             0x079
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA11_OFFSET             0x07a
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA12_OFFSET             0x07b
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA13_OFFSET             0x07c
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA14_OFFSET             0x07d
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA15_OFFSET             0x07e
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA16_OFFSET             0x07f
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA17_OFFSET             0x080
+#define OMAP2430_CONTROL_PADCONF_UART1_CTS_OFFSET              0x081
+#define OMAP2430_CONTROL_PADCONF_UART1_RTS_OFFSET              0x082
+#define OMAP2430_CONTROL_PADCONF_UART1_TX_OFFSET               0x083
+#define OMAP2430_CONTROL_PADCONF_UART1_RX_OFFSET               0x084
+#define OMAP2430_CONTROL_PADCONF_MCBSP2_DR_OFFSET              0x085
+#define OMAP2430_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET            0x086
+#define OMAP2430_CONTROL_PADCONF_DSS_PCLK_OFFSET               0x087
+#define OMAP2430_CONTROL_PADCONF_DSS_VSYNC_OFFSET              0x088
+#define OMAP2430_CONTROL_PADCONF_DSS_HSYNC_OFFSET              0x089
+#define OMAP2430_CONTROL_PADCONF_DSS_ACBIAS_OFFSET             0x08a
+#define OMAP2430_CONTROL_PADCONF_SYS_NRESPWRON_OFFSET          0x08b
+#define OMAP2430_CONTROL_PADCONF_SYS_NRESWARM_OFFSET           0x08c
+#define OMAP2430_CONTROL_PADCONF_SYS_NIRQ0_OFFSET              0x08d
+#define OMAP2430_CONTROL_PADCONF_SYS_NIRQ1_OFFSET              0x08e
+#define OMAP2430_CONTROL_PADCONF_SYS_VMODE_OFFSET              0x08f
+#define OMAP2430_CONTROL_PADCONF_GPIO_128_OFFSET               0x090
+#define OMAP2430_CONTROL_PADCONF_GPIO_129_OFFSET               0x091
+#define OMAP2430_CONTROL_PADCONF_GPIO_130_OFFSET               0x092
+#define OMAP2430_CONTROL_PADCONF_GPIO_131_OFFSET               0x093
+#define OMAP2430_CONTROL_PADCONF_SYS_32K_OFFSET                        0x094
+#define OMAP2430_CONTROL_PADCONF_SYS_XTALIN_OFFSET             0x095
+#define OMAP2430_CONTROL_PADCONF_SYS_XTALOUT_OFFSET            0x096
+#define OMAP2430_CONTROL_PADCONF_GPIO_132_OFFSET               0x097
+#define OMAP2430_CONTROL_PADCONF_SYS_CLKREQ_OFFSET             0x098
+#define OMAP2430_CONTROL_PADCONF_SYS_CLKOUT_OFFSET             0x099
+#define OMAP2430_CONTROL_PADCONF_GPIO_151_OFFSET               0x09a
+#define OMAP2430_CONTROL_PADCONF_GPIO_133_OFFSET               0x09b
+#define OMAP2430_CONTROL_PADCONF_JTAG_EMU1_OFFSET              0x09c
+#define OMAP2430_CONTROL_PADCONF_JTAG_EMU0_OFFSET              0x09d
+#define OMAP2430_CONTROL_PADCONF_JTAG_NTRST_OFFSET             0x09e
+#define OMAP2430_CONTROL_PADCONF_JTAG_TCK_OFFSET               0x09f
+#define OMAP2430_CONTROL_PADCONF_JTAG_RTCK_OFFSET              0x0a0
+#define OMAP2430_CONTROL_PADCONF_JTAG_TMS_OFFSET               0x0a1
+#define OMAP2430_CONTROL_PADCONF_JTAG_TDI_OFFSET               0x0a2
+#define OMAP2430_CONTROL_PADCONF_JTAG_TDO_OFFSET               0x0a3
+#define OMAP2430_CONTROL_PADCONF_CAM_D9_OFFSET                 0x0a4
+#define OMAP2430_CONTROL_PADCONF_CAM_D8_OFFSET                 0x0a5
+#define OMAP2430_CONTROL_PADCONF_CAM_D7_OFFSET                 0x0a6
+#define OMAP2430_CONTROL_PADCONF_CAM_D6_OFFSET                 0x0a7
+#define OMAP2430_CONTROL_PADCONF_CAM_D5_OFFSET                 0x0a8
+#define OMAP2430_CONTROL_PADCONF_CAM_D4_OFFSET                 0x0a9
+#define OMAP2430_CONTROL_PADCONF_CAM_D3_OFFSET                 0x0aa
+#define OMAP2430_CONTROL_PADCONF_CAM_D2_OFFSET                 0x0ab
+#define OMAP2430_CONTROL_PADCONF_CAM_D1_OFFSET                 0x0ac
+#define OMAP2430_CONTROL_PADCONF_CAM_D0_OFFSET                 0x0ad
+#define OMAP2430_CONTROL_PADCONF_CAM_HS_OFFSET                 0x0ae
+#define OMAP2430_CONTROL_PADCONF_CAM_VS_OFFSET                 0x0af
+#define OMAP2430_CONTROL_PADCONF_CAM_LCLK_OFFSET               0x0b0
+#define OMAP2430_CONTROL_PADCONF_CAM_XCLK_OFFSET               0x0b1
+#define OMAP2430_CONTROL_PADCONF_CAM_D11_OFFSET                        0x0b2
+#define OMAP2430_CONTROL_PADCONF_CAM_D10_OFFSET                        0x0b3
+#define OMAP2430_CONTROL_PADCONF_GPIO_134_OFFSET               0x0b4
+#define OMAP2430_CONTROL_PADCONF_GPIO_135_OFFSET               0x0b5
+#define OMAP2430_CONTROL_PADCONF_GPIO_136_OFFSET               0x0b6
+#define OMAP2430_CONTROL_PADCONF_GPIO_137_OFFSET               0x0b7
+#define OMAP2430_CONTROL_PADCONF_GPIO_138_OFFSET               0x0b8
+#define OMAP2430_CONTROL_PADCONF_GPIO_139_OFFSET               0x0b9
+#define OMAP2430_CONTROL_PADCONF_GPIO_140_OFFSET               0x0ba
+#define OMAP2430_CONTROL_PADCONF_GPIO_141_OFFSET               0x0bb
+#define OMAP2430_CONTROL_PADCONF_GPIO_142_OFFSET               0x0bc
+#define OMAP2430_CONTROL_PADCONF_GPIO_154_OFFSET               0x0bd
+#define OMAP2430_CONTROL_PADCONF_GPIO_148_OFFSET               0x0be
+#define OMAP2430_CONTROL_PADCONF_GPIO_149_OFFSET               0x0bf
+#define OMAP2430_CONTROL_PADCONF_GPIO_150_OFFSET               0x0c0
+#define OMAP2430_CONTROL_PADCONF_GPIO_152_OFFSET               0x0c1
+#define OMAP2430_CONTROL_PADCONF_GPIO_153_OFFSET               0x0c2
+#define OMAP2430_CONTROL_PADCONF_SDMMC1_CLKO_OFFSET            0x0c3
+#define OMAP2430_CONTROL_PADCONF_SDMMC1_CMD_OFFSET             0x0c4
+#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT0_OFFSET            0x0c5
+#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET            0x0c6
+#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET            0x0c7
+#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET            0x0c8
+#define OMAP2430_CONTROL_PADCONF_SDMMC2_CLKO_OFFSET            0x0c9
+#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT3_OFFSET            0x0ca
+#define OMAP2430_CONTROL_PADCONF_SDMMC2_CMD_OFFSET             0x0cb
+#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET            0x0cc
+#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT2_OFFSET            0x0cd
+#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT1_OFFSET            0x0ce
+#define OMAP2430_CONTROL_PADCONF_UART2_CTS_OFFSET              0x0cf
+#define OMAP2430_CONTROL_PADCONF_UART2_RTS_OFFSET              0x0d0
+#define OMAP2430_CONTROL_PADCONF_UART2_TX_OFFSET               0x0d1
+#define OMAP2430_CONTROL_PADCONF_UART2_RX_OFFSET               0x0d2
+#define OMAP2430_CONTROL_PADCONF_MCBSP3_CLKX_OFFSET            0x0d3
+#define OMAP2430_CONTROL_PADCONF_MCBSP3_FSX_OFFSET             0x0d4
+#define OMAP2430_CONTROL_PADCONF_MCBSP3_DR_OFFSET              0x0d5
+#define OMAP2430_CONTROL_PADCONF_MCBSP3_DX_OFFSET              0x0d6
+#define OMAP2430_CONTROL_PADCONF_SSI1_DAT_TX_OFFSET            0x0d7
+#define OMAP2430_CONTROL_PADCONF_SSI1_FLAG_TX_OFFSET           0x0d8
+#define OMAP2430_CONTROL_PADCONF_SSI1_RDY_TX_OFFSET            0x0d9
+#define OMAP2430_CONTROL_PADCONF_SSI1_DAT_RX_OFFSET            0x0da
+#define OMAP2430_CONTROL_PADCONF_GPIO_63_OFFSET                        0x0db
+#define OMAP2430_CONTROL_PADCONF_SSI1_FLAG_RX_OFFSET           0x0dc
+#define OMAP2430_CONTROL_PADCONF_SSI1_RDY_RX_OFFSET            0x0dd
+#define OMAP2430_CONTROL_PADCONF_SSI1_WAKE_OFFSET              0x0de
+#define OMAP2430_CONTROL_PADCONF_SPI1_CLK_OFFSET               0x0df
+#define OMAP2430_CONTROL_PADCONF_SPI1_SIMO_OFFSET              0x0e0
+#define OMAP2430_CONTROL_PADCONF_SPI1_SOMI_OFFSET              0x0e1
+#define OMAP2430_CONTROL_PADCONF_SPI1_CS0_OFFSET               0x0e2
+#define OMAP2430_CONTROL_PADCONF_SPI1_CS1_OFFSET               0x0e3
+#define OMAP2430_CONTROL_PADCONF_SPI1_CS2_OFFSET               0x0e4
+#define OMAP2430_CONTROL_PADCONF_SPI1_CS3_OFFSET               0x0e5
+#define OMAP2430_CONTROL_PADCONF_SPI2_CLK_OFFSET               0x0e6
+#define OMAP2430_CONTROL_PADCONF_SPI2_SIMO_OFFSET              0x0e7
+#define OMAP2430_CONTROL_PADCONF_SPI2_SOMI_OFFSET              0x0e8
+#define OMAP2430_CONTROL_PADCONF_SPI2_CS0_OFFSET               0x0e9
+#define OMAP2430_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET            0x0ea
+#define OMAP2430_CONTROL_PADCONF_MCBSP1_FSR_OFFSET             0x0eb
+#define OMAP2430_CONTROL_PADCONF_MCBSP1_DX_OFFSET              0x0ec
+#define OMAP2430_CONTROL_PADCONF_MCBSP1_DR_OFFSET              0x0ed
+#define OMAP2430_CONTROL_PADCONF_MCBSP_CLKS_OFFSET             0x0ee
+#define OMAP2430_CONTROL_PADCONF_MCBSP1_FSX_OFFSET             0x0ef
+#define OMAP2430_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET            0x0f0
+#define OMAP2430_CONTROL_PADCONF_I2C1_SCL_OFFSET               0x0f1
+#define OMAP2430_CONTROL_PADCONF_I2C1_SDA_OFFSET               0x0f2
+#define OMAP2430_CONTROL_PADCONF_I2C2_SCL_OFFSET               0x0f3
+#define OMAP2430_CONTROL_PADCONF_I2C2_SDA_OFFSET               0x0f4
+#define OMAP2430_CONTROL_PADCONF_HDQ_SIO_OFFSET                        0x0f5
+#define OMAP2430_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET         0x0f6
+#define OMAP2430_CONTROL_PADCONF_UART3_RTS_SD_OFFSET           0x0f7
+#define OMAP2430_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET          0x0f8
+#define OMAP2430_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET          0x0f9
+#define OMAP2430_CONTROL_PADCONF_GPIO_7_OFFSET                 0x0fa
+#define OMAP2430_CONTROL_PADCONF_GPIO_78_OFFSET                        0x0fb
+#define OMAP2430_CONTROL_PADCONF_GPIO_79_OFFSET                        0x0fc
+#define OMAP2430_CONTROL_PADCONF_GPIO_80_OFFSET                        0x0fd
+#define OMAP2430_CONTROL_PADCONF_GPIO_113_OFFSET               0x0fe
+#define OMAP2430_CONTROL_PADCONF_GPIO_114_OFFSET               0x0ff
+#define OMAP2430_CONTROL_PADCONF_GPIO_115_OFFSET               0x100
+#define OMAP2430_CONTROL_PADCONF_GPIO_116_OFFSET               0x101
+#define OMAP2430_CONTROL_PADCONF_SYS_DRM_MSECURE_OFFSET                0x102
+#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA3_OFFSET           0x103
+#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA4_OFFSET           0x104
+#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA5_OFFSET           0x105
+#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA6_OFFSET           0x106
+#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA2_OFFSET           0x107
+#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA0_OFFSET           0x108
+#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA1_OFFSET           0x109
+#define OMAP2430_CONTROL_PADCONF_USB0HS_CLK_OFFSET             0x10a
+#define OMAP2430_CONTROL_PADCONF_USB0HS_DIR_OFFSET             0x10b
+#define OMAP2430_CONTROL_PADCONF_USB0HS_STP_OFFSET             0x10c
+#define OMAP2430_CONTROL_PADCONF_USB0HS_NXT_OFFSET             0x10d
+#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA7_OFFSET           0x10e
+#define OMAP2430_CONTROL_PADCONF_TV_OUT_OFFSET                 0x10f
+#define OMAP2430_CONTROL_PADCONF_TV_VREF_OFFSET                        0x110
+#define OMAP2430_CONTROL_PADCONF_TV_RSET_OFFSET                        0x111
+#define OMAP2430_CONTROL_PADCONF_TV_VFB_OFFSET                 0x112
+#define OMAP2430_CONTROL_PADCONF_TV_DACOUT_OFFSET              0x113
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD0_OFFSET              0x114
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD1_OFFSET              0x115
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD2_OFFSET              0x116
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD3_OFFSET              0x117
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD4_OFFSET              0x118
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD5_OFFSET              0x119
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD6_OFFSET              0x11a
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD7_OFFSET              0x11b
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD8_OFFSET              0x11c
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD9_OFFSET              0x11d
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD10_OFFSET             0x11e
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD11_OFFSET             0x11f
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD12_OFFSET             0x120
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD13_OFFSET             0x121
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD14_OFFSET             0x122
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD15_OFFSET             0x123
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD16_OFFSET             0x124
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD17_OFFSET             0x125
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD18_OFFSET             0x126
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD19_OFFSET             0x127
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD20_OFFSET             0x128
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD21_OFFSET             0x129
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD22_OFFSET             0x12a
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD23_OFFSET             0x12b
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD24_OFFSET             0x12c
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD25_OFFSET             0x12d
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD26_OFFSET             0x12e
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD27_OFFSET             0x12f
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD28_OFFSET             0x130
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD29_OFFSET             0x131
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD30_OFFSET             0x132
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD31_OFFSET             0x133
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD32_OFFSET             0x134
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD33_OFFSET             0x135
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD34_OFFSET             0x136
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD35_OFFSET             0x137
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD36_OFFSET             0x138
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD37_OFFSET             0x139
+#define OMAP2430_CONTROL_PADCONF_AD2DMWRITE_OFFSET             0x13a
+#define OMAP2430_CONTROL_PADCONF_D2DCLK26MI_OFFSET             0x13b
+#define OMAP2430_CONTROL_PADCONF_D2DNRESPWRON1_OFFSET          0x13c
+#define OMAP2430_CONTROL_PADCONF_D2DNRESWARM_OFFSET            0x13d
+#define OMAP2430_CONTROL_PADCONF_D2DARM9NIRQ_OFFSET            0x13e
+#define OMAP2430_CONTROL_PADCONF_D2DUMA2P6FIQ_OFFSET           0x13f
+#define OMAP2430_CONTROL_PADCONF_D2DSPINT_OFFSET               0x140
+#define OMAP2430_CONTROL_PADCONF_D2DFRINT_OFFSET               0x141
+#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ0_OFFSET             0x142
+#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ1_OFFSET             0x143
+#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ2_OFFSET             0x144
+#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ3_OFFSET             0x145
+#define OMAP2430_CONTROL_PADCONF_D2DN3GTRST_OFFSET             0x146
+#define OMAP2430_CONTROL_PADCONF_D2DN3GTDI_OFFSET              0x147
+#define OMAP2430_CONTROL_PADCONF_D2DN3GTDO_OFFSET              0x148
+#define OMAP2430_CONTROL_PADCONF_D2DN3GTMS_OFFSET              0x149
+#define OMAP2430_CONTROL_PADCONF_D2DN3GTCK_OFFSET              0x14a
+#define OMAP2430_CONTROL_PADCONF_D2DN3GRTCK_OFFSET             0x14b
+#define OMAP2430_CONTROL_PADCONF_D2DMSTDBY_OFFSET              0x14c
+#define OMAP2430_CONTROL_PADCONF_AD2DSREAD_OFFSET              0x14d
+#define OMAP2430_CONTROL_PADCONF_D2DSWAKEUP_OFFSET             0x14e
+#define OMAP2430_CONTROL_PADCONF_D2DIDLEREQ_OFFSET             0x14f
+#define OMAP2430_CONTROL_PADCONF_D2DIDLEACK_OFFSET             0x150
+#define OMAP2430_CONTROL_PADCONF_D2DSPARE0_OFFSET              0x151
+#define OMAP2430_CONTROL_PADCONF_AD2DSWRITE_OFFSET             0x152
+#define OMAP2430_CONTROL_PADCONF_AD2DMREAD_OFFSET              0x153
+
+#define OMAP2430_CONTROL_PADCONF_MUX_SIZE                      \
+               (OMAP2430_CONTROL_PADCONF_AD2DMREAD_OFFSET + 0x1)

diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c
index 2ff4dce95ee87c113cfc6631de8a669a9523ab59..f64d7eea34519763a7fb0d343bcc02dfdcad577a 100644 (file)
--- a/arch/arm/mach-omap2/mux34xx.c
+++ b/arch/arm/mach-omap2/mux34xx.c
@@ -2032,19 +2032,19 @@ int __init omap3_mux_init(struct omap_board_mux *board_subset, int flags)
        struct omap_ball *package_balls;
 
        switch (flags & OMAP_PACKAGE_MASK) {
-       case (OMAP_PACKAGE_CBC):
+       case OMAP_PACKAGE_CBC:
                package_subset = omap3_cbc_subset;
                package_balls = omap3_cbc_ball;
                break;
-       case (OMAP_PACKAGE_CBB):
+       case OMAP_PACKAGE_CBB:
                package_subset = omap3_cbb_subset;
                package_balls = omap3_cbb_ball;
                break;
-       case (OMAP_PACKAGE_CUS):
+       case OMAP_PACKAGE_CUS:
                package_subset = omap3_cus_subset;
                package_balls = omap3_cus_ball;
                break;
-       case (OMAP_PACKAGE_CBP):
+       case OMAP_PACKAGE_CBP:
                package_subset = omap36xx_cbp_subset;
                package_balls = omap36xx_cbp_ball;
                break;

diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index ef0e7a00dd6c6187732524cb1ecdcb1e6f74789e..6ae937a06cc1883f83af604845bf51c859f2adeb 100644 (file)
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -47,19 +47,3 @@ hold:        ldr     r12,=0x103
        b       secondary_startup
 END(omap_secondary_startup)
 
-
-ENTRY(omap_modify_auxcoreboot0)
-       stmfd   sp!, {r1-r12, lr}
-       ldr     r12, =0x104
-       dsb
-       smc     #0
-       ldmfd   sp!, {r1-r12, pc}
-END(omap_modify_auxcoreboot0)
-
-ENTRY(omap_auxcoreboot_addr)
-       stmfd   sp!, {r2-r12, lr}
-       ldr     r12, =0x105
-       dsb
-       smc     #0
-       ldmfd   sp!, {r2-r12, pc}
-END(omap_auxcoreboot_addr)

diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
new file mode 100644 (file)
index 0000000..6cee456
--- /dev/null
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -0,0 +1,79 @@
+/*
+ * OMAP4 SMP cpu-hotplug support
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Author:
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * Platform file needed for the OMAP4 SMP. This file is based on arm
+ * realview smp platform.
+ * Copyright (c) 2002 ARM Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+#include <linux/completion.h>
+
+#include <asm/cacheflush.h>
+#include <mach/omap4-common.h>
+
+static DECLARE_COMPLETION(cpu_killed);
+
+int platform_cpu_kill(unsigned int cpu)
+{
+       return wait_for_completion_timeout(&cpu_killed, 5000);
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ * Called with IRQs disabled
+ */
+void platform_cpu_die(unsigned int cpu)
+{
+       unsigned int this_cpu = hard_smp_processor_id();
+
+       if (cpu != this_cpu) {
+               pr_crit("platform_cpu_die running on %u, should be %u\n",
+                          this_cpu, cpu);
+               BUG();
+       }
+       pr_notice("CPU%u: shutdown\n", cpu);
+       complete(&cpu_killed);
+       flush_cache_all();
+       dsb();
+
+       /*
+        * we're ready for shutdown now, so do it
+        */
+       if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
+               printk(KERN_CRIT "Secure clear status failed\n");
+
+       for (;;) {
+               /*
+                * Execute WFI
+                */
+               do_wfi();
+
+               if (omap_read_auxcoreboot0() == cpu) {
+                       /*
+                        * OK, proper wakeup, we're done
+                        */
+                       break;
+               }
+               pr_debug("CPU%u: spurious wakeup call\n", cpu);
+       }
+}
+
+int platform_cpu_disable(unsigned int cpu)
+{
+       /*
+        * we don't allow CPU 0 to be shutdown (it is still too special
+        * e.g. clock tick interrupts)
+        */
+       return cpu == 0 ? -EPERM : 0;
+}

diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index eb9bee73e0cb6cad0e23dcfacdcc5e8f354cd8bd..f5a1aad1a5c0e45be50291a1ab017c120f5a8962 100644 (file)
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -59,7 +59,7 @@ static struct platform_device *omap3_iommu_pdev[NR_OMAP3_IOMMU_DEVICES];
 static struct iommu_device omap4_devices[] = {
        {
                .base = OMAP4_MMU1_BASE,
-               .irq = INT_44XX_DUCATI_MMU_IRQ,
+               .irq = OMAP44XX_IRQ_DUCATI_MMU,
                .pdata = {
                        .name = "ducati",
                        .nr_tlb_entries = 32,

diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 1cf52313759ebfdca3e49e298b7c4b22d48c8da3..af3c20c8d3f9202e742068f8ba1e57c911e3c265 100644 (file)
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -73,9 +73,10 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
         * the AuxCoreBoot1 register is updated with cpu state
         * A barrier is added to ensure that write buffer is drained
         */
-       omap_modify_auxcoreboot0(0x200, 0x0);
+       omap_modify_auxcoreboot0(0x200, 0xfffffdff);
        flush_cache_all();
        smp_wmb();
+       smp_cross_call(cpumask_of(cpu));
 
        /*
         * Now the secondary core is starting up let it run its

diff --git a/arch/arm/mach-omap2/omap44xx-smc.S b/arch/arm/mach-omap2/omap44xx-smc.S
index f61c7771ca47e580cfebc4c654f49433290cfe02..1980dc31a1a2e85a28e0fc612eee5b41004db5d8 100644 (file)
--- a/arch/arm/mach-omap2/omap44xx-smc.S
+++ b/arch/arm/mach-omap2/omap44xx-smc.S
@@ -30,3 +30,28 @@ ENTRY(omap_smc1)
        smc     #0
        ldmfd   sp!, {r2-r12, pc}
 END(omap_smc1)
+
+ENTRY(omap_modify_auxcoreboot0)
+       stmfd   sp!, {r1-r12, lr}
+       ldr     r12, =0x104
+       dsb
+       smc     #0
+       ldmfd   sp!, {r1-r12, pc}
+END(omap_modify_auxcoreboot0)
+
+ENTRY(omap_auxcoreboot_addr)
+       stmfd   sp!, {r2-r12, lr}
+       ldr     r12, =0x105
+       dsb
+       smc     #0
+       ldmfd   sp!, {r2-r12, pc}
+END(omap_auxcoreboot_addr)
+
+ENTRY(omap_read_auxcoreboot0)
+       stmfd   sp!, {r2-r12, lr}
+       ldr     r12, =0x103
+       dsb
+       smc     #0
+       mov     r0, r0, lsr #9
+       ldmfd   sp!, {r2-r12, pc}
+END(omap_read_auxcoreboot0)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index b7a4133267d80b73cd0ff59fe8d339efae649839..cb911d7d1a3c1535ba88eda74577ea6ef2e1ecd0 100644 (file)
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1,7 +1,7 @@
 /*
  * omap_hwmod implementation for OMAP2/3/4
  *
- * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2009-2010 Nokia Corporation
  *
  * Paul Walmsley, Benoît Cousson, Kevin Hilman
  *
@@ -423,7 +423,7 @@ static int _init_main_clk(struct omap_hwmod *oh)
 }
 
 /**
- * _init_interface_clk - get a struct clk * for the the hwmod's interface clks
+ * _init_interface_clks - get a struct clk * for the the hwmod's interface clks
  * @oh: struct omap_hwmod *
  *
  * Called from _init_clocks().  Populates the @oh OCP slave interface
@@ -764,6 +764,7 @@ static struct omap_hwmod *_lookup(const char *name)
 /**
  * _init_clocks - clk_get() all clocks associated with this hwmod
  * @oh: struct omap_hwmod *
+ * @data: not used; pass NULL
  *
  * Called by omap_hwmod_late_init() (after omap2_clk_init()).
  * Resolves all clock names embedded in the hwmod.  Must be called
@@ -771,7 +772,7 @@ static struct omap_hwmod *_lookup(const char *name)
  * has not yet been registered or if the clocks have already been
  * initialized, 0 on success, or a non-zero error on failure.
  */
-static int _init_clocks(struct omap_hwmod *oh)
+static int _init_clocks(struct omap_hwmod *oh, void *data)
 {
        int ret = 0;
 
@@ -886,7 +887,7 @@ static int _reset(struct omap_hwmod *oh)
 }
 
 /**
- * _enable - enable an omap_hwmod
+ * _omap_hwmod_enable - enable an omap_hwmod
  * @oh: struct omap_hwmod *
  *
  * Enables an omap_hwmod @oh such that the MPU can access the hwmod's
@@ -894,7 +895,7 @@ static int _reset(struct omap_hwmod *oh)
  * Returns -EINVAL if the hwmod is in the wrong state or passes along
  * the return value of _wait_target_ready().
  */
-static int _enable(struct omap_hwmod *oh)
+int _omap_hwmod_enable(struct omap_hwmod *oh)
 {
        int r;
 
@@ -939,7 +940,7 @@ static int _enable(struct omap_hwmod *oh)
  * no further work.  Returns -EINVAL if the hwmod is in the wrong
  * state or returns 0.
  */
-static int _idle(struct omap_hwmod *oh)
+int _omap_hwmod_idle(struct omap_hwmod *oh)
 {
        if (oh->_state != _HWMOD_STATE_ENABLED) {
                WARN(1, "omap_hwmod: %s: idle state can only be entered from "
@@ -996,19 +997,25 @@ static int _shutdown(struct omap_hwmod *oh)
 /**
  * _setup - do initial configuration of omap_hwmod
  * @oh: struct omap_hwmod *
+ * @skip_setup_idle_p: do not idle hwmods at the end of the fn if 1
  *
  * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh
- * OCP_SYSCONFIG register.  Must be called with omap_hwmod_mutex
- * held.  Returns -EINVAL if the hwmod is in the wrong state or returns
- * 0.
+ * OCP_SYSCONFIG register.  Must be called with omap_hwmod_mutex held.
+ * @skip_setup_idle is intended to be used on a system that will not
+ * call omap_hwmod_enable() to enable devices (e.g., a system without
+ * PM runtime).  Returns -EINVAL if the hwmod is in the wrong state or
+ * returns 0.
  */
-static int _setup(struct omap_hwmod *oh)
+static int _setup(struct omap_hwmod *oh, void *data)
 {
        int i, r;
+       u8 skip_setup_idle;
 
-       if (!oh)
+       if (!oh || !data)
                return -EINVAL;
 
+       skip_setup_idle = *(u8 *)data;
+
        /* Set iclk autoidle mode */
        if (oh->slaves_cnt > 0) {
                for (i = 0; i < oh->slaves_cnt; i++) {
@@ -1029,7 +1036,7 @@ static int _setup(struct omap_hwmod *oh)
 
        oh->_state = _HWMOD_STATE_INITIALIZED;
 
-       r = _enable(oh);
+       r = _omap_hwmod_enable(oh);
        if (r) {
                pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n",
                           oh->name, oh->_state);
@@ -1041,7 +1048,7 @@ static int _setup(struct omap_hwmod *oh)
                 * XXX Do the OCP_SYSCONFIG bits need to be
                 * reprogrammed after a reset?  If not, then this can
                 * be removed.  If they do, then probably the
-                * _enable() function should be split to avoid the
+                * _omap_hwmod_enable() function should be split to avoid the
                 * rewrite of the OCP_SYSCONFIG register.
                 */
                if (oh->class->sysc) {
@@ -1050,8 +1057,8 @@ static int _setup(struct omap_hwmod *oh)
                }
        }
 
-       if (!(oh->flags & HWMOD_INIT_NO_IDLE))
-               _idle(oh);
+       if (!(oh->flags & HWMOD_INIT_NO_IDLE) && !skip_setup_idle)
+               _omap_hwmod_idle(oh);
 
        return 0;
 }
@@ -1062,14 +1069,29 @@ static int _setup(struct omap_hwmod *oh)
 
 u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs)
 {
-       return __raw_readl(oh->_rt_va + reg_offs);
+       return __raw_readl(oh->_mpu_rt_va + reg_offs);
 }
 
 void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs)
 {
-       __raw_writel(v, oh->_rt_va + reg_offs);
+       __raw_writel(v, oh->_mpu_rt_va + reg_offs);
 }
 
+/**
+ * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode
+ * @oh: struct omap_hwmod *
+ * @idlemode: SIDLEMODE field bits (shifted to bit 0)
+ *
+ * Sets the IP block's OCP slave idlemode in hardware, and updates our
+ * local copy.  Intended to be used by drivers that have some erratum
+ * that requires direct manipulation of the SIDLEMODE bits.  Returns
+ * -EINVAL if @oh is null, or passes along the return value from
+ * _set_slave_idlemode().
+ *
+ * XXX Does this function have any current users?  If not, we should
+ * remove it; it is better to let the rest of the hwmod code handle this.
+ * Any users of this function should be scrutinized carefully.
+ */
 int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode)
 {
        u32 v;
@@ -1124,7 +1146,7 @@ int omap_hwmod_register(struct omap_hwmod *oh)
        ms_id = _find_mpu_port_index(oh);
        if (!IS_ERR_VALUE(ms_id)) {
                oh->_mpu_port_index = ms_id;
-               oh->_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
+               oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
        } else {
                oh->_int_flags |= _HWMOD_NO_MPU_PORT;
        }
@@ -1164,6 +1186,7 @@ struct omap_hwmod *omap_hwmod_lookup(const char *name)
 /**
  * omap_hwmod_for_each - call function for each registered omap_hwmod
  * @fn: pointer to a callback function
+ * @data: void * data to pass to callback function
  *
  * Call @fn for each registered omap_hwmod, passing @data to each
  * function.  @fn must return 0 for success or any other value for
@@ -1172,7 +1195,8 @@ struct omap_hwmod *omap_hwmod_lookup(const char *name)
  * caller of omap_hwmod_for_each().  @fn is called with
  * omap_hwmod_for_each() held.
  */
-int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh))
+int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
+                       void *data)
 {
        struct omap_hwmod *temp_oh;
        int ret;
@@ -1182,7 +1206,7 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh))
 
        mutex_lock(&omap_hwmod_mutex);
        list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
-               ret = (*fn)(temp_oh);
+               ret = (*fn)(temp_oh, data);
                if (ret)
                        break;
        }
@@ -1229,24 +1253,28 @@ int omap_hwmod_init(struct omap_hwmod **ohs)
 
 /**
  * omap_hwmod_late_init - do some post-clock framework initialization
+ * @skip_setup_idle: if 1, do not idle hwmods in _setup()
  *
  * Must be called after omap2_clk_init().  Resolves the struct clk names
  * to struct clk pointers for each registered omap_hwmod.  Also calls
  * _setup() on each hwmod.  Returns 0.
  */
-int omap_hwmod_late_init(void)
+int omap_hwmod_late_init(u8 skip_setup_idle)
 {
        int r;
 
        /* XXX check return value */
-       r = omap_hwmod_for_each(_init_clocks);
+       r = omap_hwmod_for_each(_init_clocks, NULL);
        WARN(r, "omap_hwmod: omap_hwmod_late_init(): _init_clocks failed\n");
 
        mpu_oh = omap_hwmod_lookup(MPU_INITIATOR_NAME);
        WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n",
             MPU_INITIATOR_NAME);
 
-       omap_hwmod_for_each(_setup);
+       if (skip_setup_idle)
+               pr_debug("omap_hwmod: will leave hwmods enabled during setup\n");
+
+       omap_hwmod_for_each(_setup, &skip_setup_idle);
 
        return 0;
 }
@@ -1270,7 +1298,7 @@ int omap_hwmod_unregister(struct omap_hwmod *oh)
        pr_debug("omap_hwmod: %s: unregistering\n", oh->name);
 
        mutex_lock(&omap_hwmod_mutex);
-       iounmap(oh->_rt_va);
+       iounmap(oh->_mpu_rt_va);
        list_del(&oh->node);
        mutex_unlock(&omap_hwmod_mutex);
 
@@ -1292,12 +1320,13 @@ int omap_hwmod_enable(struct omap_hwmod *oh)
                return -EINVAL;
 
        mutex_lock(&omap_hwmod_mutex);
-       r = _enable(oh);
+       r = _omap_hwmod_enable(oh);
        mutex_unlock(&omap_hwmod_mutex);
 
        return r;
 }
 
+
 /**
  * omap_hwmod_idle - idle an omap_hwmod
  * @oh: struct omap_hwmod *
@@ -1311,7 +1340,7 @@ int omap_hwmod_idle(struct omap_hwmod *oh)
                return -EINVAL;
 
        mutex_lock(&omap_hwmod_mutex);
-       _idle(oh);
+       _omap_hwmod_idle(oh);
        mutex_unlock(&omap_hwmod_mutex);
 
        return 0;
@@ -1413,7 +1442,7 @@ int omap_hwmod_reset(struct omap_hwmod *oh)
        mutex_lock(&omap_hwmod_mutex);
        r = _reset(oh);
        if (!r)
-               r = _enable(oh);
+               r = _omap_hwmod_enable(oh);
        mutex_unlock(&omap_hwmod_mutex);
 
        return r;
@@ -1529,6 +1558,29 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
 
 }
 
+/**
+ * omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU)
+ * @oh: struct omap_hwmod *
+ *
+ * Returns the virtual address corresponding to the beginning of the
+ * module's register target, in the address range that is intended to
+ * be used by the MPU.  Returns the virtual address upon success or NULL
+ * upon error.
+ */
+void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh)
+{
+       if (!oh)
+               return NULL;
+
+       if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+               return NULL;
+
+       if (oh->_state == _HWMOD_STATE_UNKNOWN)
+               return NULL;
+
+       return oh->_mpu_rt_va;
+}
+
 /**
  * omap_hwmod_add_initiator_dep - add sleepdep from @init_oh to @oh
  * @oh: struct omap_hwmod *

diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index e5530c51f77dd15729967ee1490f3211ba884954..3cc768e8bc04f41a38ae335f941eb5577009037a 100644 (file)
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -30,42 +30,44 @@
  */
 
 static struct omap_hwmod omap2420_mpu_hwmod;
-static struct omap_hwmod omap2420_l3_hwmod;
+static struct omap_hwmod omap2420_iva_hwmod;
+static struct omap_hwmod omap2420_l3_main_hwmod;
 static struct omap_hwmod omap2420_l4_core_hwmod;
 
 /* L3 -> L4_CORE interface */
-static struct omap_hwmod_ocp_if omap2420_l3__l4_core = {
-       .master = &omap2420_l3_hwmod,
+static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
+       .master = &omap2420_l3_main_hwmod,
        .slave  = &omap2420_l4_core_hwmod,
        .user   = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* MPU -> L3 interface */
-static struct omap_hwmod_ocp_if omap2420_mpu__l3 = {
+static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = {
        .master = &omap2420_mpu_hwmod,
-       .slave  = &omap2420_l3_hwmod,
+       .slave  = &omap2420_l3_main_hwmod,
        .user   = OCP_USER_MPU,
 };
 
 /* Slave interfaces on the L3 interconnect */
-static struct omap_hwmod_ocp_if *omap2420_l3_slaves[] = {
-       &omap2420_mpu__l3,
+static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = {
+       &omap2420_mpu__l3_main,
 };
 
 /* Master interfaces on the L3 interconnect */
-static struct omap_hwmod_ocp_if *omap2420_l3_masters[] = {
-       &omap2420_l3__l4_core,
+static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = {
+       &omap2420_l3_main__l4_core,
 };
 
 /* L3 */
-static struct omap_hwmod omap2420_l3_hwmod = {
-       .name           = "l3_hwmod",
+static struct omap_hwmod omap2420_l3_main_hwmod = {
+       .name           = "l3_main",
        .class          = &l3_hwmod_class,
-       .masters        = omap2420_l3_masters,
-       .masters_cnt    = ARRAY_SIZE(omap2420_l3_masters),
-       .slaves         = omap2420_l3_slaves,
-       .slaves_cnt     = ARRAY_SIZE(omap2420_l3_slaves),
-       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+       .masters        = omap2420_l3_main_masters,
+       .masters_cnt    = ARRAY_SIZE(omap2420_l3_main_masters),
+       .slaves         = omap2420_l3_main_slaves,
+       .slaves_cnt     = ARRAY_SIZE(omap2420_l3_main_slaves),
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+       .flags          = HWMOD_NO_IDLEST,
 };
 
 static struct omap_hwmod omap2420_l4_wkup_hwmod;
@@ -79,7 +81,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
 
 /* Slave interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
-       &omap2420_l3__l4_core,
+       &omap2420_l3_main__l4_core,
 };
 
 /* Master interfaces on the L4_CORE interconnect */
@@ -89,13 +91,14 @@ static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
 
 /* L4 CORE */
 static struct omap_hwmod omap2420_l4_core_hwmod = {
-       .name           = "l4_core_hwmod",
+       .name           = "l4_core",
        .class          = &l4_hwmod_class,
        .masters        = omap2420_l4_core_masters,
        .masters_cnt    = ARRAY_SIZE(omap2420_l4_core_masters),
        .slaves         = omap2420_l4_core_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_l4_core_slaves),
-       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+       .flags          = HWMOD_NO_IDLEST,
 };
 
 /* Slave interfaces on the L4_WKUP interconnect */
@@ -109,18 +112,19 @@ static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = {
 
 /* L4 WKUP */
 static struct omap_hwmod omap2420_l4_wkup_hwmod = {
-       .name           = "l4_wkup_hwmod",
+       .name           = "l4_wkup",
        .class          = &l4_hwmod_class,
        .masters        = omap2420_l4_wkup_masters,
        .masters_cnt    = ARRAY_SIZE(omap2420_l4_wkup_masters),
        .slaves         = omap2420_l4_wkup_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2420_l4_wkup_slaves),
-       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+       .flags          = HWMOD_NO_IDLEST,
 };
 
 /* Master interfaces on the MPU device */
 static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = {
-       &omap2420_mpu__l3,
+       &omap2420_mpu__l3_main,
 };
 
 /* MPU */
@@ -133,11 +137,40 @@ static struct omap_hwmod omap2420_mpu_hwmod = {
        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
+/*
+ * IVA1 interface data
+ */
+
+/* IVA <- L3 interface */
+static struct omap_hwmod_ocp_if omap2420_l3__iva = {
+       .master         = &omap2420_l3_main_hwmod,
+       .slave          = &omap2420_iva_hwmod,
+       .clk            = "iva1_ifck",
+       .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = {
+       &omap2420_l3__iva,
+};
+
+/*
+ * IVA2 (IVA2)
+ */
+
+static struct omap_hwmod omap2420_iva_hwmod = {
+       .name           = "iva",
+       .class          = &iva_hwmod_class,
+       .masters        = omap2420_iva_masters,
+       .masters_cnt    = ARRAY_SIZE(omap2420_iva_masters),
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
 static __initdata struct omap_hwmod *omap2420_hwmods[] = {
-       &omap2420_l3_hwmod,
+       &omap2420_l3_main_hwmod,
        &omap2420_l4_core_hwmod,
        &omap2420_l4_wkup_hwmod,
        &omap2420_mpu_hwmod,
+       &omap2420_iva_hwmod,
        NULL,
 };
 

diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 0852d954da406590e954e018b5287819b000608b..4526628ed287222cba29d2f42521fbaaca052f37 100644 (file)
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -30,47 +30,47 @@
  */
 
 static struct omap_hwmod omap2430_mpu_hwmod;
-static struct omap_hwmod omap2430_l3_hwmod;
+static struct omap_hwmod omap2430_iva_hwmod;
+static struct omap_hwmod omap2430_l3_main_hwmod;
 static struct omap_hwmod omap2430_l4_core_hwmod;
 
 /* L3 -> L4_CORE interface */
-static struct omap_hwmod_ocp_if omap2430_l3__l4_core = {
-       .master = &omap2430_l3_hwmod,
+static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
+       .master = &omap2430_l3_main_hwmod,
        .slave  = &omap2430_l4_core_hwmod,
        .user   = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* MPU -> L3 interface */
-static struct omap_hwmod_ocp_if omap2430_mpu__l3 = {
+static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = {
        .master = &omap2430_mpu_hwmod,
-       .slave  = &omap2430_l3_hwmod,
+       .slave  = &omap2430_l3_main_hwmod,
        .user   = OCP_USER_MPU,
 };
 
 /* Slave interfaces on the L3 interconnect */
-static struct omap_hwmod_ocp_if *omap2430_l3_slaves[] = {
-       &omap2430_mpu__l3,
+static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
+       &omap2430_mpu__l3_main,
 };
 
 /* Master interfaces on the L3 interconnect */
-static struct omap_hwmod_ocp_if *omap2430_l3_masters[] = {
-       &omap2430_l3__l4_core,
+static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
+       &omap2430_l3_main__l4_core,
 };
 
 /* L3 */
-static struct omap_hwmod omap2430_l3_hwmod = {
-       .name           = "l3_hwmod",
+static struct omap_hwmod omap2430_l3_main_hwmod = {
+       .name           = "l3_main",
        .class          = &l3_hwmod_class,
-       .masters        = omap2430_l3_masters,
-       .masters_cnt    = ARRAY_SIZE(omap2430_l3_masters),
-       .slaves         = omap2430_l3_slaves,
-       .slaves_cnt     = ARRAY_SIZE(omap2430_l3_slaves),
-       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+       .masters        = omap2430_l3_main_masters,
+       .masters_cnt    = ARRAY_SIZE(omap2430_l3_main_masters),
+       .slaves         = omap2430_l3_main_slaves,
+       .slaves_cnt     = ARRAY_SIZE(omap2430_l3_main_slaves),
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+       .flags          = HWMOD_NO_IDLEST,
 };
 
 static struct omap_hwmod omap2430_l4_wkup_hwmod;
-static struct omap_hwmod omap2430_mmc1_hwmod;
-static struct omap_hwmod omap2430_mmc2_hwmod;
 
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
@@ -81,7 +81,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
 
 /* Slave interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
-       &omap2430_l3__l4_core,
+       &omap2430_l3_main__l4_core,
 };
 
 /* Master interfaces on the L4_CORE interconnect */
@@ -91,13 +91,14 @@ static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
 
 /* L4 CORE */
 static struct omap_hwmod omap2430_l4_core_hwmod = {
-       .name           = "l4_core_hwmod",
+       .name           = "l4_core",
        .class          = &l4_hwmod_class,
        .masters        = omap2430_l4_core_masters,
        .masters_cnt    = ARRAY_SIZE(omap2430_l4_core_masters),
        .slaves         = omap2430_l4_core_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_l4_core_slaves),
-       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+       .flags          = HWMOD_NO_IDLEST,
 };
 
 /* Slave interfaces on the L4_WKUP interconnect */
@@ -111,18 +112,19 @@ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
 
 /* L4 WKUP */
 static struct omap_hwmod omap2430_l4_wkup_hwmod = {
-       .name           = "l4_wkup_hwmod",
+       .name           = "l4_wkup",
        .class          = &l4_hwmod_class,
        .masters        = omap2430_l4_wkup_masters,
        .masters_cnt    = ARRAY_SIZE(omap2430_l4_wkup_masters),
        .slaves         = omap2430_l4_wkup_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap2430_l4_wkup_slaves),
-       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+       .flags          = HWMOD_NO_IDLEST,
 };
 
 /* Master interfaces on the MPU device */
 static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = {
-       &omap2430_mpu__l3,
+       &omap2430_mpu__l3_main,
 };
 
 /* MPU */
@@ -135,11 +137,40 @@ static struct omap_hwmod omap2430_mpu_hwmod = {
        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
+/*
+ * IVA2_1 interface data
+ */
+
+/* IVA2 <- L3 interface */
+static struct omap_hwmod_ocp_if omap2430_l3__iva = {
+       .master         = &omap2430_l3_main_hwmod,
+       .slave          = &omap2430_iva_hwmod,
+       .clk            = "dsp_fck",
+       .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = {
+       &omap2430_l3__iva,
+};
+
+/*
+ * IVA2 (IVA2)
+ */
+
+static struct omap_hwmod omap2430_iva_hwmod = {
+       .name           = "iva",
+       .class          = &iva_hwmod_class,
+       .masters        = omap2430_iva_masters,
+       .masters_cnt    = ARRAY_SIZE(omap2430_iva_masters),
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
-       &omap2430_l3_hwmod,
+       &omap2430_l3_main_hwmod,
        &omap2430_l4_core_hwmod,
        &omap2430_l4_wkup_hwmod,
        &omap2430_mpu_hwmod,
+       &omap2430_iva_hwmod,
        NULL,
 };
 

diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 39b0c0eaa37d27d89552984c4de8bbdb171ac387..5d8eb58ba5e340f68875f28936aa38d6451b8ebd 100644 (file)
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -32,51 +32,53 @@
  */
 
 static struct omap_hwmod omap3xxx_mpu_hwmod;
-static struct omap_hwmod omap3xxx_l3_hwmod;
+static struct omap_hwmod omap3xxx_iva_hwmod;
+static struct omap_hwmod omap3xxx_l3_main_hwmod;
 static struct omap_hwmod omap3xxx_l4_core_hwmod;
 static struct omap_hwmod omap3xxx_l4_per_hwmod;
 
 /* L3 -> L4_CORE interface */
-static struct omap_hwmod_ocp_if omap3xxx_l3__l4_core = {
-       .master = &omap3xxx_l3_hwmod,
+static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
+       .master = &omap3xxx_l3_main_hwmod,
        .slave  = &omap3xxx_l4_core_hwmod,
        .user   = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* L3 -> L4_PER interface */
-static struct omap_hwmod_ocp_if omap3xxx_l3__l4_per = {
-       .master = &omap3xxx_l3_hwmod,
+static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
+       .master = &omap3xxx_l3_main_hwmod,
        .slave  = &omap3xxx_l4_per_hwmod,
        .user   = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* MPU -> L3 interface */
-static struct omap_hwmod_ocp_if omap3xxx_mpu__l3 = {
+static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
        .master = &omap3xxx_mpu_hwmod,
-       .slave  = &omap3xxx_l3_hwmod,
+       .slave  = &omap3xxx_l3_main_hwmod,
        .user   = OCP_USER_MPU,
 };
 
 /* Slave interfaces on the L3 interconnect */
-static struct omap_hwmod_ocp_if *omap3xxx_l3_slaves[] = {
-       &omap3xxx_mpu__l3,
+static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
+       &omap3xxx_mpu__l3_main,
 };
 
 /* Master interfaces on the L3 interconnect */
-static struct omap_hwmod_ocp_if *omap3xxx_l3_masters[] = {
-       &omap3xxx_l3__l4_core,
-       &omap3xxx_l3__l4_per,
+static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
+       &omap3xxx_l3_main__l4_core,
+       &omap3xxx_l3_main__l4_per,
 };
 
 /* L3 */
-static struct omap_hwmod omap3xxx_l3_hwmod = {
-       .name           = "l3_hwmod",
+static struct omap_hwmod omap3xxx_l3_main_hwmod = {
+       .name           = "l3_main",
        .class          = &l3_hwmod_class,
-       .masters        = omap3xxx_l3_masters,
-       .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_masters),
-       .slaves         = omap3xxx_l3_slaves,
-       .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_slaves),
-       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+       .masters        = omap3xxx_l3_main_masters,
+       .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
+       .slaves         = omap3xxx_l3_main_slaves,
+       .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+       .flags          = HWMOD_NO_IDLEST,
 };
 
 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
@@ -90,7 +92,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
 
 /* Slave interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
-       &omap3xxx_l3__l4_core,
+       &omap3xxx_l3_main__l4_core,
 };
 
 /* Master interfaces on the L4_CORE interconnect */
@@ -100,18 +102,19 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
 
 /* L4 CORE */
 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
-       .name           = "l4_core_hwmod",
+       .name           = "l4_core",
        .class          = &l4_hwmod_class,
        .masters        = omap3xxx_l4_core_masters,
        .masters_cnt    = ARRAY_SIZE(omap3xxx_l4_core_masters),
        .slaves         = omap3xxx_l4_core_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
-       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+       .flags          = HWMOD_NO_IDLEST,
 };
 
 /* Slave interfaces on the L4_PER interconnect */
 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
-       &omap3xxx_l3__l4_per,
+       &omap3xxx_l3_main__l4_per,
 };
 
 /* Master interfaces on the L4_PER interconnect */
@@ -120,13 +123,14 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
 
 /* L4 PER */
 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
-       .name           = "l4_per_hwmod",
+       .name           = "l4_per",
        .class          = &l4_hwmod_class,
        .masters        = omap3xxx_l4_per_masters,
        .masters_cnt    = ARRAY_SIZE(omap3xxx_l4_per_masters),
        .slaves         = omap3xxx_l4_per_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
-       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+       .flags          = HWMOD_NO_IDLEST,
 };
 
 /* Slave interfaces on the L4_WKUP interconnect */
@@ -140,18 +144,19 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = {
 
 /* L4 WKUP */
 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
-       .name           = "l4_wkup_hwmod",
+       .name           = "l4_wkup",
        .class          = &l4_hwmod_class,
        .masters        = omap3xxx_l4_wkup_masters,
        .masters_cnt    = ARRAY_SIZE(omap3xxx_l4_wkup_masters),
        .slaves         = omap3xxx_l4_wkup_slaves,
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
-       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+       .flags          = HWMOD_NO_IDLEST,
 };
 
 /* Master interfaces on the MPU device */
 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
-       &omap3xxx_mpu__l3,
+       &omap3xxx_mpu__l3_main,
 };
 
 /* MPU */
@@ -164,12 +169,41 @@ static struct omap_hwmod omap3xxx_mpu_hwmod = {
        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
+/*
+ * IVA2_2 interface data
+ */
+
+/* IVA2 <- L3 interface */
+static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
+       .master         = &omap3xxx_l3_main_hwmod,
+       .slave          = &omap3xxx_iva_hwmod,
+       .clk            = "iva2_ck",
+       .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
+       &omap3xxx_l3__iva,
+};
+
+/*
+ * IVA2 (IVA2)
+ */
+
+static struct omap_hwmod omap3xxx_iva_hwmod = {
+       .name           = "iva",
+       .class          = &iva_hwmod_class,
+       .masters        = omap3xxx_iva_masters,
+       .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
+       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
-       &omap3xxx_l3_hwmod,
+       &omap3xxx_l3_main_hwmod,
        &omap3xxx_l4_core_hwmod,
        &omap3xxx_l4_per_hwmod,
        &omap3xxx_l4_wkup_hwmod,
        &omap3xxx_mpu_hwmod,
+       &omap3xxx_iva_hwmod,
        NULL,
 };
 

diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c
index 1e80b914fa1ab32c7e6161bd84ff64ea2c4be8f7..08a134243ecba3febb134effb19dda5cda8dbd25 100644 (file)
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c
@@ -66,3 +66,6 @@ struct omap_hwmod_class mpu_hwmod_class = {
        .name = "mpu"
 };
 
+struct omap_hwmod_class iva_hwmod_class = {
+       .name = "iva"
+};

diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index 3645a28c7c27935723f2de7984740346f2e46304..c34e98bf124295906fc578873d21a1c84bad7bb3 100644 (file)
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -20,5 +20,6 @@
 extern struct omap_hwmod_class l3_hwmod_class;
 extern struct omap_hwmod_class l4_hwmod_class;
 extern struct omap_hwmod_class mpu_hwmod_class;
+extern struct omap_hwmod_class iva_hwmod_class;
 
 #endif

diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
new file mode 100644 (file)
index 0000000..68f9f2e
--- /dev/null
+++ b/arch/arm/mach-omap2/pm.c
@@ -0,0 +1,84 @@
+/*
+ * pm.c - Common OMAP2+ power management-related code
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/err.h>
+
+#include <plat/omap-pm.h>
+#include <plat/omap_device.h>
+#include <plat/common.h>
+
+static struct omap_device_pm_latency *pm_lats;
+
+static struct device *mpu_dev;
+static struct device *dsp_dev;
+static struct device *l3_dev;
+
+struct device *omap2_get_mpuss_device(void)
+{
+       WARN_ON_ONCE(!mpu_dev);
+       return mpu_dev;
+}
+
+struct device *omap2_get_dsp_device(void)
+{
+       WARN_ON_ONCE(!dsp_dev);
+       return dsp_dev;
+}
+
+struct device *omap2_get_l3_device(void)
+{
+       WARN_ON_ONCE(!l3_dev);
+       return l3_dev;
+}
+
+/* static int _init_omap_device(struct omap_hwmod *oh, void *user) */
+static int _init_omap_device(char *name, struct device **new_dev)
+{
+       struct omap_hwmod *oh;
+       struct omap_device *od;
+
+       oh = omap_hwmod_lookup(name);
+       if (WARN(!oh, "%s: could not find omap_hwmod for %s\n",
+                __func__, name))
+               return -ENODEV;
+
+       od = omap_device_build(oh->name, 0, oh, NULL, 0, pm_lats, 0, false);
+       if (WARN(IS_ERR(od), "%s: could not build omap_device for %s\n",
+                __func__, name))
+               return -ENODEV;
+
+       *new_dev = &od->pdev.dev;
+
+       return 0;
+}
+
+/*
+ * Build omap_devices for processors and bus.
+ */
+static void omap2_init_processor_devices(void)
+{
+       _init_omap_device("mpu", &mpu_dev);
+       _init_omap_device("iva", &dsp_dev);
+       _init_omap_device("l3_main", &l3_dev);
+}
+
+static int __init omap2_common_pm_init(void)
+{
+       omap2_init_processor_devices();
+       omap_pm_if_init();
+
+       return 0;
+}
+device_initcall(omap2_common_pm_init);
+

diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index e321281ab6e167f8ed04f0a671eec154ad400749..6aeedeacdad86b78cb9ef511a822f20d7c40cd1c 100644 (file)
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -39,7 +39,6 @@
 #include <plat/clock.h>
 #include <plat/sram.h>
 #include <plat/control.h>
-#include <plat/mux.h>
 #include <plat/dma.h>
 #include <plat/board.h>
 

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index b88737fd6cfe7a434f6254e81dad7f90d8e3cd1a..fb4994ad622ec469aaec34665a98af6250d29dc8 100644 (file)
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -385,8 +385,9 @@ void omap_sram_idle(void)
        /* Enable IO-PAD and IO-CHAIN wakeups */
        per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
        core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
-       if (per_next_state < PWRDM_POWER_ON ||
-                       core_next_state < PWRDM_POWER_ON) {
+       if (omap3_has_io_wakeup() && \
+                       (per_next_state < PWRDM_POWER_ON ||
+                       core_next_state < PWRDM_POWER_ON)) {
                prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
                omap3_enable_io_chain();
        }
@@ -479,7 +480,7 @@ void omap_sram_idle(void)
        }
 
        /* Disable IO-PAD and IO-CHAIN wakeup */
-       if (core_next_state < PWRDM_POWER_ON) {
+       if (omap3_has_io_wakeup() && core_next_state < PWRDM_POWER_ON) {
                prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
                omap3_disable_io_chain();
        }

diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
new file mode 100644 (file)
index 0000000..54544b4
--- /dev/null
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -0,0 +1,135 @@
+/*
+ * OMAP4 Power Management Routines
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/pm.h>
+#include <linux/suspend.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+
+#include <plat/powerdomain.h>
+#include <mach/omap4-common.h>
+
+struct power_state {
+       struct powerdomain *pwrdm;
+       u32 next_state;
+#ifdef CONFIG_SUSPEND
+       u32 saved_state;
+#endif
+       struct list_head node;
+};
+
+static LIST_HEAD(pwrst_list);
+
+#ifdef CONFIG_SUSPEND
+static int omap4_pm_prepare(void)
+{
+       disable_hlt();
+       return 0;
+}
+
+static int omap4_pm_suspend(void)
+{
+       do_wfi();
+       return 0;
+}
+
+static int omap4_pm_enter(suspend_state_t suspend_state)
+{
+       int ret = 0;
+
+       switch (suspend_state) {
+       case PM_SUSPEND_STANDBY:
+       case PM_SUSPEND_MEM:
+               ret = omap4_pm_suspend();
+               break;
+       default:
+               ret = -EINVAL;
+       }
+
+       return ret;
+}
+
+static void omap4_pm_finish(void)
+{
+       enable_hlt();
+       return;
+}
+
+static int omap4_pm_begin(suspend_state_t state)
+{
+       return 0;
+}
+
+static void omap4_pm_end(void)
+{
+       return;
+}
+
+static struct platform_suspend_ops omap_pm_ops = {
+       .begin          = omap4_pm_begin,
+       .end            = omap4_pm_end,
+       .prepare        = omap4_pm_prepare,
+       .enter          = omap4_pm_enter,
+       .finish         = omap4_pm_finish,
+       .valid          = suspend_valid_only_mem,
+};
+#endif /* CONFIG_SUSPEND */
+
+static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
+{
+       struct power_state *pwrst;
+
+       if (!pwrdm->pwrsts)
+               return 0;
+
+       pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
+       if (!pwrst)
+               return -ENOMEM;
+       pwrst->pwrdm = pwrdm;
+       pwrst->next_state = PWRDM_POWER_ON;
+       list_add(&pwrst->node, &pwrst_list);
+
+       return pwrdm_set_next_pwrst(pwrst->pwrdm, pwrst->next_state);
+}
+
+/**
+ * omap4_pm_init - Init routine for OMAP4 PM
+ *
+ * Initializes all powerdomain and clockdomain target states
+ * and all PRCM settings.
+ */
+static int __init omap4_pm_init(void)
+{
+       int ret;
+
+       if (!cpu_is_omap44xx())
+               return -ENODEV;
+
+       pr_err("Power Management for TI OMAP4.\n");
+
+#ifdef CONFIG_PM
+       ret = pwrdm_for_each(pwrdms_setup, NULL);
+       if (ret) {
+               pr_err("Failed to setup powerdomains\n");
+               goto err2;
+       }
+#endif
+
+#ifdef CONFIG_SUSPEND
+       suspend_set_ops(&omap_pm_ops);
+#endif /* CONFIG_SUSPEND */
+
+err2:
+       return ret;
+}
+late_initcall(omap4_pm_init);

diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index a2904aa7065e6f47d6a4f531d4aca7ea6e9a0411..6527ec30dc17ec7e57469ec7fc451cc320ccfd1b 100644 (file)
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -875,6 +875,7 @@ int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
                break;
        case 4:
                m = OMAP_MEM4_RETSTATE_MASK;
+               break;
        default:
                WARN_ON(1); /* should never happen */
                return -EEXIST;

diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h
index bd87112beea8e305609b5beb4048ed661a7258eb..fa904861668b42c2144de8c9c87d65a2561575e7 100644 (file)
--- a/arch/arm/mach-omap2/powerdomains34xx.h
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -75,12 +75,19 @@ static struct powerdomain mpu_3xxx_pwrdm = {
        },
 };
 
+/*
+ * The USBTLL Save-and-Restore mechanism is broken on
+ * 3430s upto ES3.0 and 3630ES1.0. Hence this feature
+ * needs to be disabled on these chips.
+ * Refer: 3430 errata ID i459 and 3630 errata ID i579
+ */
 static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
        .name             = "core_pwrdm",
        .prcm_offs        = CORE_MOD,
        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
                                           CHIP_IS_OMAP3430ES2 |
-                                          CHIP_IS_OMAP3430ES3_0),
+                                          CHIP_IS_OMAP3430ES3_0 |
+                                          CHIP_IS_OMAP3630ES1),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        .banks            = 2,
@@ -97,7 +104,8 @@ static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
 static struct powerdomain core_3xxx_es3_1_pwrdm = {
        .name             = "core_pwrdm",
        .prcm_offs        = CORE_MOD,
-       .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1),
+       .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1 |
+                                         CHIP_GE_OMAP3630ES1_1),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_OFF_RET,
        .flags            = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */

diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 3771254dfa811a45efda31a7afc7a0cc48ce86d5..566e991ede81248057eeb3fbab3aca2078353276 100644 (file)
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -37,6 +37,9 @@
 #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV    0x52
 #define UART_OMAP_WER          0x17    /* Wake-up enable register */
 
+#define UART_ERRATA_FIFO_FULL_ABORT    (0x1 << 0)
+#define UART_ERRATA_i202_MDR1_ACCESS   (0x1 << 1)
+
 /*
  * NOTE: By default the serial timeout is disabled as it causes lost characters
  * over the serial ports. This means that the UART clocks will stay on until
@@ -64,6 +67,7 @@ struct omap_uart_state {
        struct list_head node;
        struct platform_device pdev;
 
+       u32 errata;
 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
        int context_valid;
 
@@ -74,6 +78,7 @@ struct omap_uart_state {
        u16 sysc;
        u16 scr;
        u16 wer;
+       u16 mcr;
 #endif
 };
 
@@ -180,6 +185,42 @@ static inline void __init omap_uart_reset(struct omap_uart_state *uart)
 
 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
 
+/*
+ * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6)
+ * The access to uart register after MDR1 Access
+ * causes UART to corrupt data.
+ *
+ * Need a delay =
+ * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
+ * give 10 times as much
+ */
+static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
+               u8 fcr_val)
+{
+       struct plat_serial8250_port *p = uart->p;
+       u8 timeout = 255;
+
+       serial_write_reg(p, UART_OMAP_MDR1, mdr1_val);
+       udelay(2);
+       serial_write_reg(p, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
+                       UART_FCR_CLEAR_RCVR);
+       /*
+        * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
+        * TX_FIFO_E bit is 1.
+        */
+       while (UART_LSR_THRE != (serial_read_reg(p, UART_LSR) &
+                               (UART_LSR_THRE | UART_LSR_DR))) {
+               timeout--;
+               if (!timeout) {
+                       /* Should *never* happen. we warn and carry on */
+                       dev_crit(&uart->pdev.dev, "Errata i202: timedout %x\n",
+                               serial_read_reg(p, UART_LSR));
+                       break;
+               }
+               udelay(1);
+       }
+}
+
 static void omap_uart_save_context(struct omap_uart_state *uart)
 {
        u16 lcr = 0;
@@ -197,6 +238,9 @@ static void omap_uart_save_context(struct omap_uart_state *uart)
        uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
        uart->scr = serial_read_reg(p, UART_OMAP_SCR);
        uart->wer = serial_read_reg(p, UART_OMAP_WER);
+       serial_write_reg(p, UART_LCR, 0x80);
+       uart->mcr = serial_read_reg(p, UART_MCR);
+       serial_write_reg(p, UART_LCR, lcr);
 
        uart->context_valid = 1;
 }
@@ -214,7 +258,10 @@ static void omap_uart_restore_context(struct omap_uart_state *uart)
 
        uart->context_valid = 0;
 
-       serial_write_reg(p, UART_OMAP_MDR1, 0x7);
+       if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
+               omap_uart_mdr1_errataset(uart, 0x07, 0xA0);
+       else
+               serial_write_reg(p, UART_OMAP_MDR1, 0x7);
        serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
        efr = serial_read_reg(p, UART_EFR);
        serial_write_reg(p, UART_EFR, UART_EFR_ECB);
@@ -225,14 +272,18 @@ static void omap_uart_restore_context(struct omap_uart_state *uart)
        serial_write_reg(p, UART_DLM, uart->dlh);
        serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
        serial_write_reg(p, UART_IER, uart->ier);
-       serial_write_reg(p, UART_FCR, 0xA1);
+       serial_write_reg(p, UART_LCR, 0x80);
+       serial_write_reg(p, UART_MCR, uart->mcr);
        serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
        serial_write_reg(p, UART_EFR, efr);
        serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
        serial_write_reg(p, UART_OMAP_SCR, uart->scr);
        serial_write_reg(p, UART_OMAP_WER, uart->wer);
        serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
-       serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
+       if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
+               omap_uart_mdr1_errataset(uart, 0x00, 0xA1);
+       else
+               serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
 }
 #else
 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
@@ -489,8 +540,8 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
                }
                uart->wk_mask = wk_mask;
        } else {
-               uart->wk_en = 0;
-               uart->wk_st = 0;
+               uart->wk_en = NULL;
+               uart->wk_st = NULL;
                uart->wk_mask = 0;
                uart->padconf = 0;
        }
@@ -552,7 +603,8 @@ static ssize_t sleep_timeout_store(struct device *dev,
        return n;
 }
 
-DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
+static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show,
+               sleep_timeout_store);
 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
 #else
 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
@@ -749,14 +801,20 @@ void __init omap_serial_init_port(int port)
         * omap3xxx: Never read empty UART fifo on UARTs
         * with IP rev >=0x52
         */
-       if (cpu_is_omap44xx()) {
-               uart->p->serial_in = serial_in_override;
-               uart->p->serial_out = serial_out_override;
-       } else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
-                       >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) {
+       if (cpu_is_omap44xx())
+               uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
+       else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
+                       >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
+               uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
+
+       if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) {
                uart->p->serial_in = serial_in_override;
                uart->p->serial_out = serial_out_override;
        }
+
+       /* Enable the MDR1 errata for OMAP3 */
+       if (cpu_is_omap34xx())
+               uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
 }
 
 /**

diff --git a/arch/arm/mach-omap2/usb-ehci.c b/arch/arm/mach-omap2/usb-ehci.c
index d72d1ac303338e23bed5abe38392e9aed6e0183b..b11bf385d360485ba1d0b9ecbef4f3d33460a6ea 100644 (file)
--- a/arch/arm/mach-omap2/usb-ehci.c
+++ b/arch/arm/mach-omap2/usb-ehci.c
@@ -23,7 +23,6 @@
 #include <linux/dma-mapping.h>
 
 #include <asm/io.h>
-#include <plat/mux.h>
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>

diff --git a/arch/arm/mach-omap2/usb-fs.c b/arch/arm/mach-omap2/usb-fs.c
new file mode 100644 (file)
index 0000000..a216d88
--- /dev/null
+++ b/arch/arm/mach-omap2/usb-fs.c
@@ -0,0 +1,359 @@
+/*
+ * Platform level USB initialization for FS USB OTG controller on omap1 and 24xx
+ *
+ * Copyright (C) 2004 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include <asm/irq.h>
+
+#include <plat/control.h>
+#include <plat/usb.h>
+#include <plat/board.h>
+
+#define INT_USB_IRQ_GEN                INT_24XX_USB_IRQ_GEN
+#define INT_USB_IRQ_NISO       INT_24XX_USB_IRQ_NISO
+#define INT_USB_IRQ_ISO                INT_24XX_USB_IRQ_ISO
+#define INT_USB_IRQ_HGEN       INT_24XX_USB_IRQ_HGEN
+#define INT_USB_IRQ_OTG                INT_24XX_USB_IRQ_OTG
+
+#include "mux.h"
+
+#if defined(CONFIG_ARCH_OMAP2)
+
+#ifdef CONFIG_USB_GADGET_OMAP
+
+static struct resource udc_resources[] = {
+       /* order is significant! */
+       {               /* registers */
+               .start          = UDC_BASE,
+               .end            = UDC_BASE + 0xff,
+               .flags          = IORESOURCE_MEM,
+       }, {            /* general IRQ */
+               .start          = INT_USB_IRQ_GEN,
+               .flags          = IORESOURCE_IRQ,
+       }, {            /* PIO IRQ */
+               .start          = INT_USB_IRQ_NISO,
+               .flags          = IORESOURCE_IRQ,
+       }, {            /* SOF IRQ */
+               .start          = INT_USB_IRQ_ISO,
+               .flags          = IORESOURCE_IRQ,
+       },
+};
+
+static u64 udc_dmamask = ~(u32)0;
+
+static struct platform_device udc_device = {
+       .name           = "omap_udc",
+       .id             = -1,
+       .dev = {
+               .dma_mask               = &udc_dmamask,
+               .coherent_dma_mask      = 0xffffffff,
+       },
+       .num_resources  = ARRAY_SIZE(udc_resources),
+       .resource       = udc_resources,
+};
+
+static inline void udc_device_init(struct omap_usb_config *pdata)
+{
+       pdata->udc_device = &udc_device;
+}
+
+#else
+
+static inline void udc_device_init(struct omap_usb_config *pdata)
+{
+}
+
+#endif
+
+#if    defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+
+/* The dmamask must be set for OHCI to work */
+static u64 ohci_dmamask = ~(u32)0;
+
+static struct resource ohci_resources[] = {
+       {
+               .start  = OMAP_OHCI_BASE,
+               .end    = OMAP_OHCI_BASE + 0xff,
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .start  = INT_USB_IRQ_HGEN,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device ohci_device = {
+       .name                   = "ohci",
+       .id                     = -1,
+       .dev = {
+               .dma_mask               = &ohci_dmamask,
+               .coherent_dma_mask      = 0xffffffff,
+       },
+       .num_resources  = ARRAY_SIZE(ohci_resources),
+       .resource               = ohci_resources,
+};
+
+static inline void ohci_device_init(struct omap_usb_config *pdata)
+{
+       pdata->ohci_device = &ohci_device;
+}
+
+#else
+
+static inline void ohci_device_init(struct omap_usb_config *pdata)
+{
+}
+
+#endif
+
+#if    defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG)
+
+static struct resource otg_resources[] = {
+       /* order is significant! */
+       {
+               .start          = OTG_BASE,
+               .end            = OTG_BASE + 0xff,
+               .flags          = IORESOURCE_MEM,
+       }, {
+               .start          = INT_USB_IRQ_OTG,
+               .flags          = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device otg_device = {
+       .name           = "omap_otg",
+       .id             = -1,
+       .num_resources  = ARRAY_SIZE(otg_resources),
+       .resource       = otg_resources,
+};
+
+static inline void otg_device_init(struct omap_usb_config *pdata)
+{
+       pdata->otg_device = &otg_device;
+}
+
+#else
+
+static inline void otg_device_init(struct omap_usb_config *pdata)
+{
+}
+
+#endif
+
+static void omap2_usb_devconf_clear(u8 port, u32 mask)
+{
+       u32 r;
+
+       r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+       r &= ~USBTXWRMODEI(port, mask);
+       omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
+}
+
+static void omap2_usb_devconf_set(u8 port, u32 mask)
+{
+       u32 r;
+
+       r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+       r |= USBTXWRMODEI(port, mask);
+       omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
+}
+
+static void omap2_usb2_disable_5pinbitll(void)
+{
+       u32 r;
+
+       r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+       r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI);
+       omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
+}
+
+static void omap2_usb2_enable_5pinunitll(void)
+{
+       u32 r;
+
+       r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+       r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI;
+       omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
+}
+
+static u32 __init omap2_usb0_init(unsigned nwires, unsigned is_device)
+{
+       u32     syscon1 = 0;
+
+       omap2_usb_devconf_clear(0, USB_BIDIR_TLL);
+
+       if (nwires == 0)
+               return 0;
+
+       if (is_device)
+               omap_mux_init_signal("usb0_puen", 0);
+
+       omap_mux_init_signal("usb0_dat", 0);
+       omap_mux_init_signal("usb0_txen", 0);
+       omap_mux_init_signal("usb0_se0", 0);
+       if (nwires != 3)
+               omap_mux_init_signal("usb0_rcv", 0);
+
+       switch (nwires) {
+       case 3:
+               syscon1 = 2;
+               omap2_usb_devconf_set(0, USB_BIDIR);
+               break;
+       case 4:
+               syscon1 = 1;
+               omap2_usb_devconf_set(0, USB_BIDIR);
+               break;
+       case 6:
+               syscon1 = 3;
+               omap_mux_init_signal("usb0_vp", 0);
+               omap_mux_init_signal("usb0_vm", 0);
+               omap2_usb_devconf_set(0, USB_UNIDIR);
+               break;
+       default:
+               printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
+                       0, nwires);
+       }
+
+       return syscon1 << 16;
+}
+
+static u32 __init omap2_usb1_init(unsigned nwires)
+{
+       u32     syscon1 = 0;
+
+       omap2_usb_devconf_clear(1, USB_BIDIR_TLL);
+
+       if (nwires == 0)
+               return 0;
+
+       /* NOTE:  board-specific code must set up pin muxing for usb1,
+        * since each signal could come out on either of two balls.
+        */
+
+       switch (nwires) {
+       case 2:
+               /* NOTE: board-specific code must override this setting if
+                * this TLL link is not using DP/DM
+                */
+               syscon1 = 1;
+               omap2_usb_devconf_set(1, USB_BIDIR_TLL);
+               break;
+       case 3:
+               syscon1 = 2;
+               omap2_usb_devconf_set(1, USB_BIDIR);
+               break;
+       case 4:
+               syscon1 = 1;
+               omap2_usb_devconf_set(1, USB_BIDIR);
+               break;
+       case 6:
+       default:
+               printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
+                       1, nwires);
+       }
+
+       return syscon1 << 20;
+}
+
+static u32 __init omap2_usb2_init(unsigned nwires, unsigned alt_pingroup)
+{
+       u32     syscon1 = 0;
+
+       omap2_usb2_disable_5pinbitll();
+       alt_pingroup = 0;
+
+       /* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */
+       if (alt_pingroup || nwires == 0)
+               return 0;
+
+       omap_mux_init_signal("usb2_dat", 0);
+       omap_mux_init_signal("usb2_se0", 0);
+       if (nwires > 2)
+               omap_mux_init_signal("usb2_txen", 0);
+       if (nwires > 3)
+               omap_mux_init_signal("usb2_rcv", 0);
+
+       switch (nwires) {
+       case 2:
+               /* NOTE: board-specific code must override this setting if
+                * this TLL link is not using DP/DM
+                */
+               syscon1 = 1;
+               omap2_usb_devconf_set(2, USB_BIDIR_TLL);
+               break;
+       case 3:
+               syscon1 = 2;
+               omap2_usb_devconf_set(2, USB_BIDIR);
+               break;
+       case 4:
+               syscon1 = 1;
+               omap2_usb_devconf_set(2, USB_BIDIR);
+               break;
+       case 5:
+               /* NOTE: board-specific code must mux this setting depending
+                * on TLL link using DP/DM.  Something must also
+                * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED}
+                * 2420: hdq_sio.usb2_tllse0 or vlynq_rx0.usb2_tllse0
+                * 2430: hdq_sio.usb2_tllse0 or sdmmc2_dat0.usb2_tllse0
+                */
+
+               syscon1 = 3;
+               omap2_usb2_enable_5pinunitll();
+               break;
+       case 6:
+       default:
+               printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
+                       2, nwires);
+       }
+
+       return syscon1 << 24;
+}
+
+void __init omap2_usbfs_init(struct omap_usb_config *pdata)
+{
+       struct clk *ick;
+
+       if (!cpu_is_omap24xx())
+               return;
+
+       ick = clk_get(NULL, "usb_l4_ick");
+       if (IS_ERR(ick))
+               return;
+
+       clk_enable(ick);
+       pdata->usb0_init = omap2_usb0_init;
+       pdata->usb1_init = omap2_usb1_init;
+       pdata->usb2_init = omap2_usb2_init;
+       udc_device_init(pdata);
+       ohci_device_init(pdata);
+       otg_device_init(pdata);
+       omap_otg_init(pdata);
+       clk_disable(ick);
+       clk_put(ick);
+}
+
+#endif

diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 96f6787e00b25071294d26f8659cc5afded6d6db..33a5cde1c227ab1767ca53e47e3189147a7a61cb 100644 (file)
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -28,7 +28,6 @@
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>
-#include <plat/mux.h>
 #include <plat/usb.h>
 
 #ifdef CONFIG_USB_MUSB_SOC

diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index 10a2013c110439e090a4c5aa181acffd3935e7a5..64a0112b70a5f0657db5911cad920ff488e47f8e 100644 (file)
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -17,8 +17,8 @@
 #include <linux/usb/musb.h>
 
 #include <plat/gpmc.h>
-#include <plat/mux.h>
 
+#include "mux.h"
 
 static u8              async_cs, sync_cs;
 static unsigned                refclk_psec;
@@ -325,17 +325,17 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
        else {
                /* assume OMAP 2420 ES2.0 and later */
                if (dmachan & (1 << 0))
-                       omap_cfg_reg(AA10_242X_DMAREQ0);
+                       omap_mux_init_signal("sys_ndmareq0", 0);
                if (dmachan & (1 << 1))
-                       omap_cfg_reg(AA6_242X_DMAREQ1);
+                       omap_mux_init_signal("sys_ndmareq1", 0);
                if (dmachan & (1 << 2))
-                       omap_cfg_reg(E4_242X_DMAREQ2);
+                       omap_mux_init_signal("sys_ndmareq2", 0);
                if (dmachan & (1 << 3))
-                       omap_cfg_reg(G4_242X_DMAREQ3);
+                       omap_mux_init_signal("sys_ndmareq3", 0);
                if (dmachan & (1 << 4))
-                       omap_cfg_reg(D3_242X_DMAREQ4);
+                       omap_mux_init_signal("sys_ndmareq4", 0);
                if (dmachan & (1 << 5))
-                       omap_cfg_reg(E3_242X_DMAREQ5);
+                       omap_mux_init_signal("sys_ndmareq5", 0);
        }
 
        /* so far so good ... register the device */

diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 905719a677ae31b8be356f356b289569157ec48d..c897e03e413d05eb91c836d0472d9534f71633f7 100644 (file)
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -26,6 +26,7 @@ config MACH_KUROBOX_PRO
 config MACH_DNS323
        bool "D-Link DNS-323"
        select I2C_BOARDINFO
+       select PHYLIB
        help
          Say 'Y' here if you want your kernel to support the
          D-Link DNS-323 platform.

diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index fe0de1698edc95c9e4aedf78aac576d2fc9e69b8..a47100d46a4e88a9f3f41b4d1705ddc397cfe622 100644 (file)
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -3,6 +3,10 @@
  *
  * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
  *
+ * Support for HW Rev C1:
+ *
+ * Copyright (C) 2010 Benjamin Herrenschmidt <benh@kernel.crashing.org>
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU Lesser General Public License as
  * published by the Free Software Foundation; either version 2 of the
@@ -23,6 +27,8 @@
 #include <linux/input.h>
 #include <linux/i2c.h>
 #include <linux/ata_platform.h>
+#include <linux/phy.h>
+#include <linux/marvell_phy.h>
 #include <asm/mach-types.h>
 #include <asm/gpio.h>
 #include <asm/mach/arch.h>
@@ -31,6 +37,7 @@
 #include "common.h"
 #include "mpp.h"
 
+/* Rev A1 and B1 */
 #define DNS323_GPIO_LED_RIGHT_AMBER    1
 #define DNS323_GPIO_LED_LEFT_AMBER     2
 #define DNS323_GPIO_SYSTEM_UP          3
@@ -42,6 +49,23 @@
 #define DNS323_GPIO_KEY_POWER          9
 #define DNS323_GPIO_KEY_RESET          10
 
+/* Rev C1 */
+#define DNS323C_GPIO_KEY_POWER         1
+#define DNS323C_GPIO_POWER_OFF         2
+#define DNS323C_GPIO_LED_RIGHT_AMBER   8
+#define DNS323C_GPIO_LED_LEFT_AMBER    9
+#define DNS323C_GPIO_LED_POWER         17
+#define DNS323C_GPIO_FAN_BIT1          18
+#define DNS323C_GPIO_FAN_BIT0          19
+
+/* Exposed to userspace, do not change */
+enum {
+       DNS323_REV_A1,  /* 0 */
+       DNS323_REV_B1,  /* 1 */
+       DNS323_REV_C1,  /* 2 */
+};
+
+
 /****************************************************************************
  * PCI setup
  */
@@ -68,21 +92,12 @@ static struct hw_pci dns323_pci __initdata = {
        .map_irq        = dns323_pci_map_irq,
 };
 
-static int __init dns323_dev_id(void)
-{
-       u32 dev, rev;
-
-       orion5x_pcie_id(&dev, &rev);
-
-       return dev;
-}
-
 static int __init dns323_pci_init(void)
 {
-       /* The 5182 doesn't really use its PCI bus, and initialising PCI
+       /* Rev B1 and C1 doesn't really use its PCI bus, and initialising PCI
         * gets in the way of initialising the SATA controller.
         */
-       if (machine_is_dns323() && dns323_dev_id() != MV88F5182_DEV_ID)
+       if (machine_is_dns323() && system_rev == DNS323_REV_A1)
                pci_common_init(&dns323_pci);
 
        return 0;
@@ -221,7 +236,7 @@ static int __init dns323_read_mac_addr(void)
        }
 
        iounmap(mac_page);
-       printk("DNS323: Found ethernet MAC address: ");
+       printk("DNS-323: Found ethernet MAC address: ");
        for (i = 0; i < 6; i++)
                printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n");
 
@@ -259,12 +274,11 @@ static int dns323_gpio_blink_set(unsigned gpio, int state,
        return 0;
 }
 
-static struct gpio_led dns323_leds[] = {
+static struct gpio_led dns323ab_leds[] = {
        {
                .name = "power:blue",
                .gpio = DNS323_GPIO_LED_POWER2,
-               .default_trigger = "timer",
-               .active_low = 1,
+               .default_trigger = "default-on",
        }, {
                .name = "right:amber",
                .gpio = DNS323_GPIO_LED_RIGHT_AMBER,
@@ -276,9 +290,34 @@ static struct gpio_led dns323_leds[] = {
        },
 };
 
-static struct gpio_led_platform_data dns323_led_data = {
-       .num_leds       = ARRAY_SIZE(dns323_leds),
-       .leds           = dns323_leds,
+
+static struct gpio_led dns323c_leds[] = {
+       {
+               .name = "power:blue",
+               .gpio = DNS323C_GPIO_LED_POWER,
+               .default_trigger = "timer",
+               .active_low = 1,
+       }, {
+               .name = "right:amber",
+               .gpio = DNS323C_GPIO_LED_RIGHT_AMBER,
+               .active_low = 1,
+       }, {
+               .name = "left:amber",
+               .gpio = DNS323C_GPIO_LED_LEFT_AMBER,
+               .active_low = 1,
+       },
+};
+
+
+static struct gpio_led_platform_data dns323ab_led_data = {
+       .num_leds       = ARRAY_SIZE(dns323ab_leds),
+       .leds           = dns323ab_leds,
+       .gpio_blink_set = dns323_gpio_blink_set,
+};
+
+static struct gpio_led_platform_data dns323c_led_data = {
+       .num_leds       = ARRAY_SIZE(dns323c_leds),
+       .leds           = dns323c_leds,
        .gpio_blink_set = dns323_gpio_blink_set,
 };
 
@@ -286,7 +325,7 @@ static struct platform_device dns323_gpio_leds = {
        .name           = "leds-gpio",
        .id             = -1,
        .dev            = {
-               .platform_data  = &dns323_led_data,
+               .platform_data  = &dns323ab_led_data,
        },
 };
 
@@ -294,7 +333,7 @@ static struct platform_device dns323_gpio_leds = {
  * GPIO Attached Keys
  */
 
-static struct gpio_keys_button dns323_buttons[] = {
+static struct gpio_keys_button dns323ab_buttons[] = {
        {
                .code           = KEY_RESTART,
                .gpio           = DNS323_GPIO_KEY_RESET,
@@ -308,9 +347,23 @@ static struct gpio_keys_button dns323_buttons[] = {
        },
 };
 
-static struct gpio_keys_platform_data dns323_button_data = {
-       .buttons        = dns323_buttons,
-       .nbuttons       = ARRAY_SIZE(dns323_buttons),
+static struct gpio_keys_platform_data dns323ab_button_data = {
+       .buttons        = dns323ab_buttons,
+       .nbuttons       = ARRAY_SIZE(dns323ab_buttons),
+};
+
+static struct gpio_keys_button dns323c_buttons[] = {
+       {
+               .code           = KEY_POWER,
+               .gpio           = DNS323C_GPIO_KEY_POWER,
+               .desc           = "Power Button",
+               .active_low     = 1,
+       },
+};
+
+static struct gpio_keys_platform_data dns323c_button_data = {
+       .buttons        = dns323c_buttons,
+       .nbuttons       = ARRAY_SIZE(dns323c_buttons),
 };
 
 static struct platform_device dns323_button_device = {
@@ -318,7 +371,7 @@ static struct platform_device dns323_button_device = {
        .id             = -1,
        .num_resources  = 0,
        .dev            = {
-               .platform_data  = &dns323_button_data,
+               .platform_data  = &dns323ab_button_data,
        },
 };
 
@@ -332,7 +385,7 @@ static struct mv_sata_platform_data dns323_sata_data = {
 /****************************************************************************
  * General Setup
  */
-static struct orion5x_mpp_mode dns323_mv88f5181_mpp_modes[] __initdata = {
+static struct orion5x_mpp_mode dns323a_mpp_modes[] __initdata = {
        {  0, MPP_PCIE_RST_OUTn },
        {  1, MPP_GPIO },               /* right amber LED (sata ch0) */
        {  2, MPP_GPIO },               /* left amber LED (sata ch1) */
@@ -356,7 +409,7 @@ static struct orion5x_mpp_mode dns323_mv88f5181_mpp_modes[] __initdata = {
        { -1 },
 };
 
-static struct orion5x_mpp_mode dns323_mv88f5182_mpp_modes[] __initdata = {
+static struct orion5x_mpp_mode dns323b_mpp_modes[] __initdata = {
        {  0, MPP_UNUSED },
        {  1, MPP_GPIO },               /* right amber LED (sata ch0) */
        {  2, MPP_GPIO },               /* left amber LED (sata ch1) */
@@ -380,15 +433,57 @@ static struct orion5x_mpp_mode dns323_mv88f5182_mpp_modes[] __initdata = {
        { -1 },
 };
 
+static struct orion5x_mpp_mode dns323c_mpp_modes[] __initdata = {
+       {  0, MPP_GPIO },               /* ? input */
+       {  1, MPP_GPIO },               /* input power switch (0 = pressed) */
+       {  2, MPP_GPIO },               /* output power off */
+       {  3, MPP_UNUSED },             /* ? output */
+       {  4, MPP_UNUSED },             /* ? output */
+       {  5, MPP_UNUSED },             /* ? output */
+       {  6, MPP_UNUSED },             /* ? output */
+       {  7, MPP_UNUSED },             /* ? output */
+       {  8, MPP_GPIO },               /* i/o right amber LED */
+       {  9, MPP_GPIO },               /* i/o left amber LED */
+       { 10, MPP_GPIO },               /* input */
+       { 11, MPP_UNUSED },
+       { 12, MPP_SATA_LED },
+       { 13, MPP_SATA_LED },
+       { 14, MPP_SATA_LED },
+       { 15, MPP_SATA_LED },
+       { 16, MPP_UNUSED },
+       { 17, MPP_GPIO },               /* power button LED */
+       { 18, MPP_GPIO },               /* fan speed bit 0 */
+       { 19, MPP_GPIO },               /* fan speed bit 1 */
+       { -1 },
+};
+
+/* Rev C1 Fan speed notes:
+ *
+ * The fan is controlled by 2 GPIOs on this board. The settings
+ * of the bits is as follow:
+ *
+ *  GPIO 18    GPIO 19    Fan
+ *
+ *    0          0        stopped
+ *    0          1        low speed
+ *    1          0        high speed
+ *    1          1        don't do that (*)
+ *
+ * (*) I think the two bits control two feed-in resistors into a fixed
+ *     PWN circuit, setting both bits will basically go a 'bit' faster
+ *     than high speed, but d-link doesn't do it and you may get out of
+ *     HW spec so don't do it.
+ */
+
 /*
- * On the DNS-323 the following devices are attached via I2C:
+ * On the DNS-323 A1 and B1 the following devices are attached via I2C:
  *
  *  i2c addr | chip        | description
  *  0x3e     | GMT G760Af  | fan speed PWM controller
  *  0x48     | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible)
  *  0x68     | ST M41T80   | RTC w/ alarm
  */
-static struct i2c_board_info __initdata dns323_i2c_devices[] = {
+static struct i2c_board_info __initdata dns323ab_i2c_devices[] = {
        {
                I2C_BOARD_INFO("g760a", 0x3e),
        }, {
@@ -398,36 +493,140 @@ static struct i2c_board_info __initdata dns323_i2c_devices[] = {
        },
 };
 
+/*
+ * On the DNS-323 C1 the following devices are attached via I2C:
+ *
+ *  i2c addr | chip        | description
+ *  0x48     | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible)
+ *  0x68     | ST M41T80   | RTC w/ alarm
+ */
+static struct i2c_board_info __initdata dns323c_i2c_devices[] = {
+       {
+               I2C_BOARD_INFO("lm75", 0x48),
+       }, {
+               I2C_BOARD_INFO("m41t80", 0x68),
+       },
+};
+
 /* DNS-323 rev. A specific power off method */
 static void dns323a_power_off(void)
 {
-       pr_info("%s: triggering power-off...\n", __func__);
+       pr_info("DNS-323: Triggering power-off...\n");
        gpio_set_value(DNS323_GPIO_POWER_OFF, 1);
 }
 
 /* DNS-323 rev B specific power off method */
 static void dns323b_power_off(void)
 {
-       pr_info("%s: triggering power-off...\n", __func__);
+       pr_info("DNS-323: Triggering power-off...\n");
        /* Pin has to be changed to 1 and back to 0 to do actual power off. */
        gpio_set_value(DNS323_GPIO_POWER_OFF, 1);
        mdelay(100);
        gpio_set_value(DNS323_GPIO_POWER_OFF, 0);
 }
 
+/* DNS-323 rev. C specific power off method */
+static void dns323c_power_off(void)
+{
+       pr_info("DNS-323: Triggering power-off...\n");
+       gpio_set_value(DNS323C_GPIO_POWER_OFF, 1);
+}
+
+static int dns323c_phy_fixup(struct phy_device *phy)
+{
+       phy->dev_flags |= MARVELL_PHY_M1118_DNS323_LEDS;
+
+       return 0;
+}
+
+static int __init dns323_identify_rev(void)
+{
+       u32 dev, rev, i, reg;
+
+       pr_debug("DNS-323: Identifying board ... \n");
+
+       /* Rev A1 has a 5181 */
+       orion5x_pcie_id(&dev, &rev);
+       if (dev == MV88F5181_DEV_ID) {
+               pr_debug("DNS-323: 5181 found, board is A1\n");
+               return DNS323_REV_A1;
+       }
+       pr_debug("DNS-323: 5182 found, board is B1 or C1, checking PHY...\n");
+
+       /* Rev B1 and C1 both have 5182, let's poke at the eth PHY. This is
+        * a bit gross but we want to do that without links into the eth
+        * driver so let's poke at it directly. We default to rev B1 in
+        * case the accesses fail
+        */
+
+#define ETH_SMI_REG            (ORION5X_ETH_VIRT_BASE + 0x2000 + 0x004)
+#define  SMI_BUSY              0x10000000
+#define  SMI_READ_VALID                0x08000000
+#define  SMI_OPCODE_READ       0x04000000
+#define  SMI_OPCODE_WRITE      0x00000000
+
+       for (i = 0; i < 1000; i++) {
+               reg = readl(ETH_SMI_REG);
+               if (!(reg & SMI_BUSY))
+                       break;
+       }
+       if (i >= 1000) {
+               pr_warning("DNS-323: Timeout accessing PHY, assuming rev B1\n");
+               return DNS323_REV_B1;
+       }
+       writel((3 << 21)        /* phy ID reg */ |
+              (8 << 16)        /* phy addr */ |
+              SMI_OPCODE_READ, ETH_SMI_REG);
+       for (i = 0; i < 1000; i++) {
+               reg = readl(ETH_SMI_REG);
+               if (reg & SMI_READ_VALID)
+                       break;
+       }
+       if (i >= 1000) {
+               pr_warning("DNS-323: Timeout reading PHY, assuming rev B1\n");
+               return DNS323_REV_B1;
+       }
+       pr_debug("DNS-323: Ethernet PHY ID 0x%x\n", reg & 0xffff);
+
+       /* Note: the Marvell tools mask the ID with 0x3f0 before comparison
+        * but I don't see that making a difference here, at least with
+        * any known Marvell PHY ID
+        */
+       switch(reg & 0xfff0) {
+       case 0x0cc0: /* MV88E1111 */
+               return DNS323_REV_B1;
+       case 0x0e10: /* MV88E1118 */
+               return DNS323_REV_C1;
+       default:
+               pr_warning("DNS-323: Unknown PHY ID 0x%04x, assuming rev B1\n",
+                          reg & 0xffff);
+       }
+       return DNS323_REV_B1;
+}
+
 static void __init dns323_init(void)
 {
        /* Setup basic Orion functions. Need to be called early. */
        orion5x_init();
 
+       /* Identify revision */
+       system_rev = dns323_identify_rev();
+       pr_info("DNS-323: Identified HW revision %c1\n", 'A' + system_rev);
+
        /* Just to be tricky, the 5182 has a completely different
         * set of MPP modes to the 5181.
         */
-       if (dns323_dev_id() == MV88F5182_DEV_ID)
-               orion5x_mpp_conf(dns323_mv88f5182_mpp_modes);
-       else {
-               orion5x_mpp_conf(dns323_mv88f5181_mpp_modes);
+       switch(system_rev) {
+       case DNS323_REV_A1:
+               orion5x_mpp_conf(dns323a_mpp_modes);
                writel(0, MPP_DEV_CTRL);                /* DEV_D[31:16] */
+               break;
+       case DNS323_REV_B1:
+               orion5x_mpp_conf(dns323b_mpp_modes);
+               break;
+       case DNS323_REV_C1:
+               orion5x_mpp_conf(dns323c_mpp_modes);
+               break;
        }
 
        /* setup flash mapping
@@ -436,53 +635,96 @@ static void __init dns323_init(void)
        orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE);
        platform_device_register(&dns323_nor_flash);
 
-       /* The 5181 power LED is active low and requires
-        * DNS323_GPIO_LED_POWER1 to also be low.
-        */
-       if (dns323_dev_id() == MV88F5181_DEV_ID) {
-               dns323_leds[0].active_low = 1;
-               gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable");
-               gpio_direction_output(DNS323_GPIO_LED_POWER1, 0);
+       /* Sort out LEDs, Buttons and i2c devices */
+       switch(system_rev) {
+       case DNS323_REV_A1:
+               /* The 5181 power LED is active low and requires
+                * DNS323_GPIO_LED_POWER1 to also be low.
+                */
+                dns323ab_leds[0].active_low = 1;
+                gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable");
+                gpio_direction_output(DNS323_GPIO_LED_POWER1, 0);
+               /* Fall through */
+       case DNS323_REV_B1:
+               i2c_register_board_info(0, dns323ab_i2c_devices,
+                               ARRAY_SIZE(dns323ab_i2c_devices));
+               break;
+       case DNS323_REV_C1:
+               /* Hookup LEDs & Buttons */
+               dns323_gpio_leds.dev.platform_data = &dns323c_led_data;
+               dns323_button_device.dev.platform_data = &dns323c_button_data;
+
+               /* Hookup i2c devices and fan driver */
+               i2c_register_board_info(0, dns323c_i2c_devices,
+                               ARRAY_SIZE(dns323c_i2c_devices));
+               platform_device_register_simple("dns323c-fan", 0, NULL, 0);
+
+               /* Register fixup for the PHY LEDs */
+               phy_register_fixup_for_uid(MARVELL_PHY_ID_88E1118,
+                                          MARVELL_PHY_ID_MASK,
+                                          dns323c_phy_fixup);
        }
 
        platform_device_register(&dns323_gpio_leds);
-
        platform_device_register(&dns323_button_device);
 
-       i2c_register_board_info(0, dns323_i2c_devices,
-                               ARRAY_SIZE(dns323_i2c_devices));
-
        /*
         * Configure peripherals.
         */
        if (dns323_read_mac_addr() < 0)
-               printk("DNS323: Failed to read MAC address\n");
-
+               printk("DNS-323: Failed to read MAC address\n");
        orion5x_ehci0_init();
        orion5x_eth_init(&dns323_eth_data);
        orion5x_i2c_init();
        orion5x_uart0_init();
 
-       /* The 5182 has its SATA controller on-chip, and needs its own little
-        * init routine.
-        */
-       if (dns323_dev_id() == MV88F5182_DEV_ID)
+       /* Remaining GPIOs */
+       switch(system_rev) {
+       case DNS323_REV_A1:
+               /* Poweroff GPIO */
+               if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
+                   gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
+                       pr_err("DNS-323: failed to setup power-off GPIO\n");
+               pm_power_off = dns323a_power_off;
+               break;
+       case DNS323_REV_B1:
+               /* 5182 built-in SATA init */
                orion5x_sata_init(&dns323_sata_data);
 
-       /* The 5182 has flag to indicate the system is up. Without this flag
-        * set, power LED will flash and cannot be controlled via leds-gpio.
-        */
-       if (dns323_dev_id() == MV88F5182_DEV_ID)
-               gpio_set_value(DNS323_GPIO_SYSTEM_UP, 1);
-
-       /* Register dns323 specific power-off method */
-       if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
-           gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
-               pr_err("DNS323: failed to setup power-off GPIO\n");
-       if (dns323_dev_id() == MV88F5182_DEV_ID)
+               /* The DNS323 rev B1 has flag to indicate the system is up.
+                * Without this flag set, power LED will flash and cannot be
+                * controlled via leds-gpio.
+                */
+               if (gpio_request(DNS323_GPIO_SYSTEM_UP, "SYS_READY") == 0)
+                       gpio_direction_output(DNS323_GPIO_SYSTEM_UP, 1);
+
+               /* Poweroff GPIO */
+               if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
+                   gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
+                       pr_err("DNS-323: failed to setup power-off GPIO\n");
                pm_power_off = dns323b_power_off;
-       else
-               pm_power_off = dns323a_power_off;
+               break;
+       case DNS323_REV_C1:
+               /* 5182 built-in SATA init */
+               orion5x_sata_init(&dns323_sata_data);
+
+               /* Poweroff GPIO */
+               if (gpio_request(DNS323C_GPIO_POWER_OFF, "POWEROFF") != 0 ||
+                   gpio_direction_output(DNS323C_GPIO_POWER_OFF, 0) != 0)
+                       pr_err("DNS-323: failed to setup power-off GPIO\n");
+               pm_power_off = dns323c_power_off;
+
+               /* Now, -this- should theorically be done by the sata_mv driver
+                * once I figure out what's going on there. Maybe the behaviour
+                * of the LEDs should be somewhat passed via the platform_data.
+                * for now, just whack the register and make the LEDs happy
+                *
+                * Note: AFAIK, rev B1 needs the same treatement but I'll let
+                * somebody else test it.
+                */
+               writel(0x5, ORION5X_SATA_VIRT_BASE | 0x2c);
+               break;
+       }
 }
 
 /* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */

diff --git a/arch/arm/mach-orion5x/include/mach/system.h b/arch/arm/mach-orion5x/include/mach/system.h
index 60e734c104584c3765268b310c18e6df37b84937..a1d6e46ab0355fd5e6410ff4449bbcca28427d81 100644 (file)
--- a/arch/arm/mach-orion5x/include/mach/system.h
+++ b/arch/arm/mach-orion5x/include/mach/system.h
@@ -25,6 +25,8 @@ static inline void arch_reset(char mode, const char *cmd)
         */
        orion5x_setbits(RSTOUTn_MASK, (1 << 2));
        orion5x_setbits(CPU_SOFT_RESET, 1);
+       mdelay(200);
+       orion5x_clrbits(CPU_SOFT_RESET, 1);
 }
 
 

diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c
index 161fc2d6120705b2f4737c5f1980b7631fd089a5..0f3130599770f2a7008d2de009ea09266620e708 100644 (file)
--- a/arch/arm/mach-pxa/cm-x2xx-pci.c
+++ b/arch/arm/mach-pxa/cm-x2xx-pci.c
@@ -35,7 +35,7 @@ static int cmx2xx_it8152_irq_gpio;
  * This is really ugly and we need a better way of specifying
  * DMA-capable regions of memory.
  */
-void __init cmx2xx_pci_adjust_zones(int node, unsigned long *zone_size,
+void __init cmx2xx_pci_adjust_zones(unsigned long *zone_size,
        unsigned long *zhole_size)
 {
        unsigned int sz = SZ_64M >> PAGE_SHIFT;
@@ -46,7 +46,7 @@ void __init cmx2xx_pci_adjust_zones(int node, unsigned long *zone_size,
                /*
                 * Only adjust if > 64M on current system
                 */
-               if (node || (zone_size[0] <= sz))
+               if (zone_size[0] <= sz)
                        return;
 
                zone_size[1] = zone_size[0] - sz;

diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 51ffa6afb67530e5cde74659319584ac52646593..461ba4080155414d6e64b8d0f61f4dcee49a24fa 100644 (file)
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -715,7 +715,6 @@ static void __init fixup_corgi(struct machine_desc *desc,
        sharpsl_save_param();
        mi->nr_banks=1;
        mi->bank[0].start = 0xa0000000;
-       mi->bank[0].node = 0;
        if (machine_is_corgi())
                mi->bank[0].size = (32*1024*1024);
        else

diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index 96ed13081639598335309b23b992751d27102ea5..a0ab3082a0009d31b3837f1234f6f4175cde6a8b 100644 (file)
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -34,7 +34,6 @@ void __init eseries_fixup(struct machine_desc *desc,
 {
        mi->nr_banks=1;
        mi->bank[0].start = 0xa0000000;
-       mi->bank[0].node = 0;
        if (machine_is_e800())
                mi->bank[0].size = (128*1024*1024);
        else

diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index 890fb90a672f5e957af6f9d75f78425f4d371fd5..c6305c5b8a72c1497ee05aee42d7795b07513c94 100644 (file)
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -26,8 +26,7 @@ extern unsigned int get_clk_frequency_khz(int info);
 
 #define SET_BANK(__nr,__start,__size) \
        mi->bank[__nr].start = (__start), \
-       mi->bank[__nr].size = (__size), \
-       mi->bank[__nr].node = (((unsigned)(__start) - PHYS_OFFSET) >> 27)
+       mi->bank[__nr].size = (__size)
 
 #define ARRAY_AND_SIZE(x)      (x), ARRAY_SIZE(x)
 

diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h
index f626730ee42e11a8071149677b43f55fb85666a7..92361a66b223d9f62243074d26ee534a131cba64 100644 (file)
--- a/arch/arm/mach-pxa/include/mach/memory.h
+++ b/arch/arm/mach-pxa/include/mach/memory.h
@@ -17,24 +17,11 @@
  */
 #define PHYS_OFFSET    UL(0xa0000000)
 
-/*
- * The nodes are matched with the physical SDRAM banks as follows:
- *
- *     node 0:  0xa0000000-0xa3ffffff  -->  0xc0000000-0xc3ffffff
- *     node 1:  0xa4000000-0xa7ffffff  -->  0xc4000000-0xc7ffffff
- *     node 2:  0xa8000000-0xabffffff  -->  0xc8000000-0xcbffffff
- *     node 3:  0xac000000-0xafffffff  -->  0xcc000000-0xcfffffff
- *
- * This needs a node mem size of 26 bits.
- */
-#define NODE_MEM_SIZE_BITS     26
-
 #if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
-void cmx2xx_pci_adjust_zones(int node, unsigned long *size,
-                            unsigned long *holes);
+void cmx2xx_pci_adjust_zones(unsigned long *size, unsigned long *holes);
 
-#define arch_adjust_zones(node, size, holes) \
-       cmx2xx_pci_adjust_zones(node, size, holes)
+#define arch_adjust_zones(size, holes) \
+       cmx2xx_pci_adjust_zones(size, holes)
 
 #define ISA_DMA_THRESHOLD      (PHYS_OFFSET + SZ_64M - 1)
 #define MAX_DMA_ADDRESS                (PAGE_OFFSET + SZ_64M)

diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
index 5305a3993e694b77666920db5e1581a1abb503fc..5e92d84fe50d0805be94a07f583c40ee46f0e6c4 100644 (file)
--- a/arch/arm/mach-pxa/palmt5.c
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -21,6 +21,7 @@
 #include <linux/irq.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
+#include <linux/memblock.h>
 #include <linux/pda_power.h>
 #include <linux/pwm_backlight.h>
 #include <linux/gpio.h>
@@ -396,6 +397,11 @@ static void __init palmt5_udc_init(void)
        }
 }
 
+static void __init palmt5_reserve(void)
+{
+       memblock_reserve(0xa0200000, 0x1000);
+}
+
 static void __init palmt5_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(palmt5_pin_config));
@@ -421,6 +427,7 @@ MACHINE_START(PALMT5, "Palm Tungsten|T5")
        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
        .boot_params    = 0xa0000100,
        .map_io         = pxa_map_io,
+       .reserve        = palmt5_reserve,
        .init_irq       = pxa27x_init_irq,
        .timer          = &pxa_timer,
        .init_machine   = palmt5_init

diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c
index d8b4469607a1e1794a1775238bddd8c478e99e4a..3d0c9cc2a40648a049a3ccc81a34c5f03f4126de 100644 (file)
--- a/arch/arm/mach-pxa/palmtreo.c
+++ b/arch/arm/mach-pxa/palmtreo.c
@@ -20,6 +20,7 @@
 #include <linux/irq.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
+#include <linux/memblock.h>
 #include <linux/pda_power.h>
 #include <linux/pwm_backlight.h>
 #include <linux/gpio.h>
@@ -633,6 +634,12 @@ static void __init treo_lcd_power_init(void)
        treo_lcd_screen.pxafb_lcd_power = treo_lcd_power;
 }
 
+static void __init treo_reserve(void)
+{
+       memblock_reserve(0xa0000000, 0x1000);
+       memblock_reserve(0xa2000000, 0x1000);
+}
+
 static void __init treo_init(void)
 {
        pxa_set_ffuart_info(NULL);
@@ -668,6 +675,7 @@ MACHINE_START(TREO680, "Palm Treo 680")
        .io_pg_offst    = io_p2v(0x40000000),
        .boot_params    = 0xa0000100,
        .map_io         = pxa_map_io,
+       .reserve        = treo_reserve,
        .init_irq       = pxa27x_init_irq,
        .timer          = &pxa_timer,
        .init_machine   = treo680_init,
@@ -691,6 +699,7 @@ MACHINE_START(CENTRO, "Palm Centro 685")
        .io_pg_offst    = io_p2v(0x40000000),
        .boot_params    = 0xa0000100,
        .map_io         = pxa_map_io,
+       .reserve        = treo_reserve,
        .init_irq       = pxa27x_init_irq,
        .timer          = &pxa_timer,
        .init_machine   = centro_init,

diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index f4abdaafdac4d5c552bd7aa72421b8f8bd97a263..bc2758b54446fc5cc38db451fc70a9ed77d0511a 100644 (file)
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -463,7 +463,6 @@ static void __init fixup_poodle(struct machine_desc *desc,
        sharpsl_save_param();
        mi->nr_banks=1;
        mi->bank[0].start = 0xa0000000;
-       mi->bank[0].node = 0;
        mi->bank[0].size = (32*1024*1024);
 }
 

diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index c1048a35f187e990984a83111110671241ff1f93..51756c723557e8c25eee690aa57e252a1aa08376 100644 (file)
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -847,7 +847,6 @@ static void __init fixup_spitz(struct machine_desc *desc,
        sharpsl_save_param();
        mi->nr_banks = 1;
        mi->bank[0].start = 0xa0000000;
-       mi->bank[0].node = 0;
        mi->bank[0].size = (64*1024*1024);
 }
 

diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 7512b822c6cac0f1b0473a7ec029a66a45b33030..83cc3a18c2e9a0ded180a0b223f29167b3a290f7 100644 (file)
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -948,7 +948,6 @@ static void __init fixup_tosa(struct machine_desc *desc,
        sharpsl_save_param();
        mi->nr_banks=1;
        mi->bank[0].start = 0xa0000000;
-       mi->bank[0].node = 0;
        mi->bank[0].size = (64*1024*1024);
 }
 

diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 02e9fdeb8faf26891bdf43cb5846ae717fb720ea..2fa38df284140e08099739d55305a93e7899ebe3 100644 (file)
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -61,12 +61,11 @@ void __iomem *gic_cpu_base_addr;
 /*
  * Adjust the zones if there are restrictions for DMA access.
  */
-void __init realview_adjust_zones(int node, unsigned long *size,
-                                 unsigned long *hole)
+void __init realview_adjust_zones(unsigned long *size, unsigned long *hole)
 {
        unsigned long dma_size = SZ_256M >> PAGE_SHIFT;
 
-       if (!machine_is_realview_pbx() || node || (size[0] <= dma_size))
+       if (!machine_is_realview_pbx() || size[0] <= dma_size)
                return;
 
        size[ZONE_NORMAL] = size[0] - dma_size;
@@ -232,6 +231,21 @@ static unsigned int realview_mmc_status(struct device *dev)
        struct amba_device *adev = container_of(dev, struct amba_device, dev);
        u32 mask;
 
+       if (machine_is_realview_pb1176()) {
+               static bool inserted = false;
+
+               /*
+                * The PB1176 does not have the status register,
+                * assume it is inserted at startup, then invert
+                * for each call so card insertion/removal will
+                * be detected anyway. This will not be called if
+                * GPIO on PL061 is active, which is the proper
+                * way to do this on the PB1176.
+                */
+               inserted = !inserted;
+               return inserted ? 0 : 1;
+       }
+
        if (adev->res.start == REALVIEW_MMCI0_BASE)
                mask = 1;
        else
@@ -300,8 +314,13 @@ static struct clk ref24_clk = {
        .rate   = 24000000,
 };
 
+static struct clk dummy_apb_pclk;
+
 static struct clk_lookup lookups[] = {
-       {       /* UART0 */
+       {       /* Bus clock */
+               .con_id         = "apb_pclk",
+               .clk            = &dummy_apb_pclk,
+       }, {    /* UART0 */
                .dev_id         = "dev:uart0",
                .clk            = &ref24_clk,
        }, {    /* UART1 */
@@ -313,6 +332,12 @@ static struct clk_lookup lookups[] = {
        }, {    /* UART3 */
                .dev_id         = "fpga:uart3",
                .clk            = &ref24_clk,
+       }, {    /* UART3 is on the dev chip in PB1176 */
+               .dev_id         = "dev:uart3",
+               .clk            = &ref24_clk,
+       }, {    /* UART4 only exists in PB1176 */
+               .dev_id         = "fpga:uart4",
+               .clk            = &ref24_clk,
        }, {    /* KMI0 */
                .dev_id         = "fpga:kmi0",
                .clk            = &ref24_clk,
@@ -322,12 +347,15 @@ static struct clk_lookup lookups[] = {
        }, {    /* MMC0 */
                .dev_id         = "fpga:mmc0",
                .clk            = &ref24_clk,
-       }, {    /* EB:CLCD */
+       }, {    /* CLCD is in the PB1176 and EB DevChip */
                .dev_id         = "dev:clcd",
                .clk            = &oscvco_clk,
        }, {    /* PB:CLCD */
                .dev_id         = "issp:clcd",
                .clk            = &oscvco_clk,
+       }, {    /* SSP */
+               .dev_id         = "dev:ssp0",
+               .clk            = &ref24_clk,
        }
 };
 
@@ -342,7 +370,7 @@ static int __init clk_init(void)
 
        return 0;
 }
-arch_initcall(clk_init);
+core_initcall(clk_init);
 
 /*
  * CLCD support.

diff --git a/arch/arm/mach-realview/include/mach/board-pb1176.h b/arch/arm/mach-realview/include/mach/board-pb1176.h
index 2f5ccb298858def61458ed544fdac81383718982..002ab5d8c11c31705ce2f419b16a0fa9b23ccfa8 100644 (file)
--- a/arch/arm/mach-realview/include/mach/board-pb1176.h
+++ b/arch/arm/mach-realview/include/mach/board-pb1176.h
@@ -26,6 +26,7 @@
 /*
  * Peripheral addresses
  */
+#define REALVIEW_PB1176_UART4_BASE             0x10009000 /* UART 4 */
 #define REALVIEW_PB1176_SCTL_BASE              0x10100000 /* System controller */
 #define REALVIEW_PB1176_SMC_BASE               0x10111000 /* SMC */
 #define REALVIEW_PB1176_DMC_BASE               0x10109000 /* DMC configuration */

diff --git a/arch/arm/mach-realview/include/mach/irqs-pb1176.h b/arch/arm/mach-realview/include/mach/irqs-pb1176.h
index 830055bb86289860626fd5cbbfb08a3c64bfe04e..5c3c625e3e04f3b84db19f25a3c1c849f3833a5b 100644 (file)
--- a/arch/arm/mach-realview/include/mach/irqs-pb1176.h
+++ b/arch/arm/mach-realview/include/mach/irqs-pb1176.h
@@ -40,6 +40,7 @@
 #define IRQ_DC1176_L2CC                (IRQ_DC1176_GIC_START + 13)
 #define IRQ_DC1176_RTC         (IRQ_DC1176_GIC_START + 14)
 #define IRQ_DC1176_CLCD                (IRQ_DC1176_GIC_START + 15)     /* CLCD controller */
+#define IRQ_DC1176_SSP         (IRQ_DC1176_GIC_START + 17)     /* SSP port */
 #define IRQ_DC1176_UART0       (IRQ_DC1176_GIC_START + 18)     /* UART 0 on development chip */
 #define IRQ_DC1176_UART1       (IRQ_DC1176_GIC_START + 19)     /* UART 1 on development chip */
 #define IRQ_DC1176_UART2       (IRQ_DC1176_GIC_START + 20)     /* UART 2 on development chip */
@@ -73,7 +74,6 @@
 #define IRQ_PB1176_RTC         (IRQ_PB1176_GIC_START + 25)     /* Real Time Clock */
 
 #define IRQ_PB1176_GPIO0       -1
-#define IRQ_PB1176_SSP         -1
 #define IRQ_PB1176_SCTL                -1
 
 #define NR_GIC_PB1176          2

diff --git a/arch/arm/mach-realview/include/mach/memory.h b/arch/arm/mach-realview/include/mach/memory.h
index 2417bbcf97fd267ff236c09f31d71ef86ad2a047..5dafc157b276207f91837923cd2efd51762820cd 100644 (file)
--- a/arch/arm/mach-realview/include/mach/memory.h
+++ b/arch/arm/mach-realview/include/mach/memory.h
@@ -30,10 +30,9 @@
 #endif
 
 #if !defined(__ASSEMBLY__) && defined(CONFIG_ZONE_DMA)
-extern void realview_adjust_zones(int node, unsigned long *size,
-                                 unsigned long *hole);
-#define arch_adjust_zones(node, size, hole) \
-       realview_adjust_zones(node, size, hole)
+extern void realview_adjust_zones(unsigned long *size, unsigned long *hole);
+#define arch_adjust_zones(size, hole) \
+       realview_adjust_zones(size, hole)
 
 #define ISA_DMA_THRESHOLD      (PHYS_OFFSET + SZ_256M - 1)
 #define MAX_DMA_ADDRESS                (PAGE_OFFSET + SZ_256M)

diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 4425018fab828c864e662dfb4bfd5db369a76a15..991c1f8390e2a8eccfbbfae39ccab3768a7badbe 100644 (file)
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -25,6 +25,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
+#include <linux/amba/pl022.h>
 #include <linux/io.h>
 
 #include <mach/hardware.h>
@@ -129,6 +130,12 @@ static struct pl061_platform_data gpio2_plat_data = {
        .irq_base       = -1,
 };
 
+static struct pl022_ssp_controller ssp0_plat_data = {
+       .bus_id = 0,
+       .enable_dma = 0,
+       .num_chipselect = 1,
+};
+
 /*
  * RealView EB AMBA devices
  */
@@ -213,7 +220,7 @@ AMBA_DEVICE(sci0,  "dev:sci0",  SCI,      NULL);
 AMBA_DEVICE(uart0, "dev:uart0", EB_UART0, NULL);
 AMBA_DEVICE(uart1, "dev:uart1", EB_UART1, NULL);
 AMBA_DEVICE(uart2, "dev:uart2", EB_UART2, NULL);
-AMBA_DEVICE(ssp0,  "dev:ssp0",  EB_SSP,   NULL);
+AMBA_DEVICE(ssp0,  "dev:ssp0",  EB_SSP,   &ssp0_plat_data);
 
 static struct amba_device *amba_devs[] __initdata = {
        &dmac_device,
@@ -324,6 +331,26 @@ static struct platform_device pmu_device = {
        .resource               = pmu_resources,
 };
 
+static struct resource char_lcd_resources[] = {
+       {
+               .start = REALVIEW_CHAR_LCD_BASE,
+               .end   = (REALVIEW_CHAR_LCD_BASE + SZ_4K - 1),
+               .flags = IORESOURCE_MEM,
+       },
+       {
+               .start  = IRQ_EB_CHARLCD,
+               .end    = IRQ_EB_CHARLCD,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device char_lcd_device = {
+       .name           =       "arm-charlcd",
+       .id             =       -1,
+       .num_resources  =       ARRAY_SIZE(char_lcd_resources),
+       .resource       =       char_lcd_resources,
+};
+
 static void __init gic_init_irq(void)
 {
        if (core_tile_eb11mp() || core_tile_a9mp()) {
@@ -442,6 +469,7 @@ static void __init realview_eb_init(void)
 
        realview_flash_register(&realview_eb_flash_resource, 1);
        platform_device_register(&realview_i2c_device);
+       platform_device_register(&char_lcd_device);
        eth_device_register();
        realview_usb_register(realview_eb_isp1761_resources);
 

diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index 099a1f125cf8f6c10b1720ccdcee7623ff5a73ad..d2be12eb829eb3b759be8a37bc8020df9f01d253 100644 (file)
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -25,6 +25,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
+#include <linux/amba/pl022.h>
 #include <linux/io.h>
 
 #include <mach/hardware.h>
@@ -123,6 +124,12 @@ static struct pl061_platform_data gpio2_plat_data = {
        .irq_base       = -1,
 };
 
+static struct pl022_ssp_controller ssp0_plat_data = {
+       .bus_id = 0,
+       .enable_dma = 0,
+       .num_chipselect = 1,
+};
+
 /*
  * RealView PB1176 AMBA devices
  */
@@ -144,8 +151,6 @@ static struct pl061_platform_data gpio2_plat_data = {
 #define MPMC_DMA       { 0, 0 }
 #define PB1176_CLCD_IRQ        { IRQ_DC1176_CLCD, NO_IRQ }
 #define PB1176_CLCD_DMA        { 0, 0 }
-#define DMAC_IRQ       { IRQ_PB1176_DMAC, NO_IRQ }
-#define DMAC_DMA       { 0, 0 }
 #define SCTL_IRQ       { NO_IRQ, NO_IRQ }
 #define SCTL_DMA       { 0, 0 }
 #define PB1176_WATCHDOG_IRQ    { IRQ_DC1176_WATCHDOG, NO_IRQ }
@@ -166,7 +171,9 @@ static struct pl061_platform_data gpio2_plat_data = {
 #define PB1176_UART2_DMA       { 11, 10 }
 #define PB1176_UART3_IRQ       { IRQ_DC1176_UART3, NO_IRQ }
 #define PB1176_UART3_DMA       { 0x86, 0x87 }
-#define PB1176_SSP_IRQ         { IRQ_PB1176_SSP, NO_IRQ }
+#define PB1176_UART4_IRQ       { IRQ_PB1176_UART4, NO_IRQ }
+#define PB1176_UART4_DMA       { 0, 0 }
+#define PB1176_SSP_IRQ         { IRQ_DC1176_SSP, NO_IRQ }
 #define PB1176_SSP_DMA         { 9, 8 }
 
 /* FPGA Primecells */
@@ -174,7 +181,7 @@ AMBA_DEVICE(aaci,   "fpga:aaci",    AACI,           NULL);
 AMBA_DEVICE(mmc0,      "fpga:mmc0",    MMCI0,          &realview_mmc0_plat_data);
 AMBA_DEVICE(kmi0,      "fpga:kmi0",    KMI0,           NULL);
 AMBA_DEVICE(kmi1,      "fpga:kmi1",    KMI1,           NULL);
-AMBA_DEVICE(uart3,     "fpga:uart3",   PB1176_UART3,   NULL);
+AMBA_DEVICE(uart4,     "fpga:uart4",   PB1176_UART4,   NULL);
 
 /* DevChip Primecells */
 AMBA_DEVICE(smc,       "dev:smc",      PB1176_SMC,     NULL);
@@ -188,18 +195,16 @@ AMBA_DEVICE(sci0, "dev:sci0",     SCI,            NULL);
 AMBA_DEVICE(uart0,     "dev:uart0",    PB1176_UART0,   NULL);
 AMBA_DEVICE(uart1,     "dev:uart1",    PB1176_UART1,   NULL);
 AMBA_DEVICE(uart2,     "dev:uart2",    PB1176_UART2,   NULL);
-AMBA_DEVICE(ssp0,      "dev:ssp0",     PB1176_SSP,     NULL);
-
-/* Primecells on the NEC ISSP chip */
-AMBA_DEVICE(clcd,      "issp:clcd",    PB1176_CLCD,    &clcd_plat_data);
-//AMBA_DEVICE(dmac,    "issp:dmac",    PB1176_DMAC,    NULL);
+AMBA_DEVICE(uart3,     "dev:uart3",    PB1176_UART3,   NULL);
+AMBA_DEVICE(ssp0,      "dev:ssp0",     PB1176_SSP,     &ssp0_plat_data);
+AMBA_DEVICE(clcd,      "dev:clcd",     PB1176_CLCD,    &clcd_plat_data);
 
 static struct amba_device *amba_devs[] __initdata = {
-//     &dmac_device,
        &uart0_device,
        &uart1_device,
        &uart2_device,
        &uart3_device,
+       &uart4_device,
        &smc_device,
        &clcd_device,
        &sctl_device,
@@ -276,6 +281,26 @@ static struct platform_device pmu_device = {
        .resource               = &pmu_resource,
 };
 
+static struct resource char_lcd_resources[] = {
+       {
+               .start = REALVIEW_CHAR_LCD_BASE,
+               .end   = (REALVIEW_CHAR_LCD_BASE + SZ_4K - 1),
+               .flags = IORESOURCE_MEM,
+       },
+       {
+               .start  = IRQ_PB1176_CHARLCD,
+               .end    = IRQ_PB1176_CHARLCD,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device char_lcd_device = {
+       .name           =       "arm-charlcd",
+       .id             =       -1,
+       .num_resources  =       ARRAY_SIZE(char_lcd_resources),
+       .resource       =       char_lcd_resources,
+};
+
 static void __init gic_init_irq(void)
 {
        /* ARM1176 DevChip GIC, primary */
@@ -338,6 +363,7 @@ static void __init realview_pb1176_init(void)
        platform_device_register(&realview_i2c_device);
        realview_usb_register(realview_pb1176_isp1761_resources);
        platform_device_register(&pmu_device);
+       platform_device_register(&char_lcd_device);
 
        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
                struct amba_device *d = amba_devs[i];

diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index 0e07a5ccb75f56de33bec477f242d93d88bca448..d591bc00b86ec74147b0ff0b8c7bb85e99d52041 100644 (file)
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -25,6 +25,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
+#include <linux/amba/pl022.h>
 #include <linux/io.h>
 
 #include <mach/hardware.h>
@@ -124,6 +125,12 @@ static struct pl061_platform_data gpio2_plat_data = {
        .irq_base       = -1,
 };
 
+static struct pl022_ssp_controller ssp0_plat_data = {
+       .bus_id = 0,
+       .enable_dma = 0,
+       .num_chipselect = 1,
+};
+
 /*
  * RealView PB11MPCore AMBA devices
  */
@@ -190,7 +197,7 @@ AMBA_DEVICE(sci0,   "dev:sci0",     SCI,            NULL);
 AMBA_DEVICE(uart0,     "dev:uart0",    PB11MP_UART0,   NULL);
 AMBA_DEVICE(uart1,     "dev:uart1",    PB11MP_UART1,   NULL);
 AMBA_DEVICE(uart2,     "dev:uart2",    PB11MP_UART2,   NULL);
-AMBA_DEVICE(ssp0,      "dev:ssp0",     PB11MP_SSP,     NULL);
+AMBA_DEVICE(ssp0,      "dev:ssp0",     PB11MP_SSP,     &ssp0_plat_data);
 
 /* Primecells on the NEC ISSP chip */
 AMBA_DEVICE(clcd,      "issp:clcd",    PB11MP_CLCD,    &clcd_plat_data);

diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index ac2f06f1ca500e9bd26603b21ba6c6badf046e11..6c37621217bc916fba02af26a8d3163c4b1d4aec 100644 (file)
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -25,6 +25,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
+#include <linux/amba/pl022.h>
 #include <linux/io.h>
 
 #include <asm/irq.h>
@@ -114,6 +115,12 @@ static struct pl061_platform_data gpio2_plat_data = {
        .irq_base       = -1,
 };
 
+static struct pl022_ssp_controller ssp0_plat_data = {
+       .bus_id = 0,
+       .enable_dma = 0,
+       .num_chipselect = 1,
+};
+
 /*
  * RealView PBA8Core AMBA devices
  */
@@ -180,7 +187,7 @@ AMBA_DEVICE(sci0,   "dev:sci0",     SCI,            NULL);
 AMBA_DEVICE(uart0,     "dev:uart0",    PBA8_UART0,     NULL);
 AMBA_DEVICE(uart1,     "dev:uart1",    PBA8_UART1,     NULL);
 AMBA_DEVICE(uart2,     "dev:uart2",    PBA8_UART2,     NULL);
-AMBA_DEVICE(ssp0,      "dev:ssp0",     PBA8_SSP,       NULL);
+AMBA_DEVICE(ssp0,      "dev:ssp0",     PBA8_SSP,       &ssp0_plat_data);
 
 /* Primecells on the NEC ISSP chip */
 AMBA_DEVICE(clcd,      "issp:clcd",    PBA8_CLCD,      &clcd_plat_data);

diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 08fd683adc4ced929eb255fd8da2e3b733850a87..9428eff0b116addda238d99d492cbe9d80c6b8a5 100644 (file)
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -24,6 +24,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
+#include <linux/amba/pl022.h>
 #include <linux/io.h>
 
 #include <asm/irq.h>
@@ -136,6 +137,12 @@ static struct pl061_platform_data gpio2_plat_data = {
        .irq_base       = -1,
 };
 
+static struct pl022_ssp_controller ssp0_plat_data = {
+       .bus_id = 0,
+       .enable_dma = 0,
+       .num_chipselect = 1,
+};
+
 /*
  * RealView PBXCore AMBA devices
  */
@@ -202,7 +209,7 @@ AMBA_DEVICE(sci0,   "dev:sci0",     SCI,            NULL);
 AMBA_DEVICE(uart0,     "dev:uart0",    PBX_UART0,      NULL);
 AMBA_DEVICE(uart1,     "dev:uart1",    PBX_UART1,      NULL);
 AMBA_DEVICE(uart2,     "dev:uart2",    PBX_UART2,      NULL);
-AMBA_DEVICE(ssp0,      "dev:ssp0",     PBX_SSP,        NULL);
+AMBA_DEVICE(ssp0,      "dev:ssp0",     PBX_SSP,        &ssp0_plat_data);
 
 /* Primecells on the NEC ISSP chip */
 AMBA_DEVICE(clcd,      "issp:clcd",    PBX_CLCD,       &clcd_plat_data);

diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 779b45b3f80fdca1f6815782eef8b8dfa81b4841..3ba3bab139d0917ce45feaeb079573428f8a2af2 100644 (file)
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -15,6 +15,7 @@
 #include <linux/types.h>
 #include <linux/interrupt.h>
 #include <linux/list.h>
+#include <linux/memblock.h>
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/sysdev.h>
@@ -304,6 +305,13 @@ static void __init h1940_map_io(void)
        s3c_pm_init();
 }
 
+/* H1940 and RX3715 need to reserve this for suspend */
+static void __init h1940_reserve(void)
+{
+       memblock_reserve(0x30003000, 0x1000);
+       memblock_reserve(0x30081000, 0x1000);
+}
+
 static void __init h1940_init_irq(void)
 {
        s3c24xx_init_irq();
@@ -346,6 +354,7 @@ MACHINE_START(H1940, "IPAQ-H1940")
        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
        .boot_params    = S3C2410_SDRAM_PA + 0x100,
        .map_io         = h1940_map_io,
+       .reserve        = h1940_reserve,
        .init_irq       = h1940_init_irq,
        .init_machine   = h1940_init,
        .timer          = &s3c24xx_timer,

diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
index ba93a356a83998a2b6e0ab2dfc83be7945321345..054c9f92232aa676dad11c0b86359ad21ef47fa6 100644 (file)
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -119,7 +119,6 @@ static void __init smdk2413_fixup(struct machine_desc *desc,
                mi->nr_banks=1;
                mi->bank[0].start = 0x30000000;
                mi->bank[0].size = SZ_64M;
-               mi->bank[0].node = 0;
        }
 }
 

diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c
index 3ca9265b699716f518d6d5b9e28f4e6f3c9e3d53..f291ac25d31252a8882bc632434a2c03f71e0361 100644 (file)
--- a/arch/arm/mach-s3c2412/mach-vstms.c
+++ b/arch/arm/mach-s3c2412/mach-vstms.c
@@ -137,7 +137,6 @@ static void __init vstms_fixup(struct machine_desc *desc,
                mi->nr_banks=1;
                mi->bank[0].start = 0x30000000;
                mi->bank[0].size = SZ_64M;
-               mi->bank[0].node = 0;
        }
 }
 

diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c
index 8603b577a24b7673703db6992e2a4e3d7549e8c6..142d1f92117651e60fdad7e55fcc52997e430962 100644 (file)
--- a/arch/arm/mach-s3c2440/mach-rx1950.c
+++ b/arch/arm/mach-s3c2440/mach-rx1950.c
@@ -15,6 +15,7 @@
 #include <linux/types.h>
 #include <linux/interrupt.h>
 #include <linux/list.h>
+#include <linux/memblock.h>
 #include <linux/delay.h>
 #include <linux/timer.h>
 #include <linux/init.h>
@@ -570,12 +571,20 @@ static void __init rx1950_init_machine(void)
        platform_add_devices(rx1950_devices, ARRAY_SIZE(rx1950_devices));
 }
 
+/* H1940 and RX3715 need to reserve this for suspend */
+static void __init rx1950_reserve(void)
+{
+       memblock_reserve(0x30003000, 0x1000);
+       memblock_reserve(0x30081000, 0x1000);
+}
+
 MACHINE_START(RX1950, "HP iPAQ RX1950")
     /* Maintainers: Vasily Khoruzhick */
     .phys_io = S3C2410_PA_UART,
        .io_pg_offst = (((u32) S3C24XX_VA_UART) >> 18) & 0xfffc,
        .boot_params = S3C2410_SDRAM_PA + 0x100,
        .map_io = rx1950_map_io,
+       .reserve        = rx1950_reserve,
        .init_irq = s3c24xx_init_irq,
        .init_machine = rx1950_init_machine,
        .timer = &s3c24xx_timer,

diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index d2946de3f3659d3e2588cc980a727973b9716062..6bb44f75a9ce65094a35c1bdad78775c1c655eee 100644 (file)
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -15,6 +15,7 @@
 #include <linux/types.h>
 #include <linux/interrupt.h>
 #include <linux/list.h>
+#include <linux/memblock.h>
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/tty.h>
@@ -191,6 +192,13 @@ static void __init rx3715_map_io(void)
        s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
 }
 
+/* H1940 and RX3715 need to reserve this for suspend */
+static void __init rx3715_reserve(void)
+{
+       memblock_reserve(0x30003000, 0x1000);
+       memblock_reserve(0x30081000, 0x1000);
+}
+
 static void __init rx3715_init_irq(void)
 {
        s3c24xx_init_irq();
@@ -214,6 +222,7 @@ MACHINE_START(RX3715, "IPAQ-RX3715")
        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
        .boot_params    = S3C2410_SDRAM_PA + 0x100,
        .map_io         = rx3715_map_io,
+       .reserve        = rx3715_reserve,
        .init_irq       = rx3715_init_irq,
        .init_machine   = rx3715_init_machine,
        .timer          = &s3c24xx_timer,

diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h
index ec03f187c52bcef3e1cf28145b373016b7e66e2d..b7a9a601c2d1e18a407c6110976812e35ebf93a3 100644 (file)
--- a/arch/arm/mach-sa1100/generic.h
+++ b/arch/arm/mach-sa1100/generic.h
@@ -13,8 +13,7 @@ extern void __init sa1100_init_gpio(void);
 
 #define SET_BANK(__nr,__start,__size) \
        mi->bank[__nr].start = (__start), \
-       mi->bank[__nr].size = (__size), \
-       mi->bank[__nr].node = (((unsigned)(__start) - PHYS_OFFSET) >> 27)
+       mi->bank[__nr].size = (__size)
 
 extern void (*sa1100fb_backlight_power)(int on);
 extern void (*sa1100fb_lcd_power)(int on);

diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h
index d5277f9bee77d8dc7a98b2acb60d494e5fcc9df1..128a1dfa96b9b4ae9f64286f5b11df60c2297d79 100644 (file)
--- a/arch/arm/mach-sa1100/include/mach/memory.h
+++ b/arch/arm/mach-sa1100/include/mach/memory.h
@@ -17,10 +17,10 @@
 #ifndef __ASSEMBLY__
 
 #ifdef CONFIG_SA1111
-void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes);
+void sa1111_adjust_zones(unsigned long *size, unsigned long *holes);
 
-#define arch_adjust_zones(node, size, holes) \
-       sa1111_adjust_zones(node, size, holes)
+#define arch_adjust_zones(size, holes) \
+       sa1111_adjust_zones(size, holes)
 
 #define ISA_DMA_THRESHOLD      (PHYS_OFFSET + SZ_1M - 1)
 #define MAX_DMA_ADDRESS                (PAGE_OFFSET + SZ_1M)

diff --git a/arch/arm/mach-shark/include/mach/memory.h b/arch/arm/mach-shark/include/mach/memory.h
index 3053e5b7f1685290eccc1c44a9b011c030ffd741..d9c4812f1c316c69ab650a44cd513948410320ce 100644 (file)
--- a/arch/arm/mach-shark/include/mach/memory.h
+++ b/arch/arm/mach-shark/include/mach/memory.h
@@ -19,9 +19,8 @@
 
 #ifndef __ASSEMBLY__
 
-static inline void __arch_adjust_zones(int node, unsigned long *zone_size, unsigned long *zhole_size) 
+static inline void __arch_adjust_zones(unsigned long *zone_size, unsigned long *zhole_size)
 {
-  if (node != 0) return;
   /* Only the first 4 MB (=1024 Pages) are usable for DMA */
   /* See dev / -> .properties in OpenFirmware. */
   zone_size[1] = zone_size[0] - 1024;
@@ -30,8 +29,8 @@ static inline void __arch_adjust_zones(int node, unsigned long *zone_size, unsig
   zhole_size[0] = 0;
 }
 
-#define arch_adjust_zones(node, size, holes) \
-       __arch_adjust_zones(node, size, holes)
+#define arch_adjust_zones(size, holes) \
+       __arch_adjust_zones(size, holes)
 
 #define ISA_DMA_THRESHOLD      (PHYS_OFFSET + SZ_4M - 1)
 #define MAX_DMA_ADDRESS                (PAGE_OFFSET + SZ_4M)

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index f2b88c5fe142841e718928a0bd787dc6185032c3..4c704b4e8b340c9a6482e2c3ec87da15029c67a8 100644 (file)
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -70,6 +70,18 @@ endmenu
 
 menu "Timer and clock configuration"
 
+config SHMOBILE_TIMER_HZ
+       int "Kernel HZ (jiffies per second)"
+       range 32 1024
+       default "128"
+       help
+         Allows the configuration of the timer frequency. It is customary
+         to have the timer interrupt run at 1000 Hz or 100 Hz, but in the
+         case of low timer frequencies other values may be more suitable.
+         SH-Mobile systems using a 32768 Hz RCLK for clock events may want
+         to select a HZ value such as 128 that can evenly divide RCLK.
+         A HZ value that does not divide evenly may cause timer drift.
+
 config SH_TIMER_CMT
        bool "CMT timer driver"
        default y

diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
index 5179b72e1ee3d04186f2cfba7d675778853735ae..132256bb8c817b1b5ab9aa08cd1af7875b22ca00 100644 (file)
--- a/arch/arm/mach-shmobile/include/mach/irqs.h
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -2,7 +2,6 @@
 #define __ASM_MACH_IRQS_H
 
 #define NR_IRQS         512
-#define NR_IRQS_LEGACY  8
 
 #define evt2irq(evt)           (((evt) >> 5) - 16)
 #define irq2evt(irq)           (((irq) + 16) << 5)

diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 39f6ccf22294d1e8a9c27f90a771a3c0090fa2d5..18febf92f20a10bfe38df87fc75d6c7f23dd9d83 100644 (file)
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -341,8 +341,11 @@ static struct clk gpio_clk = {
        .recalc = &follow_parent,
 };
 
+static struct clk dummy_apb_pclk;
+
 /* array of all spear 3xx clock lookups */
 static struct clk_lookup spear_clk_lookups[] = {
+       { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
        /* root clks */
        { .con_id = "osc_32k_clk",      .clk = &osc_32k_clk},
        { .con_id = "osc_24m_clk",      .clk = &osc_24m_clk},

diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index 13e27c769685018bb82b75b745ca45c56bf6d5d9..36ff056b73219f5b07339ab627558a64eb96adae 100644 (file)
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -428,8 +428,11 @@ static struct clk gpio2_clk = {
        .recalc = &follow_parent,
 };
 
+static struct clk dummy_apb_pclk;
+
 /* array of all spear 6xx clock lookups */
 static struct clk_lookup spear_clk_lookups[] = {
+       { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
        /* root clks */
        { .con_id = "osc_32k_clk",      .clk = &osc_32k_clk},
        { .con_id = "osc_30m_clk",      .clk = &osc_30m_clk},

diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c
index 5af71d5ba6656c648fc724a36b66e6d419389a1d..5d12d547789e3f17ee993c9df7d8e1056486045b 100644 (file)
--- a/arch/arm/mach-u300/clock.c
+++ b/arch/arm/mach-u300/clock.c
@@ -1212,6 +1212,8 @@ static struct clk ppm_clk = {
 };
 #endif
 
+static struct clk dummy_apb_pclk;
+
 #define DEF_LOOKUP(devid, clkref)              \
        {                                       \
        .dev_id = devid,                        \
@@ -1223,6 +1225,10 @@ static struct clk ppm_clk = {
  * look up through clockdevice.
  */
 static struct clk_lookup lookups[] = {
+       {
+               .con_id = "apb_pclk",
+               .clk = &dummy_apb_pclk,
+       },
        /* Connected directly to the AMBA bus */
        DEF_LOOKUP("amba",      &amba_clk),
        DEF_LOOKUP("cpu",       &cpu_clk),

diff --git a/arch/arm/mach-u300/include/mach/memory.h b/arch/arm/mach-u300/include/mach/memory.h
index ab000df7fc0337c7f75ef31deb9bef182ac172f0..bf134bcc129d612cde5362a6971a08360a42b582 100644 (file)
--- a/arch/arm/mach-u300/include/mach/memory.h
+++ b/arch/arm/mach-u300/include/mach/memory.h
@@ -34,14 +34,6 @@
            (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024 + 0x100)
 #endif
 
-/*
- * TCM memory whereabouts
- */
-#define ITCM_OFFSET    0xffff2000
-#define ITCM_END       0xffff3fff
-#define DTCM_OFFSET    0xffff4000
-#define DTCM_END       0xffff5fff
-
 /*
  * We enable a real big DMA buffer if need be.
  */

diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c
index d2a0b8847a18061e36576f5dec89bc567745d473..bfcda9820888b6083fd10779b63fe89580f76036 100644 (file)
--- a/arch/arm/mach-u300/u300.c
+++ b/arch/arm/mach-u300/u300.c
@@ -14,6 +14,7 @@
 #include <linux/sched.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
+#include <linux/memblock.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
@@ -22,6 +23,21 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+static void __init u300_reserve(void)
+{
+       /*
+        * U300 - This platform family can share physical memory
+        * between two ARM cpus, one running Linux and the other
+        * running another OS.
+        */
+#ifdef CONFIG_MACH_U300_SINGLE_RAM
+#if ((CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1) == 1) && \
+       CONFIG_MACH_U300_2MB_ALIGNMENT_FIX
+        memblock_reserve(PHYS_OFFSET, 0x00100000);
+#endif
+#endif
+}
+
 static void __init u300_init_machine(void)
 {
        u300_init_devices();
@@ -49,6 +65,7 @@ MACHINE_START(U300, MACH_U300_STRING)
        .io_pg_offst    = ((U300_AHB_PER_VIRT_BASE) >> 18) & 0xfffc,
        .boot_params    = BOOT_PARAMS_OFFSET,
        .map_io         = u300_map_io,
+       .reserve        = u300_reserve,
        .init_irq       = u300_init_irq,
        .timer          = &u300_timer,
        .init_machine   = u300_init_machine,

diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index bb8d7b771817b774a7ff3406e87d46552cf8391c..0e8fd135a57dee1d56afb200208d62bf7d756fa8 100644 (file)
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -13,19 +13,42 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/gpio.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/pl022.h>
 #include <linux/spi/spi.h>
+#include <linux/mfd/ab8500.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include <plat/pincfg.h>
 #include <plat/i2c.h>
 
 #include <mach/hardware.h>
 #include <mach/setup.h>
 #include <mach/devices.h>
 
+#include "pins-db8500.h"
+
+static pin_cfg_t mop500_pins[] = {
+       /* SSP0 */
+       GPIO143_SSP0_CLK,
+       GPIO144_SSP0_FRM,
+       GPIO145_SSP0_RXD,
+       GPIO146_SSP0_TXD,
+
+       /* I2C */
+       GPIO147_I2C0_SCL,
+       GPIO148_I2C0_SDA,
+       GPIO16_I2C1_SCL,
+       GPIO17_I2C1_SDA,
+       GPIO10_I2C2_SDA,
+       GPIO11_I2C2_SCL,
+       GPIO229_I2C3_SDA,
+       GPIO230_I2C3_SCL,
+};
+
 static void ab4500_spi_cs_control(u32 command)
 {
        /* set the FRM signal, which is CS  - TODO */
@@ -48,15 +71,20 @@ struct pl022_config_chip ab4500_chip_info = {
        .cs_control = ab4500_spi_cs_control,
 };
 
+static struct ab8500_platform_data ab8500_platdata = {
+       .irq_base       = MOP500_AB8500_IRQ_BASE,
+};
+
 static struct spi_board_info u8500_spi_devices[] = {
        {
                .modalias = "ab8500",
                .controller_data = &ab4500_chip_info,
+               .platform_data = &ab8500_platdata,
                .max_speed_hz = 12000000,
                .bus_num = 0,
                .chip_select = 0,
                .mode = SPI_MODE_0,
-               .irq = IRQ_AB4500,
+               .irq = IRQ_DB8500_AB8500,
        },
 };
 
@@ -118,6 +146,10 @@ static void __init u8500_init_machine(void)
 {
        int i;
 
+       u8500_init_devices();
+
+       nmk_config_pins(mop500_pins, ARRAY_SIZE(mop500_pins));
+
        u8500_i2c0_device.dev.platform_data = &u8500_i2c0_data;
        ux500_i2c1_device.dev.platform_data = &u8500_i2c1_data;
        ux500_i2c2_device.dev.platform_data = &u8500_i2c2_data;
@@ -133,8 +165,6 @@ static void __init u8500_init_machine(void)
 
        spi_register_board_info(u8500_spi_devices,
                        ARRAY_SIZE(u8500_spi_devices));
-
-       u8500_init_devices();
 }
 
 MACHINE_START(U8500, "ST-Ericsson MOP500 platform")

diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index 0a1318fc8e2bd6c29774bcf1ab8cc48f6a5cfa0c..d8ab7f184fe439ec2492079a063def04c5e3c690 100644 (file)
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -453,7 +453,11 @@ static DEFINE_PRCC_CLK_CUSTOM(7, mtu0_ed, 2, -1, NULL, clk_mtu_get_rate, 0);
 static DEFINE_PRCC_CLK(7, wdg_ed,      1, -1, NULL);
 static DEFINE_PRCC_CLK(7, cfgreg_ed,   0, -1, NULL);
 
+static struct clk clk_dummy_apb_pclk;
+
 static struct clk_lookup u8500_common_clks[] = {
+       CLK(dummy_apb_pclk, NULL,       "apb_pclk"),
+
        /* Peripheral Cluster #1 */
        CLK(gpio0,      "gpio.0",       NULL),
        CLK(gpio0,      "gpio.1",       NULL),

diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 8229034219432ad1f2090fe99b5da7723992ac22..654fca944e6554cd65eb77fff9c9563a96e58173 100644 (file)
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -65,7 +65,7 @@ struct amba_device u8500_ssp0_device = {
                .end   = U8500_SSP0_BASE + SZ_4K - 1,
                .flags = IORESOURCE_MEM,
        },
-       .irq = {IRQ_SSP0, NO_IRQ },
+       .irq = {IRQ_DB8500_SSP0, NO_IRQ },
        /* ST-Ericsson modified id */
        .periphid = SSP_PER_ID,
 };
@@ -77,8 +77,8 @@ static struct resource u8500_i2c0_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-               .start  = IRQ_I2C0,
-               .end    = IRQ_I2C0,
+               .start  = IRQ_DB8500_I2C0,
+               .end    = IRQ_DB8500_I2C0,
                .flags  = IORESOURCE_IRQ,
        }
 };
@@ -97,8 +97,8 @@ static struct resource u8500_i2c4_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-               .start  = IRQ_I2C4,
-               .end    = IRQ_I2C4,
+               .start  = IRQ_DB8500_I2C4,
+               .end    = IRQ_DB8500_I2C4,
                .flags  = IORESOURCE_IRQ,
        }
 };
@@ -130,8 +130,8 @@ static struct resource dma40_resources[] = {
                .name = "lcla",
        },
        [3] = {
-               .start = IRQ_DMA,
-               .end = IRQ_DMA,
+               .start = IRQ_DB8500_DMA,
+               .end   = IRQ_DB8500_DMA,
                .flags = IORESOURCE_IRQ}
 };
 

diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
new file mode 100644 (file)
index 0000000..cca4f70
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com>
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#ifndef __MACH_IRQS_BOARD_MOP500_H
+#define __MACH_IRQS_BOARD_MOP500_H
+
+#define AB8500_NR_IRQS                 104
+
+#define MOP500_AB8500_IRQ_BASE         IRQ_BOARD_START
+#define MOP500_AB8500_IRQ_END          (MOP500_AB8500_IRQ_BASE \
+                                        + AB8500_NR_IRQS)
+#define MOP500_IRQ_END                 MOP500_AB8500_IRQ_END
+
+#if MOP500_IRQ_END > IRQ_BOARD_END
+#undef IRQ_BOARD_END
+#define IRQ_BOARD_END  MOP500_IRQ_END
+#endif
+
+#endif

diff --git a/arch/arm/mach-ux500/include/mach/irqs-db5500.h b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
new file mode 100644 (file)
index 0000000..6fbfe5e
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com>
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#ifndef __MACH_IRQS_DB5500_H
+#define __MACH_IRQS_DB5500_H
+
+#define IRQ_DB5500_MTU0                        (IRQ_SHPI_START + 4)
+#define IRQ_DB5500_SPI2                        (IRQ_SHPI_START + 6)
+#define IRQ_DB5500_PMU0                        (IRQ_SHPI_START + 7)
+#define IRQ_DB5500_SPI0                        (IRQ_SHPI_START + 8)
+#define IRQ_DB5500_RTT                 (IRQ_SHPI_START + 9)
+#define IRQ_DB5500_PKA                 (IRQ_SHPI_START + 10)
+#define IRQ_DB5500_UART0               (IRQ_SHPI_START + 11)
+#define IRQ_DB5500_I2C3                        (IRQ_SHPI_START + 12)
+#define IRQ_DB5500_L2CC                        (IRQ_SHPI_START + 13)
+#define IRQ_DB5500_MSP0                        (IRQ_SHPI_START + 14)
+#define IRQ_DB5500_CRYP1               (IRQ_SHPI_START + 15)
+#define IRQ_DB5500_PMU1                        (IRQ_SHPI_START + 16)
+#define IRQ_DB5500_MTU1                        (IRQ_SHPI_START + 17)
+#define IRQ_DB5500_RTC                 (IRQ_SHPI_START + 18)
+#define IRQ_DB5500_UART1               (IRQ_SHPI_START + 19)
+#define IRQ_DB5500_USB_WAKEUP          (IRQ_SHPI_START + 20)
+#define IRQ_DB5500_I2C0                        (IRQ_SHPI_START + 21)
+#define IRQ_DB5500_I2C1                        (IRQ_SHPI_START + 22)
+#define IRQ_DB5500_USBOTG              (IRQ_SHPI_START + 23)
+#define IRQ_DB5500_DMA_SECURE          (IRQ_SHPI_START + 24)
+#define IRQ_DB5500_DMA                 (IRQ_SHPI_START + 25)
+#define IRQ_DB5500_UART2               (IRQ_SHPI_START + 26)
+#define IRQ_DB5500_ICN_PMU1            (IRQ_SHPI_START + 27)
+#define IRQ_DB5500_ICN_PMU2            (IRQ_SHPI_START + 28)
+#define IRQ_DB5500_UART3               (IRQ_SHPI_START + 29)
+#define IRQ_DB5500_SPI3                        (IRQ_SHPI_START + 30)
+#define IRQ_DB5500_SDMMC4              (IRQ_SHPI_START + 31)
+#define IRQ_DB5500_IRRC                        (IRQ_SHPI_START + 33)
+#define IRQ_DB5500_IRDA_FT             (IRQ_SHPI_START + 34)
+#define IRQ_DB5500_IRDA_SD             (IRQ_SHPI_START + 35)
+#define IRQ_DB5500_IRDA_FI             (IRQ_SHPI_START + 36)
+#define IRQ_DB5500_IRDA_FD             (IRQ_SHPI_START + 37)
+#define IRQ_DB5500_FSMC_CODEREADY      (IRQ_SHPI_START + 38)
+#define IRQ_DB5500_FSMC_NANDWAIT       (IRQ_SHPI_START + 39)
+#define IRQ_DB5500_AB5500              (IRQ_SHPI_START + 40)
+#define IRQ_DB5500_SDMMC2              (IRQ_SHPI_START + 41)
+#define IRQ_DB5500_SIA                 (IRQ_SHPI_START + 42)
+#define IRQ_DB5500_SIA2                        (IRQ_SHPI_START + 43)
+#define IRQ_DB5500_HVA                 (IRQ_SHPI_START + 44)
+#define IRQ_DB5500_HVA2                        (IRQ_SHPI_START + 45)
+#define IRQ_DB5500_PRCMU0              (IRQ_SHPI_START + 46)
+#define IRQ_DB5500_PRCMU1              (IRQ_SHPI_START + 47)
+#define IRQ_DB5500_DISP                        (IRQ_SHPI_START + 48)
+#define IRQ_DB5500_SDMMC1              (IRQ_SHPI_START + 50)
+#define IRQ_DB5500_MSP1                        (IRQ_SHPI_START + 52)
+#define IRQ_DB5500_KBD                 (IRQ_SHPI_START + 53)
+#define IRQ_DB5500_I2C2                        (IRQ_SHPI_START + 55)
+#define IRQ_DB5500_B2R2                        (IRQ_SHPI_START + 56)
+#define IRQ_DB5500_CRYP0               (IRQ_SHPI_START + 57)
+#define IRQ_DB5500_SDMMC3              (IRQ_SHPI_START + 59)
+#define IRQ_DB5500_SDMMC0              (IRQ_SHPI_START + 60)
+#define IRQ_DB5500_HSEM                        (IRQ_SHPI_START + 61)
+#define IRQ_DB5500_SBAG                        (IRQ_SHPI_START + 63)
+#define IRQ_DB5500_SPI1                        (IRQ_SHPI_START + 96)
+#define IRQ_DB5500_MSP2                        (IRQ_SHPI_START + 98)
+#define IRQ_DB5500_SRPTIMER            (IRQ_SHPI_START + 101)
+#define IRQ_DB5500_CTI0                        (IRQ_SHPI_START + 108)
+#define IRQ_DB5500_CTI1                        (IRQ_SHPI_START + 109)
+#define IRQ_DB5500_ICN_ERR             (IRQ_SHPI_START + 110)
+#define IRQ_DB5500_MALI_PPMMU          (IRQ_SHPI_START + 112)
+#define IRQ_DB5500_MALI_PP             (IRQ_SHPI_START + 113)
+#define IRQ_DB5500_MALI_GPMMU          (IRQ_SHPI_START + 114)
+#define IRQ_DB5500_MALI_GP             (IRQ_SHPI_START + 115)
+#define IRQ_DB5500_MALI                        (IRQ_SHPI_START + 116)
+#define IRQ_DB5500_PRCMU_SEM           (IRQ_SHPI_START + 118)
+#define IRQ_DB5500_GPIO0               (IRQ_SHPI_START + 119)
+#define IRQ_DB5500_GPIO1               (IRQ_SHPI_START + 120)
+#define IRQ_DB5500_GPIO2               (IRQ_SHPI_START + 121)
+#define IRQ_DB5500_GPIO3               (IRQ_SHPI_START + 122)
+#define IRQ_DB5500_GPIO4               (IRQ_SHPI_START + 123)
+#define IRQ_DB5500_GPIO5               (IRQ_SHPI_START + 124)
+#define IRQ_DB5500_GPIO6               (IRQ_SHPI_START + 125)
+#define IRQ_DB5500_GPIO7               (IRQ_SHPI_START + 126)
+
+#endif

diff --git a/arch/arm/mach-ux500/include/mach/irqs-db8500.h b/arch/arm/mach-ux500/include/mach/irqs-db8500.h
new file mode 100644 (file)
index 0000000..8b5d9f0
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs-db8500.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com>
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#ifndef __MACH_IRQS_DB8500_H
+#define __MACH_IRQS_DB8500_H
+
+#define IRQ_DB8500_MTU0                        (IRQ_SHPI_START + 4)
+#define IRQ_DB8500_SPI2                        (IRQ_SHPI_START + 6)
+#define IRQ_DB8500_PMU                 (IRQ_SHPI_START + 7)
+#define IRQ_DB8500_SPI0                        (IRQ_SHPI_START + 8)
+#define IRQ_DB8500_RTT                 (IRQ_SHPI_START + 9)
+#define IRQ_DB8500_PKA                 (IRQ_SHPI_START + 10)
+#define IRQ_DB8500_UART0               (IRQ_SHPI_START + 11)
+#define IRQ_DB8500_I2C3                        (IRQ_SHPI_START + 12)
+#define IRQ_DB8500_L2CC                        (IRQ_SHPI_START + 13)
+#define IRQ_DB8500_SSP0                        (IRQ_SHPI_START + 14)
+#define IRQ_DB8500_CRYP1               (IRQ_SHPI_START + 15)
+#define IRQ_DB8500_MSP1_RX             (IRQ_SHPI_START + 16)
+#define IRQ_DB8500_MTU1                        (IRQ_SHPI_START + 17)
+#define IRQ_DB8500_RTC                 (IRQ_SHPI_START + 18)
+#define IRQ_DB8500_UART1               (IRQ_SHPI_START + 19)
+#define IRQ_DB8500_USB_WAKEUP          (IRQ_SHPI_START + 20)
+#define IRQ_DB8500_I2C0                        (IRQ_SHPI_START + 21)
+#define IRQ_DB8500_I2C1                        (IRQ_SHPI_START + 22)
+#define IRQ_DB8500_USBOTG              (IRQ_SHPI_START + 23)
+#define IRQ_DB8500_DMA_SECURE          (IRQ_SHPI_START + 24)
+#define IRQ_DB8500_DMA                 (IRQ_SHPI_START + 25)
+#define IRQ_DB8500_UART2               (IRQ_SHPI_START + 26)
+#define IRQ_DB8500_ICN_PMU1            (IRQ_SHPI_START + 27)
+#define IRQ_DB8500_ICN_PMU2            (IRQ_SHPI_START + 28)
+#define IRQ_DB8500_HSIR_EXCEP          (IRQ_SHPI_START + 29)
+#define IRQ_DB8500_MSP0                        (IRQ_SHPI_START + 31)
+#define IRQ_DB8500_HSIR_CH0_OVRRUN     (IRQ_SHPI_START + 32)
+#define IRQ_DB8500_HSIR_CH1_OVRRUN     (IRQ_SHPI_START + 33)
+#define IRQ_DB8500_HSIR_CH2_OVRRUN     (IRQ_SHPI_START + 34)
+#define IRQ_DB8500_HSIR_CH3_OVRRUN     (IRQ_SHPI_START + 35)
+#define IRQ_DB8500_HSIR_CH4_OVRRUN     (IRQ_SHPI_START + 36)
+#define IRQ_DB8500_HSIR_CH5_OVRRUN     (IRQ_SHPI_START + 37)
+#define IRQ_DB8500_HSIR_CH6_OVRRUN     (IRQ_SHPI_START + 38)
+#define IRQ_DB8500_HSIR_CH7_OVRRUN     (IRQ_SHPI_START + 39)
+#define IRQ_DB8500_AB8500              (IRQ_SHPI_START + 40)
+#define IRQ_DB8500_SDMMC2              (IRQ_SHPI_START + 41)
+#define IRQ_DB8500_SIA                 (IRQ_SHPI_START + 42)
+#define IRQ_DB8500_SIA2                        (IRQ_SHPI_START + 43)
+#define IRQ_DB8500_SVA                 (IRQ_SHPI_START + 44)
+#define IRQ_DB8500_SVA2                        (IRQ_SHPI_START + 45)
+#define IRQ_DB8500_PRCMU0              (IRQ_SHPI_START + 46)
+#define IRQ_DB8500_PRCMU1              (IRQ_SHPI_START + 47)
+#define IRQ_DB8500_DISP                        (IRQ_SHPI_START + 48)
+#define IRQ_DB8500_SPI3                        (IRQ_SHPI_START + 49)
+#define IRQ_DB8500_SDMMC1              (IRQ_SHPI_START + 50)
+#define IRQ_DB8500_I2C4                        (IRQ_SHPI_START + 51)
+#define IRQ_DB8500_SSP1                        (IRQ_SHPI_START + 52)
+#define IRQ_DB8500_SKE                 (IRQ_SHPI_START + 53)
+#define IRQ_DB8500_KB                  (IRQ_SHPI_START + 54)
+#define IRQ_DB8500_I2C2                        (IRQ_SHPI_START + 55)
+#define IRQ_DB8500_B2R2                        (IRQ_SHPI_START + 56)
+#define IRQ_DB8500_CRYP0               (IRQ_SHPI_START + 57)
+#define IRQ_DB8500_SDMMC3              (IRQ_SHPI_START + 59)
+#define IRQ_DB8500_SDMMC0              (IRQ_SHPI_START + 60)
+#define IRQ_DB8500_HSEM                        (IRQ_SHPI_START + 61)
+#define IRQ_DB8500_MSP1                        (IRQ_SHPI_START + 62)
+#define IRQ_DB8500_SBAG                        (IRQ_SHPI_START + 63)
+#define IRQ_DB8500_SPI1                        (IRQ_SHPI_START + 96)
+#define IRQ_DB8500_SRPTIMER            (IRQ_SHPI_START + 97)
+#define IRQ_DB8500_MSP2                        (IRQ_SHPI_START + 98)
+#define IRQ_DB8500_SDMMC4              (IRQ_SHPI_START + 99)
+#define IRQ_DB8500_SDMMC5              (IRQ_SHPI_START + 100)
+#define IRQ_DB8500_HSIRD0              (IRQ_SHPI_START + 104)
+#define IRQ_DB8500_HSIRD1              (IRQ_SHPI_START + 105)
+#define IRQ_DB8500_HSITD0              (IRQ_SHPI_START + 106)
+#define IRQ_DB8500_HSITD1              (IRQ_SHPI_START + 107)
+#define IRQ_DB8500_CTI0                        (IRQ_SHPI_START + 108)
+#define IRQ_DB8500_CTI1                        (IRQ_SHPI_START + 109)
+#define IRQ_DB8500_ICN_ERR             (IRQ_SHPI_START + 110)
+#define IRQ_DB8500_MALI_PPMMU          (IRQ_SHPI_START + 112)
+#define IRQ_DB8500_MALI_PP             (IRQ_SHPI_START + 113)
+#define IRQ_DB8500_MALI_GPMMU          (IRQ_SHPI_START + 114)
+#define IRQ_DB8500_MALI_GP             (IRQ_SHPI_START + 115)
+#define IRQ_DB8500_MALI                        (IRQ_SHPI_START + 116)
+#define IRQ_DB8500_PRCMU_SEM           (IRQ_SHPI_START + 118)
+#define IRQ_DB8500_GPIO0               (IRQ_SHPI_START + 119)
+#define IRQ_DB8500_GPIO1               (IRQ_SHPI_START + 120)
+#define IRQ_DB8500_GPIO2               (IRQ_SHPI_START + 121)
+#define IRQ_DB8500_GPIO3               (IRQ_SHPI_START + 122)
+#define IRQ_DB8500_GPIO4               (IRQ_SHPI_START + 123)
+#define IRQ_DB8500_GPIO5               (IRQ_SHPI_START + 124)
+#define IRQ_DB8500_GPIO6               (IRQ_SHPI_START + 125)
+#define IRQ_DB8500_GPIO7               (IRQ_SHPI_START + 126)
+#define IRQ_DB8500_GPIO8               (IRQ_SHPI_START + 127)
+
+#endif

diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index 7970684b1d0983841bd74e623daf93412fd8797e..10385bdc2b7760506af333077fd1fd34fe5972fc 100644 (file)
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -10,7 +10,8 @@
 #ifndef ASM_ARCH_IRQS_H
 #define ASM_ARCH_IRQS_H
 
-#include <mach/hardware.h>
+#include <mach/irqs-db5500.h>
+#include <mach/irqs-db8500.h>
 
 #define IRQ_LOCALTIMER                  29
 #define IRQ_LOCALWDOG                   30
@@ -67,12 +68,21 @@
 /* There are 128 shared peripheral interrupts assigned to
  * INTID[160:32]. The first 32 interrupts are reserved.
  */
-#define U8500_SOC_NR_IRQS              161
+#define DBX500_NR_INTERNAL_IRQS                161
 
 /* After chip-specific IRQ numbers we have the GPIO ones */
 #define NOMADIK_NR_GPIO                        288
-#define NOMADIK_GPIO_TO_IRQ(gpio)      ((gpio) + U8500_SOC_NR_IRQS)
-#define NOMADIK_IRQ_TO_GPIO(irq)       ((irq) - U8500_SOC_NR_IRQS)
-#define NR_IRQS                                NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
+#define NOMADIK_GPIO_TO_IRQ(gpio)      ((gpio) + DBX500_NR_INTERNAL_IRQS)
+#define NOMADIK_IRQ_TO_GPIO(irq)       ((irq) - DBX500_NR_INTERNAL_IRQS)
+#define IRQ_BOARD_START                        NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
 
-#endif /*ASM_ARCH_IRQS_H*/
+/* This will be overridden by board-specific irq headers */
+#define IRQ_BOARD_END                  IRQ_BOARD_START
+
+#ifdef CONFIG_MACH_U8500_MOP
+#include <mach/irqs-board-mop500.h>
+#endif
+
+#define NR_IRQS                                IRQ_BOARD_END
+
+#endif /* ASM_ARCH_IRQS_H */

diff --git a/arch/arm/mach-ux500/pins-db8500.h b/arch/arm/mach-ux500/pins-db8500.h
new file mode 100644 (file)
index 0000000..9055d5d
--- /dev/null
+++ b/arch/arm/mach-ux500/pins-db8500.h
@@ -0,0 +1,742 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License terms: GNU General Public License, version 2
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com>
+ */
+
+#ifndef __MACH_PINS_DB8500_H
+#define __MACH_PINS_DB8500_H
+
+/*
+ * TODO: Eventually encode all non-board specific pull up/down configuration
+ * here.
+ */
+
+#define GPIO0_GPIO             PIN_CFG(0, GPIO)
+#define GPIO0_U0_CTSn          PIN_CFG(0, ALT_A)
+#define GPIO0_TRIG_OUT         PIN_CFG(0, ALT_B)
+#define GPIO0_IP_TDO           PIN_CFG(0, ALT_C)
+
+#define GPIO1_GPIO             PIN_CFG(1, GPIO)
+#define GPIO1_U0_RTSn          PIN_CFG(1, ALT_A)
+#define GPIO1_TRIG_IN          PIN_CFG(1, ALT_B)
+#define GPIO1_IP_TDI           PIN_CFG(1, ALT_C)
+
+#define GPIO2_GPIO             PIN_CFG(2, GPIO)
+#define GPIO2_U0_RXD           PIN_CFG(2, ALT_A)
+#define GPIO2_NONE             PIN_CFG(2, ALT_B)
+#define GPIO2_IP_TMS           PIN_CFG(2, ALT_C)
+
+#define GPIO3_GPIO             PIN_CFG(3, GPIO)
+#define GPIO3_U0_TXD           PIN_CFG(3, ALT_A)
+#define GPIO3_NONE             PIN_CFG(3, ALT_B)
+#define GPIO3_IP_TCK           PIN_CFG(3, ALT_C)
+
+#define GPIO4_GPIO             PIN_CFG(4, GPIO)
+#define GPIO4_U1_RXD           PIN_CFG(4, ALT_A)
+#define GPIO4_I2C4_SCL         PIN_CFG_PULL(4, ALT_B, UP)
+#define GPIO4_IP_TRSTn         PIN_CFG(4, ALT_C)
+
+#define GPIO5_GPIO             PIN_CFG(5, GPIO)
+#define GPIO5_U1_TXD           PIN_CFG(5, ALT_A)
+#define GPIO5_I2C4_SDA         PIN_CFG_PULL(5, ALT_B, UP)
+#define GPIO5_IP_GPIO6         PIN_CFG(5, ALT_C)
+
+#define GPIO6_GPIO             PIN_CFG(6, GPIO)
+#define GPIO6_U1_CTSn          PIN_CFG(6, ALT_A)
+#define GPIO6_I2C1_SCL         PIN_CFG_PULL(6, ALT_B, UP)
+#define GPIO6_IP_GPIO0         PIN_CFG(6, ALT_C)
+
+#define GPIO7_GPIO             PIN_CFG(7, GPIO)
+#define GPIO7_U1_RTSn          PIN_CFG(7, ALT_A)
+#define GPIO7_I2C1_SDA         PIN_CFG_PULL(7, ALT_B, UP)
+#define GPIO7_IP_GPIO1         PIN_CFG(7, ALT_C)
+
+#define GPIO8_GPIO             PIN_CFG(8, GPIO)
+#define GPIO8_IPI2C_SDA                PIN_CFG_PULL(8, ALT_A, UP)
+#define GPIO8_I2C2_SDA         PIN_CFG_PULL(8, ALT_B, UP)
+
+#define GPIO9_GPIO             PIN_CFG(9, GPIO)
+#define GPIO9_IPI2C_SCL                PIN_CFG_PULL(9, ALT_A, UP)
+#define GPIO9_I2C2_SCL         PIN_CFG_PULL(9, ALT_B, UP)
+
+#define GPIO10_GPIO            PIN_CFG(10, GPIO)
+#define GPIO10_IPI2C_SDA       PIN_CFG_PULL(10, ALT_A, UP)
+#define GPIO10_I2C2_SDA                PIN_CFG_PULL(10, ALT_B, UP)
+#define GPIO10_IP_GPIO3                PIN_CFG(10, ALT_C)
+
+#define GPIO11_GPIO            PIN_CFG(11, GPIO)
+#define GPIO11_IPI2C_SCL       PIN_CFG_PULL(11, ALT_A, UP)
+#define GPIO11_I2C2_SCL                PIN_CFG_PULL(11, ALT_B, UP)
+#define GPIO11_IP_GPIO2                PIN_CFG(11, ALT_C)
+
+#define GPIO12_GPIO            PIN_CFG(12, GPIO)
+#define GPIO12_MSP0_TXD                PIN_CFG(12, ALT_A)
+#define GPIO12_MSP0_RXD                PIN_CFG(12, ALT_B)
+
+#define GPIO13_GPIO            PIN_CFG(13, GPIO)
+#define GPIO13_MSP0_TFS                PIN_CFG(13, ALT_A)
+
+#define GPIO14_GPIO            PIN_CFG(14, GPIO)
+#define GPIO14_MSP0_TCK                PIN_CFG(14, ALT_A)
+
+#define GPIO15_GPIO            PIN_CFG(15, GPIO)
+#define GPIO15_MSP0_RXD                PIN_CFG(15, ALT_A)
+#define GPIO15_MSP0_TXD                PIN_CFG(15, ALT_B)
+
+#define GPIO16_GPIO            PIN_CFG(16, GPIO)
+#define GPIO16_MSP0_RFS                PIN_CFG(16, ALT_A)
+#define GPIO16_I2C1_SCL                PIN_CFG_PULL(16, ALT_B, UP)
+#define GPIO16_SLIM0_DAT       PIN_CFG(16, ALT_C)
+
+#define GPIO17_GPIO            PIN_CFG(17, GPIO)
+#define GPIO17_MSP0_RCK                PIN_CFG(17, ALT_A)
+#define GPIO17_I2C1_SDA                PIN_CFG_PULL(17, ALT_B, UP)
+#define GPIO17_SLIM0_CLK       PIN_CFG(17, ALT_C)
+
+#define GPIO18_GPIO            PIN_CFG(18, GPIO)
+#define GPIO18_MC0_CMDDIR      PIN_CFG(18, ALT_A)
+#define GPIO18_U2_RXD          PIN_CFG(18, ALT_B)
+#define GPIO18_MS_IEP          PIN_CFG(18, ALT_C)
+
+#define GPIO19_GPIO            PIN_CFG(19, GPIO)
+#define GPIO19_MC0_DAT0DIR     PIN_CFG(19, ALT_A)
+#define GPIO19_U2_TXD          PIN_CFG(19, ALT_B)
+#define GPIO19_MS_DAT0DIR      PIN_CFG(19, ALT_C)
+
+#define GPIO20_GPIO            PIN_CFG(20, GPIO)
+#define GPIO20_MC0_DAT2DIR     PIN_CFG(20, ALT_A)
+#define GPIO20_UARTMOD_TXD     PIN_CFG(20, ALT_B)
+#define GPIO20_IP_TRIGOUT      PIN_CFG(20, ALT_C)
+
+#define GPIO21_GPIO            PIN_CFG(21, GPIO)
+#define GPIO21_MC0_DAT31DIR    PIN_CFG(21, ALT_A)
+#define GPIO21_MSP0_SCK                PIN_CFG(21, ALT_B)
+#define GPIO21_MS_DAT31DIR     PIN_CFG(21, ALT_C)
+
+#define GPIO22_GPIO            PIN_CFG(22, GPIO)
+#define GPIO22_MC0_FBCLK       PIN_CFG(22, ALT_A)
+#define GPIO22_UARTMOD_RXD     PIN_CFG(22, ALT_B)
+#define GPIO22_MS_FBCLK                PIN_CFG(22, ALT_C)
+
+#define GPIO23_GPIO            PIN_CFG(23, GPIO)
+#define GPIO23_MC0_CLK         PIN_CFG(23, ALT_A)
+#define GPIO23_STMMOD_CLK      PIN_CFG(23, ALT_B)
+#define GPIO23_MS_CLK          PIN_CFG(23, ALT_C)
+
+#define GPIO24_GPIO            PIN_CFG(24, GPIO)
+#define GPIO24_MC0_CMD         PIN_CFG(24, ALT_A)
+#define GPIO24_UARTMOD_RXD     PIN_CFG(24, ALT_B)
+#define GPIO24_MS_BS           PIN_CFG(24, ALT_C)
+
+#define GPIO25_GPIO            PIN_CFG(25, GPIO)
+#define GPIO25_MC0_DAT0                PIN_CFG(25, ALT_A)
+#define GPIO25_STMMOD_DAT0     PIN_CFG(25, ALT_B)
+#define GPIO25_MS_DAT0         PIN_CFG(25, ALT_C)
+
+#define GPIO26_GPIO            PIN_CFG(26, GPIO)
+#define GPIO26_MC0_DAT1                PIN_CFG(26, ALT_A)
+#define GPIO26_STMMOD_DAT1     PIN_CFG(26, ALT_B)
+#define GPIO26_MS_DAT1         PIN_CFG(26, ALT_C)
+
+#define GPIO27_GPIO            PIN_CFG(27, GPIO)
+#define GPIO27_MC0_DAT2                PIN_CFG(27, ALT_A)
+#define GPIO27_STMMOD_DAT2     PIN_CFG(27, ALT_B)
+#define GPIO27_MS_DAT2         PIN_CFG(27, ALT_C)
+
+#define GPIO28_GPIO            PIN_CFG(28, GPIO)
+#define GPIO28_MC0_DAT3                PIN_CFG(28, ALT_A)
+#define GPIO28_STMMOD_DAT3     PIN_CFG(28, ALT_B)
+#define GPIO28_MS_DAT3         PIN_CFG(28, ALT_C)
+
+#define GPIO29_GPIO            PIN_CFG(29, GPIO)
+#define GPIO29_MC0_DAT4                PIN_CFG(29, ALT_A)
+#define GPIO29_SPI3_CLK                PIN_CFG(29, ALT_B)
+#define GPIO29_U2_RXD          PIN_CFG(29, ALT_C)
+
+#define GPIO30_GPIO            PIN_CFG(30, GPIO)
+#define GPIO30_MC0_DAT5                PIN_CFG(30, ALT_A)
+#define GPIO30_SPI3_RXD                PIN_CFG(30, ALT_B)
+#define GPIO30_U2_TXD          PIN_CFG(30, ALT_C)
+
+#define GPIO31_GPIO            PIN_CFG(31, GPIO)
+#define GPIO31_MC0_DAT6                PIN_CFG(31, ALT_A)
+#define GPIO31_SPI3_FRM                PIN_CFG(31, ALT_B)
+#define GPIO31_U2_CTSn         PIN_CFG(31, ALT_C)
+
+#define GPIO32_GPIO            PIN_CFG(32, GPIO)
+#define GPIO32_MC0_DAT7                PIN_CFG(32, ALT_A)
+#define GPIO32_SPI3_TXD                PIN_CFG(32, ALT_B)
+#define GPIO32_U2_RTSn         PIN_CFG(32, ALT_C)
+
+#define GPIO33_GPIO            PIN_CFG(33, GPIO)
+#define GPIO33_MSP1_TXD                PIN_CFG(33, ALT_A)
+#define GPIO33_MSP1_RXD                PIN_CFG(33, ALT_B)
+#define GPIO33_U0_DTRn         PIN_CFG(33, ALT_C)
+
+#define GPIO34_GPIO            PIN_CFG(34, GPIO)
+#define GPIO34_MSP1_TFS                PIN_CFG(34, ALT_A)
+#define GPIO34_NONE            PIN_CFG(34, ALT_B)
+#define GPIO34_U0_DCDn         PIN_CFG(34, ALT_C)
+
+#define GPIO35_GPIO            PIN_CFG(35, GPIO)
+#define GPIO35_MSP1_TCK                PIN_CFG(35, ALT_A)
+#define GPIO35_NONE            PIN_CFG(35, ALT_B)
+#define GPIO35_U0_DSRn         PIN_CFG(35, ALT_C)
+
+#define GPIO36_GPIO            PIN_CFG(36, GPIO)
+#define GPIO36_MSP1_RXD                PIN_CFG(36, ALT_A)
+#define GPIO36_MSP1_TXD                PIN_CFG(36, ALT_B)
+#define GPIO36_U0_RIn          PIN_CFG(36, ALT_C)
+
+#define GPIO64_GPIO            PIN_CFG(64, GPIO)
+#define GPIO64_LCDB_DE         PIN_CFG(64, ALT_A)
+#define GPIO64_KP_O1           PIN_CFG(64, ALT_B)
+#define GPIO64_IP_GPIO4                PIN_CFG(64, ALT_C)
+
+#define GPIO65_GPIO            PIN_CFG(65, GPIO)
+#define GPIO65_LCDB_HSO                PIN_CFG(65, ALT_A)
+#define GPIO65_KP_O0           PIN_CFG(65, ALT_B)
+#define GPIO65_IP_GPIO5                PIN_CFG(65, ALT_C)
+
+#define GPIO66_GPIO            PIN_CFG(66, GPIO)
+#define GPIO66_LCDB_VSO                PIN_CFG(66, ALT_A)
+#define GPIO66_KP_I1           PIN_CFG(66, ALT_B)
+#define GPIO66_IP_GPIO6                PIN_CFG(66, ALT_C)
+
+#define GPIO67_GPIO            PIN_CFG(67, GPIO)
+#define GPIO67_LCDB_CLK                PIN_CFG(67, ALT_A)
+#define GPIO67_KP_I0           PIN_CFG(67, ALT_B)
+#define GPIO67_IP_GPIO7                PIN_CFG(67, ALT_C)
+
+#define GPIO68_GPIO            PIN_CFG(68, GPIO)
+#define GPIO68_LCD_VSI0                PIN_CFG(68, ALT_A)
+#define GPIO68_KP_O7           PIN_CFG(68, ALT_B)
+#define GPIO68_SM_CLE          PIN_CFG(68, ALT_C)
+
+#define GPIO69_GPIO            PIN_CFG(69, GPIO)
+#define GPIO69_LCD_VSI1                PIN_CFG(69, ALT_A)
+#define GPIO69_KP_I7           PIN_CFG(69, ALT_B)
+#define GPIO69_SM_ALE          PIN_CFG(69, ALT_C)
+
+#define GPIO70_GPIO            PIN_CFG(70, GPIO)
+#define GPIO70_LCD_D0          PIN_CFG(70, ALT_A)
+#define GPIO70_KP_O5           PIN_CFG(70, ALT_B)
+#define GPIO70_STMAPE_CLK      PIN_CFG(70, ALT_C)
+
+#define GPIO71_GPIO            PIN_CFG(71, GPIO)
+#define GPIO71_LCD_D1          PIN_CFG(71, ALT_A)
+#define GPIO71_KP_O4           PIN_CFG(71, ALT_B)
+#define GPIO71_STMAPE_DAT3     PIN_CFG(71, ALT_C)
+
+#define GPIO72_GPIO            PIN_CFG(72, GPIO)
+#define GPIO72_LCD_D2          PIN_CFG(72, ALT_A)
+#define GPIO72_KP_O3           PIN_CFG(72, ALT_B)
+#define GPIO72_STMAPE_DAT2     PIN_CFG(72, ALT_C)
+
+#define GPIO73_GPIO            PIN_CFG(73, GPIO)
+#define GPIO73_LCD_D3          PIN_CFG(73, ALT_A)
+#define GPIO73_KP_O2           PIN_CFG(73, ALT_B)
+#define GPIO73_STMAPE_DAT1     PIN_CFG(73, ALT_C)
+
+#define GPIO74_GPIO            PIN_CFG(74, GPIO)
+#define GPIO74_LCD_D4          PIN_CFG(74, ALT_A)
+#define GPIO74_KP_I5           PIN_CFG(74, ALT_B)
+#define GPIO74_STMAPE_DAT0     PIN_CFG(74, ALT_C)
+
+#define GPIO75_GPIO            PIN_CFG(75, GPIO)
+#define GPIO75_LCD_D5          PIN_CFG(75, ALT_A)
+#define GPIO75_KP_I4           PIN_CFG(75, ALT_B)
+#define GPIO75_U2_RXD          PIN_CFG(75, ALT_C)
+
+#define GPIO76_GPIO            PIN_CFG(76, GPIO)
+#define GPIO76_LCD_D6          PIN_CFG(76, ALT_A)
+#define GPIO76_KP_I3           PIN_CFG(76, ALT_B)
+#define GPIO76_U2_TXD          PIN_CFG(76, ALT_C)
+
+#define GPIO77_GPIO            PIN_CFG(77, GPIO)
+#define GPIO77_LCD_D7          PIN_CFG(77, ALT_A)
+#define GPIO77_KP_I2           PIN_CFG(77, ALT_B)
+#define GPIO77_NONE            PIN_CFG(77, ALT_C)
+
+#define GPIO78_GPIO            PIN_CFG(78, GPIO)
+#define GPIO78_LCD_D8          PIN_CFG(78, ALT_A)
+#define GPIO78_KP_O6           PIN_CFG(78, ALT_B)
+#define GPIO78_IP_GPIO2                PIN_CFG(78, ALT_C)
+
+#define GPIO79_GPIO            PIN_CFG(79, GPIO)
+#define GPIO79_LCD_D9          PIN_CFG(79, ALT_A)
+#define GPIO79_KP_I6           PIN_CFG(79, ALT_B)
+#define GPIO79_IP_GPIO3                PIN_CFG(79, ALT_C)
+
+#define GPIO80_GPIO            PIN_CFG(80, GPIO)
+#define GPIO80_LCD_D10         PIN_CFG(80, ALT_A)
+#define GPIO80_KP_SKA0         PIN_CFG(80, ALT_B)
+#define GPIO80_IP_GPIO4                PIN_CFG(80, ALT_C)
+
+#define GPIO81_GPIO            PIN_CFG(81, GPIO)
+#define GPIO81_LCD_D11         PIN_CFG(81, ALT_A)
+#define GPIO81_KP_SKB0         PIN_CFG(81, ALT_B)
+#define GPIO81_IP_GPIO5                PIN_CFG(81, ALT_C)
+
+#define GPIO82_GPIO            PIN_CFG(82, GPIO)
+#define GPIO82_LCD_D12         PIN_CFG(82, ALT_A)
+#define GPIO82_KP_O5           PIN_CFG(82, ALT_B)
+
+#define GPIO83_GPIO            PIN_CFG(83, GPIO)
+#define GPIO83_LCD_D13         PIN_CFG(83, ALT_A)
+#define GPIO83_KP_O4           PIN_CFG(83, ALT_B)
+
+#define GPIO84_GPIO            PIN_CFG(84, GPIO)
+#define GPIO84_LCD_D14         PIN_CFG(84, ALT_A)
+#define GPIO84_KP_I5           PIN_CFG(84, ALT_B)
+
+#define GPIO85_GPIO            PIN_CFG(85, GPIO)
+#define GPIO85_LCD_D15         PIN_CFG(85, ALT_A)
+#define GPIO85_KP_I4           PIN_CFG(85, ALT_B)
+
+#define GPIO86_GPIO            PIN_CFG(86, GPIO)
+#define GPIO86_LCD_D16         PIN_CFG(86, ALT_A)
+#define GPIO86_SM_ADQ0         PIN_CFG(86, ALT_B)
+#define GPIO86_MC5_DAT0                PIN_CFG(86, ALT_C)
+
+#define GPIO87_GPIO            PIN_CFG(87, GPIO)
+#define GPIO87_LCD_D17         PIN_CFG(87, ALT_A)
+#define GPIO87_SM_ADQ1         PIN_CFG(87, ALT_B)
+#define GPIO87_MC5_DAT1                PIN_CFG(87, ALT_C)
+
+#define GPIO88_GPIO            PIN_CFG(88, GPIO)
+#define GPIO88_LCD_D18         PIN_CFG(88, ALT_A)
+#define GPIO88_SM_ADQ2         PIN_CFG(88, ALT_B)
+#define GPIO88_MC5_DAT2                PIN_CFG(88, ALT_C)
+
+#define GPIO89_GPIO            PIN_CFG(89, GPIO)
+#define GPIO89_LCD_D19         PIN_CFG(89, ALT_A)
+#define GPIO89_SM_ADQ3         PIN_CFG(89, ALT_B)
+#define GPIO89_MC5_DAT3                PIN_CFG(89, ALT_C)
+
+#define GPIO90_GPIO            PIN_CFG(90, GPIO)
+#define GPIO90_LCD_D20         PIN_CFG(90, ALT_A)
+#define GPIO90_SM_ADQ4         PIN_CFG(90, ALT_B)
+#define GPIO90_MC5_CMD         PIN_CFG(90, ALT_C)
+
+#define GPIO91_GPIO            PIN_CFG(91, GPIO)
+#define GPIO91_LCD_D21         PIN_CFG(91, ALT_A)
+#define GPIO91_SM_ADQ5         PIN_CFG(91, ALT_B)
+#define GPIO91_MC5_FBCLK       PIN_CFG(91, ALT_C)
+
+#define GPIO92_GPIO            PIN_CFG(92, GPIO)
+#define GPIO92_LCD_D22         PIN_CFG(92, ALT_A)
+#define GPIO92_SM_ADQ6         PIN_CFG(92, ALT_B)
+#define GPIO92_MC5_CLK         PIN_CFG(92, ALT_C)
+
+#define GPIO93_GPIO            PIN_CFG(93, GPIO)
+#define GPIO93_LCD_D23         PIN_CFG(93, ALT_A)
+#define GPIO93_SM_ADQ7         PIN_CFG(93, ALT_B)
+#define GPIO93_MC5_DAT4                PIN_CFG(93, ALT_C)
+
+#define GPIO94_GPIO            PIN_CFG(94, GPIO)
+#define GPIO94_KP_O7           PIN_CFG(94, ALT_A)
+#define GPIO94_SM_ADVn         PIN_CFG(94, ALT_B)
+#define GPIO94_MC5_DAT5                PIN_CFG(94, ALT_C)
+
+#define GPIO95_GPIO            PIN_CFG(95, GPIO)
+#define GPIO95_KP_I7           PIN_CFG(95, ALT_A)
+#define GPIO95_SM_CS0n         PIN_CFG(95, ALT_B)
+#define GPIO95_SM_PS0n         PIN_CFG(95, ALT_C)
+
+#define GPIO96_GPIO            PIN_CFG(96, GPIO)
+#define GPIO96_KP_O6           PIN_CFG(96, ALT_A)
+#define GPIO96_SM_OEn          PIN_CFG(96, ALT_B)
+#define GPIO96_MC5_DAT6                PIN_CFG(96, ALT_C)
+
+#define GPIO97_GPIO            PIN_CFG(97, GPIO)
+#define GPIO97_KP_I6           PIN_CFG(97, ALT_A)
+#define GPIO97_SM_WEn          PIN_CFG(97, ALT_B)
+#define GPIO97_MC5_DAT7                PIN_CFG(97, ALT_C)
+
+#define GPIO128_GPIO           PIN_CFG(128, GPIO)
+#define GPIO128_MC2_CLK                PIN_CFG(128, ALT_A)
+#define GPIO128_SM_CKO         PIN_CFG(128, ALT_B)
+
+#define GPIO129_GPIO           PIN_CFG(129, GPIO)
+#define GPIO129_MC2_CMD                PIN_CFG(129, ALT_A)
+#define GPIO129_SM_WAIT0n      PIN_CFG(129, ALT_B)
+
+#define GPIO130_GPIO           PIN_CFG(130, GPIO)
+#define GPIO130_MC2_FBCLK      PIN_CFG(130, ALT_A)
+#define GPIO130_SM_FBCLK       PIN_CFG(130, ALT_B)
+#define GPIO130_MC2_RSTN       PIN_CFG(130, ALT_C)
+
+#define GPIO131_GPIO           PIN_CFG(131, GPIO)
+#define GPIO131_MC2_DAT0       PIN_CFG(131, ALT_A)
+#define GPIO131_SM_ADQ8                PIN_CFG(131, ALT_B)
+
+#define GPIO132_GPIO           PIN_CFG(132, GPIO)
+#define GPIO132_MC2_DAT1       PIN_CFG(132, ALT_A)
+#define GPIO132_SM_ADQ9                PIN_CFG(132, ALT_B)
+
+#define GPIO133_GPIO           PIN_CFG(133, GPIO)
+#define GPIO133_MC2_DAT2       PIN_CFG(133, ALT_A)
+#define GPIO133_SM_ADQ10       PIN_CFG(133, ALT_B)
+
+#define GPIO134_GPIO           PIN_CFG(134, GPIO)
+#define GPIO134_MC2_DAT3       PIN_CFG(134, ALT_A)
+#define GPIO134_SM_ADQ11       PIN_CFG(134, ALT_B)
+
+#define GPIO135_GPIO           PIN_CFG(135, GPIO)
+#define GPIO135_MC2_DAT4       PIN_CFG(135, ALT_A)
+#define GPIO135_SM_ADQ12       PIN_CFG(135, ALT_B)
+
+#define GPIO136_GPIO           PIN_CFG(136, GPIO)
+#define GPIO136_MC2_DAT5       PIN_CFG(136, ALT_A)
+#define GPIO136_SM_ADQ13       PIN_CFG(136, ALT_B)
+
+#define GPIO137_GPIO           PIN_CFG(137, GPIO)
+#define GPIO137_MC2_DAT6       PIN_CFG(137, ALT_A)
+#define GPIO137_SM_ADQ14       PIN_CFG(137, ALT_B)
+
+#define GPIO138_GPIO           PIN_CFG(138, GPIO)
+#define GPIO138_MC2_DAT7       PIN_CFG(138, ALT_A)
+#define GPIO138_SM_ADQ15       PIN_CFG(138, ALT_B)
+
+#define GPIO139_GPIO           PIN_CFG(139, GPIO)
+#define GPIO139_SSP1_RXD       PIN_CFG(139, ALT_A)
+#define GPIO139_SM_WAIT1n      PIN_CFG(139, ALT_B)
+#define GPIO139_KP_O8          PIN_CFG(139, ALT_C)
+
+#define GPIO140_GPIO           PIN_CFG(140, GPIO)
+#define GPIO140_SSP1_TXD       PIN_CFG(140, ALT_A)
+#define GPIO140_IP_GPIO7       PIN_CFG(140, ALT_B)
+#define GPIO140_KP_SKA1                PIN_CFG(140, ALT_C)
+
+#define GPIO141_GPIO           PIN_CFG(141, GPIO)
+#define GPIO141_SSP1_CLK       PIN_CFG(141, ALT_A)
+#define GPIO141_IP_GPIO2       PIN_CFG(141, ALT_B)
+#define GPIO141_KP_O9          PIN_CFG(141, ALT_C)
+
+#define GPIO142_GPIO           PIN_CFG(142, GPIO)
+#define GPIO142_SSP1_FRM       PIN_CFG(142, ALT_A)
+#define GPIO142_IP_GPIO3       PIN_CFG(142, ALT_B)
+#define GPIO142_KP_SKB1                PIN_CFG(142, ALT_C)
+
+#define GPIO143_GPIO           PIN_CFG(143, GPIO)
+#define GPIO143_SSP0_CLK       PIN_CFG(143, ALT_A)
+
+#define GPIO144_GPIO           PIN_CFG(144, GPIO)
+#define GPIO144_SSP0_FRM       PIN_CFG(144, ALT_A)
+
+#define GPIO145_GPIO           PIN_CFG(145, GPIO)
+#define GPIO145_SSP0_RXD       PIN_CFG(145, ALT_A)
+
+#define GPIO146_GPIO           PIN_CFG(146, GPIO)
+#define GPIO146_SSP0_TXD       PIN_CFG(146, ALT_A)
+
+#define GPIO147_GPIO           PIN_CFG(147, GPIO)
+#define GPIO147_I2C0_SCL       PIN_CFG_PULL(147, ALT_A, UP)
+
+#define GPIO148_GPIO           PIN_CFG(148, GPIO)
+#define GPIO148_I2C0_SDA       PIN_CFG_PULL(148, ALT_A, UP)
+
+#define GPIO149_GPIO           PIN_CFG(149, GPIO)
+#define GPIO149_IP_GPIO0       PIN_CFG(149, ALT_A)
+#define GPIO149_SM_CS1n                PIN_CFG(149, ALT_B)
+#define GPIO149_SM_PS1n                PIN_CFG(149, ALT_C)
+
+#define GPIO150_GPIO           PIN_CFG(150, GPIO)
+#define GPIO150_IP_GPIO1       PIN_CFG(150, ALT_A)
+#define GPIO150_LCDA_CLK       PIN_CFG(150, ALT_B)
+
+#define GPIO151_GPIO           PIN_CFG(151, GPIO)
+#define GPIO151_KP_SKA0                PIN_CFG(151, ALT_A)
+#define GPIO151_LCD_VSI0       PIN_CFG(151, ALT_B)
+#define GPIO151_KP_O8          PIN_CFG(151, ALT_C)
+
+#define GPIO152_GPIO           PIN_CFG(152, GPIO)
+#define GPIO152_KP_SKB0                PIN_CFG(152, ALT_A)
+#define GPIO152_LCD_VSI1       PIN_CFG(152, ALT_B)
+#define GPIO152_KP_O9          PIN_CFG(152, ALT_C)
+
+#define GPIO153_GPIO           PIN_CFG(153, GPIO)
+#define GPIO153_KP_I7          PIN_CFG(153, ALT_A)
+#define GPIO153_LCD_D24                PIN_CFG(153, ALT_B)
+#define GPIO153_U2_RXD         PIN_CFG(153, ALT_C)
+
+#define GPIO154_GPIO           PIN_CFG(154, GPIO)
+#define GPIO154_KP_I6          PIN_CFG(154, ALT_A)
+#define GPIO154_LCD_D25                PIN_CFG(154, ALT_B)
+#define GPIO154_U2_TXD         PIN_CFG(154, ALT_C)
+
+#define GPIO155_GPIO           PIN_CFG(155, GPIO)
+#define GPIO155_KP_I5          PIN_CFG(155, ALT_A)
+#define GPIO155_LCD_D26                PIN_CFG(155, ALT_B)
+#define GPIO155_STMAPE_CLK     PIN_CFG(155, ALT_C)
+
+#define GPIO156_GPIO           PIN_CFG(156, GPIO)
+#define GPIO156_KP_I4          PIN_CFG(156, ALT_A)
+#define GPIO156_LCD_D27                PIN_CFG(156, ALT_B)
+#define GPIO156_STMAPE_DAT3    PIN_CFG(156, ALT_C)
+
+#define GPIO157_GPIO           PIN_CFG(157, GPIO)
+#define GPIO157_KP_O7          PIN_CFG(157, ALT_A)
+#define GPIO157_LCD_D28                PIN_CFG(157, ALT_B)
+#define GPIO157_STMAPE_DAT2    PIN_CFG(157, ALT_C)
+
+#define GPIO158_GPIO           PIN_CFG(158, GPIO)
+#define GPIO158_KP_O6          PIN_CFG(158, ALT_A)
+#define GPIO158_LCD_D29                PIN_CFG(158, ALT_B)
+#define GPIO158_STMAPE_DAT1    PIN_CFG(158, ALT_C)
+
+#define GPIO159_GPIO           PIN_CFG(159, GPIO)
+#define GPIO159_KP_O5          PIN_CFG(159, ALT_A)
+#define GPIO159_LCD_D30                PIN_CFG(159, ALT_B)
+#define GPIO159_STMAPE_DAT0    PIN_CFG(159, ALT_C)
+
+#define GPIO160_GPIO           PIN_CFG(160, GPIO)
+#define GPIO160_KP_O4          PIN_CFG(160, ALT_A)
+#define GPIO160_LCD_D31                PIN_CFG(160, ALT_B)
+#define GPIO160_NONE           PIN_CFG(160, ALT_C)
+
+#define GPIO161_GPIO           PIN_CFG(161, GPIO)
+#define GPIO161_KP_I3          PIN_CFG(161, ALT_A)
+#define GPIO161_LCD_D32                PIN_CFG(161, ALT_B)
+#define GPIO161_UARTMOD_RXD    PIN_CFG(161, ALT_C)
+
+#define GPIO162_GPIO           PIN_CFG(162, GPIO)
+#define GPIO162_KP_I2          PIN_CFG(162, ALT_A)
+#define GPIO162_LCD_D33                PIN_CFG(162, ALT_B)
+#define GPIO162_UARTMOD_TXD    PIN_CFG(162, ALT_C)
+
+#define GPIO163_GPIO           PIN_CFG(163, GPIO)
+#define GPIO163_KP_I1          PIN_CFG(163, ALT_A)
+#define GPIO163_LCD_D34                PIN_CFG(163, ALT_B)
+#define GPIO163_STMMOD_CLK     PIN_CFG(163, ALT_C)
+
+#define GPIO164_GPIO           PIN_CFG(164, GPIO)
+#define GPIO164_KP_I0          PIN_CFG(164, ALT_A)
+#define GPIO164_LCD_D35                PIN_CFG(164, ALT_B)
+#define GPIO164_STMMOD_DAT3    PIN_CFG(164, ALT_C)
+
+#define GPIO165_GPIO           PIN_CFG(165, GPIO)
+#define GPIO165_KP_O3          PIN_CFG(165, ALT_A)
+#define GPIO165_LCD_D36                PIN_CFG(165, ALT_B)
+#define GPIO165_STMMOD_DAT2    PIN_CFG(165, ALT_C)
+
+#define GPIO166_GPIO           PIN_CFG(166, GPIO)
+#define GPIO166_KP_O2          PIN_CFG(166, ALT_A)
+#define GPIO166_LCD_D37                PIN_CFG(166, ALT_B)
+#define GPIO166_STMMOD_DAT1    PIN_CFG(166, ALT_C)
+
+#define GPIO167_GPIO           PIN_CFG(167, GPIO)
+#define GPIO167_KP_O1          PIN_CFG(167, ALT_A)
+#define GPIO167_LCD_D38                PIN_CFG(167, ALT_B)
+#define GPIO167_STMMOD_DAT0    PIN_CFG(167, ALT_C)
+
+#define GPIO168_GPIO           PIN_CFG(168, GPIO)
+#define GPIO168_KP_O0          PIN_CFG(168, ALT_A)
+#define GPIO168_LCD_D39                PIN_CFG(168, ALT_B)
+#define GPIO168_NONE           PIN_CFG(168, ALT_C)
+
+#define GPIO169_GPIO           PIN_CFG(169, GPIO)
+#define GPIO169_RF_PURn                PIN_CFG(169, ALT_A)
+#define GPIO169_LCDA_DE                PIN_CFG(169, ALT_B)
+#define GPIO169_USBSIM_PDC     PIN_CFG(169, ALT_C)
+
+#define GPIO170_GPIO           PIN_CFG(170, GPIO)
+#define GPIO170_MODEM_STATE    PIN_CFG(170, ALT_A)
+#define GPIO170_LCDA_VSO       PIN_CFG(170, ALT_B)
+#define GPIO170_KP_SKA1                PIN_CFG(170, ALT_C)
+
+#define GPIO171_GPIO           PIN_CFG(171, GPIO)
+#define GPIO171_MODEM_PWREN    PIN_CFG(171, ALT_A)
+#define GPIO171_LCDA_HSO       PIN_CFG(171, ALT_B)
+#define GPIO171_KP_SKB1                PIN_CFG(171, ALT_C)
+
+#define GPIO192_GPIO           PIN_CFG(192, GPIO)
+#define GPIO192_MSP2_SCK       PIN_CFG(192, ALT_A)
+
+#define GPIO193_GPIO           PIN_CFG(193, GPIO)
+#define GPIO193_MSP2_TXD       PIN_CFG(193, ALT_A)
+
+#define GPIO194_GPIO           PIN_CFG(194, GPIO)
+#define GPIO194_MSP2_TCK       PIN_CFG(194, ALT_A)
+
+#define GPIO195_GPIO           PIN_CFG(195, GPIO)
+#define GPIO195_MSP2_TFS       PIN_CFG(195, ALT_A)
+
+#define GPIO196_GPIO           PIN_CFG(196, GPIO)
+#define GPIO196_MSP2_RXD       PIN_CFG(196, ALT_A)
+
+#define GPIO197_GPIO           PIN_CFG(197, GPIO)
+#define GPIO197_MC4_DAT3       PIN_CFG(197, ALT_A)
+
+#define GPIO198_GPIO           PIN_CFG(198, GPIO)
+#define GPIO198_MC4_DAT2       PIN_CFG(198, ALT_A)
+
+#define GPIO199_GPIO           PIN_CFG(199, GPIO)
+#define GPIO199_MC4_DAT1       PIN_CFG(199, ALT_A)
+
+#define GPIO200_GPIO           PIN_CFG(200, GPIO)
+#define GPIO200_MC4_DAT0       PIN_CFG(200, ALT_A)
+
+#define GPIO201_GPIO           PIN_CFG(201, GPIO)
+#define GPIO201_MC4_CMD                PIN_CFG(201, ALT_A)
+
+#define GPIO202_GPIO           PIN_CFG(202, GPIO)
+#define GPIO202_MC4_FBCLK      PIN_CFG(202, ALT_A)
+#define GPIO202_PWL            PIN_CFG(202, ALT_B)
+#define GPIO202_MC4_RSTN       PIN_CFG(202, ALT_C)
+
+#define GPIO203_GPIO           PIN_CFG(203, GPIO)
+#define GPIO203_MC4_CLK                PIN_CFG(203, ALT_A)
+
+#define GPIO204_GPIO           PIN_CFG(204, GPIO)
+#define GPIO204_MC4_DAT7       PIN_CFG(204, ALT_A)
+
+#define GPIO205_GPIO           PIN_CFG(205, GPIO)
+#define GPIO205_MC4_DAT6       PIN_CFG(205, ALT_A)
+
+#define GPIO206_GPIO           PIN_CFG(206, GPIO)
+#define GPIO206_MC4_DAT5       PIN_CFG(206, ALT_A)
+
+#define GPIO207_GPIO           PIN_CFG(207, GPIO)
+#define GPIO207_MC4_DAT4       PIN_CFG(207, ALT_A)
+
+#define GPIO208_GPIO           PIN_CFG(208, GPIO)
+#define GPIO208_MC1_CLK                PIN_CFG(208, ALT_A)
+
+#define GPIO209_GPIO           PIN_CFG(209, GPIO)
+#define GPIO209_MC1_FBCLK      PIN_CFG(209, ALT_A)
+#define GPIO209_SPI1_CLK       PIN_CFG(209, ALT_B)
+
+#define GPIO210_GPIO           PIN_CFG(210, GPIO)
+#define GPIO210_MC1_CMD                PIN_CFG(210, ALT_A)
+
+#define GPIO211_GPIO           PIN_CFG(211, GPIO)
+#define GPIO211_MC1_DAT0       PIN_CFG(211, ALT_A)
+
+#define GPIO212_GPIO           PIN_CFG(212, GPIO)
+#define GPIO212_MC1_DAT1       PIN_CFG(212, ALT_A)
+#define GPIO212_SPI1_FRM       PIN_CFG(212, ALT_B)
+
+#define GPIO213_GPIO           PIN_CFG(213, GPIO)
+#define GPIO213_MC1_DAT2       PIN_CFG(213, ALT_A)
+#define GPIO213_SPI1_TXD       PIN_CFG(213, ALT_B)
+
+#define GPIO214_GPIO           PIN_CFG(214, GPIO)
+#define GPIO214_MC1_DAT3       PIN_CFG(214, ALT_A)
+#define GPIO214_SPI1_RXD       PIN_CFG(214, ALT_B)
+
+#define GPIO215_GPIO           PIN_CFG(215, GPIO)
+#define GPIO215_MC1_CMDDIR     PIN_CFG(215, ALT_A)
+#define GPIO215_MC3_DAT2DIR    PIN_CFG(215, ALT_B)
+#define GPIO215_CLKOUT1                PIN_CFG(215, ALT_C)
+
+#define GPIO216_GPIO           PIN_CFG(216, GPIO)
+#define GPIO216_MC1_DAT2DIR    PIN_CFG(216, ALT_A)
+#define GPIO216_MC3_CMDDIR     PIN_CFG(216, ALT_B)
+#define GPIO216_I2C3_SDA       PIN_CFG_PULL(216, ALT_C, UP)
+
+#define GPIO217_GPIO           PIN_CFG(217, GPIO)
+#define GPIO217_MC1_DAT0DIR    PIN_CFG(217, ALT_A)
+#define GPIO217_MC3_DAT31DIR   PIN_CFG(217, ALT_B)
+#define GPIO217_CLKOUT2                PIN_CFG(217, ALT_C)
+
+#define GPIO218_GPIO           PIN_CFG(218, GPIO)
+#define GPIO218_MC1_DAT31DIR   PIN_CFG(218, ALT_A)
+#define GPIO218_MC3_DAT0DIR    PIN_CFG(218, ALT_B)
+#define GPIO218_I2C3_SCL       PIN_CFG_PULL(218, ALT_C, UP)
+
+#define GPIO219_GPIO           PIN_CFG(219, GPIO)
+#define GPIO219_HSIR_FLA0      PIN_CFG(219, ALT_A)
+#define GPIO219_MC3_CLK                PIN_CFG(219, ALT_B)
+
+#define GPIO220_GPIO           PIN_CFG(220, GPIO)
+#define GPIO220_HSIR_DAT0      PIN_CFG(220, ALT_A)
+#define GPIO220_MC3_FBCLK      PIN_CFG(220, ALT_B)
+#define GPIO220_SPI0_CLK       PIN_CFG(220, ALT_C)
+
+#define GPIO221_GPIO           PIN_CFG(221, GPIO)
+#define GPIO221_HSIR_RDY0      PIN_CFG(221, ALT_A)
+#define GPIO221_MC3_CMD                PIN_CFG(221, ALT_B)
+
+#define GPIO222_GPIO           PIN_CFG(222, GPIO)
+#define GPIO222_HSIT_FLA0      PIN_CFG(222, ALT_A)
+#define GPIO222_MC3_DAT0       PIN_CFG(222, ALT_B)
+
+#define GPIO223_GPIO           PIN_CFG(223, GPIO)
+#define GPIO223_HSIT_DAT0      PIN_CFG(223, ALT_A)
+#define GPIO223_MC3_DAT1       PIN_CFG(223, ALT_B)
+#define GPIO223_SPI0_FRM       PIN_CFG(223, ALT_C)
+
+#define GPIO224_GPIO           PIN_CFG(224, GPIO)
+#define GPIO224_HSIT_RDY0      PIN_CFG(224, ALT_A)
+#define GPIO224_MC3_DAT2       PIN_CFG(224, ALT_B)
+#define GPIO224_SPI0_TXD       PIN_CFG(224, ALT_C)
+
+#define GPIO225_GPIO           PIN_CFG(225, GPIO)
+#define GPIO225_HSIT_CAWAKE0   PIN_CFG(225, ALT_A)
+#define GPIO225_MC3_DAT3       PIN_CFG(225, ALT_B)
+#define GPIO225_SPI0_RXD       PIN_CFG(225, ALT_C)
+
+#define GPIO226_GPIO           PIN_CFG(226, GPIO)
+#define GPIO226_HSIT_ACWAKE0   PIN_CFG(226, ALT_A)
+#define GPIO226_PWL            PIN_CFG(226, ALT_B)
+#define GPIO226_USBSIM_PDC     PIN_CFG(226, ALT_C)
+
+#define GPIO227_GPIO           PIN_CFG(227, GPIO)
+#define GPIO227_CLKOUT1                PIN_CFG(227, ALT_A)
+
+#define GPIO228_GPIO           PIN_CFG(228, GPIO)
+#define GPIO228_CLKOUT2                PIN_CFG(228, ALT_A)
+
+#define GPIO229_GPIO           PIN_CFG(229, GPIO)
+#define GPIO229_CLKOUT1                PIN_CFG(229, ALT_A)
+#define GPIO229_PWL            PIN_CFG(229, ALT_B)
+#define GPIO229_I2C3_SDA       PIN_CFG_PULL(229, ALT_C, UP)
+
+#define GPIO230_GPIO           PIN_CFG(230, GPIO)
+#define GPIO230_CLKOUT2                PIN_CFG(230, ALT_A)
+#define GPIO230_PWL            PIN_CFG(230, ALT_B)
+#define GPIO230_I2C3_SCL       PIN_CFG_PULL(230, ALT_C, UP)
+
+#define GPIO256_GPIO           PIN_CFG(256, GPIO)
+#define GPIO256_USB_NXT                PIN_CFG(256, ALT_A)
+
+#define GPIO257_GPIO           PIN_CFG(257, GPIO)
+#define GPIO257_USB_STP                PIN_CFG(257, ALT_A)
+
+#define GPIO258_GPIO           PIN_CFG(258, GPIO)
+#define GPIO258_USB_XCLK       PIN_CFG(258, ALT_A)
+#define GPIO258_NONE           PIN_CFG(258, ALT_B)
+#define GPIO258_DDR_TRIG       PIN_CFG(258, ALT_C)
+
+#define GPIO259_GPIO           PIN_CFG(259, GPIO)
+#define GPIO259_USB_DIR                PIN_CFG(259, ALT_A)
+
+#define GPIO260_GPIO           PIN_CFG(260, GPIO)
+#define GPIO260_USB_DAT7       PIN_CFG(260, ALT_A)
+
+#define GPIO261_GPIO           PIN_CFG(261, GPIO)
+#define GPIO261_USB_DAT6       PIN_CFG(261, ALT_A)
+
+#define GPIO262_GPIO           PIN_CFG(262, GPIO)
+#define GPIO262_USB_DAT5       PIN_CFG(262, ALT_A)
+
+#define GPIO263_GPIO           PIN_CFG(263, GPIO)
+#define GPIO263_USB_DAT4       PIN_CFG(263, ALT_A)
+
+#define GPIO264_GPIO           PIN_CFG(264, GPIO)
+#define GPIO264_USB_DAT3       PIN_CFG(264, ALT_A)
+
+#define GPIO265_GPIO           PIN_CFG(265, GPIO)
+#define GPIO265_USB_DAT2       PIN_CFG(265, ALT_A)
+
+#define GPIO266_GPIO           PIN_CFG(266, GPIO)
+#define GPIO266_USB_DAT1       PIN_CFG(266, ALT_A)
+
+#define GPIO267_GPIO           PIN_CFG(267, GPIO)
+#define GPIO267_USB_DAT0       PIN_CFG(267, ALT_A)
+
+#endif

diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 3dff8641b03fa7a639d5f886345dad1e84706445..e38acb0f89c884b961bdb1dc11fa59b1a0112bc0 100644 (file)
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -28,6 +28,7 @@
 #include <linux/amba/clcd.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
+#include <linux/amba/pl022.h>
 #include <linux/io.h>
 #include <linux/gfp.h>
 
@@ -354,6 +355,21 @@ static struct mmci_platform_data mmc0_plat_data = {
        .gpio_cd        = -1,
 };
 
+static struct resource char_lcd_resources[] = {
+       {
+               .start = VERSATILE_CHAR_LCD_BASE,
+               .end   = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
+               .flags = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device char_lcd_device = {
+       .name           =       "arm-charlcd",
+       .id             =       -1,
+       .num_resources  =       ARRAY_SIZE(char_lcd_resources),
+       .resource       =       char_lcd_resources,
+};
+
 /*
  * Clock handling
  */
@@ -400,8 +416,13 @@ static struct clk ref24_clk = {
        .rate   = 24000000,
 };
 
+static struct clk dummy_apb_pclk;
+
 static struct clk_lookup lookups[] = {
-       {       /* UART0 */
+       {       /* AMBA bus clock */
+               .con_id         = "apb_pclk",
+               .clk            = &dummy_apb_pclk,
+       }, {    /* UART0 */
                .dev_id         = "dev:f1",
                .clk            = &ref24_clk,
        }, {    /* UART1 */
@@ -425,6 +446,9 @@ static struct clk_lookup lookups[] = {
        }, {    /* MMC1 */
                .dev_id         = "fpga:0b",
                .clk            = &ref24_clk,
+       }, {    /* SSP */
+               .dev_id         = "dev:f4",
+               .clk            = &ref24_clk,
        }, {    /* CLCD */
                .dev_id         = "dev:20",
                .clk            = &osc4_clk,
@@ -703,6 +727,12 @@ static struct pl061_platform_data gpio1_plat_data = {
        .irq_base       = IRQ_GPIO1_START,
 };
 
+static struct pl022_ssp_controller ssp0_plat_data = {
+       .bus_id = 0,
+       .enable_dma = 0,
+       .num_chipselect = 1,
+};
+
 #define AACI_IRQ       { IRQ_AACI, NO_IRQ }
 #define AACI_DMA       { 0x80, 0x81 }
 #define MMCI0_IRQ      { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
@@ -772,7 +802,7 @@ AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
 AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
 AMBA_DEVICE(uart1, "dev:f2",  UART1,    NULL);
 AMBA_DEVICE(uart2, "dev:f3",  UART2,    NULL);
-AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      NULL);
+AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      &ssp0_plat_data);
 
 static struct amba_device *amba_devs[] __initdata = {
        &dmac_device,
@@ -843,6 +873,7 @@ void __init versatile_init(void)
        platform_device_register(&versatile_flash_device);
        platform_device_register(&versatile_i2c_device);
        platform_device_register(&smc91x_device);
+       platform_device_register(&char_lcd_device);
 
        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
                struct amba_device *d = amba_devs[i];

diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
index 334f0df4e948bc46c322c3ca0c50fe8002b676c0..13c7e5f90a82eb1d4f52883e784eea8d08257546 100644 (file)
--- a/arch/arm/mach-versatile/pci.c
+++ b/arch/arm/mach-versatile/pci.c
@@ -304,7 +304,7 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
 }
 
 
-struct pci_bus *pci_versatile_scan_bus(int nr, struct pci_sys_data *sys)
+struct pci_bus * __init pci_versatile_scan_bus(int nr, struct pci_sys_data *sys)
 {
        return pci_scan_bus(sys->busnr, &pci_versatile_ops, sys);
 }

diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 6353459bb5671bc2623377529b9a6dfcd5db4a8f..577df6cccb0891503bf0188f3c0f33103c159000 100644 (file)
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -16,6 +16,7 @@
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/pmu.h>
+#include <asm/smp_twd.h>
 
 #include <mach/clkdev.h>
 #include <mach/ct-ca9x4.h>
@@ -53,6 +54,7 @@ static struct map_desc ct_ca9x4_io_desc[] __initdata = {
 
 static void __init ct_ca9x4_map_io(void)
 {
+       twd_base = MMIO_P2V(A9_MPCORE_TWD);
        v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
 }
 

diff --git a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
index 8650f04136efa0e744edb230f4d94afb1325f755..f9e2f8d229623d5825251e1999b0bf501a18b4a6 100644 (file)
--- a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
+++ b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
@@ -28,6 +28,7 @@
 #define A9_MPCORE_SCU          (CT_CA9X4_MPIC + 0x0000)
 #define A9_MPCORE_GIC_CPU      (CT_CA9X4_MPIC + 0x0100)
 #define A9_MPCORE_GIT          (CT_CA9X4_MPIC + 0x0200)
+#define A9_MPCORE_TWD          (CT_CA9X4_MPIC + 0x0600)
 #define A9_MPCORE_GIC_DIST     (CT_CA9X4_MPIC + 0x1000)
 
 /*

diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index c84239761cb4a2881d226f6f82b3acb694d30dae..817f0ad38a0b5100ec0884e8c908c84af471bec4 100644 (file)
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -298,8 +298,13 @@ static struct clk osc2_clk = {
        .rate   = 24000000,
 };
 
+static struct clk dummy_apb_pclk;
+
 static struct clk_lookup v2m_lookups[] = {
-       {       /* UART0 */
+       {       /* AMBA bus clock */
+               .con_id         = "apb_pclk",
+               .clk            = &dummy_apb_pclk,
+       }, {    /* UART0 */
                .dev_id         = "mb:uart0",
                .clk            = &osc2_clk,
        }, {    /* UART1 */

diff --git a/arch/arm/mach-w90x900/dev.c b/arch/arm/mach-w90x900/dev.c
index b2eda4dc1c34ea7172a773899275c18bbfab5dd4..7a1fa6adb7c32d5645b1f0e608b1e61794081afc 100644 (file)
--- a/arch/arm/mach-w90x900/dev.c
+++ b/arch/arm/mach-w90x900/dev.c
@@ -36,6 +36,8 @@
 #include <mach/nuc900_spi.h>
 #include <mach/map.h>
 #include <mach/fb.h>
+#include <mach/regs-ldm.h>
+#include <mach/w90p910_keypad.h>
 
 #include "cpu.h"
 
@@ -207,7 +209,7 @@ static struct nuc900_spi_info nuc900_spiflash_data = {
        .divider        = 24,
        .sleep          = 0,
        .txnum          = 0,
-       .txbitlen       = 1,
+       .txbitlen       = 8,
        .bus_num        = 0,
 };
 
@@ -256,7 +258,7 @@ static struct spi_board_info nuc900_spi_board_info[] __initdata = {
                .modalias = "m25p80",
                .max_speed_hz = 20000000,
                .bus_num = 0,
-               .chip_select = 1,
+               .chip_select = 0,
                .platform_data = &nuc900_spi_flash_data,
                .mode = SPI_MODE_0,
        },
@@ -361,6 +363,39 @@ struct platform_device nuc900_device_fmi = {
 
 /* KPI controller*/
 
+static int nuc900_keymap[] = {
+       KEY(0, 0, KEY_A),
+       KEY(0, 1, KEY_B),
+       KEY(0, 2, KEY_C),
+       KEY(0, 3, KEY_D),
+
+       KEY(1, 0, KEY_E),
+       KEY(1, 1, KEY_F),
+       KEY(1, 2, KEY_G),
+       KEY(1, 3, KEY_H),
+
+       KEY(2, 0, KEY_I),
+       KEY(2, 1, KEY_J),
+       KEY(2, 2, KEY_K),
+       KEY(2, 3, KEY_L),
+
+       KEY(3, 0, KEY_M),
+       KEY(3, 1, KEY_N),
+       KEY(3, 2, KEY_O),
+       KEY(3, 3, KEY_P),
+};
+
+static struct matrix_keymap_data nuc900_map_data = {
+       .keymap                 = nuc900_keymap,
+       .keymap_size            = ARRAY_SIZE(nuc900_keymap),
+};
+
+struct w90p910_keypad_platform_data nuc900_keypad_info = {
+       .keymap_data    = &nuc900_map_data,
+       .prescale       = 0xfa,
+       .debounce       = 0x50,
+};
+
 static struct resource nuc900_kpi_resource[] = {
        [0] = {
                .start = W90X900_PA_KPI,
@@ -380,9 +415,49 @@ struct platform_device nuc900_device_kpi = {
        .id             = -1,
        .num_resources  = ARRAY_SIZE(nuc900_kpi_resource),
        .resource       = nuc900_kpi_resource,
+       .dev            = {
+                               .platform_data = &nuc900_keypad_info,
+                       }
 };
 
-#ifdef CONFIG_FB_NUC900
+/* LCD controller*/
+
+static struct nuc900fb_display __initdata nuc900_lcd_info[] = {
+       /* Giantplus Technology GPM1040A0 320x240 Color TFT LCD */
+       [0] = {
+               .type           = LCM_DCCS_VA_SRC_RGB565,
+               .width          = 320,
+               .height         = 240,
+               .xres           = 320,
+               .yres           = 240,
+               .bpp            = 16,
+               .pixclock       = 200000,
+               .left_margin    = 34,
+               .right_margin   = 54,
+               .hsync_len      = 10,
+               .upper_margin   = 18,
+               .lower_margin   = 4,
+               .vsync_len      = 1,
+               .dccs           = 0x8e00041a,
+               .devctl         = 0x060800c0,
+               .fbctrl         = 0x00a000a0,
+               .scale          = 0x04000400,
+       },
+};
+
+static struct nuc900fb_mach_info nuc900_fb_info __initdata = {
+#if defined(CONFIG_GPM1040A0_320X240)
+       .displays               = &nuc900_lcd_info[0],
+#else
+       .displays               = nuc900_lcd_info,
+#endif
+       .num_displays           = ARRAY_SIZE(nuc900_lcd_info),
+       .default_display        = 0,
+       .gpio_dir               = 0x00000004,
+       .gpio_dir_mask          = 0xFFFFFFFD,
+       .gpio_data              = 0x00000004,
+       .gpio_data_mask         = 0xFFFFFFFD,
+};
 
 static struct resource nuc900_lcd_resource[] = {
        [0] = {
@@ -406,23 +481,10 @@ struct platform_device nuc900_device_lcd = {
        .dev              = {
                .dma_mask               = &nuc900_device_lcd_dmamask,
                .coherent_dma_mask      = -1,
+               .platform_data = &nuc900_fb_info,
        }
 };
 
-void  nuc900_fb_set_platdata(struct nuc900fb_mach_info *pd)
-{
-       struct nuc900fb_mach_info *npd;
-
-       npd = kmalloc(sizeof(*npd), GFP_KERNEL);
-       if (npd) {
-               memcpy(npd, pd, sizeof(*npd));
-               nuc900_device_lcd.dev.platform_data = npd;
-       } else {
-               printk(KERN_ERR "no memory for LCD platform data\n");
-       }
-}
-#endif
-
 /* AUDIO controller*/
 static u64 nuc900_device_audio_dmamask = -1;
 static struct resource nuc900_ac97_resource[] = {

diff --git a/arch/arm/mach-w90x900/include/mach/regs-gcr.h b/arch/arm/mach-w90x900/include/mach/regs-gcr.h
new file mode 100644 (file)
index 0000000..6087abd
--- /dev/null
+++ b/arch/arm/mach-w90x900/include/mach/regs-gcr.h
@@ -0,0 +1,39 @@
+/*
+ * arch/arm/mach-w90x900/include/mach/regs-gcr.h
+ *
+ * Copyright (c) 2010 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_REGS_GCR_H
+#define __ASM_ARCH_REGS_GCR_H
+
+/* Global control registers */
+
+#define GCR_BA         W90X900_VA_GCR
+#define REG_PDID       (GCR_BA+0x000)
+#define REG_PWRON      (GCR_BA+0x004)
+#define REG_ARBCON     (GCR_BA+0x008)
+#define REG_MFSEL      (GCR_BA+0x00C)
+#define REG_EBIDPE     (GCR_BA+0x010)
+#define REG_LCDDPE     (GCR_BA+0x014)
+#define REG_GPIOCPE    (GCR_BA+0x018)
+#define REG_GPIODPE    (GCR_BA+0x01C)
+#define REG_GPIOEPE    (GCR_BA+0x020)
+#define REG_GPIOFPE    (GCR_BA+0x024)
+#define REG_GPIOGPE    (GCR_BA+0x028)
+#define REG_GPIOHPE    (GCR_BA+0x02C)
+#define REG_GPIOIPE    (GCR_BA+0x030)
+#define REG_GTMP1      (GCR_BA+0x034)
+#define REG_GTMP2      (GCR_BA+0x038)
+#define REG_GTMP3      (GCR_BA+0x03C)
+
+#endif /*  __ASM_ARCH_REGS_GCR_H */

diff --git a/arch/arm/mach-w90x900/mach-nuc950evb.c b/arch/arm/mach-w90x900/mach-nuc950evb.c
index b3edc3cccf52f4c152ce9008e4d92fcc157c1584..04d295f89eb049f86ed0b8c6ba8386c5d0c0c09e 100644 (file)
--- a/arch/arm/mach-w90x900/mach-nuc950evb.c
+++ b/arch/arm/mach-w90x900/mach-nuc950evb.c
@@ -20,51 +20,10 @@
 #include <asm/mach/map.h>
 #include <asm/mach-types.h>
 #include <mach/map.h>
-#include <mach/regs-ldm.h>
 #include <mach/fb.h>
 
 #include "nuc950.h"
 
-#ifdef CONFIG_FB_NUC900
-/* LCD Controller */
-static struct nuc900fb_display __initdata nuc950_lcd_info[] = {
-       /* Giantplus Technology GPM1040A0 320x240 Color TFT LCD */
-       [0] = {
-               .type           = LCM_DCCS_VA_SRC_RGB565,
-               .width          = 320,
-               .height         = 240,
-               .xres           = 320,
-               .yres           = 240,
-               .bpp            = 16,
-               .pixclock       = 200000,
-               .left_margin    = 34,
-               .right_margin   = 54,
-               .hsync_len      = 10,
-               .upper_margin   = 18,
-               .lower_margin   = 4,
-               .vsync_len      = 1,
-               .dccs           = 0x8e00041a,
-               .devctl         = 0x060800c0,
-               .fbctrl         = 0x00a000a0,
-               .scale          = 0x04000400,
-       },
-};
-
-static struct nuc900fb_mach_info nuc950_fb_info __initdata = {
-#if defined(CONFIG_GPM1040A0_320X240)
-       .displays               = &nuc950_lcd_info[0],
-#else
-       .displays               = nuc950_lcd_info,
-#endif
-       .num_displays           = ARRAY_SIZE(nuc950_lcd_info),
-       .default_display        = 0,
-       .gpio_dir               = 0x00000004,
-       .gpio_dir_mask          = 0xFFFFFFFD,
-       .gpio_data              = 0x00000004,
-       .gpio_data_mask         = 0xFFFFFFFD,
-};
-#endif
-
 static void __init nuc950evb_map_io(void)
 {
        nuc950_map_io();
@@ -74,9 +33,6 @@ static void __init nuc950evb_map_io(void)
 static void __init nuc950evb_init(void)
 {
        nuc950_board_init();
-#ifdef CONFIG_FB_NUC900
-       nuc900_fb_set_platdata(&nuc950_fb_info);
-#endif
 }
 
 MACHINE_START(W90P950EVB, "W90P950EVB")

diff --git a/arch/arm/mach-w90x900/nuc910.c b/arch/arm/mach-w90x900/nuc910.c
index 656f03b3b629f28e8972d983f652a406ef7d7e94..1523f41369857a95ad8669679bae3ecf88820a00 100644 (file)
--- a/arch/arm/mach-w90x900/nuc910.c
+++ b/arch/arm/mach-w90x900/nuc910.c
@@ -26,6 +26,8 @@
 static struct platform_device *nuc910_dev[] __initdata = {
        &nuc900_device_ts,
        &nuc900_device_rtc,
+       &nuc900_device_lcd,
+       &nuc900_device_kpi,
 };
 
 /* define specific CPU platform io map */

diff --git a/arch/arm/mach-w90x900/nuc950.c b/arch/arm/mach-w90x900/nuc950.c
index 4d1f1ab044c48868d588b6081d8ebcabad98c7b5..5704f74a50eeaf768667c07669108396fdcd1fe0 100644 (file)
--- a/arch/arm/mach-w90x900/nuc950.c
+++ b/arch/arm/mach-w90x900/nuc950.c
@@ -26,9 +26,7 @@
 static struct platform_device *nuc950_dev[] __initdata = {
        &nuc900_device_kpi,
        &nuc900_device_fmi,
-#ifdef CONFIG_FB_NUC900
        &nuc900_device_lcd,
-#endif
 };
 
 /* define specific CPU platform io map */

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 101105e5261070118f8039c5ecbcde350792f38f..87ec141fcaa6e5ad0d5d7eef0e1a8249ac2bdcc3 100644 (file)
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -717,17 +717,6 @@ config TLS_REG_EMUL
          a few prototypes like that in existence) and therefore access to
          that required register must be emulated.
 
-config HAS_TLS_REG
-       bool
-       depends on !TLS_REG_EMUL
-       default y if SMP || CPU_32v7
-       help
-         This selects support for the CP15 thread register.
-         It is defined to be available on some ARMv6 processors (including
-         all SMP capable ARMv6's) or later processors.  User space may
-         assume directly accessing that register and always obtain the
-         expected value only on ARMv7 and above.
-
 config NEEDS_SYSCALL_FOR_CMPXCHG
        bool
        help

diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index e8d34a80851c66baf47c3d97e89e029e5e9a96ca..d63b6c413758a23389cbb09ea1ab8686c61e56db 100644 (file)
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -15,7 +15,6 @@ endif
 obj-$(CONFIG_MODULES)          += proc-syms.o
 
 obj-$(CONFIG_ALIGNMENT_TRAP)   += alignment.o
-obj-$(CONFIG_DISCONTIGMEM)     += discontig.o
 obj-$(CONFIG_HIGHMEM)          += highmem.o
 
 obj-$(CONFIG_CPU_ABRT_NOMMU)   += abort-nommu.o

diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 6f98c358989a63347a6a1150f99f25b52b106dbe..d073b64ae87ec4f6652c67959244292dbb3e69ad 100644 (file)
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -924,8 +924,20 @@ static int __init alignment_init(void)
                ai_usermode = UM_FIXUP;
        }
 
-       hook_fault_code(1, do_alignment, SIGILL, "alignment exception");
-       hook_fault_code(3, do_alignment, SIGILL, "alignment exception");
+       hook_fault_code(1, do_alignment, SIGBUS, BUS_ADRALN,
+                       "alignment exception");
+
+       /*
+        * ARMv6K and ARMv7 use fault status 3 (0b00011) as Access Flag section
+        * fault, not as alignment error.
+        *
+        * TODO: handle ARMv6K properly. Runtime check for 'K' extension is
+        * needed.
+        */
+       if (cpu_architecture() <= CPU_ARCH_ARMv6) {
+               hook_fault_code(3, do_alignment, SIGBUS, BUS_ADRALN,
+                               "alignment exception");
+       }
 
        return 0;
 }

diff --git a/arch/arm/mm/discontig.c b/arch/arm/mm/discontig.c
deleted file mode 100644 (file)
index c8c0c4b..0000000
--- a/arch/arm/mm/discontig.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * linux/arch/arm/mm/discontig.c
- *
- * Discontiguous memory support.
- *
- * Initial code: Copyright (C) 1999-2000 Nicolas Pitre
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/module.h>
-#include <linux/mmzone.h>
-#include <linux/bootmem.h>
-
-#if MAX_NUMNODES != 4 && MAX_NUMNODES != 16
-# error Fix Me Please
-#endif
-
-/*
- * Our node_data structure for discontiguous memory.
- */
-
-pg_data_t discontig_node_data[MAX_NUMNODES] = {
-  { .bdata = &bootmem_node_data[0] },
-  { .bdata = &bootmem_node_data[1] },
-  { .bdata = &bootmem_node_data[2] },
-  { .bdata = &bootmem_node_data[3] },
-#if MAX_NUMNODES == 16
-  { .bdata = &bootmem_node_data[4] },
-  { .bdata = &bootmem_node_data[5] },
-  { .bdata = &bootmem_node_data[6] },
-  { .bdata = &bootmem_node_data[7] },
-  { .bdata = &bootmem_node_data[8] },
-  { .bdata = &bootmem_node_data[9] },
-  { .bdata = &bootmem_node_data[10] },
-  { .bdata = &bootmem_node_data[11] },
-  { .bdata = &bootmem_node_data[12] },
-  { .bdata = &bootmem_node_data[13] },
-  { .bdata = &bootmem_node_data[14] },
-  { .bdata = &bootmem_node_data[15] },
-#endif
-};
-
-EXPORT_SYMBOL(discontig_node_data);

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 9e7742f0a102fe5c7d091134391db81d93d71726..c704eed63c5ddba4c5f849f7ab7b6420008cef21 100644 (file)
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -183,6 +183,8 @@ static void *
 __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot)
 {
        struct arm_vmregion *c;
+       size_t align;
+       int bit;
 
        if (!consistent_pte[0]) {
                printk(KERN_ERR "%s: not initialised\n", __func__);
@@ -190,10 +192,21 @@ __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot)
                return NULL;
        }
 
+       /*
+        * Align the virtual region allocation - maximum alignment is
+        * a section size, minimum is a page size.  This helps reduce
+        * fragmentation of the DMA space, and also prevents allocations
+        * smaller than a section from crossing a section boundary.
+        */
+       bit = fls(size - 1) + 1;
+       if (bit > SECTION_SHIFT)
+               bit = SECTION_SHIFT;
+       align = 1 << bit;
+
        /*
         * Allocate a virtual address in the consistent mapping region.
         */
-       c = arm_vmregion_alloc(&consistent_head, size,
+       c = arm_vmregion_alloc(&consistent_head, align, size,
                            gfp & ~(__GFP_DMA | __GFP_HIGHMEM));
        if (c) {
                pte_t *pte;

diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index cbfb2edcf7d12a3a1cae18f04c041d94dc055bcc..23b0b03af5ea84b8a01e10c59a97091d92f4618b 100644 (file)
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -413,7 +413,16 @@ do_translation_fault(unsigned long addr, unsigned int fsr,
        pmd_k = pmd_offset(pgd_k, addr);
        pmd   = pmd_offset(pgd, addr);
 
-       if (pmd_none(*pmd_k))
+       /*
+        * On ARM one Linux PGD entry contains two hardware entries (see page
+        * tables layout in pgtable.h). We normally guarantee that we always
+        * fill both L1 entries. But create_mapping() doesn't follow the rule.
+        * It can create inidividual L1 entries, so here we have to call
+        * pmd_none() check for the entry really corresponded to address, not
+        * for the first of pair.
+        */
+       index = (addr >> SECTION_SHIFT) & 1;
+       if (pmd_none(pmd_k[index]))
                goto bad_area;
 
        copy_pmd(pmd, pmd_k);
@@ -463,15 +472,10 @@ static struct fsr_info {
         * defines these to be "precise" aborts.
         */
        { do_bad,               SIGSEGV, 0,             "vector exception"                 },
-       { do_bad,               SIGILL,  BUS_ADRALN,    "alignment exception"              },
+       { do_bad,               SIGBUS,  BUS_ADRALN,    "alignment exception"              },
        { do_bad,               SIGKILL, 0,             "terminal exception"               },
-       { do_bad,               SIGILL,  BUS_ADRALN,    "alignment exception"              },
-/* Do we need runtime check ? */
-#if __LINUX_ARM_ARCH__ < 6
+       { do_bad,               SIGBUS,  BUS_ADRALN,    "alignment exception"              },
        { do_bad,               SIGBUS,  0,             "external abort on linefetch"      },
-#else
-       { do_translation_fault, SIGSEGV, SEGV_MAPERR,   "I-cache maintenance fault"        },
-#endif
        { do_translation_fault, SIGSEGV, SEGV_MAPERR,   "section translation fault"        },
        { do_bad,               SIGBUS,  0,             "external abort on linefetch"      },
        { do_page_fault,        SIGSEGV, SEGV_MAPERR,   "page translation fault"           },
@@ -508,13 +512,15 @@ static struct fsr_info {
 
 void __init
 hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int, struct pt_regs *),
-               int sig, const char *name)
+               int sig, int code, const char *name)
 {
-       if (nr >= 0 && nr < ARRAY_SIZE(fsr_info)) {
-               fsr_info[nr].fn   = fn;
-               fsr_info[nr].sig  = sig;
-               fsr_info[nr].name = name;
-       }
+       if (nr < 0 || nr >= ARRAY_SIZE(fsr_info))
+               BUG();
+
+       fsr_info[nr].fn   = fn;
+       fsr_info[nr].sig  = sig;
+       fsr_info[nr].code = code;
+       fsr_info[nr].name = name;
 }
 
 /*
@@ -594,3 +600,25 @@ do_PrefetchAbort(unsigned long addr, unsigned int ifsr, struct pt_regs *regs)
        arm_notify_die("", regs, &info, ifsr, 0);
 }
 
+static int __init exceptions_init(void)
+{
+       if (cpu_architecture() >= CPU_ARCH_ARMv6) {
+               hook_fault_code(4, do_translation_fault, SIGSEGV, SEGV_MAPERR,
+                               "I-cache maintenance fault");
+       }
+
+       if (cpu_architecture() >= CPU_ARCH_ARMv7) {
+               /*
+                * TODO: Access flag faults introduced in ARMv6K.
+                * Runtime check for 'K' extension is needed
+                */
+               hook_fault_code(3, do_bad, SIGSEGV, SEGV_MAPERR,
+                               "section access flag fault");
+               hook_fault_code(6, do_bad, SIGSEGV, SEGV_MAPERR,
+                               "section access flag fault");
+       }
+
+       return 0;
+}
+
+arch_initcall(exceptions_init);

diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index f6a9994653237ddc2a56c7c1fbd9070615cea937..7185b00650fe419d0fa0f43b3e79e2e0d90cf6e6 100644 (file)
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -17,6 +17,7 @@
 #include <linux/initrd.h>
 #include <linux/highmem.h>
 #include <linux/gfp.h>
+#include <linux/memblock.h>
 
 #include <asm/mach-types.h>
 #include <asm/sections.h>
@@ -79,38 +80,37 @@ struct meminfo meminfo;
 void show_mem(void)
 {
        int free = 0, total = 0, reserved = 0;
-       int shared = 0, cached = 0, slab = 0, node, i;
+       int shared = 0, cached = 0, slab = 0, i;
        struct meminfo * mi = &meminfo;
 
        printk("Mem-info:\n");
        show_free_areas();
-       for_each_online_node(node) {
-               for_each_nodebank (i,mi,node) {
-                       struct membank *bank = &mi->bank[i];
-                       unsigned int pfn1, pfn2;
-                       struct page *page, *end;
-
-                       pfn1 = bank_pfn_start(bank);
-                       pfn2 = bank_pfn_end(bank);
-
-                       page = pfn_to_page(pfn1);
-                       end  = pfn_to_page(pfn2 - 1) + 1;
-
-                       do {
-                               total++;
-                               if (PageReserved(page))
-                                       reserved++;
-                               else if (PageSwapCache(page))
-                                       cached++;
-                               else if (PageSlab(page))
-                                       slab++;
-                               else if (!page_count(page))
-                                       free++;
-                               else
-                                       shared += page_count(page) - 1;
-                               page++;
-                       } while (page < end);
-               }
+
+       for_each_bank (i, mi) {
+               struct membank *bank = &mi->bank[i];
+               unsigned int pfn1, pfn2;
+               struct page *page, *end;
+
+               pfn1 = bank_pfn_start(bank);
+               pfn2 = bank_pfn_end(bank);
+
+               page = pfn_to_page(pfn1);
+               end  = pfn_to_page(pfn2 - 1) + 1;
+
+               do {
+                       total++;
+                       if (PageReserved(page))
+                               reserved++;
+                       else if (PageSwapCache(page))
+                               cached++;
+                       else if (PageSlab(page))
+                               slab++;
+                       else if (!page_count(page))
+                               free++;
+                       else
+                               shared += page_count(page) - 1;
+                       page++;
+               } while (page < end);
        }
 
        printk("%d pages of RAM\n", total);
@@ -121,7 +121,7 @@ void show_mem(void)
        printk("%d pages swap cached\n", cached);
 }
 
-static void __init find_node_limits(int node, struct meminfo *mi,
+static void __init find_limits(struct meminfo *mi,
        unsigned long *min, unsigned long *max_low, unsigned long *max_high)
 {
        int i;
@@ -129,7 +129,7 @@ static void __init find_node_limits(int node, struct meminfo *mi,
        *min = -1UL;
        *max_low = *max_high = 0;
 
-       for_each_nodebank(i, mi, node) {
+       for_each_bank (i, mi) {
                struct membank *bank = &mi->bank[i];
                unsigned long start, end;
 
@@ -147,155 +147,64 @@ static void __init find_node_limits(int node, struct meminfo *mi,
        }
 }
 
-/*
- * FIXME: We really want to avoid allocating the bootmap bitmap
- * over the top of the initrd.  Hopefully, this is located towards
- * the start of a bank, so if we allocate the bootmap bitmap at
- * the end, we won't clash.
- */
-static unsigned int __init
-find_bootmap_pfn(int node, struct meminfo *mi, unsigned int bootmap_pages)
-{
-       unsigned int start_pfn, i, bootmap_pfn;
-
-       start_pfn   = PAGE_ALIGN(__pa(_end)) >> PAGE_SHIFT;
-       bootmap_pfn = 0;
-
-       for_each_nodebank(i, mi, node) {
-               struct membank *bank = &mi->bank[i];
-               unsigned int start, end;
-
-               start = bank_pfn_start(bank);
-               end   = bank_pfn_end(bank);
-
-               if (end < start_pfn)
-                       continue;
-
-               if (start < start_pfn)
-                       start = start_pfn;
-
-               if (end <= start)
-                       continue;
-
-               if (end - start >= bootmap_pages) {
-                       bootmap_pfn = start;
-                       break;
-               }
-       }
-
-       if (bootmap_pfn == 0)
-               BUG();
-
-       return bootmap_pfn;
-}
-
-static int __init check_initrd(struct meminfo *mi)
-{
-       int initrd_node = -2;
-#ifdef CONFIG_BLK_DEV_INITRD
-       unsigned long end = phys_initrd_start + phys_initrd_size;
-
-       /*
-        * Make sure that the initrd is within a valid area of
-        * memory.
-        */
-       if (phys_initrd_size) {
-               unsigned int i;
-
-               initrd_node = -1;
-
-               for (i = 0; i < mi->nr_banks; i++) {
-                       struct membank *bank = &mi->bank[i];
-                       if (bank_phys_start(bank) <= phys_initrd_start &&
-                           end <= bank_phys_end(bank))
-                               initrd_node = bank->node;
-               }
-       }
-
-       if (initrd_node == -1) {
-               printk(KERN_ERR "INITRD: 0x%08lx+0x%08lx extends beyond "
-                      "physical memory - disabling initrd\n",
-                      phys_initrd_start, phys_initrd_size);
-               phys_initrd_start = phys_initrd_size = 0;
-       }
-#endif
-
-       return initrd_node;
-}
-
-static void __init bootmem_init_node(int node, struct meminfo *mi,
+static void __init arm_bootmem_init(struct meminfo *mi,
        unsigned long start_pfn, unsigned long end_pfn)
 {
-       unsigned long boot_pfn;
        unsigned int boot_pages;
+       phys_addr_t bitmap;
        pg_data_t *pgdat;
        int i;
 
        /*
-        * Allocate the bootmem bitmap page.
+        * Allocate the bootmem bitmap page.  This must be in a region
+        * of memory which has already been mapped.
         */
        boot_pages = bootmem_bootmap_pages(end_pfn - start_pfn);
-       boot_pfn = find_bootmap_pfn(node, mi, boot_pages);
+       bitmap = memblock_alloc_base(boot_pages << PAGE_SHIFT, L1_CACHE_BYTES,
+                               __pfn_to_phys(end_pfn));
 
        /*
-        * Initialise the bootmem allocator for this node, handing the
+        * Initialise the bootmem allocator, handing the
         * memory banks over to bootmem.
         */
-       node_set_online(node);
-       pgdat = NODE_DATA(node);
-       init_bootmem_node(pgdat, boot_pfn, start_pfn, end_pfn);
+       node_set_online(0);
+       pgdat = NODE_DATA(0);
+       init_bootmem_node(pgdat, __phys_to_pfn(bitmap), start_pfn, end_pfn);
 
-       for_each_nodebank(i, mi, node) {
+       for_each_bank(i, mi) {
                struct membank *bank = &mi->bank[i];
                if (!bank->highmem)
-                       free_bootmem_node(pgdat, bank_phys_start(bank), bank_phys_size(bank));
+                       free_bootmem(bank_phys_start(bank), bank_phys_size(bank));
        }
 
        /*
-        * Reserve the bootmem bitmap for this node.
+        * Reserve the memblock reserved regions in bootmem.
         */
-       reserve_bootmem_node(pgdat, boot_pfn << PAGE_SHIFT,
-                            boot_pages << PAGE_SHIFT, BOOTMEM_DEFAULT);
-}
-
-static void __init bootmem_reserve_initrd(int node)
-{
-#ifdef CONFIG_BLK_DEV_INITRD
-       pg_data_t *pgdat = NODE_DATA(node);
-       int res;
-
-       res = reserve_bootmem_node(pgdat, phys_initrd_start,
-                            phys_initrd_size, BOOTMEM_EXCLUSIVE);
-
-       if (res == 0) {
-               initrd_start = __phys_to_virt(phys_initrd_start);
-               initrd_end = initrd_start + phys_initrd_size;
-       } else {
-               printk(KERN_ERR
-                       "INITRD: 0x%08lx+0x%08lx overlaps in-use "
-                       "memory region - disabling initrd\n",
-                       phys_initrd_start, phys_initrd_size);
+       for (i = 0; i < memblock.reserved.cnt; i++) {
+               phys_addr_t start = memblock_start_pfn(&memblock.reserved, i);
+               if (start >= start_pfn &&
+                   memblock_end_pfn(&memblock.reserved, i) <= end_pfn)
+                       reserve_bootmem_node(pgdat, __pfn_to_phys(start),
+                               memblock_size_bytes(&memblock.reserved, i),
+                               BOOTMEM_DEFAULT);
        }
-#endif
 }
 
-static void __init bootmem_free_node(int node, struct meminfo *mi)
+static void __init arm_bootmem_free(struct meminfo *mi, unsigned long min,
+       unsigned long max_low, unsigned long max_high)
 {
        unsigned long zone_size[MAX_NR_ZONES], zhole_size[MAX_NR_ZONES];
-       unsigned long min, max_low, max_high;
        int i;
 
-       find_node_limits(node, mi, &min, &max_low, &max_high);
-
        /*
-        * initialise the zones within this node.
+        * initialise the zones.
         */
        memset(zone_size, 0, sizeof(zone_size));
 
        /*
-        * The size of this node has already been determined.  If we need
-        * to do anything fancy with the allocation of this memory to the
-        * zones, now is the time to do it.
+        * The memory size has already been determined.  If we need
+        * to do anything fancy with the allocation of this memory
+        * to the zones, now is the time to do it.
         */
        zone_size[0] = max_low - min;
 #ifdef CONFIG_HIGHMEM
@@ -303,11 +212,11 @@ static void __init bootmem_free_node(int node, struct meminfo *mi)
 #endif
 
        /*
-        * For each bank in this node, calculate the size of the holes.
-        *  holes = node_size - sum(bank_sizes_in_node)
+        * Calculate the size of the holes.
+        *  holes = node_size - sum(bank_sizes)
         */
        memcpy(zhole_size, zone_size, sizeof(zhole_size));
-       for_each_nodebank(i, mi, node) {
+       for_each_bank(i, mi) {
                int idx = 0;
 #ifdef CONFIG_HIGHMEM
                if (mi->bank[i].highmem)
@@ -320,24 +229,23 @@ static void __init bootmem_free_node(int node, struct meminfo *mi)
         * Adjust the sizes according to any special requirements for
         * this machine type.
         */
-       arch_adjust_zones(node, zone_size, zhole_size);
+       arch_adjust_zones(zone_size, zhole_size);
 
-       free_area_init_node(node, zone_size, min, zhole_size);
+       free_area_init_node(0, zone_size, min, zhole_size);
 }
 
 #ifndef CONFIG_SPARSEMEM
 int pfn_valid(unsigned long pfn)
 {
-       struct meminfo *mi = &meminfo;
-       unsigned int left = 0, right = mi->nr_banks;
+       struct memblock_region *mem = &memblock.memory;
+       unsigned int left = 0, right = mem->cnt;
 
        do {
                unsigned int mid = (right + left) / 2;
-               struct membank *bank = &mi->bank[mid];
 
-               if (pfn < bank_pfn_start(bank))
+               if (pfn < memblock_start_pfn(mem, mid))
                        right = mid;
-               else if (pfn >= bank_pfn_end(bank))
+               else if (pfn >= memblock_end_pfn(mem, mid))
                        left = mid + 1;
                else
                        return 1;
@@ -346,73 +254,69 @@ int pfn_valid(unsigned long pfn)
 }
 EXPORT_SYMBOL(pfn_valid);
 
-static void arm_memory_present(struct meminfo *mi, int node)
+static void arm_memory_present(void)
 {
 }
 #else
-static void arm_memory_present(struct meminfo *mi, int node)
+static void arm_memory_present(void)
 {
        int i;
-       for_each_nodebank(i, mi, node) {
-               struct membank *bank = &mi->bank[i];
-               memory_present(node, bank_pfn_start(bank), bank_pfn_end(bank));
-       }
+       for (i = 0; i < memblock.memory.cnt; i++)
+               memory_present(0, memblock_start_pfn(&memblock.memory, i),
+                                 memblock_end_pfn(&memblock.memory, i));
 }
 #endif
 
-void __init bootmem_init(void)
+void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc)
 {
-       struct meminfo *mi = &meminfo;
-       unsigned long min, max_low, max_high;
-       int node, initrd_node;
+       int i;
 
-       /*
-        * Locate which node contains the ramdisk image, if any.
-        */
-       initrd_node = check_initrd(mi);
+       memblock_init();
+       for (i = 0; i < mi->nr_banks; i++)
+               memblock_add(mi->bank[i].start, mi->bank[i].size);
 
-       max_low = max_high = 0;
+       /* Register the kernel text, kernel data and initrd with memblock. */
+#ifdef CONFIG_XIP_KERNEL
+       memblock_reserve(__pa(_data), _end - _data);
+#else
+       memblock_reserve(__pa(_stext), _end - _stext);
+#endif
+#ifdef CONFIG_BLK_DEV_INITRD
+       if (phys_initrd_size) {
+               memblock_reserve(phys_initrd_start, phys_initrd_size);
 
-       /*
-        * Run through each node initialising the bootmem allocator.
-        */
-       for_each_node(node) {
-               unsigned long node_low, node_high;
+               /* Now convert initrd to virtual addresses */
+               initrd_start = __phys_to_virt(phys_initrd_start);
+               initrd_end = initrd_start + phys_initrd_size;
+       }
+#endif
 
-               find_node_limits(node, mi, &min, &node_low, &node_high);
+       arm_mm_memblock_reserve();
 
-               if (node_low > max_low)
-                       max_low = node_low;
-               if (node_high > max_high)
-                       max_high = node_high;
+       /* reserve any platform specific memblock areas */
+       if (mdesc->reserve)
+               mdesc->reserve();
 
-               /*
-                * If there is no memory in this node, ignore it.
-                * (We can't have nodes which have no lowmem)
-                */
-               if (node_low == 0)
-                       continue;
+       memblock_analyze();
+       memblock_dump_all();
+}
 
-               bootmem_init_node(node, mi, min, node_low);
+void __init bootmem_init(void)
+{
+       struct meminfo *mi = &meminfo;
+       unsigned long min, max_low, max_high;
 
-               /*
-                * Reserve any special node zero regions.
-                */
-               if (node == 0)
-                       reserve_node_zero(NODE_DATA(node));
+       max_low = max_high = 0;
 
-               /*
-                * If the initrd is in this node, reserve its memory.
-                */
-               if (node == initrd_node)
-                       bootmem_reserve_initrd(node);
+       find_limits(mi, &min, &max_low, &max_high);
 
-               /*
-                * Sparsemem tries to allocate bootmem in memory_present(),
-                * so must be done after the fixed reservations
-                */
-               arm_memory_present(mi, node);
-       }
+       arm_bootmem_init(mi, min, max_low);
+
+       /*
+        * Sparsemem tries to allocate bootmem in memory_present(),
+        * so must be done after the fixed reservations
+        */
+       arm_memory_present();
 
        /*
         * sparse_init() needs the bootmem allocator up and running.
@@ -420,12 +324,11 @@ void __init bootmem_init(void)
        sparse_init();
 
        /*
-        * Now free memory in each node - free_area_init_node needs
+        * Now free the memory - free_area_init_node needs
         * the sparse mem_map arrays initialized by sparse_init()
         * for memmap_init_zone(), otherwise all PFNs are invalid.
         */
-       for_each_node(node)
-               bootmem_free_node(node, mi);
+       arm_bootmem_free(mi, min, max_low, max_high);
 
        high_memory = __va((max_low << PAGE_SHIFT) - 1) + 1;
 
@@ -460,7 +363,7 @@ static inline int free_area(unsigned long pfn, unsigned long end, char *s)
 }
 
 static inline void
-free_memmap(int node, unsigned long start_pfn, unsigned long end_pfn)
+free_memmap(unsigned long start_pfn, unsigned long end_pfn)
 {
        struct page *start_pg, *end_pg;
        unsigned long pg, pgend;
@@ -483,40 +386,39 @@ free_memmap(int node, unsigned long start_pfn, unsigned long end_pfn)
         * free the section of the memmap array.
         */
        if (pg < pgend)
-               free_bootmem_node(NODE_DATA(node), pg, pgend - pg);
+               free_bootmem(pg, pgend - pg);
 }
 
 /*
  * The mem_map array can get very big.  Free the unused area of the memory map.
  */
-static void __init free_unused_memmap_node(int node, struct meminfo *mi)
+static void __init free_unused_memmap(struct meminfo *mi)
 {
        unsigned long bank_start, prev_bank_end = 0;
        unsigned int i;
 
        /*
-        * [FIXME] This relies on each bank being in address order.  This
-        * may not be the case, especially if the user has provided the
-        * information on the command line.
+        * This relies on each bank being in address order.
+        * The banks are sorted previously in bootmem_init().
         */
-       for_each_nodebank(i, mi, node) {
+       for_each_bank(i, mi) {
                struct membank *bank = &mi->bank[i];
 
                bank_start = bank_pfn_start(bank);
-               if (bank_start < prev_bank_end) {
-                       printk(KERN_ERR "MEM: unordered memory banks.  "
-                               "Not freeing memmap.\n");
-                       break;
-               }
 
                /*
                 * If we had a previous bank, and there is a space
                 * between the current bank and the previous, free it.
                 */
-               if (prev_bank_end && prev_bank_end != bank_start)
-                       free_memmap(node, prev_bank_end, bank_start);
+               if (prev_bank_end && prev_bank_end < bank_start)
+                       free_memmap(prev_bank_end, bank_start);
 
-               prev_bank_end = bank_pfn_end(bank);
+               /*
+                * Align up here since the VM subsystem insists that the
+                * memmap entries are valid from the bank end aligned to
+                * MAX_ORDER_NR_PAGES.
+                */
+               prev_bank_end = ALIGN(bank_pfn_end(bank), MAX_ORDER_NR_PAGES);
        }
 }
 
@@ -528,21 +430,19 @@ static void __init free_unused_memmap_node(int node, struct meminfo *mi)
 void __init mem_init(void)
 {
        unsigned long reserved_pages, free_pages;
-       int i, node;
+       int i;
+#ifdef CONFIG_HAVE_TCM
+       /* These pointers are filled in on TCM detection */
+       extern u32 dtcm_end;
+       extern u32 itcm_end;
+#endif
 
-#ifndef CONFIG_DISCONTIGMEM
        max_mapnr   = pfn_to_page(max_pfn + PHYS_PFN_OFFSET) - mem_map;
-#endif
 
        /* this will put all unused low memory onto the freelists */
-       for_each_online_node(node) {
-               pg_data_t *pgdat = NODE_DATA(node);
+       free_unused_memmap(&meminfo);
 
-               free_unused_memmap_node(node, &meminfo);
-
-               if (pgdat->node_spanned_pages != 0)
-                       totalram_pages += free_all_bootmem_node(pgdat);
-       }
+       totalram_pages += free_all_bootmem();
 
 #ifdef CONFIG_SA1111
        /* now that our DMA memory is actually so designated, we can free it */
@@ -552,39 +452,35 @@ void __init mem_init(void)
 
 #ifdef CONFIG_HIGHMEM
        /* set highmem page free */
-       for_each_online_node(node) {
-               for_each_nodebank (i, &meminfo, node) {
-                       unsigned long start = bank_pfn_start(&meminfo.bank[i]);
-                       unsigned long end = bank_pfn_end(&meminfo.bank[i]);
-                       if (start >= max_low_pfn + PHYS_PFN_OFFSET)
-                               totalhigh_pages += free_area(start, end, NULL);
-               }
+       for_each_bank (i, &meminfo) {
+               unsigned long start = bank_pfn_start(&meminfo.bank[i]);
+               unsigned long end = bank_pfn_end(&meminfo.bank[i]);
+               if (start >= max_low_pfn + PHYS_PFN_OFFSET)
+                       totalhigh_pages += free_area(start, end, NULL);
        }
        totalram_pages += totalhigh_pages;
 #endif
 
        reserved_pages = free_pages = 0;
 
-       for_each_online_node(node) {
-               for_each_nodebank(i, &meminfo, node) {
-                       struct membank *bank = &meminfo.bank[i];
-                       unsigned int pfn1, pfn2;
-                       struct page *page, *end;
-
-                       pfn1 = bank_pfn_start(bank);
-                       pfn2 = bank_pfn_end(bank);
-
-                       page = pfn_to_page(pfn1);
-                       end  = pfn_to_page(pfn2 - 1) + 1;
-
-                       do {
-                               if (PageReserved(page))
-                                       reserved_pages++;
-                               else if (!page_count(page))
-                                       free_pages++;
-                               page++;
-                       } while (page < end);
-               }
+       for_each_bank(i, &meminfo) {
+               struct membank *bank = &meminfo.bank[i];
+               unsigned int pfn1, pfn2;
+               struct page *page, *end;
+
+               pfn1 = bank_pfn_start(bank);
+               pfn2 = bank_pfn_end(bank);
+
+               page = pfn_to_page(pfn1);
+               end  = pfn_to_page(pfn2 - 1) + 1;
+
+               do {
+                       if (PageReserved(page))
+                               reserved_pages++;
+                       else if (!page_count(page))
+                               free_pages++;
+                       page++;
+               } while (page < end);
        }
 
        /*
@@ -611,6 +507,10 @@ void __init mem_init(void)
 
        printk(KERN_NOTICE "Virtual kernel memory layout:\n"
                        "    vector  : 0x%08lx - 0x%08lx   (%4ld kB)\n"
+#ifdef CONFIG_HAVE_TCM
+                       "    DTCM    : 0x%08lx - 0x%08lx   (%4ld kB)\n"
+                       "    ITCM    : 0x%08lx - 0x%08lx   (%4ld kB)\n"
+#endif
                        "    fixmap  : 0x%08lx - 0x%08lx   (%4ld kB)\n"
 #ifdef CONFIG_MMU
                        "    DMA     : 0x%08lx - 0x%08lx   (%4ld MB)\n"
@@ -627,6 +527,10 @@ void __init mem_init(void)
 
                        MLK(UL(CONFIG_VECTORS_BASE), UL(CONFIG_VECTORS_BASE) +
                                (PAGE_SIZE)),
+#ifdef CONFIG_HAVE_TCM
+                       MLK(DTCM_OFFSET, (unsigned long) dtcm_end),
+                       MLK(ITCM_OFFSET, (unsigned long) itcm_end),
+#endif
                        MLK(FIXADDR_START, FIXADDR_TOP),
 #ifdef CONFIG_MMU
                        MLM(CONSISTENT_BASE, CONSISTENT_END),

diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 28c8b950ef04e84f6d0893712fb22c5394808ee6..ab506272b2d3ef459b264b7741d61af46f6aa6b8 100644 (file)
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -42,78 +42,11 @@
  */
 #define VM_ARM_SECTION_MAPPING 0x80000000
 
-static int remap_area_pte(pmd_t *pmd, unsigned long addr, unsigned long end,
-                         unsigned long phys_addr, const struct mem_type *type)
-{
-       pgprot_t prot = __pgprot(type->prot_pte);
-       pte_t *pte;
-
-       pte = pte_alloc_kernel(pmd, addr);
-       if (!pte)
-               return -ENOMEM;
-
-       do {
-               if (!pte_none(*pte))
-                       goto bad;
-
-               set_pte_ext(pte, pfn_pte(phys_addr >> PAGE_SHIFT, prot), 0);
-               phys_addr += PAGE_SIZE;
-       } while (pte++, addr += PAGE_SIZE, addr != end);
-       return 0;
-
- bad:
-       printk(KERN_CRIT "remap_area_pte: page already exists\n");
-       BUG();
-}
-
-static inline int remap_area_pmd(pgd_t *pgd, unsigned long addr,
-                                unsigned long end, unsigned long phys_addr,
-                                const struct mem_type *type)
-{
-       unsigned long next;
-       pmd_t *pmd;
-       int ret = 0;
-
-       pmd = pmd_alloc(&init_mm, pgd, addr);
-       if (!pmd)
-               return -ENOMEM;
-
-       do {
-               next = pmd_addr_end(addr, end);
-               ret = remap_area_pte(pmd, addr, next, phys_addr, type);
-               if (ret)
-                       return ret;
-               phys_addr += next - addr;
-       } while (pmd++, addr = next, addr != end);
-       return ret;
-}
-
-static int remap_area_pages(unsigned long start, unsigned long pfn,
-                           size_t size, const struct mem_type *type)
-{
-       unsigned long addr = start;
-       unsigned long next, end = start + size;
-       unsigned long phys_addr = __pfn_to_phys(pfn);
-       pgd_t *pgd;
-       int err = 0;
-
-       BUG_ON(addr >= end);
-       pgd = pgd_offset_k(addr);
-       do {
-               next = pgd_addr_end(addr, end);
-               err = remap_area_pmd(pgd, addr, next, phys_addr, type);
-               if (err)
-                       break;
-               phys_addr += next - addr;
-       } while (pgd++, addr = next, addr != end);
-
-       return err;
-}
-
 int ioremap_page(unsigned long virt, unsigned long phys,
                 const struct mem_type *mtype)
 {
-       return remap_area_pages(virt, __phys_to_pfn(phys), PAGE_SIZE, mtype);
+       return ioremap_page_range(virt, virt + PAGE_SIZE, phys,
+                                 __pgprot(mtype->prot_pte));
 }
 EXPORT_SYMBOL(ioremap_page);
 
@@ -268,6 +201,12 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
        if (pfn >= 0x100000 && (__pfn_to_phys(pfn) & ~SUPERSECTION_MASK))
                return NULL;
 
+       /*
+        * Don't allow RAM to be mapped - this causes problems with ARMv6+
+        */
+       if (WARN_ON(pfn_valid(pfn)))
+               return NULL;
+
        type = get_mem_type(mtype);
        if (!type)
                return NULL;
@@ -294,7 +233,8 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
                err = remap_area_sections(addr, pfn, size, type);
        } else
 #endif
-               err = remap_area_pages(addr, pfn, size, type);
+               err = ioremap_page_range(addr, addr + size, __pfn_to_phys(pfn),
+                                        __pgprot(type->prot_pte));
 
        if (err) {
                vunmap((void *)addr);

diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index 815d08eecbb0f69a15a46f6990c481fd49dae779..6630620380a4aa0f538aed006a2de6f04c71d3dd 100644 (file)
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -28,7 +28,5 @@ extern void __flush_dcache_page(struct address_space *mapping, struct page *page
 
 #endif
 
-struct pglist_data;
-
 void __init bootmem_init(void);
-void reserve_node_zero(struct pglist_data *pgdat);
+void arm_mm_memblock_reserve(void);

diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
index f5abc51c5a07ff24e047ef333c7dd47b942fc3a4..4f5b39687df541a417d4c3a9ac888fc53a31b999 100644 (file)
--- a/arch/arm/mm/mmap.c
+++ b/arch/arm/mm/mmap.c
@@ -7,6 +7,7 @@
 #include <linux/shm.h>
 #include <linux/sched.h>
 #include <linux/io.h>
+#include <linux/random.h>
 #include <asm/cputype.h>
 #include <asm/system.h>
 
@@ -80,6 +81,9 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
                start_addr = addr = TASK_UNMAPPED_BASE;
                mm->cached_hole_size = 0;
        }
+       /* 8 bits of randomness in 20 address space bits */
+       if (current->flags & PF_RANDOMIZE)
+               addr += (get_random_int() % (1 << 8)) << PAGE_SHIFT;
 
 full_search:
        if (do_align)

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 28589417118643aec349aff677e3c1e0be53efa3..6e1c4f6a2b3f3a09ed3f10be9aeafab36c9a0924 100644 (file)
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -11,13 +11,12 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/init.h>
-#include <linux/bootmem.h>
 #include <linux/mman.h>
 #include <linux/nodemask.h>
+#include <linux/memblock.h>
 #include <linux/sort.h>
 
 #include <asm/cputype.h>
-#include <asm/mach-types.h>
 #include <asm/sections.h>
 #include <asm/cachetype.h>
 #include <asm/setup.h>
@@ -258,6 +257,19 @@ static struct mem_type mem_types[] = {
                .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
                .domain    = DOMAIN_KERNEL,
        },
+       [MT_MEMORY_DTCM] = {
+               .prot_pte       = L_PTE_PRESENT | L_PTE_YOUNG |
+                                 L_PTE_DIRTY | L_PTE_WRITE,
+               .prot_l1        = PMD_TYPE_TABLE,
+               .prot_sect      = PMD_TYPE_SECT | PMD_SECT_XN,
+               .domain         = DOMAIN_KERNEL,
+       },
+       [MT_MEMORY_ITCM] = {
+               .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
+                               L_PTE_USER | L_PTE_EXEC,
+               .prot_l1   = PMD_TYPE_TABLE,
+               .domain    = DOMAIN_IO,
+       },
 };
 
 const struct mem_type *get_mem_type(unsigned int type)
@@ -488,18 +500,28 @@ static void __init build_mem_type_table(void)
 
 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
 
-static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
-                                 unsigned long end, unsigned long pfn,
-                                 const struct mem_type *type)
+static void __init *early_alloc(unsigned long sz)
 {
-       pte_t *pte;
+       void *ptr = __va(memblock_alloc(sz, sz));
+       memset(ptr, 0, sz);
+       return ptr;
+}
 
+static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
+{
        if (pmd_none(*pmd)) {
-               pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t));
-               __pmd_populate(pmd, __pa(pte) | type->prot_l1);
+               pte_t *pte = early_alloc(2 * PTRS_PER_PTE * sizeof(pte_t));
+               __pmd_populate(pmd, __pa(pte) | prot);
        }
+       BUG_ON(pmd_bad(*pmd));
+       return pte_offset_kernel(pmd, addr);
+}
 
-       pte = pte_offset_kernel(pmd, addr);
+static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
+                                 unsigned long end, unsigned long pfn,
+                                 const struct mem_type *type)
+{
+       pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
        do {
                set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
                pfn++;
@@ -668,7 +690,7 @@ void __init iotable_init(struct map_desc *io_desc, int nr)
                create_mapping(io_desc + i);
 }
 
-static unsigned long __initdata vmalloc_reserve = SZ_128M;
+static void * __initdata vmalloc_min = (void *)(VMALLOC_END - SZ_128M);
 
 /*
  * vmalloc=size forces the vmalloc area to be exactly 'size'
@@ -677,7 +699,7 @@ static unsigned long __initdata vmalloc_reserve = SZ_128M;
  */
 static int __init early_vmalloc(char *arg)
 {
-       vmalloc_reserve = memparse(arg, NULL);
+       unsigned long vmalloc_reserve = memparse(arg, NULL);
 
        if (vmalloc_reserve < SZ_16M) {
                vmalloc_reserve = SZ_16M;
@@ -692,22 +714,26 @@ static int __init early_vmalloc(char *arg)
                        "vmalloc area is too big, limiting to %luMB\n",
                        vmalloc_reserve >> 20);
        }
+
+       vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
        return 0;
 }
 early_param("vmalloc", early_vmalloc);
 
-#define VMALLOC_MIN    (void *)(VMALLOC_END - vmalloc_reserve)
+phys_addr_t lowmem_end_addr;
 
 static void __init sanity_check_meminfo(void)
 {
        int i, j, highmem = 0;
 
+       lowmem_end_addr = __pa(vmalloc_min - 1) + 1;
+
        for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
                struct membank *bank = &meminfo.bank[j];
                *bank = meminfo.bank[i];
 
 #ifdef CONFIG_HIGHMEM
-               if (__va(bank->start) > VMALLOC_MIN ||
+               if (__va(bank->start) > vmalloc_min ||
                    __va(bank->start) < (void *)PAGE_OFFSET)
                        highmem = 1;
 
@@ -717,8 +743,8 @@ static void __init sanity_check_meminfo(void)
                 * Split those memory banks which are partially overlapping
                 * the vmalloc area greatly simplifying things later.
                 */
-               if (__va(bank->start) < VMALLOC_MIN &&
-                   bank->size > VMALLOC_MIN - __va(bank->start)) {
+               if (__va(bank->start) < vmalloc_min &&
+                   bank->size > vmalloc_min - __va(bank->start)) {
                        if (meminfo.nr_banks >= NR_BANKS) {
                                printk(KERN_CRIT "NR_BANKS too low, "
                                                 "ignoring high memory\n");
@@ -727,12 +753,12 @@ static void __init sanity_check_meminfo(void)
                                        (meminfo.nr_banks - i) * sizeof(*bank));
                                meminfo.nr_banks++;
                                i++;
-                               bank[1].size -= VMALLOC_MIN - __va(bank->start);
-                               bank[1].start = __pa(VMALLOC_MIN - 1) + 1;
+                               bank[1].size -= vmalloc_min - __va(bank->start);
+                               bank[1].start = __pa(vmalloc_min - 1) + 1;
                                bank[1].highmem = highmem = 1;
                                j++;
                        }
-                       bank->size = VMALLOC_MIN - __va(bank->start);
+                       bank->size = vmalloc_min - __va(bank->start);
                }
 #else
                bank->highmem = highmem;
@@ -741,7 +767,7 @@ static void __init sanity_check_meminfo(void)
                 * Check whether this memory bank would entirely overlap
                 * the vmalloc area.
                 */
-               if (__va(bank->start) >= VMALLOC_MIN ||
+               if (__va(bank->start) >= vmalloc_min ||
                    __va(bank->start) < (void *)PAGE_OFFSET) {
                        printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx "
                               "(vmalloc region overlap).\n",
@@ -753,9 +779,9 @@ static void __init sanity_check_meminfo(void)
                 * Check whether this memory bank would partially overlap
                 * the vmalloc area.
                 */
-               if (__va(bank->start + bank->size) > VMALLOC_MIN ||
+               if (__va(bank->start + bank->size) > vmalloc_min ||
                    __va(bank->start + bank->size) < __va(bank->start)) {
-                       unsigned long newsize = VMALLOC_MIN - __va(bank->start);
+                       unsigned long newsize = vmalloc_min - __va(bank->start);
                        printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx "
                               "to -%.8lx (vmalloc region overlap).\n",
                               bank->start, bank->start + bank->size - 1,
@@ -827,101 +853,23 @@ static inline void prepare_page_table(void)
 }
 
 /*
- * Reserve the various regions of node 0
+ * Reserve the special regions of memory
  */
-void __init reserve_node_zero(pg_data_t *pgdat)
+void __init arm_mm_memblock_reserve(void)
 {
-       unsigned long res_size = 0;
-
-       /*
-        * Register the kernel text and data with bootmem.
-        * Note that this can only be in node 0.
-        */
-#ifdef CONFIG_XIP_KERNEL
-       reserve_bootmem_node(pgdat, __pa(_data), _end - _data,
-                       BOOTMEM_DEFAULT);
-#else
-       reserve_bootmem_node(pgdat, __pa(_stext), _end - _stext,
-                       BOOTMEM_DEFAULT);
-#endif
-
        /*
         * Reserve the page tables.  These are already in use,
         * and can only be in node 0.
         */
-       reserve_bootmem_node(pgdat, __pa(swapper_pg_dir),
-                            PTRS_PER_PGD * sizeof(pgd_t), BOOTMEM_DEFAULT);
-
-       /*
-        * Hmm... This should go elsewhere, but we really really need to
-        * stop things allocating the low memory; ideally we need a better
-        * implementation of GFP_DMA which does not assume that DMA-able
-        * memory starts at zero.
-        */
-       if (machine_is_integrator() || machine_is_cintegrator())
-               res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
-
-       /*
-        * These should likewise go elsewhere.  They pre-reserve the
-        * screen memory region at the start of main system memory.
-        */
-       if (machine_is_edb7211())
-               res_size = 0x00020000;
-       if (machine_is_p720t())
-               res_size = 0x00014000;
-
-       /* H1940, RX3715 and RX1950 need to reserve this for suspend */
-
-       if (machine_is_h1940() || machine_is_rx3715()
-               || machine_is_rx1950()) {
-               reserve_bootmem_node(pgdat, 0x30003000, 0x1000,
-                               BOOTMEM_DEFAULT);
-               reserve_bootmem_node(pgdat, 0x30081000, 0x1000,
-                               BOOTMEM_DEFAULT);
-       }
-
-       if (machine_is_palmld() || machine_is_palmtx()) {
-               reserve_bootmem_node(pgdat, 0xa0000000, 0x1000,
-                               BOOTMEM_EXCLUSIVE);
-               reserve_bootmem_node(pgdat, 0xa0200000, 0x1000,
-                               BOOTMEM_EXCLUSIVE);
-       }
-
-       if (machine_is_treo680() || machine_is_centro()) {
-               reserve_bootmem_node(pgdat, 0xa0000000, 0x1000,
-                               BOOTMEM_EXCLUSIVE);
-               reserve_bootmem_node(pgdat, 0xa2000000, 0x1000,
-                               BOOTMEM_EXCLUSIVE);
-       }
-
-       if (machine_is_palmt5())
-               reserve_bootmem_node(pgdat, 0xa0200000, 0x1000,
-                               BOOTMEM_EXCLUSIVE);
-
-       /*
-        * U300 - This platform family can share physical memory
-        * between two ARM cpus, one running Linux and the other
-        * running another OS.
-        */
-       if (machine_is_u300()) {
-#ifdef CONFIG_MACH_U300_SINGLE_RAM
-#if ((CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1) == 1) &&   \
-       CONFIG_MACH_U300_2MB_ALIGNMENT_FIX
-               res_size = 0x00100000;
-#endif
-#endif
-       }
+       memblock_reserve(__pa(swapper_pg_dir), PTRS_PER_PGD * sizeof(pgd_t));
 
 #ifdef CONFIG_SA1111
        /*
         * Because of the SA1111 DMA bug, we want to preserve our
         * precious DMA-able memory...
         */
-       res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
+       memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
 #endif
-       if (res_size)
-               reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size,
-                               BOOTMEM_DEFAULT);
 }
 
 /*
@@ -940,7 +888,7 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
        /*
         * Allocate the vector page early.
         */
-       vectors = alloc_bootmem_low_pages(PAGE_SIZE);
+       vectors = early_alloc(PAGE_SIZE);
 
        for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
                pmd_clear(pmd_off_k(addr));
@@ -1011,11 +959,8 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
 static void __init kmap_init(void)
 {
 #ifdef CONFIG_HIGHMEM
-       pmd_t *pmd = pmd_off_k(PKMAP_BASE);
-       pte_t *pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t));
-       BUG_ON(!pmd_none(*pmd) || !pte);
-       __pmd_populate(pmd, __pa(pte) | _PAGE_KERNEL_TABLE);
-       pkmap_page_table = pte + PTRS_PER_PTE;
+       pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
+               PKMAP_BASE, _PAGE_KERNEL_TABLE);
 #endif
 }
 
@@ -1066,17 +1011,16 @@ void __init paging_init(struct machine_desc *mdesc)
        sanity_check_meminfo();
        prepare_page_table();
        map_lowmem();
-       bootmem_init();
        devicemaps_init(mdesc);
        kmap_init();
 
        top_pmd = pmd_off_k(0xffff0000);
 
-       /*
-        * allocate the zero page.  Note that this always succeeds and
-        * returns a zeroed result.
-        */
-       zero_page = alloc_bootmem_low_pages(PAGE_SIZE);
+       /* allocate the zero page. */
+       zero_page = early_alloc(PAGE_SIZE);
+
+       bootmem_init();
+
        empty_zero_page = virt_to_page(zero_page);
        __flush_dcache_page(NULL, empty_zero_page);
 }

diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index 33b327379f0756e14eff3d9f0cd23a2f022eb112..687d02319a41ea68afcfe65698204a4db84d8400 100644 (file)
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -6,8 +6,8 @@
 #include <linux/module.h>
 #include <linux/mm.h>
 #include <linux/pagemap.h>
-#include <linux/bootmem.h>
 #include <linux/io.h>
+#include <linux/memblock.h>
 
 #include <asm/cacheflush.h>
 #include <asm/sections.h>
@@ -17,30 +17,14 @@
 
 #include "mm.h"
 
-/*
- * Reserve the various regions of node 0
- */
-void __init reserve_node_zero(pg_data_t *pgdat)
+void __init arm_mm_memblock_reserve(void)
 {
-       /*
-        * Register the kernel text and data with bootmem.
-        * Note that this can only be in node 0.
-        */
-#ifdef CONFIG_XIP_KERNEL
-       reserve_bootmem_node(pgdat, __pa(_data), _end - _data,
-                       BOOTMEM_DEFAULT);
-#else
-       reserve_bootmem_node(pgdat, __pa(_stext), _end - _stext,
-                       BOOTMEM_DEFAULT);
-#endif
-
        /*
         * Register the exception vector page.
         * some architectures which the DRAM is the exception vector to trap,
         * alloc_page breaks with error, although it is not NULL, but "0."
         */
-       reserve_bootmem_node(pgdat, CONFIG_VECTORS_BASE, PAGE_SIZE,
-                       BOOTMEM_DEFAULT);
+       memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE);
 }
 
 /*

diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 72507c630ceb563e9242145722b542b52731a7b3..203a4e944d9e43c53051725c084f542cceb8b7a3 100644 (file)
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -79,15 +79,11 @@ ENTRY(cpu_arm1020_proc_init)
  * cpu_arm1020_proc_fin()
  */
 ENTRY(cpu_arm1020_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-       bl      arm1020_flush_kern_cache_all
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_arm1020_reset(loc)

diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index d27829805609f5793e23bb2fd0c67ac85993e955..1a511e765909957d81b463c17f0000b8893d3770 100644 (file)
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -79,15 +79,11 @@ ENTRY(cpu_arm1020e_proc_init)
  * cpu_arm1020e_proc_fin()
  */
 ENTRY(cpu_arm1020e_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-       bl      arm1020e_flush_kern_cache_all
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_arm1020e_reset(loc)

diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index ce13e4a827de8ed9e787b11bf3a784b0bf803dab..1ffa4eb9c34f7d7d2f1b5ad5e3825daf67d14156 100644 (file)
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -68,15 +68,11 @@ ENTRY(cpu_arm1022_proc_init)
  * cpu_arm1022_proc_fin()
  */
 ENTRY(cpu_arm1022_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-       bl      arm1022_flush_kern_cache_all
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_arm1022_reset(loc)

diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 636672a29c6d1e58ad905850cba7374ba09d8f45..5697c34b95b0cdb38c31aad752c172b6990b5567 100644 (file)
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -68,15 +68,11 @@ ENTRY(cpu_arm1026_proc_init)
  * cpu_arm1026_proc_fin()
  */
 ENTRY(cpu_arm1026_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-       bl      arm1026_flush_kern_cache_all
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_arm1026_reset(loc)

diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 795dc615f43bb6f4b6513f4ac6a17a287911876e..64e0b327c7c5f504ec00757dcfd832d1fe56ac9e 100644 (file)
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -184,8 +184,6 @@ ENTRY(cpu_arm7_proc_init)
 
 ENTRY(cpu_arm6_proc_fin)
 ENTRY(cpu_arm7_proc_fin)
-               mov     r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-               msr     cpsr_c, r0
                mov     r0, #0x31                       @ ....S..DP...M
                mcr     p15, 0, r0, c1, c0, 0           @ disable caches
                mov     pc, lr

diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index 0b62de24466646d8b7e8aa65b84e8ac5191335f5..9d96824134fc4db4b0cd24f9df65c405717b4341 100644 (file)
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -54,15 +54,11 @@ ENTRY(cpu_arm720_proc_init)
                mov     pc, lr
 
 ENTRY(cpu_arm720_proc_fin)
-               stmfd   sp!, {lr}
-               mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-               msr     cpsr_c, ip
                mrc     p15, 0, r0, c1, c0, 0
                bic     r0, r0, #0x1000                 @ ...i............
                bic     r0, r0, #0x000e                 @ ............wca.
                mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-               mcr     p15, 0, r1, c7, c7, 0           @ invalidate cache
-               ldmfd   sp!, {pc}
+               mov     pc, lr
 
 /*
  * Function: arm720_proc_do_idle(void)

diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S
index 01860cdeb2ec3df451947f325c7d132449820717..6c1a9ab059aedb2f48e0d2bff8b823b3bb306dab 100644 (file)
--- a/arch/arm/mm/proc-arm740.S
+++ b/arch/arm/mm/proc-arm740.S
@@ -36,15 +36,11 @@ ENTRY(cpu_arm740_switch_mm)
  * cpu_arm740_proc_fin()
  */
 ENTRY(cpu_arm740_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
        mrc     p15, 0, r0, c1, c0, 0
        bic     r0, r0, #0x3f000000             @ bank/f/lock/s
        bic     r0, r0, #0x0000000c             @ w-buffer/cache
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       mcr     p15, 0, r0, c7, c0, 0           @ invalidate cache
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_arm740_reset(loc)

diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S
index 1201b98638298087063d3ec02eefd3a7e58d9aa6..6a850dbba22e5ff7be9aae70476489feeaaeef18 100644 (file)
--- a/arch/arm/mm/proc-arm7tdmi.S
+++ b/arch/arm/mm/proc-arm7tdmi.S
@@ -36,8 +36,6 @@ ENTRY(cpu_arm7tdmi_switch_mm)
  * cpu_arm7tdmi_proc_fin()
  */
 ENTRY(cpu_arm7tdmi_proc_fin)
-               mov     r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-               msr     cpsr_c, r0
                mov     pc, lr
 
 /*

diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 8be81992645d8d814517510ea473d85c604888bd..86f80aa56216b8ecf3159c090a83eeb2da372820 100644 (file)
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -69,19 +69,11 @@ ENTRY(cpu_arm920_proc_init)
  * cpu_arm920_proc_fin()
  */
 ENTRY(cpu_arm920_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
-       bl      arm920_flush_kern_cache_all
-#else
-       bl      v4wt_flush_kern_cache_all
-#endif
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_arm920_reset(loc)

diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index c0ff8e4b1074bac560f318a25c2715b89976c603..f76ce9b62883be61a1abe9baf67ae1a4ca4d8324 100644 (file)
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -71,19 +71,11 @@ ENTRY(cpu_arm922_proc_init)
  * cpu_arm922_proc_fin()
  */
 ENTRY(cpu_arm922_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
-       bl      arm922_flush_kern_cache_all
-#else
-       bl      v4wt_flush_kern_cache_all
-#endif
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_arm922_reset(loc)

diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 3c6cffe400f685f4dc3e32ccf078ef726d88d625..657bd3f7c153bf033f704636a323339129bb5d11 100644 (file)
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -92,15 +92,11 @@ ENTRY(cpu_arm925_proc_init)
  * cpu_arm925_proc_fin()
  */
 ENTRY(cpu_arm925_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-       bl      arm925_flush_kern_cache_all
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_arm925_reset(loc)

diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 75b707c9cce1ad31c2adf960d99e99cb5a266f8d..73f1f3c689108fcade13d8dbb26e057105247645 100644 (file)
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -61,15 +61,11 @@ ENTRY(cpu_arm926_proc_init)
  * cpu_arm926_proc_fin()
  */
 ENTRY(cpu_arm926_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-       bl      arm926_flush_kern_cache_all
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_arm926_reset(loc)

diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 1af1657819eb8e32caf40dbbc148ca2c0259144f..fffb061a45a558ee8dc5883dcba4a0e64ef53311 100644 (file)
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -37,15 +37,11 @@ ENTRY(cpu_arm940_switch_mm)
  * cpu_arm940_proc_fin()
  */
 ENTRY(cpu_arm940_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-       bl      arm940_flush_kern_cache_all
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x00001000             @ i-cache
        bic     r0, r0, #0x00000004             @ d-cache
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_arm940_reset(loc)

diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 1664b6aaff794957723cfac21696e8a2af030f3b..249a6053760a357baa0dca13c3d67bf49ebf975e 100644 (file)
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -44,15 +44,11 @@ ENTRY(cpu_arm946_switch_mm)
  * cpu_arm946_proc_fin()
  */
 ENTRY(cpu_arm946_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-       bl      arm946_flush_kern_cache_all
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x00001000             @ i-cache
        bic     r0, r0, #0x00000004             @ d-cache
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_arm946_reset(loc)

diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S
index 28545c29dbcda317db178a564a7a894f3a846f96..db475667fac2c95df3ab30fdabda084eab94c3f3 100644 (file)
--- a/arch/arm/mm/proc-arm9tdmi.S
+++ b/arch/arm/mm/proc-arm9tdmi.S
@@ -36,8 +36,6 @@ ENTRY(cpu_arm9tdmi_switch_mm)
  * cpu_arm9tdmi_proc_fin()
  */
 ENTRY(cpu_arm9tdmi_proc_fin)
-               mov     r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-               msr     cpsr_c, r0
                mov     pc, lr
 
 /*

diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S
index 08f5ac237ad4e83e67b7540a9680d28c619edc41..7803fdf7002933da8e63a3383f9da818ecea724c 100644 (file)
--- a/arch/arm/mm/proc-fa526.S
+++ b/arch/arm/mm/proc-fa526.S
@@ -39,17 +39,13 @@ ENTRY(cpu_fa526_proc_init)
  * cpu_fa526_proc_fin()
  */
 ENTRY(cpu_fa526_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-       bl      fa_flush_kern_cache_all
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
        nop
        nop
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_fa526_reset(loc)

diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index 53e63234384992ed07daf2eb48da91eaa5fa4a7d..b304d0104a4ef9c240191e42b7e08460706408b8 100644 (file)
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -75,11 +75,6 @@ ENTRY(cpu_feroceon_proc_init)
  * cpu_feroceon_proc_fin()
  */
 ENTRY(cpu_feroceon_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-       bl      feroceon_flush_kern_cache_all
-
 #if defined(CONFIG_CACHE_FEROCEON_L2) && \
        !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
        mov     r0, #0
@@ -91,7 +86,7 @@ ENTRY(cpu_feroceon_proc_fin)
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_feroceon_reset(loc)

diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index caa31154e7dbf71417beebc71128e0d061fb17ce..5f6892fcc1671f28070f175bc6eeda03bbe614c5 100644 (file)
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -51,15 +51,11 @@ ENTRY(cpu_mohawk_proc_init)
  * cpu_mohawk_proc_fin()
  */
 ENTRY(cpu_mohawk_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-       bl      mohawk_flush_kern_cache_all
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1800                 @ ...iz...........
        bic     r0, r0, #0x0006                 @ .............ca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_mohawk_reset(loc)

diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index 7b706b38990625c08ca3595ff19b6657fcbb0648..a201eb04b5e1a6327d1a5375c00b669ee7fc439c 100644 (file)
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -44,17 +44,13 @@ ENTRY(cpu_sa110_proc_init)
  * cpu_sa110_proc_fin()
  */
 ENTRY(cpu_sa110_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-       bl      v4wb_flush_kern_cache_all       @ clean caches
-1:     mov     r0, #0
+       mov     r0, #0
        mcr     p15, 0, r0, c15, c2, 2          @ Disable clock switching
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_sa110_reset(loc)

diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 5c47760c206437c0fbe7219aebae464b19929c7b..7ddc4805bf97a6fe722f54b3a769974bfaa42a1b 100644 (file)
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -55,16 +55,12 @@ ENTRY(cpu_sa1100_proc_init)
  *  - Clean and turn off caches.
  */
 ENTRY(cpu_sa1100_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-       bl      v4wb_flush_kern_cache_all
        mcr     p15, 0, ip, c15, c2, 2          @ Disable clock switching
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_sa1100_reset(loc)

diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 7a5337ed7d68b6b1112e59ede2ce2dd5ed630a5f..22aac85151966d3058ace5cdb24eb4a608605e16 100644 (file)
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -42,14 +42,11 @@ ENTRY(cpu_v6_proc_init)
        mov     pc, lr
 
 ENTRY(cpu_v6_proc_fin)
-       stmfd   sp!, {lr}
-       cpsid   if                              @ disable interrupts
-       bl      v6_flush_kern_cache_all
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x0006                 @ .............ca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  *     cpu_v6_reset(loc)
@@ -239,7 +236,8 @@ __v6_proc_info:
        b       __v6_setup
        .long   cpu_arch_name
        .long   cpu_elf_name
-       .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
+       /* See also feat_v6_fixup() for HWCAP_TLS */
+       .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS
        .long   cpu_v6_name
        .long   v6_processor_functions
        .long   v6wbi_tlb_fns
@@ -262,7 +260,7 @@ __pj4_v6_proc_info:
        b       __v6_setup
        .long   cpu_arch_name
        .long   cpu_elf_name
-       .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+       .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
        .long   cpu_pj4_name
        .long   v6_processor_functions
        .long   v6wbi_tlb_fns

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 7aaf88a3b7aabb7a8a7268d435eda8aa78bd7671..6a8506d99ee9abbb0845f39d94d663f802c56885 100644 (file)
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -45,14 +45,11 @@ ENTRY(cpu_v7_proc_init)
 ENDPROC(cpu_v7_proc_init)
 
 ENTRY(cpu_v7_proc_fin)
-       stmfd   sp!, {lr}
-       cpsid   if                              @ disable interrupts
-       bl      v7_flush_kern_cache_all
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x0006                 @ .............ca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 ENDPROC(cpu_v7_proc_fin)
 
 /*
@@ -344,7 +341,7 @@ __v7_proc_info:
        b       __v7_setup
        .long   cpu_arch_name
        .long   cpu_elf_name
-       .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+       .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
        .long   cpu_v7_name
        .long   v7_processor_functions
        .long   v7wbi_tlb_fns

diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index e5797f1c1db7d0dd4ccf06ff308655be1d2aa2a9..361a51e4903063ffc82f6831f3bee47e3a957860 100644 (file)
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -90,15 +90,11 @@ ENTRY(cpu_xsc3_proc_init)
  * cpu_xsc3_proc_fin()
  */
 ENTRY(cpu_xsc3_proc_fin)
-       str     lr, [sp, #-4]!
-       mov     r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
-       msr     cpsr_c, r0
-       bl      xsc3_flush_kern_cache_all       @ clean caches
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1800                 @ ...IZ...........
        bic     r0, r0, #0x0006                 @ .............CA.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldr     pc, [sp], #4
+       mov     pc, lr
 
 /*
  * cpu_xsc3_reset(loc)

diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 63037e2162f201ba76ad34604c2cd09ab450d71b..14075979bcbac1a4bfe7ae346e97058de819d448 100644 (file)
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -124,15 +124,11 @@ ENTRY(cpu_xscale_proc_init)
  * cpu_xscale_proc_fin()
  */
 ENTRY(cpu_xscale_proc_fin)
-       str     lr, [sp, #-4]!
-       mov     r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
-       msr     cpsr_c, r0
-       bl      xscale_flush_kern_cache_all     @ clean caches
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1800                 @ ...IZ...........
        bic     r0, r0, #0x0006                 @ .............CA.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldr     pc, [sp], #4
+       mov     pc, lr
 
 /*
  * cpu_xscale_reset(loc)

diff --git a/arch/arm/mm/vmregion.c b/arch/arm/mm/vmregion.c
index 19e09bdb1b8a4ea3e4d892f8ab753eee25d6cd0b..935993e1b1ef53f5372344cbc6a5c764186557b9 100644 (file)
--- a/arch/arm/mm/vmregion.c
+++ b/arch/arm/mm/vmregion.c
@@ -35,7 +35,8 @@
  */
 
 struct arm_vmregion *
-arm_vmregion_alloc(struct arm_vmregion_head *head, size_t size, gfp_t gfp)
+arm_vmregion_alloc(struct arm_vmregion_head *head, size_t align,
+                  size_t size, gfp_t gfp)
 {
        unsigned long addr = head->vm_start, end = head->vm_end - size;
        unsigned long flags;
@@ -58,7 +59,7 @@ arm_vmregion_alloc(struct arm_vmregion_head *head, size_t size, gfp_t gfp)
                        goto nospc;
                if ((addr + size) <= c->vm_start)
                        goto found;
-               addr = c->vm_end;
+               addr = ALIGN(c->vm_end, align);
                if (addr > end)
                        goto nospc;
        }

diff --git a/arch/arm/mm/vmregion.h b/arch/arm/mm/vmregion.h
index 6b2cdbdf3a857a12162654140185d61616f77d49..15e9f044db9feab45a25d79eed9e1f0dce5a2a1a 100644 (file)
--- a/arch/arm/mm/vmregion.h
+++ b/arch/arm/mm/vmregion.h
@@ -21,7 +21,7 @@ struct arm_vmregion {
        int                     vm_active;
 };
 
-struct arm_vmregion *arm_vmregion_alloc(struct arm_vmregion_head *, size_t, gfp_t);
+struct arm_vmregion *arm_vmregion_alloc(struct arm_vmregion_head *, size_t, size_t, gfp_t);
 struct arm_vmregion *arm_vmregion_find(struct arm_vmregion_head *, unsigned long);
 struct arm_vmregion *arm_vmregion_find_remove(struct arm_vmregion_head *, unsigned long);
 void arm_vmregion_free(struct arm_vmregion_head *, struct arm_vmregion *);

diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c
index ce31f316ac75c1e72af3693a58633a10e50e7f7a..43f2b158237c71c99cc51f0e3d99066a05ee65cb 100644 (file)
--- a/arch/arm/plat-iop/pci.c
+++ b/arch/arm/plat-iop/pci.c
@@ -359,7 +359,7 @@ static void __init iop3xx_atu_debug(void)
        DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD);
        DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR);
 
-       hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort");
+       hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, 0, "imprecise external abort");
 }
 
 /* for platforms that might be host-bus-adapters */

diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index 6c8a02ad98e33f9a374fd62c58c5ea7630427f0c..85d3e55ca4a9c293c67d4b2557bb52d90f93d22f 100644 (file)
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -28,6 +28,11 @@
 #include <asm/mach/time.h>
 #include <mach/time.h>
 
+/*
+ * Minimum clocksource/clockevent timer range in seconds
+ */
+#define IOP_MIN_RANGE 4
+
 /*
  * IOP clocksource (free-running timer 1).
  */
@@ -44,27 +49,6 @@ static struct clocksource iop_clocksource = {
        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
-static void __init iop_clocksource_set_hz(struct clocksource *cs, unsigned int hz)
-{
-       u64 temp;
-       u32 shift;
-
-       /* Find shift and mult values for hz. */
-       shift = 32;
-       do {
-               temp = (u64) NSEC_PER_SEC << shift;
-               do_div(temp, hz);
-               if ((temp >> 32) == 0)
-                       break;
-       } while (--shift != 0);
-
-       cs->shift = shift;
-       cs->mult = (u32) temp;
-
-       printk(KERN_INFO "clocksource: %s uses shift %u mult %#x\n",
-              cs->name, cs->shift, cs->mult);
-}
-
 /*
  * IOP sched_clock() implementation via its clocksource.
  */
@@ -130,27 +114,6 @@ static struct clock_event_device iop_clockevent = {
        .set_mode       = iop_set_mode,
 };
 
-static void __init iop_clockevent_set_hz(struct clock_event_device *ce, unsigned int hz)
-{
-       u64 temp;
-       u32 shift;
-
-       /* Find shift and mult values for hz. */
-       shift = 32;
-       do {
-               temp = (u64) hz << shift;
-               do_div(temp, NSEC_PER_SEC);
-               if ((temp >> 32) == 0)
-                       break;
-       } while (--shift != 0);
-
-       ce->shift = shift;
-       ce->mult = (u32) temp;
-
-       printk(KERN_INFO "clockevent: %s uses shift %u mult %#lx\n",
-              ce->name, ce->shift, ce->mult);
-}
-
 static irqreturn_t
 iop_timer_interrupt(int irq, void *dev_id)
 {
@@ -190,7 +153,8 @@ void __init iop_init_time(unsigned long tick_rate)
         */
        write_tmr0(timer_ctl & ~IOP_TMR_EN);
        setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
-       iop_clockevent_set_hz(&iop_clockevent, tick_rate);
+       clockevents_calc_mult_shift(&iop_clockevent,
+                                   tick_rate, IOP_MIN_RANGE);
        iop_clockevent.max_delta_ns =
                clockevent_delta2ns(0xfffffffe, &iop_clockevent);
        iop_clockevent.min_delta_ns =
@@ -207,6 +171,7 @@ void __init iop_init_time(unsigned long tick_rate)
        write_trr1(0xffffffff);
        write_tcr1(0xffffffff);
        write_tmr1(timer_ctl);
-       iop_clocksource_set_hz(&iop_clocksource, tick_rate);
+       clocksource_calc_mult_shift(&iop_clocksource, tick_rate,
+                                   IOP_MIN_RANGE);
        clocksource_register(&iop_clocksource);
 }

diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c
new file mode 100644 (file)
index 0000000..639c54a
--- /dev/null
+++ b/arch/arm/plat-mxc/3ds_debugboard.c
@@ -0,0 +1,202 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/smsc911x.h>
+
+#include <mach/hardware.h>
+
+/* LAN9217 ethernet base address */
+#define LAN9217_BASE_ADDR(n)   (n + 0x0)
+/* External UART */
+#define UARTA_BASE_ADDR(n)     (n + 0x8000)
+#define UARTB_BASE_ADDR(n)     (n + 0x10000)
+
+#define BOARD_IO_ADDR(n)       (n + 0x20000)
+/* LED switchs */
+#define LED_SWITCH_REG         0x00
+/* buttons */
+#define SWITCH_BUTTONS_REG     0x08
+/* status, interrupt */
+#define INTR_STATUS_REG        0x10
+#define INTR_MASK_REG          0x38
+#define INTR_RESET_REG         0x20
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER1_REG      0x40
+#define MAGIC_NUMBER2_REG      0x48
+/* CPLD code version */
+#define CPLD_CODE_VER_REG      0x50
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER3_REG      0x58
+/* module reset register*/
+#define MODULE_RESET_REG       0x60
+/* CPU ID and Personality ID */
+#define MCU_BOARD_ID_REG       0x68
+
+#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_BOARD_IRQ_START)
+#define MXC_IRQ_TO_GPIO(irq)   ((irq) - MXC_INTERNAL_IRQS)
+
+#define MXC_EXP_IO_BASE                (MXC_BOARD_IRQ_START)
+#define MXC_MAX_EXP_IO_LINES   16
+
+/* interrupts like external uart , external ethernet etc*/
+#define EXPIO_INT_ENET         (MXC_BOARD_IRQ_START + 0)
+#define EXPIO_INT_XUART_A      (MXC_BOARD_IRQ_START + 1)
+#define EXPIO_INT_XUART_B      (MXC_BOARD_IRQ_START + 2)
+#define EXPIO_INT_BUTTON_A     (MXC_BOARD_IRQ_START + 3)
+#define EXPIO_INT_BUTTON_B     (MXC_BOARD_IRQ_START + 4)
+
+static void __iomem *brd_io;
+static void expio_ack_irq(u32 irq);
+
+static struct resource smsc911x_resources[] = {
+       {
+               .flags = IORESOURCE_MEM,
+       } , {
+               .start = EXPIO_INT_ENET,
+               .end = EXPIO_INT_ENET,
+               .flags = IORESOURCE_IRQ,
+       },
+};
+
+static struct smsc911x_platform_config smsc911x_config = {
+       .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+       .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
+};
+
+static struct platform_device smsc_lan9217_device = {
+       .name = "smsc911x",
+       .id = 0,
+       .dev = {
+               .platform_data = &smsc911x_config,
+       },
+       .num_resources = ARRAY_SIZE(smsc911x_resources),
+       .resource = smsc911x_resources,
+};
+
+static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
+{
+       u32 imr_val;
+       u32 int_valid;
+       u32 expio_irq;
+
+       desc->chip->mask(irq);  /* irq = gpio irq number */
+
+       imr_val = __raw_readw(brd_io + INTR_MASK_REG);
+       int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
+
+       expio_irq = MXC_BOARD_IRQ_START;
+       for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
+               struct irq_desc *d;
+               if ((int_valid & 1) == 0)
+                       continue;
+               d = irq_desc + expio_irq;
+               if (unlikely(!(d->handle_irq)))
+                       pr_err("\nEXPIO irq: %d unhandled\n", expio_irq);
+               else
+                       d->handle_irq(expio_irq, d);
+       }
+
+       desc->chip->ack(irq);
+       desc->chip->unmask(irq);
+}
+
+/*
+ * Disable an expio pin's interrupt by setting the bit in the imr.
+ * Irq is an expio virtual irq number
+ */
+static void expio_mask_irq(u32 irq)
+{
+       u16 reg;
+       u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+       reg = __raw_readw(brd_io + INTR_MASK_REG);
+       reg |= (1 << expio);
+       __raw_writew(reg, brd_io + INTR_MASK_REG);
+}
+
+static void expio_ack_irq(u32 irq)
+{
+       u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+       __raw_writew(1 << expio, brd_io + INTR_RESET_REG);
+       __raw_writew(0, brd_io + INTR_RESET_REG);
+       expio_mask_irq(irq);
+}
+
+static void expio_unmask_irq(u32 irq)
+{
+       u16 reg;
+       u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+       reg = __raw_readw(brd_io + INTR_MASK_REG);
+       reg &= ~(1 << expio);
+       __raw_writew(reg, brd_io + INTR_MASK_REG);
+}
+
+static struct irq_chip expio_irq_chip = {
+       .ack = expio_ack_irq,
+       .mask = expio_mask_irq,
+       .unmask = expio_unmask_irq,
+};
+
+int __init mxc_expio_init(u32 base, u32 p_irq)
+{
+       int i;
+
+       brd_io = ioremap(BOARD_IO_ADDR(base), SZ_4K);
+       if (brd_io == NULL)
+               return -ENOMEM;
+
+       if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||
+           (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||
+           (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {
+               pr_info("3-Stack Debug board not detected\n");
+               iounmap(brd_io);
+               brd_io = NULL;
+               return -ENODEV;
+       }
+
+       pr_info("3-Stack Debug board detected, rev = 0x%04X\n",
+               readw(brd_io + CPLD_CODE_VER_REG));
+
+       /*
+        * Configure INT line as GPIO input
+        */
+       gpio_request(MXC_IRQ_TO_GPIO(p_irq), "expio_pirq");
+       gpio_direction_input(MXC_IRQ_TO_GPIO(p_irq));
+
+       /* disable the interrupt and clear the status */
+       __raw_writew(0, brd_io + INTR_MASK_REG);
+       __raw_writew(0xFFFF, brd_io + INTR_RESET_REG);
+       __raw_writew(0, brd_io + INTR_RESET_REG);
+       __raw_writew(0x1F, brd_io + INTR_MASK_REG);
+       for (i = MXC_EXP_IO_BASE;
+            i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) {
+               set_irq_chip(i, &expio_irq_chip);
+               set_irq_handler(i, handle_level_irq);
+               set_irq_flags(i, IRQF_VALID);
+       }
+       set_irq_type(p_irq, IRQF_TRIGGER_LOW);
+       set_irq_chained_handler(p_irq, mxc_expio_irq_handler);
+
+       /* Register Lan device on the debugboard */
+       smsc911x_resources[0].start = LAN9217_BASE_ADDR(base);
+       smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1;
+       platform_device_register(&smsc_lan9217_device);
+
+       return 0;
+}

diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 7f7ad6f289bd53383ed5ed952099d62c2a4f52b1..0527e65318f4a647b5b00192ce08ba47368ce5f8 100644 (file)
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -1,5 +1,7 @@
 if ARCH_MXC
 
+source "arch/arm/plat-mxc/devices/Kconfig"
+
 menu "Freescale MXC Implementations"
 
 choice
@@ -8,15 +10,12 @@ choice
 
 config ARCH_MX1
        bool "MX1-based"
-       select CPU_ARM920T
-       select IMX_HAVE_IOMUX_V1
+       select SOC_IMX1
        help
          This enables support for systems based on the Freescale i.MX1 family
 
 config ARCH_MX2
        bool "MX2-based"
-       select CPU_ARM926T
-       select IMX_HAVE_IOMUX_V1
        help
          This enables support for systems based on the Freescale i.MX2 family
 
@@ -25,6 +24,7 @@ config ARCH_MX25
        select CPU_ARM926T
        select ARCH_MXC_IOMUX_V3
        select HAVE_FB_IMX
+       select ARCH_MXC_AUDMUX_V2
        help
          This enables support for systems based on the Freescale i.MX25 family
 
@@ -48,8 +48,7 @@ config ARCH_MX5
 
 endchoice
 
-source "arch/arm/mach-mx1/Kconfig"
-source "arch/arm/mach-mx2/Kconfig"
+source "arch/arm/mach-imx/Kconfig"
 source "arch/arm/mach-mx3/Kconfig"
 source "arch/arm/mach-mx25/Kconfig"
 source "arch/arm/mach-mxc91231/Kconfig"
@@ -81,6 +80,17 @@ config MXC_PWM
        help
          Enable support for the i.MX PWM controller(s).
 
+config MXC_DEBUG_BOARD
+       bool "Enable MXC debug board(for 3-stack)"
+       help
+         The debug board is an integral part of the MXC 3-stack(PDK)
+         platforms, it can be attached or removed from the peripheral
+         board. On debug board, several debug devices(ethernet, UART,
+         buttons, LEDs and JTAG) are implemented. Between the MCU and
+         these devices, a CPLD is added as a bridge which performs
+         data/address de-multiplexing and decode, signal level shift,
+         interrupt control and various board functions.
+
 config MXC_ULPI
        bool
 

diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 895bc3c5e0c0a5f709018a9f855536961d1a3da6..78d405ed861656ef83182a7242c385dcab805ce0 100644 (file)
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -8,8 +8,6 @@ obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o
 # MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o)
 obj-$(CONFIG_MXC_TZIC) += tzic.o
 
-obj-$(CONFIG_ARCH_MX1) += dma-mx1-mx2.o
-obj-$(CONFIG_ARCH_MX2) += dma-mx1-mx2.o
 obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
 obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
 obj-$(CONFIG_MXC_PWM)  += pwm.o
@@ -17,7 +15,10 @@ obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
 obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
+obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
 ifdef CONFIG_SND_IMX_SOC
 obj-y += ssi-fiq.o
 obj-y += ssi-fiq-ksym.o
 endif
+
+obj-y += devices/

diff --git a/arch/arm/plat-mxc/audmux-v1.c b/arch/arm/plat-mxc/audmux-v1.c
index b62917ca3f954bba4e2b5925879ed96c55f24738..1180bef7664b3ca34359d37940a2fd20081b7017 100644 (file)
--- a/arch/arm/plat-mxc/audmux-v1.c
+++ b/arch/arm/plat-mxc/audmux-v1.c
@@ -13,10 +13,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
 #include <linux/module.h>

diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
index 0c2cc5cd4d83ac6ec5129dcba1a896eab8230f00..f9e7cdbd000568a562ac4bd062a550df73f3a853 100644 (file)
--- a/arch/arm/plat-mxc/audmux-v2.c
+++ b/arch/arm/plat-mxc/audmux-v2.c
@@ -13,10 +13,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
 #include <linux/module.h>
@@ -191,6 +187,7 @@ static int mxc_audmux_v2_init(void)
 {
        int ret;
 
+#if defined(CONFIG_ARCH_MX3)
        if (cpu_is_mx31())
                audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR);
 
@@ -204,7 +201,19 @@ static int mxc_audmux_v2_init(void)
                }
                audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR);
        }
-
+#endif
+#if defined(CONFIG_ARCH_MX25)
+       if (cpu_is_mx25()) {
+               audmux_clk = clk_get(NULL, "audmux");
+               if (IS_ERR(audmux_clk)) {
+                       ret = PTR_ERR(audmux_clk);
+                       printk(KERN_ERR "%s: cannot get clock: %d\n", __func__,
+                                       ret);
+                       return ret;
+               }
+               audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR);
+       }
+#endif
        audmux_debugfs_init();
 
        return 0;

diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index 323ff8ccc877161042a72bbf309c955878160966..2ed3ab173addcae894a1c52190e7cc9419dddc90 100644 (file)
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -52,13 +52,14 @@ static void __clk_disable(struct clk *clk)
 {
        if (clk == NULL || IS_ERR(clk))
                return;
-
-       __clk_disable(clk->parent);
-       __clk_disable(clk->secondary);
-
        WARN_ON(!clk->usecount);
-       if (!(--clk->usecount) && clk->disable)
-               clk->disable(clk);
+
+       if (!(--clk->usecount)) {
+               if (clk->disable)
+                       clk->disable(clk);
+               __clk_disable(clk->parent);
+               __clk_disable(clk->secondary);
+       }
 }
 
 static int __clk_enable(struct clk *clk)
@@ -66,12 +67,13 @@ static int __clk_enable(struct clk *clk)
        if (clk == NULL || IS_ERR(clk))
                return -EINVAL;
 
-       __clk_enable(clk->parent);
-       __clk_enable(clk->secondary);
-
-       if (clk->usecount++ == 0 && clk->enable)
-               clk->enable(clk);
+       if (clk->usecount++ == 0) {
+               __clk_enable(clk->parent);
+               __clk_enable(clk->secondary);
 
+               if (clk->enable)
+                       clk->enable(clk);
+       }
        return 0;
 }
 
@@ -160,17 +162,28 @@ EXPORT_SYMBOL(clk_set_rate);
 int clk_set_parent(struct clk *clk, struct clk *parent)
 {
        int ret = -EINVAL;
+       struct clk *old;
 
        if (clk == NULL || IS_ERR(clk) || parent == NULL ||
            IS_ERR(parent) || clk->set_parent == NULL)
                return ret;
 
+       if (clk->usecount)
+               clk_enable(parent);
+
        mutex_lock(&clocks_mutex);
        ret = clk->set_parent(clk, parent);
-       if (ret == 0)
+       if (ret == 0) {
+               old = clk->parent;
                clk->parent = parent;
+       } else {
+               old = parent;
+       }
        mutex_unlock(&clocks_mutex);
 
+       if (clk->usecount)
+               clk_disable(old);
+
        return ret;
 }
 EXPORT_SYMBOL(clk_set_parent);

diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c
index 56f2fb5cc456433e6a7f4d23b129a77004b67655..735776d8495636fd8e7429fc2d21b9797bd575ff 100644 (file)
--- a/arch/arm/plat-mxc/devices.c
+++ b/arch/arm/plat-mxc/devices.c
@@ -18,6 +18,7 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/err.h>
 #include <linux/platform_device.h>
 #include <mach/common.h>
 
@@ -35,3 +36,35 @@ int __init mxc_register_device(struct platform_device *pdev, void *data)
        return ret;
 }
 
+struct platform_device *__init imx_add_platform_device(const char *name, int id,
+               const struct resource *res, unsigned int num_resources,
+               const void *data, size_t size_data)
+{
+       int ret = -ENOMEM;
+       struct platform_device *pdev;
+
+       pdev = platform_device_alloc(name, id);
+       if (!pdev)
+               goto err;
+
+       if (res) {
+               ret = platform_device_add_resources(pdev, res, num_resources);
+               if (ret)
+                       goto err;
+       }
+
+       if (data) {
+               ret = platform_device_add_data(pdev, data, size_data);
+               if (ret)
+                       goto err;
+       }
+
+       ret = platform_device_add(pdev);
+       if (ret) {
+err:
+               platform_device_put(pdev);
+               return ERR_PTR(ret);
+       }
+
+       return pdev;
+}

diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
new file mode 100644 (file)
index 0000000..9ab784b
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -0,0 +1,15 @@
+config IMX_HAVE_PLATFORM_FLEXCAN
+       select HAVE_CAN_FLEXCAN
+       bool
+
+config IMX_HAVE_PLATFORM_IMX_I2C
+       bool
+
+config IMX_HAVE_PLATFORM_IMX_UART
+       bool
+
+config IMX_HAVE_PLATFORM_MXC_NAND
+       bool
+
+config IMX_HAVE_PLATFORM_SPI_IMX
+       bool

diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
new file mode 100644 (file)
index 0000000..347da51
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -0,0 +1,8 @@
+ifdef CONFIG_CAN_FLEXCAN
+# the ifdef can be removed once the flexcan driver has been merged
+obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) +=  platform-flexcan.o
+endif
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) +=  platform-spi_imx.o

diff --git a/arch/arm/plat-mxc/devices/platform-flexcan.c b/arch/arm/plat-mxc/devices/platform-flexcan.c
new file mode 100644 (file)
index 0000000..5e97a01
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-flexcan.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2010 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+
+#include <mach/devices-common.h>
+
+struct platform_device *__init imx_add_flexcan(int id,
+               resource_size_t iobase, resource_size_t iosize,
+               resource_size_t irq,
+               const struct flexcan_platform_data *pdata)
+{
+       struct resource res[] = {
+               {
+                       .start = iobase,
+                       .end = iobase + iosize - 1,
+                       .flags = IORESOURCE_MEM,
+               }, {
+                       .start = irq,
+                       .end = irq,
+                       .flags = IORESOURCE_IRQ,
+               },
+       };
+
+       return imx_add_platform_device("flexcan", id, res, ARRAY_SIZE(res),
+                       pdata, sizeof(*pdata));
+}

diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
new file mode 100644 (file)
index 0000000..d0af9f7
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/devices-common.h>
+
+struct platform_device *__init imx_add_imx_i2c(int id,
+               resource_size_t iobase, resource_size_t iosize, int irq,
+               const struct imxi2c_platform_data *pdata)
+{
+       struct resource res[] = {
+               {
+                       .start = iobase,
+                       .end = iobase + iosize - 1,
+                       .flags = IORESOURCE_MEM,
+               }, {
+                       .start = irq,
+                       .end = irq,
+                       .flags = IORESOURCE_IRQ,
+               },
+       };
+
+       return imx_add_platform_device("imx-i2c", id, res, ARRAY_SIZE(res),
+                       pdata, sizeof(*pdata));
+}

diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c
new file mode 100644 (file)
index 0000000..fa3dff1
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/devices-common.h>
+
+struct platform_device *__init imx_add_imx_uart_3irq(int id,
+               resource_size_t iobase, resource_size_t iosize,
+               resource_size_t irqrx, resource_size_t irqtx,
+               resource_size_t irqrts,
+               const struct imxuart_platform_data *pdata)
+{
+       struct resource res[] = {
+               {
+                       .start = iobase,
+                       .end = iobase + iosize - 1,
+                       .flags = IORESOURCE_MEM,
+               }, {
+                       .start = irqrx,
+                       .end = irqrx,
+                       .flags = IORESOURCE_IRQ,
+               }, {
+                       .start = irqtx,
+                       .end = irqtx,
+                       .flags = IORESOURCE_IRQ,
+               }, {
+                       .start = irqrts,
+                       .end = irqrx,
+                       .flags = IORESOURCE_IRQ,
+               },
+       };
+
+       return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res),
+                       pdata, sizeof(*pdata));
+}
+
+struct platform_device *__init imx_add_imx_uart_1irq(int id,
+               resource_size_t iobase, resource_size_t iosize,
+               resource_size_t irq,
+               const struct imxuart_platform_data *pdata)
+{
+       struct resource res[] = {
+               {
+                       .start = iobase,
+                       .end = iobase + iosize - 1,
+                       .flags = IORESOURCE_MEM,
+               }, {
+                       .start = irq,
+                       .end = irq,
+                       .flags = IORESOURCE_IRQ,
+               },
+       };
+
+       return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res),
+                       pdata, sizeof(*pdata));
+}

diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
new file mode 100644 (file)
index 0000000..1c28641
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <asm/sizes.h>
+#include <mach/devices-common.h>
+
+static struct platform_device *__init imx_add_mxc_nand(resource_size_t iobase,
+               int irq, const struct mxc_nand_platform_data *pdata,
+               resource_size_t iosize)
+{
+       static int id = 0;
+       
+       struct resource res[] = {
+               {
+                       .start = iobase,
+                       .end = iobase + iosize - 1,
+                       .flags = IORESOURCE_MEM,
+               }, {
+                       .start = irq,
+                       .end = irq,
+                       .flags = IORESOURCE_IRQ,
+               },
+       };
+
+       return imx_add_platform_device("mxc_nand", id++, res, ARRAY_SIZE(res),
+                       pdata, sizeof(*pdata));
+}
+
+struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase,
+               int irq, const struct mxc_nand_platform_data *pdata)
+{
+       return imx_add_mxc_nand(iobase, irq, pdata, SZ_4K);
+}
+
+struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase,
+               int irq, const struct mxc_nand_platform_data *pdata)
+{
+       return imx_add_mxc_nand(iobase, irq, pdata, SZ_8K);
+}

diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
new file mode 100644 (file)
index 0000000..2831a6d
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <asm/sizes.h>
+#include <mach/devices-common.h>
+
+struct platform_device *__init imx_add_spi_imx(int id,
+               resource_size_t iobase, resource_size_t iosize, int irq,
+               const struct spi_imx_master *pdata)
+{
+       struct resource res[] = {
+               {
+                       .start = iobase,
+                       .end = iobase + iosize - 1,
+                       .flags = IORESOURCE_MEM,
+               }, {
+                       .start = irq,
+                       .end = irq,
+                       .flags = IORESOURCE_IRQ,
+               },
+       };
+
+       return imx_add_platform_device("spi_imx", id, res, ARRAY_SIZE(res),
+                       pdata, sizeof(*pdata));
+}

diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
index 2a8646173c2f57b3270bfde937095efb606e3135..35a064ff02ba61a66b4f0425728baa4b7f74cda6 100644 (file)
--- a/arch/arm/plat-mxc/ehci.c
+++ b/arch/arm/plat-mxc/ehci.c
@@ -11,10 +11,6 @@
  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  * for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
 #include <linux/platform_device.h>
@@ -73,7 +69,51 @@
 int mxc_initialize_usb_hw(int port, unsigned int flags)
 {
        unsigned int v;
-#ifdef CONFIG_ARCH_MX3
+#if defined(CONFIG_ARCH_MX25)
+       if (cpu_is_mx25()) {
+               v = readl(MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR +
+                                    USBCTRL_OTGBASE_OFFSET));
+
+               switch (port) {
+               case 0: /* OTG port */
+                       v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
+                       v |= (flags & MXC_EHCI_INTERFACE_MASK)
+                                       << MX35_OTG_SIC_SHIFT;
+                       if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                               v |= MX35_OTG_PM_BIT;
+
+                       break;
+               case 1: /* H1 port */
+                       v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
+                               MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
+                       v |= (flags & MXC_EHCI_INTERFACE_MASK)
+                                               << MX35_H1_SIC_SHIFT;
+                       if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                               v |= MX35_H1_PM_BIT;
+
+                       if (!(flags & MXC_EHCI_TTL_ENABLED))
+                               v |= MX35_H1_TLL_BIT;
+
+                       if (flags & MXC_EHCI_INTERNAL_PHY)
+                               v |= MX35_H1_USBTE_BIT;
+
+                       if (flags & MXC_EHCI_IPPUE_DOWN)
+                               v |= MX35_H1_IPPUE_DOWN_BIT;
+
+                       if (flags & MXC_EHCI_IPPUE_UP)
+                               v |= MX35_H1_IPPUE_UP_BIT;
+
+                       break;
+               default:
+                       return -EINVAL;
+               }
+
+               writel(v, MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR +
+                                    USBCTRL_OTGBASE_OFFSET));
+               return 0;
+       }
+#endif /* CONFIG_ARCH_MX25 */
+#if defined(CONFIG_ARCH_MX3)
        if (cpu_is_mx31()) {
                v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +
                                     USBCTRL_OTGBASE_OFFSET));

diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 71437c61cfd70f65e1aafd73095faf3718e3e8e3..57ec4a896a5d983556ebae058dbf52293ebe669e 100644 (file)
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -214,13 +214,16 @@ static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
        struct mxc_gpio_port *port =
                container_of(chip, struct mxc_gpio_port, chip);
        u32 l;
+       unsigned long flags;
 
+       spin_lock_irqsave(&port->lock, flags);
        l = __raw_readl(port->base + GPIO_GDIR);
        if (dir)
                l |= 1 << offset;
        else
                l &= ~(1 << offset);
        __raw_writel(l, port->base + GPIO_GDIR);
+       spin_unlock_irqrestore(&port->lock, flags);
 }
 
 static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
@@ -229,9 +232,12 @@ static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
                container_of(chip, struct mxc_gpio_port, chip);
        void __iomem *reg = port->base + GPIO_DR;
        u32 l;
+       unsigned long flags;
 
+       spin_lock_irqsave(&port->lock, flags);
        l = (__raw_readl(reg) & (~(1 << offset))) | (value << offset);
        __raw_writel(l, reg);
+       spin_unlock_irqrestore(&port->lock, flags);
 }
 
 static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset)
@@ -285,6 +291,8 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
                port[i].chip.base = i * 32;
                port[i].chip.ngpio = 32;
 
+               spin_lock_init(&port[i].lock);
+
                /* its a serious configuration bug when it fails */
                BUG_ON( gpiochip_add(&port[i].chip) < 0 );
 
@@ -292,6 +300,12 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
                        /* setup one handler for each entry */
                        set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
                        set_irq_data(port[i].irq, &port[i]);
+                       if (port[i].irq_high) {
+                               /* setup handler for GPIO 16 to 31 */
+                               set_irq_chained_handler(port[i].irq_high,
+                                               mx3_gpio_irq_handler);
+                               set_irq_data(port[i].irq_high, &port[i]);
+                       }
                }
        }
 

diff --git a/arch/arm/plat-mxc/include/mach/3ds_debugboard.h b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h
new file mode 100644 (file)
index 0000000..a384fdd
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_MXC_3DS_DB_H__
+#define __ASM_ARCH_MXC_3DS_DB_H__
+
+extern int __init mxc_expio_init(u32 base, u32 p_irq);
+
+#endif /* __ASM_ARCH_MXC_3DS_DB_H__ */

diff --git a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h b/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
deleted file mode 100644 (file)
index 0376c13..0000000
--- a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>.
- * All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__
-#define __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__
-
-#endif

diff --git a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h
deleted file mode 100644 (file)
index 93cc66f..0000000
--- a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- *  Copyright (C) 2009  Yoichi Yuasa <yuasa@linux-mips.org>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
- */
-#ifndef __ARM_ARCH_BOARD_KZM_ARM11_H
-#define __ARM_ARCH_BOARD_KZM_ARM11_H
-
-/*
- *  KZM-ARM11-01 Board Control Registers on FPGA
- */
-#define KZM_ARM11_CTL1         (MX31_CS4_BASE_ADDR + 0x1000)
-#define KZM_ARM11_CTL2         (MX31_CS4_BASE_ADDR + 0x1001)
-#define KZM_ARM11_RSW1         (MX31_CS4_BASE_ADDR + 0x1002)
-#define KZM_ARM11_BACK_LIGHT   (MX31_CS4_BASE_ADDR + 0x1004)
-#define KZM_ARM11_FPGA_REV     (MX31_CS4_BASE_ADDR + 0x1008)
-#define KZM_ARM11_7SEG_LED     (MX31_CS4_BASE_ADDR + 0x1010)
-#define KZM_ARM11_LEDS         (MX31_CS4_BASE_ADDR + 0x1020)
-#define KZM_ARM11_DIPSW2       (MX31_CS4_BASE_ADDR + 0x1003)
-
-/*
- * External UART for touch panel on FPGA
- */
-#define KZM_ARM11_16550                (MX31_CS4_BASE_ADDR + 0x1050)
-
-#endif /* __ARM_ARCH_BOARD_KZM_ARM11_H */
-

diff --git a/arch/arm/plat-mxc/include/mach/board-mx21ads.h b/arch/arm/plat-mxc/include/mach/board-mx21ads.h
deleted file mode 100644 (file)
index 0cf4fa2..0000000
--- a/arch/arm/plat-mxc/include/mach/board-mx21ads.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX21ADS_H__
-#define __ASM_ARCH_MXC_BOARD_MX21ADS_H__
-
-/*
- * Memory-mapped I/O on MX21ADS base board
- */
-#define MX21ADS_MMIO_BASE_ADDR   0xF5000000
-#define MX21ADS_MMIO_SIZE        SZ_16M
-
-#define MX21ADS_REG_ADDR(offset)    (void __force __iomem *) \
-               (MX21ADS_MMIO_BASE_ADDR + (offset))
-
-#define MX21ADS_CS8900A_IRQ         IRQ_GPIOE(11)
-#define MX21ADS_CS8900A_IOBASE_REG  MX21ADS_REG_ADDR(0x000000)
-#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
-#define MX21ADS_VERSION_REG         MX21ADS_REG_ADDR(0x400000)
-#define MX21ADS_IO_REG              MX21ADS_REG_ADDR(0x800000)
-
-/* MX21ADS_IO_REG bit definitions */
-#define MX21ADS_IO_SD_WP        0x0001 /* read */
-#define MX21ADS_IO_TP6          0x0001 /* write */
-#define MX21ADS_IO_SW_SEL       0x0002 /* read */
-#define MX21ADS_IO_TP7          0x0002 /* write */
-#define MX21ADS_IO_RESET_E_UART 0x0004
-#define MX21ADS_IO_RESET_BASE   0x0008
-#define MX21ADS_IO_CSI_CTL2     0x0010
-#define MX21ADS_IO_CSI_CTL1     0x0020
-#define MX21ADS_IO_CSI_CTL0     0x0040
-#define MX21ADS_IO_UART1_EN     0x0080
-#define MX21ADS_IO_UART4_EN     0x0100
-#define MX21ADS_IO_LCDON        0x0200
-#define MX21ADS_IO_IRDA_EN      0x0400
-#define MX21ADS_IO_IRDA_FIR_SEL 0x0800
-#define MX21ADS_IO_IRDA_MD0_B   0x1000
-#define MX21ADS_IO_IRDA_MD1     0x2000
-#define MX21ADS_IO_LED4_ON      0x4000
-#define MX21ADS_IO_LED3_ON      0x8000
-
-#endif                         /* __ASM_ARCH_MXC_BOARD_MX21ADS_H__ */

diff --git a/arch/arm/plat-mxc/include/mach/board-mx27ads.h b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
deleted file mode 100644 (file)
index 7776d23..0000000
--- a/arch/arm/plat-mxc/include/mach/board-mx27ads.h
+++ /dev/null
@@ -1,344 +0,0 @@
-/*
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX27ADS_H__
-#define __ASM_ARCH_MXC_BOARD_MX27ADS_H__
-
-/* external interrupt multiplexer */
-#define MXC_EXP_IO_BASE                (MXC_BOARD_IRQ_START)
-
-#define MXC_VIRTUAL_INTS_BASE  (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
-#define MXC_SDIO1_CARD_IRQ     MXC_VIRTUAL_INTS_BASE
-#define MXC_SDIO2_CARD_IRQ     (MXC_VIRTUAL_INTS_BASE + 1)
-#define MXC_SDIO3_CARD_IRQ     (MXC_VIRTUAL_INTS_BASE + 2)
-
-#define MXC_MAX_BOARD_INTS      (MXC_MAX_EXP_IO_LINES + \
-                               MXC_MAX_VIRTUAL_INTS)
-
-/*
- * @name Memory Size parameters
- */
-
-/*
- * Size of SDRAM memory
- */
-#define SDRAM_MEM_SIZE          SZ_128M
-
-/*
- * PBC Controller parameters
- */
-
-/*
- * Base address of PBC controller, CS4
- */
-#define PBC_BASE_ADDRESS        0xf4300000
-#define PBC_REG_ADDR(offset)    (void __force __iomem *) \
-               (PBC_BASE_ADDRESS + (offset))
-
-/*
- * PBC Interupt name definitions
- */
-#define PBC_GPIO1_0  0
-#define PBC_GPIO1_1  1
-#define PBC_GPIO1_2  2
-#define PBC_GPIO1_3  3
-#define PBC_GPIO1_4  4
-#define PBC_GPIO1_5  5
-
-#define PBC_INTR_MAX_NUM 6
-#define PBC_INTR_SHARED_MAX_NUM 8
-
-/* When the PBC address connection is fixed in h/w, defined as 1 */
-#define PBC_ADDR_SH             0
-
-/* Offsets for the PBC Controller register */
-/*
- * PBC Board version register offset
- */
-#define PBC_VERSION_REG         PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 1 set address.
- */
-#define PBC_BCTRL1_SET_REG      PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 1 clear address.
- */
-#define PBC_BCTRL1_CLEAR_REG    PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
-/*
- * PBC Board control register 2 set address.
- */
-#define PBC_BCTRL2_SET_REG      PBC_REG_ADDR(0x00010 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 2 clear address.
- */
-#define PBC_BCTRL2_CLEAR_REG    PBC_REG_ADDR(0x00014 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 3 set address.
- */
-#define PBC_BCTRL3_SET_REG      PBC_REG_ADDR(0x00018 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 3 clear address.
- */
-#define PBC_BCTRL3_CLEAR_REG    PBC_REG_ADDR(0x0001C >> PBC_ADDR_SH)
-/*
- * PBC Board control register 3 set address.
- */
-#define PBC_BCTRL4_SET_REG      PBC_REG_ADDR(0x00020 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 4 clear address.
- */
-#define PBC_BCTRL4_CLEAR_REG    PBC_REG_ADDR(0x00024 >> PBC_ADDR_SH)
-/*PBC_ADDR_SH
- * PBC Board status register 1.
- */
-#define PBC_BSTAT1_REG          PBC_REG_ADDR(0x00028 >> PBC_ADDR_SH)
-/*
- * PBC Board interrupt status register.
- */
-#define PBC_INTSTATUS_REG       PBC_REG_ADDR(0x0002C >> PBC_ADDR_SH)
-/*
- * PBC Board interrupt current status register.
- */
-#define PBC_INTCURR_STATUS_REG  PBC_REG_ADDR(0x00034 >> PBC_ADDR_SH)
-/*
- * PBC Interrupt mask register set address.
- */
-#define PBC_INTMASK_SET_REG     PBC_REG_ADDR(0x00038 >> PBC_ADDR_SH)
-/*
- * PBC Interrupt mask register clear address.
- */
-#define PBC_INTMASK_CLEAR_REG   PBC_REG_ADDR(0x0003C >> PBC_ADDR_SH)
-/*
- * External UART A.
- */
-#define PBC_SC16C652_UARTA_REG  PBC_REG_ADDR(0x20000 >> PBC_ADDR_SH)
-/*
- * UART 4 Expanding Signal Status.
- */
-#define PBC_UART_STATUS_REG     PBC_REG_ADDR(0x22000 >> PBC_ADDR_SH)
-/*
- * UART 4 Expanding Signal Control Set.
- */
-#define PBC_UCTRL_SET_REG       PBC_REG_ADDR(0x24000 >> PBC_ADDR_SH)
-/*
- * UART 4 Expanding Signal Control Clear.
- */
-#define PBC_UCTRL_CLR_REG       PBC_REG_ADDR(0x26000 >> PBC_ADDR_SH)
-/*
- * Ethernet Controller IO base address.
- */
-#define PBC_CS8900A_IOBASE_REG  PBC_REG_ADDR(0x40000 >> PBC_ADDR_SH)
-/*
- * Ethernet Controller Memory base address.
- */
-#define PBC_CS8900A_MEMBASE_REG PBC_REG_ADDR(0x42000 >> PBC_ADDR_SH)
-/*
- * Ethernet Controller DMA base address.
- */
-#define PBC_CS8900A_DMABASE_REG PBC_REG_ADDR(0x44000 >> PBC_ADDR_SH)
-
-/* PBC Board Version Register bit definition */
-#define PBC_VERSION_ADS         0x8000 /* Bit15=1 means version for ads */
-#define PBC_VERSION_EVB_REVB    0x4000 /* BIT14=1 means version for evb revb */
-
-/* PBC Board Control Register 1 bit definitions */
-#define PBC_BCTRL1_ERST         0x0001 /* Ethernet Reset */
-#define PBC_BCTRL1_URST         0x0002 /* Reset External UART controller */
-#define PBC_BCTRL1_FRST         0x0004 /* FEC Reset */
-#define PBC_BCTRL1_ESLEEP       0x0010 /* Enable ethernet Sleep */
-#define PBC_BCTRL1_LCDON        0x0800 /* Enable the LCD */
-
-/* PBC Board Control Register 2 bit definitions */
-#define PBC_BCTRL2_VCC_EN       0x0004 /*   Enable VCC */
-#define PBC_BCTRL2_VPP_EN       0x0008 /*   Enable Vpp */
-#define PBC_BCTRL2_ATAFEC_EN    0X0010
-#define PBC_BCTRL2_ATAFEC_SEL   0X0020
-#define PBC_BCTRL2_ATA_EN       0X0040
-#define PBC_BCTRL2_IRDA_SD      0X0080
-#define PBC_BCTRL2_IRDA_EN      0X0100
-#define PBC_BCTRL2_CCTL10       0X0200
-#define PBC_BCTRL2_CCTL11       0X0400
-
-/* PBC Board Control Register 3 bit definitions */
-#define PBC_BCTRL3_HSH_EN       0X0020
-#define PBC_BCTRL3_FSH_MOD      0X0040
-#define PBC_BCTRL3_OTG_HS_EN    0X0080
-#define PBC_BCTRL3_OTG_VBUS_EN  0X0100
-#define PBC_BCTRL3_FSH_VBUS_EN  0X0200
-#define PBC_BCTRL3_USB_OTG_ON   0X0800
-#define PBC_BCTRL3_USB_FSH_ON   0X1000
-
-/* PBC Board Control Register 4 bit definitions */
-#define PBC_BCTRL4_REGEN_SEL    0X0001
-#define PBC_BCTRL4_USER_OFF     0X0002
-#define PBC_BCTRL4_VIB_EN       0X0004
-#define PBC_BCTRL4_PWRGT1_EN    0X0008
-#define PBC_BCTRL4_PWRGT2_EN    0X0010
-#define PBC_BCTRL4_STDBY_PRI    0X0020
-
-#ifndef __ASSEMBLY__
-/*
- * Enumerations for SD cards and memory stick card. This corresponds to
- * the card EN bits in the IMR: SD1_EN | MS_EN | SD3_EN | SD2_EN.
- */
-enum mxc_card_no {
-       MXC_CARD_SD2 = 0,
-       MXC_CARD_SD3,
-       MXC_CARD_MS,
-       MXC_CARD_SD1,
-       MXC_CARD_MIN = MXC_CARD_SD2,
-       MXC_CARD_MAX = MXC_CARD_SD1,
-};
-#endif
-
-#define MXC_CPLD_VER_1_50       0x01
-
-/*
- * PBC BSTAT Register bit definitions
- */
-#define PBC_BSTAT_PRI_INT       0X0001
-#define PBC_BSTAT_USB_BYP       0X0002
-#define PBC_BSTAT_ATA_IOCS16    0X0004
-#define PBC_BSTAT_ATA_CBLID     0X0008
-#define PBC_BSTAT_ATA_DASP      0X0010
-#define PBC_BSTAT_PWR_RDY       0X0020
-#define PBC_BSTAT_SD3_WP        0X0100
-#define PBC_BSTAT_SD2_WP        0X0200
-#define PBC_BSTAT_SD1_WP        0X0400
-#define PBC_BSTAT_SD3_DET       0X0800
-#define PBC_BSTAT_SD2_DET       0X1000
-#define PBC_BSTAT_SD1_DET       0X2000
-#define PBC_BSTAT_MS_DET        0X4000
-#define PBC_BSTAT_SD3_DET_BIT   11
-#define PBC_BSTAT_SD2_DET_BIT   12
-#define PBC_BSTAT_SD1_DET_BIT   13
-#define PBC_BSTAT_MS_DET_BIT    14
-#define MXC_BSTAT_BIT(n)        ((n == MXC_CARD_SD2) ? PBC_BSTAT_SD2_DET : \
-                                ((n == MXC_CARD_SD3) ? PBC_BSTAT_SD3_DET : \
-                                ((n == MXC_CARD_SD1) ? PBC_BSTAT_SD1_DET : \
-                                ((n == MXC_CARD_MS) ? PBC_BSTAT_MS_DET : \
-                                       0x0))))
-
-/*
- * PBC UART Control Register bit definitions
- */
-#define PBC_UCTRL_DCE_DCD       0X0001
-#define PBC_UCTRL_DCE_DSR       0X0002
-#define PBC_UCTRL_DCE_RI        0X0004
-#define PBC_UCTRL_DTE_DTR       0X0100
-
-/*
- * PBC UART Status Register bit definitions
- */
-#define PBC_USTAT_DTE_DCD       0X0001
-#define PBC_USTAT_DTE_DSR       0X0002
-#define PBC_USTAT_DTE_RI        0X0004
-#define PBC_USTAT_DCE_DTR       0X0100
-
-/*
- * PBC Interupt mask register bit definitions
- */
-#define PBC_INTR_SD3_R_EN_BIT   4
-#define PBC_INTR_SD2_R_EN_BIT   0
-#define PBC_INTR_SD1_R_EN_BIT   6
-#define PBC_INTR_MS_R_EN_BIT    5
-#define PBC_INTR_SD3_EN_BIT     13
-#define PBC_INTR_SD2_EN_BIT     12
-#define PBC_INTR_MS_EN_BIT      14
-#define PBC_INTR_SD1_EN_BIT     15
-
-#define PBC_INTR_SD2_R_EN       0x0001
-#define PBC_INTR_LOW_BAT        0X0002
-#define PBC_INTR_OTG_FSOVER     0X0004
-#define PBC_INTR_FSH_OVER       0X0008
-#define PBC_INTR_SD3_R_EN       0x0010
-#define PBC_INTR_MS_R_EN        0x0020
-#define PBC_INTR_SD1_R_EN       0x0040
-#define PBC_INTR_FEC_INT        0X0080
-#define PBC_INTR_ENET_INT       0X0100
-#define PBC_INTR_OTGFS_INT      0X0200
-#define PBC_INTR_XUART_INT      0X0400
-#define PBC_INTR_CCTL12         0X0800
-#define PBC_INTR_SD2_EN         0x1000
-#define PBC_INTR_SD3_EN         0x2000
-#define PBC_INTR_MS_EN          0x4000
-#define PBC_INTR_SD1_EN         0x8000
-
-
-
-/* For interrupts like xuart, enet etc */
-#define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX27_PIN_TIN)
-#define MXC_MAX_EXP_IO_LINES    16
-
-/*
- * This corresponds to PBC_INTMASK_SET_REG at offset 0x38.
- *
- */
-#define EXPIO_INT_LOW_BAT       (MXC_EXP_IO_BASE + 1)
-#define EXPIO_INT_OTG_FS_OVR    (MXC_EXP_IO_BASE + 2)
-#define EXPIO_INT_FSH_OVR       (MXC_EXP_IO_BASE + 3)
-#define EXPIO_INT_RES4          (MXC_EXP_IO_BASE + 4)
-#define EXPIO_INT_RES5          (MXC_EXP_IO_BASE + 5)
-#define EXPIO_INT_RES6          (MXC_EXP_IO_BASE + 6)
-#define EXPIO_INT_FEC           (MXC_EXP_IO_BASE + 7)
-#define EXPIO_INT_ENET_INT      (MXC_EXP_IO_BASE + 8)
-#define EXPIO_INT_OTG_FS_INT    (MXC_EXP_IO_BASE + 9)
-#define EXPIO_INT_XUART_INTA    (MXC_EXP_IO_BASE + 10)
-#define EXPIO_INT_CCTL12_INT    (MXC_EXP_IO_BASE + 11)
-#define EXPIO_INT_SD2_EN        (MXC_EXP_IO_BASE + 12)
-#define EXPIO_INT_SD3_EN        (MXC_EXP_IO_BASE + 13)
-#define EXPIO_INT_MS_EN         (MXC_EXP_IO_BASE + 14)
-#define EXPIO_INT_SD1_EN        (MXC_EXP_IO_BASE + 15)
-
-/*
- * This is System IRQ used by CS8900A for interrupt generation
- * taken from platform.h
- */
-#define CS8900AIRQ              EXPIO_INT_ENET_INT
-/* This is I/O Base address used to access registers of CS8900A on MXC ADS */
-#define CS8900A_BASE_ADDRESS    (PBC_CS8900A_IOBASE_REG + 0x300)
-
-#define MXC_PMIC_INT_LINE       IOMUX_TO_IRQ(MX27_PIN_TOUT)
-
-/*
-* This is used to detect if the CPLD version is for mx27 evb board rev-a
-*/
-#define PBC_CPLD_VERSION_IS_REVA() \
-       ((__raw_readw(PBC_VERSION_REG) & \
-       (PBC_VERSION_ADS | PBC_VERSION_EVB_REVB))\
-       == 0)
-
-/* This is used to active or inactive ata signal in CPLD .
- *  It is dependent with hardware
- */
-#define PBC_ATA_SIGNAL_ACTIVE() \
-       __raw_writew(           \
-               PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
-               PBC_BCTRL2_CLEAR_REG)
-
-#define PBC_ATA_SIGNAL_INACTIVE() \
-       __raw_writew(  \
-               PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
-               PBC_BCTRL2_SET_REG)
-
-#define MXC_BD_LED1             (1 << 5)
-#define MXC_BD_LED2             (1 << 6)
-#define MXC_BD_LED_ON(led) \
-       __raw_writew(led, PBC_BCTRL1_SET_REG)
-#define MXC_BD_LED_OFF(led) \
-       __raw_writew(led, PBC_BCTRL1_CLEAR_REG)
-
-/* to determine the correct external crystal reference */
-#define CKIH_27MHZ_BIT_SET      (1 << 3)
-
-#endif                         /* __ASM_ARCH_MXC_BOARD_MX27ADS_H__ */

diff --git a/arch/arm/plat-mxc/include/mach/board-mx27lite.h b/arch/arm/plat-mxc/include/mach/board-mx27lite.h
deleted file mode 100644 (file)
index ea87551..0000000
--- a/arch/arm/plat-mxc/include/mach/board-mx27lite.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX27LITE_H__
-#define __ASM_ARCH_MXC_BOARD_MX27LITE_H__
-
-#endif /* __ASM_ARCH_MXC_BOARD_MX27LITE_H__ */

diff --git a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h b/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
deleted file mode 100644 (file)
index fec1bcf..0000000
--- a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX27PDK_H__
-#define __ASM_ARCH_MXC_BOARD_MX27PDK_H__
-
-#endif /* __ASM_ARCH_MXC_BOARD_MX27PDK_H__ */

diff --git a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
deleted file mode 100644 (file)
index da92933..0000000
--- a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
-#define __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
-
-/* Definitions for components on the Debug board */
-
-/* Base address of CPLD controller on the Debug board */
-#define DEBUG_BASE_ADDRESS             CS5_IO_ADDRESS(CS5_BASE_ADDR)
-
-/* LAN9217 ethernet base address */
-#define LAN9217_BASE_ADDR              CS5_BASE_ADDR
-
-/* CPLD config and interrupt base address */
-#define CPLD_ADDR                      (DEBUG_BASE_ADDRESS + 0x20000)
-
-/* LED switchs */
-#define CPLD_LED_REG                   (CPLD_ADDR + 0x00)
-/* buttons */
-#define CPLD_SWITCH_BUTTONS_REG        (EXPIO_ADDR + 0x08)
-/* status, interrupt */
-#define CPLD_INT_STATUS_REG            (CPLD_ADDR + 0x10)
-#define CPLD_INT_MASK_REG              (CPLD_ADDR + 0x38)
-#define CPLD_INT_RESET_REG             (CPLD_ADDR + 0x20)
-/* magic word for debug CPLD */
-#define CPLD_MAGIC_NUMBER1_REG         (CPLD_ADDR + 0x40)
-#define CPLD_MAGIC_NUMBER2_REG         (CPLD_ADDR + 0x48)
-/* CPLD code version */
-#define CPLD_CODE_VER_REG              (CPLD_ADDR + 0x50)
-/* magic word for debug CPLD */
-#define CPLD_MAGIC_NUMBER3_REG         (CPLD_ADDR + 0x58)
-/* module reset register */
-#define CPLD_MODULE_RESET_REG          (CPLD_ADDR + 0x60)
-/* CPU ID and Personality ID */
-#define CPLD_MCU_BOARD_ID_REG          (CPLD_ADDR + 0x68)
-
-/* CPLD IRQ line for external uart, external ethernet etc */
-#define EXPIO_PARENT_INT       IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
-
-#define MXC_EXP_IO_BASE                (MXC_BOARD_IRQ_START)
-#define MXC_IRQ_TO_EXPIO(irq)  ((irq) - MXC_EXP_IO_BASE)
-
-#define EXPIO_INT_ENET         (MXC_EXP_IO_BASE + 0)
-#define EXPIO_INT_XUART_A      (MXC_EXP_IO_BASE + 1)
-#define EXPIO_INT_XUART_B      (MXC_EXP_IO_BASE + 2)
-#define EXPIO_INT_BUTTON_A     (MXC_EXP_IO_BASE + 3)
-#define EXPIO_INT_BUTTON_B     (MXC_EXP_IO_BASE + 4)
-
-#define MXC_MAX_EXP_IO_LINES   16
-
-#endif /* __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ */

diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
deleted file mode 100644 (file)
index 095a199..0000000
--- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
-#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
-
-#include <mach/hardware.h>
-
-/* Base address of PBC controller */
-#define PBC_BASE_ADDRESS        MX31_CS4_BASE_ADDR_VIRT
-/* Offsets for the PBC Controller register */
-
-/* PBC Board status register offset */
-#define PBC_BSTAT               0x000002
-
-/* PBC Board control register 1 set address */
-#define PBC_BCTRL1_SET          0x000004
-
-/* PBC Board control register 1 clear address */
-#define PBC_BCTRL1_CLEAR        0x000006
-
-/* PBC Board control register 2 set address */
-#define PBC_BCTRL2_SET          0x000008
-
-/* PBC Board control register 2 clear address */
-#define PBC_BCTRL2_CLEAR        0x00000A
-
-/* PBC Board control register 3 set address */
-#define PBC_BCTRL3_SET          0x00000C
-
-/* PBC Board control register 3 clear address */
-#define PBC_BCTRL3_CLEAR        0x00000E
-
-/* PBC Board control register 4 set address */
-#define PBC_BCTRL4_SET          0x000010
-
-/* PBC Board control register 4 clear address */
-#define PBC_BCTRL4_CLEAR        0x000012
-
-/* PBC Board status register 1 */
-#define PBC_BSTAT1              0x000014
-
-/* PBC Board interrupt status register */
-#define PBC_INTSTATUS           0x000016
-
-/* PBC Board interrupt current status register */
-#define PBC_INTCURR_STATUS      0x000018
-
-/* PBC Interrupt mask register set address */
-#define PBC_INTMASK_SET         0x00001A
-
-/* PBC Interrupt mask register clear address */
-#define PBC_INTMASK_CLEAR       0x00001C
-
-/* External UART A */
-#define PBC_SC16C652_UARTA      0x010000
-
-/* External UART B */
-#define PBC_SC16C652_UARTB      0x010010
-
-/* Ethernet Controller IO base address */
-#define PBC_CS8900A_IOBASE      0x020000
-
-/* Ethernet Controller Memory base address */
-#define PBC_CS8900A_MEMBASE     0x021000
-
-/* Ethernet Controller DMA base address */
-#define PBC_CS8900A_DMABASE     0x022000
-
-/* External chip select 0 */
-#define PBC_XCS0                0x040000
-
-/* LCD Display enable */
-#define PBC_LCD_EN_B            0x060000
-
-/* Code test debug enable */
-#define PBC_CODE_B              0x070000
-
-/* PSRAM memory select */
-#define PBC_PSRAM_B             0x5000000
-
-#define PBC_INTSTATUS_REG      (PBC_INTSTATUS + PBC_BASE_ADDRESS)
-#define PBC_INTCURR_STATUS_REG (PBC_INTCURR_STATUS + PBC_BASE_ADDRESS)
-#define PBC_INTMASK_SET_REG    (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
-#define PBC_INTMASK_CLEAR_REG  (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
-#define EXPIO_PARENT_INT       IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
-
-#define MXC_EXP_IO_BASE                (MXC_BOARD_IRQ_START)
-#define MXC_IRQ_TO_EXPIO(irq)  ((irq) - MXC_EXP_IO_BASE)
-
-#define EXPIO_INT_LOW_BAT      (MXC_EXP_IO_BASE + 0)
-#define EXPIO_INT_PB_IRQ       (MXC_EXP_IO_BASE + 1)
-#define EXPIO_INT_OTG_FS_OVR   (MXC_EXP_IO_BASE + 2)
-#define EXPIO_INT_FSH_OVR      (MXC_EXP_IO_BASE + 3)
-#define EXPIO_INT_RES4         (MXC_EXP_IO_BASE + 4)
-#define EXPIO_INT_RES5         (MXC_EXP_IO_BASE + 5)
-#define EXPIO_INT_RES6         (MXC_EXP_IO_BASE + 6)
-#define EXPIO_INT_RES7         (MXC_EXP_IO_BASE + 7)
-#define EXPIO_INT_ENET_INT     (MXC_EXP_IO_BASE + 8)
-#define EXPIO_INT_OTG_FS_INT   (MXC_EXP_IO_BASE + 9)
-#define EXPIO_INT_XUART_INTA   (MXC_EXP_IO_BASE + 10)
-#define EXPIO_INT_XUART_INTB   (MXC_EXP_IO_BASE + 11)
-#define EXPIO_INT_SYNTH_IRQ    (MXC_EXP_IO_BASE + 12)
-#define EXPIO_INT_CE_INT1      (MXC_EXP_IO_BASE + 13)
-#define EXPIO_INT_CE_INT2      (MXC_EXP_IO_BASE + 14)
-#define EXPIO_INT_RES15                (MXC_EXP_IO_BASE + 15)
-
-#define MXC_MAX_EXP_IO_LINES   16
-
-#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */

diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
index eb5a5024622efbe9da16228e44b338b51037f559..0df71bfefbb10819883de74f5bae623227b0d7f5 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
@@ -31,7 +31,7 @@ enum mx31lilly_boards {
 
 /*
  * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls baseboard's init function.
+ * its own devices, it calls the baseboard's init function.
  */
 
 extern void mx31lilly_db_init(void);

diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
index 2b2da0367578dbb13a4dbf6e12894709f079acec..c1ad0ae807cc57ee20cbddd3cb8021efe61196c6 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/board-mx31lite.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
@@ -32,7 +32,7 @@ enum mx31lite_boards {
 
 /*
  * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls baseboard's init function.
+ * its own devices, it calls the baseboard's init function.
  */
 
 extern void mx31lite_db_init(void);

diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
index 36ff3cedee1a1d3cd3d7ffbc1c32ab185ed1cdcf..de14543891cf4b40ff569fbc7a889170fdbb5c7f 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
@@ -31,7 +31,7 @@ enum mx31moboard_boards {
 
 /*
  * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls baseboard's init function.
+ * its own devices, it calls the baseboard's init function.
  */
 
 extern void mx31moboard_devboard_init(void);

diff --git a/arch/arm/plat-mxc/include/mach/board-pcm038.h b/arch/arm/plat-mxc/include/mach/board-pcm038.h
index 410f9786ed2292d7c909ddd2b690a8d7cbf83c51..6f371e35753dfbb557840a0307a931685615563a 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/board-pcm038.h
+++ b/arch/arm/plat-mxc/include/mach/board-pcm038.h
@@ -22,7 +22,7 @@
 #ifndef __ASSEMBLY__
 /*
  * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls baseboard's init function.
+ * its own devices, it calls the baseboard's init function.
  * TODO: Add your own baseboard init function and call it from
  * inside pcm038_init().
  *

diff --git a/arch/arm/plat-mxc/include/mach/board-qong.h b/arch/arm/plat-mxc/include/mach/board-qong.h
deleted file mode 100644 (file)
index 6d88c7a..0000000
--- a/arch/arm/plat-mxc/include/mach/board-qong.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_QONG_H__
-#define __ASM_ARCH_MXC_BOARD_QONG_H__
-
-/* NOR FLASH */
-#define QONG_NOR_SIZE          (128*1024*1024)
-
-#endif /* __ASM_ARCH_MXC_BOARD_QONG_H__ */

diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 0b6e11eaeb8ca0b2d64c847810a44fbc96355909..25606409aabcfb7de02a3dbce55e7221b68d2ece 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -23,8 +23,8 @@
 #error "CONFIG_DEBUG_LL is incompatible with multiple archs"
 #endif
 #include <mach/mx25.h>
-#define UART_PADDR     UART1_BASE_ADDR
-#define UART_VADDR     MX25_AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
+#define UART_PADDR     MX25_UART1_BASE_ADDR
+#define UART_VADDR     MX25_AIPS1_IO_ADDRESS(MX25_UART1_BASE_ADDR)
 #endif
 
 #ifdef CONFIG_ARCH_MX2

diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
new file mode 100644 (file)
index 0000000..c5f68c5
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+
+struct platform_device *imx_add_platform_device(const char *name, int id,
+               const struct resource *res, unsigned int num_resources,
+               const void *data, size_t size_data);
+
+#if defined (CONFIG_CAN_FLEXCAN) || defined (CONFIG_CAN_FLEXCAN_MODULE)
+#include <linux/can/platform/flexcan.h>
+struct platform_device *__init imx_add_flexcan(int id,
+               resource_size_t iobase, resource_size_t iosize,
+               resource_size_t irq,
+               const struct flexcan_platform_data *pdata);
+#else
+/* the ifdef can be removed once the flexcan driver has been merged */
+struct flexcan_platform_data;
+static inline struct platform_device *__init imx_add_flexcan(int id,
+               resource_size_t iobase, resource_size_t iosize,
+               resource_size_t irq,
+               const struct flexcan_platform_data *pdata)
+{
+       return NULL;
+}
+#endif
+
+#include <mach/i2c.h>
+struct platform_device *__init imx_add_imx_i2c(int id,
+               resource_size_t iobase, resource_size_t iosize, int irq,
+               const struct imxi2c_platform_data *pdata);
+
+#include <mach/imx-uart.h>
+struct platform_device *__init imx_add_imx_uart_3irq(int id,
+               resource_size_t iobase, resource_size_t iosize,
+               resource_size_t irqrx, resource_size_t irqtx,
+               resource_size_t irqrts,
+               const struct imxuart_platform_data *pdata);
+struct platform_device *__init imx_add_imx_uart_1irq(int id,
+               resource_size_t iobase, resource_size_t iosize,
+               resource_size_t irq,
+               const struct imxuart_platform_data *pdata);
+
+#include <mach/mxc_nand.h>
+struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase,
+               int irq, const struct mxc_nand_platform_data *pdata);
+struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase,
+               int irq, const struct mxc_nand_platform_data *pdata);
+
+#include <mach/spi.h>
+struct platform_device *__init imx_add_spi_imx(int id,
+               resource_size_t iobase, resource_size_t iosize, int irq,
+               const struct spi_imx_master *pdata);

diff --git a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h b/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h
similarity index 64%
rename from arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h
rename to arch/arm/plat-mxc/include/mach/eukrea-baseboards.h
index a1fd5830af484758c21c70d453b595746f063091..634e3f4c454df222728aa678bdcd657967286dbc 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h
+++ b/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2009 Eric Benard - eric@eukrea.com
+ * Copyright (C) 2010 Eric Benard - eric@eukrea.com
  *
  * Based on board-pcm038.h which is :
  * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
@@ -19,22 +19,29 @@
  * MA 02110-1301, USA.
  */
 
-#ifndef __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__
-#define __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__
+#ifndef __MACH_EUKREA_BASEBOARDS_H__
+#define __MACH_EUKREA_BASEBOARDS_H__
 
 #ifndef __ASSEMBLY__
 /*
  * This CPU module needs a baseboard to work. After basic initializing
  * its own devices, it calls baseboard's init function.
  * TODO: Add your own baseboard init function and call it from
- * inside eukrea_cpuimx27_init().
+ * inside eukrea_cpuimx25_init() eukrea_cpuimx27_init()
+ * eukrea_cpuimx35_init() or eukrea_cpuimx51_init().
  *
  * This example here is for the development board. Refer
- * eukrea_mbimx27-baseboard.c
+ * mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25
+ * mach-imx/eukrea_mbimx27-baseboard.c for cpuimx27
+ * mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35
+ * mach-mx5/eukrea_mbimx51-baseboard.c for cpuimx51
  */
 
+extern void eukrea_mbimx25_baseboard_init(void);
 extern void eukrea_mbimx27_baseboard_init(void);
+extern void eukrea_mbimx35_baseboard_init(void);
+extern void eukrea_mbimx51_baseboard_init(void);
 
 #endif
 
-#endif /* __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__ */
+#endif /* __MACH_EUKREA_BASEBOARDS_H__ */

diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h
index 894d2f87c85600c495d117a6d0f524060ee15aaa..661fbc6057597c2bec30545af8904396ad4d4328 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/gpio.h
+++ b/arch/arm/plat-mxc/include/mach/gpio.h
@@ -33,9 +33,11 @@
 struct mxc_gpio_port {
        void __iomem *base;
        int irq;
+       int irq_high;
        int virtual_irq_start;
        struct gpio_chip chip;
        u32 both_edges;
+       spinlock_t lock;
 };
 
 int mxc_gpio_init(struct mxc_gpio_port*, int);

diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
index f39220d1b67af1112a31ab72f713f0c45153df6d..d7f52c91f82edb09f5aa686abdae16b6ce78963b 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -252,6 +252,7 @@
 #define MX25_PAD_OE_ACD__GPIO_1_25     IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_CONTRAST__CONTRAST    IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CONTRAST__PWM4_PWMO   IOMUX_PAD(0x310, 0x118, 0x14, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_CONTRAST__FEC_CRS     IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL)
 
 #define MX25_PAD_PWM__PWM              IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL)
@@ -371,30 +372,41 @@
 #define MX25_PAD_SD1_DATA3__FEC_CRS    IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL)
 #define MX25_PAD_SD1_DATA3__GPIO_2_28  IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_KPP_ROW0__KPP_ROW0    IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, PAD_CTL_PKE)
+#define KPP_CTL_ROW    (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define KPP_CTL_COL    (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+#define MX25_PAD_KPP_ROW0__KPP_ROW0    IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, KPP_CTL_ROW)
 #define MX25_PAD_KPP_ROW0__GPIO_2_29   IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_KPP_ROW1__KPP_ROW1    IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_KPP_ROW1__KPP_ROW1    IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, KPP_CTL_ROW)
 #define MX25_PAD_KPP_ROW1__GPIO_2_30   IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_KPP_ROW2__KPP_ROW2    IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_KPP_ROW2__KPP_ROW2    IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, KPP_CTL_ROW)
 #define MX25_PAD_KPP_ROW2__CSI_D0      IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL)
 #define MX25_PAD_KPP_ROW2__GPIO_2_31   IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_KPP_ROW3__KPP_ROW3    IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_KPP_ROW3__KPP_ROW3    IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, KPP_CTL_ROW)
 #define MX25_PAD_KPP_ROW3__CSI_LD1     IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL)
 #define MX25_PAD_KPP_ROW3__GPIO_3_0    IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_KPP_COL0__KPP_COL0    IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL0__KPP_COL0    IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, KPP_CTL_COL)
+#define MX25_PAD_KPP_COL0__UART4_RXD_MUX IOMUX_PAD(0x3b0, 0x1b8, 0x11, 0x570, 1, NO_PAD_CTRL)
+#define MX25_PAD_KPP_COL0__AUD5_TXD    IOMUX_PAD(0x3b0, 0x1b8, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
 #define MX25_PAD_KPP_COL0__GPIO_3_1    IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_KPP_COL1__KPP_COL1    IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL1__KPP_COL1    IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, KPP_CTL_COL)
+#define MX25_PAD_KPP_COL1__UART4_TXD_MUX IOMUX_PAD(0x3b4, 0x1bc, 0x11, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_KPP_COL1__AUD5_RXD    IOMUX_PAD(0x3b4, 0x1bc, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
 #define MX25_PAD_KPP_COL1__GPIO_3_2    IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_KPP_COL2__KPP_COL2    IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL2__KPP_COL2    IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, KPP_CTL_COL)
+#define MX25_PAD_KPP_COL2__UART4_RTS   IOMUX_PAD(0x3b8, 0x1c0, 0x11, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_KPP_COL2__AUD5_TXC    IOMUX_PAD(0x3b8, 0x1c0, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
 #define MX25_PAD_KPP_COL2__GPIO_3_3    IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_KPP_COL3__KPP_COL3    IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL3__KPP_COL3    IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, KPP_CTL_COL)
+#define MX25_PAD_KPP_COL3__UART4_CTS   IOMUX_PAD(0x3bc, 0x1c4, 0x11, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_KPP_COL3__AUD5_TXFS   IOMUX_PAD(0x3bc, 0x1c4, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
 #define MX25_PAD_KPP_COL3__GPIO_3_4    IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_FEC_MDC__FEC_MDC      IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL)

diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index ab0f95d953d02539ab76e69973056814a79ffcd4..21bfa46785bb5254e16ed1cfd8f36d7e384dbfcc 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -27,8 +27,8 @@ typedef enum iomux_config {
        IOMUX_CONFIG_ALT5,
        IOMUX_CONFIG_ALT6,
        IOMUX_CONFIG_ALT7,
-       IOMUX_CONFIG_GPIO,      /* added to help user use GPIO mode */
-       IOMUX_CONFIG_SION = 0x1 << 4,   /* LOOPBACK:MUX SION bit */
+       IOMUX_CONFIG_GPIO,      /* added to help user use GPIO mode */
+       IOMUX_CONFIG_SION = 0x1 << 4,   /* LOOPBACK:MUX SION bit */
 } iomux_pin_cfg_t;
 
 /* Pad control groupings */
@@ -38,6 +38,8 @@ typedef enum iomux_config {
                                PAD_CTL_SRE_FAST)
 #define MX51_UART3_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
                                PAD_CTL_SRE_FAST)
+#define MX51_I2C_PAD_CTRL      (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
+                               PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)
 #define MX51_USBH1_PAD_CTRL    (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
                                PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
                                PAD_CTL_PKE | PAD_CTL_HYS)
@@ -46,289 +48,278 @@ typedef enum iomux_config {
 
 /*
  * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named
- * GPIO_<unit>_<num> see also iomux-v3.h
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
+ * See also iomux-v3.h
  */
 
-/*
- * FIXME: This was converted using scripts from existing Freescale code to
- * this form used upstream. Need to verify the name format.
- */
-
-/*                                             PAD      MUX   ALT INPSE PATH PADCTRL */
-
-#define MX51_PAD_GPIO_2_0__EIM_D16     IOMUX_PAD(0x3f0, 0x05c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_1__EIM_D17     IOMUX_PAD(0x3f4, 0x060, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_2__EIM_D18     IOMUX_PAD(0x3f8, 0x064, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_3__EIM_D19     IOMUX_PAD(0x3fc, 0x068, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_4__EIM_D20     IOMUX_PAD(0x400, 0x06c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_5__EIM_D21     IOMUX_PAD(0x404, 0x070, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__GPIO_2_5     IOMUX_PAD(0x404, 0x070, IOMUX_CONFIG_ALT1, 0x0,   0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_6__EIM_D22     IOMUX_PAD(0x408, 0x074, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_7__EIM_D23     IOMUX_PAD(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)
-
-/* Babbage UART3 */
-#define MX51_PAD_EIM_D24__UART3_CTS    IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D25__UART3_RXD    IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D26__UART3_TXD    IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D27__UART3_RTS    IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
-
-#define MX51_PAD_EIM_D28__EIM_D28      IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__EIM_D29      IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__EIM_D30      IOMUX_PAD(0x428, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__EIM_D31      IOMUX_PAD(0x42c, 0x09c, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_2_10__EIM_A16    IOMUX_PAD(0x430, 0x09c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_11__EIM_A17    IOMUX_PAD(0x434, 0x0a0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_12__EIM_A18    IOMUX_PAD(0x438, 0x0a4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_13__EIM_A19    IOMUX_PAD(0x43c, 0x0a8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_14__EIM_A20    IOMUX_PAD(0x440, 0x0ac, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_15__EIM_A21    IOMUX_PAD(0x444, 0x0b0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_16__EIM_A22    IOMUX_PAD(0x448, 0x0b4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_17__EIM_A23    IOMUX_PAD(0x44c, 0x0b8, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_2_18__EIM_A24    IOMUX_PAD(0x450, 0x0bc, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_19__EIM_A25    IOMUX_PAD(0x454, 0x0c0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_20__EIM_A26    IOMUX_PAD(0x458, 0x0c4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_21__EIM_A27    IOMUX_PAD(0x45c, 0x0c8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB0__EIM_EB0      IOMUX_PAD(0x460, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB1__EIM_EB1      IOMUX_PAD(0x464, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_22__EIM_EB2    IOMUX_PAD(0x468, 0x0d4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_23__EIM_EB3    IOMUX_PAD(0x46c, 0x0d8, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_2_24__EIM_OE     IOMUX_PAD(0x470, 0x0dc, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_25__EIM_CS0    IOMUX_PAD(0x474, 0x0e0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_26__EIM_CS1    IOMUX_PAD(0x478, 0x0e4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_27__EIM_CS2    IOMUX_PAD(0x47c, 0x0e8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_28__EIM_CS3    IOMUX_PAD(0x480, 0x0ec, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_29__EIM_CS4    IOMUX_PAD(0x484, 0x0f0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_30__EIM_CS5    IOMUX_PAD(0x488, 0x0f4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_31__EIM_DTACK  IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_3_1__EIM_LBA     IOMUX_PAD(0x494, 0xFC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_2__EIM_CRE     IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DRAM_CS1__DRAM_CS1    IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_3__NANDF_WE_B  IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_4__NANDF_RE_B  IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_5__NANDF_ALE   IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_6__NANDF_CLE   IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_7__NANDF_WP_B  IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_8__NANDF_RB0   IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_9__NANDF_RB1   IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_10__NANDF_RB2  IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_11__NANDF_RB3  IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_12__GPIO_NAND  IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL)
-/* REVISIT: Not sure of these values
-
-  #define MX51_PAD_GPIO_1___NANDF_RB4  IOMUX_PAD(, , , 0x0, 0, NO_PAD_CTRL)
-  #define MX51_PAD_GPIO_3_13__NANDF_RB5        IOMUX_PAD(0x5D8, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
-  #define MX51_PAD_GPIO_3_15__NANDF_RB7        IOMUX_PAD(0x5E0, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
-*/
-#define MX51_PAD_GPIO_3_14__NANDF_RB6  IOMUX_PAD(0x5DC, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_16__NANDF_CS0  IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_17__NANDF_CS1  IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_18__NANDF_CS2  IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_19__NANDF_CS3  IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_20__NANDF_CS4  IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_21__NANDF_CS5  IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_22__NANDF_CS6  IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_23__NANDF_CS7  IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_24__NANDF_RDY_INT      IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_25__NANDF_D15  IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_26__NANDF_D14  IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_27__NANDF_D13  IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_28__NANDF_D12  IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_29__NANDF_D11  IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_30__NANDF_D10  IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_31__NANDF_D9   IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_0__NANDF_D8    IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_1__NANDF_D7    IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_2__NANDF_D6    IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_3__NANDF_D5    IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_4__NANDF_D4    IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_5__NANDF_D3    IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_6__NANDF_D2    IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_7__NANDF_D1    IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_8__NANDF_D0    IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_12__CSI1_D8    IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_13__CSI1_D9    IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D10__CSI1_D10    IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D11__CSI1_D11    IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D12__CSI1_D12    IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D13__CSI1_D13    IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D14__CSI1_D14    IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D15__CSI1_D15    IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D16__CSI1_D16    IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D17__CSI1_D17    IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D18__CSI1_D18    IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D19__CSI1_D19    IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC        IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC        IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK      IOMUX_PAD(0x5B4, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_MCLK__CSI1_MCLK  IOMUX_PAD(0x5B8, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_PKE0__CSI1_PKE0  IOMUX_PAD(0x860, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_9__CSI2_D12    IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_10__CSI2_D13   IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_11__CSI2_D14   IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_12__CSI2_D15   IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_11__CSI2_D16   IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_12__CSI2_D17   IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_11__CSI2_D18   IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_12__CSI2_D19   IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_13__CSI2_VSYNC IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_14__CSI2_HSYNC IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_15__CSI2_PIXCLK        IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_PKE0__CSI2_PKE0  IOMUX_PAD(0x81C, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_16__I2C1_CLK   IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_17__I2C1_DAT   IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_18__AUD3_BB_TXD        IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_19__AUD3_BB_RXD        IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_20__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_21__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_22__CSPI1_MOSI IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_23__CSPI1_MISO IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_24__CSPI1_SS0  IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_25__CSPI1_SS1  IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_26__CSPI1_RDY  IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_27__CSPI1_SCLK IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
-
-/* Babbage UART1 */
-#define MX51_PAD_UART1_RXD__UART1_RXD  IOMUX_PAD(0x618, 0x228, IOMUX_CONFIG_ALT0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
-#define MX51_PAD_UART1_TXD__UART1_TXD  IOMUX_PAD(0x61C, 0x22C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
-#define MX51_PAD_UART1_RTS__UART1_RTS  IOMUX_PAD(0x620, 0x230, IOMUX_CONFIG_ALT0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
-#define MX51_PAD_UART1_CTS__UART1_CTS  IOMUX_PAD(0x624, 0x234, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL)
-
-/* Babbage UART2 */
-#define MX51_PAD_UART2_RXD__UART2_RXD  IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
-#define MX51_PAD_UART2_TXD__UART2_TXD  IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL)
-
-#define MX51_PAD_GPIO_1_22__UART3_RXD  IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_23__UART3_TXD  IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_24__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW0__KEY_ROW0    IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW1__KEY_ROW1    IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW2__KEY_ROW2    IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW3__KEY_ROW3    IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL0__KEY_COL0    IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL1__KEY_COL1    IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL2__KEY_COL2    IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL3__KEY_COL3    IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__KEY_COL4    IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__KEY_COL5    IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__USBH1_CLK  IOMUX_PAD(0x678, 0x278, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__USBH1_DIR  IOMUX_PAD(0x67C, 0x27C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__USBH1_STP  IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__GPIO_1_27  IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_GPIO, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__USBH1_NXT  IOMUX_PAD(0x684, 0x284, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA0__USBH1_DATA0      IOMUX_PAD(0x688, 0x288, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA1__USBH1_DATA1      IOMUX_PAD(0x68C, 0x28C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA2__USBH1_DATA2      IOMUX_PAD(0x690, 0x290, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA3__USBH1_DATA3      IOMUX_PAD(0x694, 0x294, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA4__USBH1_DATA4      IOMUX_PAD(0x698, 0x298, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA5__USBH1_DATA5      IOMUX_PAD(0x69C, 0x29C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA6__USBH1_DATA6      IOMUX_PAD(0x6A0, 0x2A0, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__USBH1_DATA7      IOMUX_PAD(0x6A4, 0x2A4, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_GPIO_3_0__DI1_PIN11   IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_1__DI1_PIN12   IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_2__DI1_PIN13   IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_3__DI1_D0_CS   IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_4__DI1_D1_CS   IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_5__DISPB2_SER_DIN      IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_6__DISPB2_SER_DIO      IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_7__DISPB2_SER_CLK      IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_8__DISPB2_SER_RS       IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT0__DISP1_DAT0        IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT1__DISP1_DAT1        IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT2__DISP1_DAT2        IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT3__DISP1_DAT3        IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT4__DISP1_DAT4        IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT5__DISP1_DAT5        IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT6__DISP1_DAT6        IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT7__DISP1_DAT7        IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT8__DISP1_DAT8        IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT9__DISP1_DAT9        IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT10__DISP1_DAT10      IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT11__DISP1_DAT11      IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT12__DISP1_DAT12      IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT13__DISP1_DAT13      IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT14__DISP1_DAT14      IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT15__DISP1_DAT15      IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT16__DISP1_DAT16      IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT17__DISP1_DAT17      IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__DISP1_DAT18      IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__DISP1_DAT19      IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__DISP1_DAT20      IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__DISP1_DAT21      IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__DISP1_DAT22      IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP1_DAT23      IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN3__DI1_PIN3    IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN2__DI1_PIN2    IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP1__DI_GP1        IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP2__DI_GP2        IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP3__DI_GP3        IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN4__DI2_PIN4    IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN2__DI2_PIN2    IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN3__DI2_PIN3    IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK    IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__DI_GP4        IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__DISP2_DAT0        IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__DISP2_DAT1        IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT2__DISP2_DAT2        IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT3__DISP2_DAT3        IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT4__DISP2_DAT4        IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT5__DISP2_DAT5        IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_19__DISP2_DAT6 IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_29__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_30__DISP2_DAT8 IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_31__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__DISP2_DAT10      IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__DISP2_DAT11      IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__DISP2_DAT12      IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT13__DISP2_DAT13      IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT14__DISP2_DAT14      IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__DISP2_DAT15      IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__SD1_CMD      IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CLK__SD1_CLK      IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA0__SD1_DATA0  IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA1__SD1_DATA1  IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA2__SD1_DATA2  IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__SD1_DATA3  IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_0__GPIO1_0     IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_1__GPIO1_1     IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__SD2_CMD      IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CLK__SD2_CLK      IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA0__SD2_DATA0  IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__SD2_DATA1  IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__SD2_DATA2  IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA3__SD2_DATA3  IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_2__GPIO1_2     IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_3__GPIO1_3     IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ    IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_4__GPIO1_4     IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_5__GPIO1_5     IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_6__GPIO1_6     IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_7__GPIO1_7     IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_8__GPIO1_8     IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \
-                                               (PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP |  PAD_CTL_HYS))
-#define MX51_PAD_GPIO_1_9__GPIO1_9     IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
-
-/* EIM */
-#define MX51_PAD_EIM_DA0__EIM_DA0      IOMUX_PAD(0x7a8, 0x01c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA1__EIM_DA1      IOMUX_PAD(0x7a8, 0x020, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA2__EIM_DA2      IOMUX_PAD(0x7a8, 0x024, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA3__EIM_DA3      IOMUX_PAD(0x7a8, 0x028, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA4__EIM_DA4      IOMUX_PAD(0x7ac, 0x02c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA5__EIM_DA5      IOMUX_PAD(0x7ac, 0x030, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA6__EIM_DA6      IOMUX_PAD(0x7ac, 0x034, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA7__EIM_DA7      IOMUX_PAD(0x7ac, 0x038, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_EIM_DA8__EIM_DA8      IOMUX_PAD(0x7b0, 0x03c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA9__EIM_DA9      IOMUX_PAD(0x7b0, 0x040, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA10__EIM_DA10    IOMUX_PAD(0x7b0, 0x044, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA11__EIM_DA11    IOMUX_PAD(0x7b0, 0x048, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA12__EIM_DA12    IOMUX_PAD(0x7bc, 0x04c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA13__EIM_DA13    IOMUX_PAD(0x7bc, 0x050, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA14__EIM_DA14    IOMUX_PAD(0x7bc, 0x054, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA15__EIM_DA15    IOMUX_PAD(0x7bc, 0x058, 0, 0x0,   0, NO_PAD_CTRL)
+/*                                                       PAD    MUX   ALT INPSE PATH PADCTRL */
+#define MX51_PAD_EIM_DA0__EIM_DA0              IOMUX_PAD(0x7a8, 0x01c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA1__EIM_DA1              IOMUX_PAD(0x7a8, 0x020, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA2__EIM_DA2              IOMUX_PAD(0x7a8, 0x024, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA3__EIM_DA3              IOMUX_PAD(0x7a8, 0x028, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA4__EIM_DA4              IOMUX_PAD(0x7ac, 0x02c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA5__EIM_DA5              IOMUX_PAD(0x7ac, 0x030, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA6__EIM_DA6              IOMUX_PAD(0x7ac, 0x034, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA7__EIM_DA7              IOMUX_PAD(0x7ac, 0x038, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA8__EIM_DA8              IOMUX_PAD(0x7b0, 0x03c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA9__EIM_DA9              IOMUX_PAD(0x7b0, 0x040, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA10__EIM_DA10            IOMUX_PAD(0x7b0, 0x044, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA11__EIM_DA11            IOMUX_PAD(0x7b0, 0x048, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA12__EIM_DA12            IOMUX_PAD(0x7bc, 0x04c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA13__EIM_DA13            IOMUX_PAD(0x7bc, 0x050, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA14__EIM_DA14            IOMUX_PAD(0x7bc, 0x054, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA15__EIM_DA15            IOMUX_PAD(0x7bc, 0x058, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D16__GPIO_2_0              IOMUX_PAD(0x3f0, 0x05c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D16__I2C1_SDA             IOMUX_PAD(0x3f0, 0x05c, (4 | IOMUX_CONFIG_SION), \
+                                                       0x09b4, 0, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_EIM_D17__GPIO_2_1              IOMUX_PAD(0x3f4, 0x060, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D18__GPIO_2_2              IOMUX_PAD(0x3f8, 0x064, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__GPIO_2_3              IOMUX_PAD(0x3fc, 0x068, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__I2C1_SCL             IOMUX_PAD(0x3fc, 0x068, (4 | IOMUX_CONFIG_SION), \
+                                                       0x09b0, 0, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_EIM_D20__GPIO_2_4              IOMUX_PAD(0x400, 0x06c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D21__GPIO_2_5             IOMUX_PAD(0x404, 0x070, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D22__GPIO_2_6              IOMUX_PAD(0x408, 0x074, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D23__GPIO_2_7              IOMUX_PAD(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D24__UART3_CTS             IOMUX_PAD(0x410, 0x07c, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D25__UART3_RXD             IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D25__UART2_CTS            IOMUX_PAD(0x414, 0x080, 4, 0x0,   0, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_EIM_D26__UART3_TXD             IOMUX_PAD(0x418, 0x084, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D26__UART2_RTS            IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_EIM_D27__UART3_RTS             IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D28__EIM_D28               IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D29__EIM_D29               IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D30__EIM_D30               IOMUX_PAD(0x428, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D31__EIM_D31               IOMUX_PAD(0x42c, 0x09c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A16__GPIO_2_10             IOMUX_PAD(0x430, 0x09c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A17__GPIO_2_11             IOMUX_PAD(0x434, 0x0a0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A18__GPIO_2_12             IOMUX_PAD(0x438, 0x0a4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A19__GPIO_2_13             IOMUX_PAD(0x43c, 0x0a8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A20__GPIO_2_14             IOMUX_PAD(0x440, 0x0ac, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A21__GPIO_2_15             IOMUX_PAD(0x444, 0x0b0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A22__GPIO_2_16             IOMUX_PAD(0x448, 0x0b4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A23__GPIO_2_17             IOMUX_PAD(0x44c, 0x0b8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A24__GPIO_2_18             IOMUX_PAD(0x450, 0x0bc, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A25__GPIO_2_19             IOMUX_PAD(0x454, 0x0c0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A26__GPIO_2_20             IOMUX_PAD(0x458, 0x0c4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A27__GPIO_2_21             IOMUX_PAD(0x45c, 0x0c8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB0__EIM_EB0               IOMUX_PAD(0x460, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB1__EIM_EB1               IOMUX_PAD(0x464, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB2__GPIO_2_22             IOMUX_PAD(0x468, 0x0d4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__GPIO_2_23             IOMUX_PAD(0x46c, 0x0d8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_OE__GPIO_2_24              IOMUX_PAD(0x470, 0x0dc, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS0__GPIO_2_25             IOMUX_PAD(0x474, 0x0e0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS1__GPIO_2_26             IOMUX_PAD(0x478, 0x0e4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__GPIO_2_27             IOMUX_PAD(0x47c, 0x0e8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__GPIO_2_28             IOMUX_PAD(0x480, 0x0ec, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS4__GPIO_2_29             IOMUX_PAD(0x484, 0x0f0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__GPIO_2_30             IOMUX_PAD(0x488, 0x0f4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DTACK__GPIO_2_31           IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_LBA__GPIO_3_1              IOMUX_PAD(0x494, 0x0FC, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CRE__GPIO_3_2              IOMUX_PAD(0x4A0, 0x100, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DRAM_CS1__DRAM_CS1             IOMUX_PAD(0x4D0, 0x104, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WE_B__GPIO_3_3           IOMUX_PAD(0x4E4, 0x108, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RE_B__GPIO_3_4           IOMUX_PAD(0x4E8, 0x10C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_ALE__GPIO_3_5            IOMUX_PAD(0x4EC, 0x110, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CLE__GPIO_3_6            IOMUX_PAD(0x4F0, 0x114, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WP_B__GPIO_3_7           IOMUX_PAD(0x4F4, 0x118, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB0__GPIO_3_8            IOMUX_PAD(0x4F8, 0x11C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__GPIO_3_9            IOMUX_PAD(0x4FC, 0x120, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__GPIO_3_10           IOMUX_PAD(0x500, 0x124, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__GPIO_3_11           IOMUX_PAD(0x504, 0x128, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_NAND__GPIO_3_12           IOMUX_PAD(0x514, 0x12C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS0__GPIO_3_16           IOMUX_PAD(0x518, 0x130, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS1__GPIO_3_17           IOMUX_PAD(0x51C, 0x134, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__GPIO_3_18           IOMUX_PAD(0x520, 0x138, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__GPIO_3_19           IOMUX_PAD(0x524, 0x13C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS4__GPIO_3_20           IOMUX_PAD(0x528, 0x140, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS5__GPIO_3_21           IOMUX_PAD(0x52C, 0x144, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS6__GPIO_3_22           IOMUX_PAD(0x530, 0x148, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS7__GPIO_3_23           IOMUX_PAD(0x534, 0x14C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24       IOMUX_PAD(0x538, 0x150, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__GPIO_3_25           IOMUX_PAD(0x53C, 0x154, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D14__GPIO_3_26           IOMUX_PAD(0x540, 0x158, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D13__GPIO_3_27           IOMUX_PAD(0x544, 0x15C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D12__GPIO_3_28           IOMUX_PAD(0x548, 0x160, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D11__GPIO_3_29           IOMUX_PAD(0x54C, 0x164, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D10__GPIO_3_30           IOMUX_PAD(0x550, 0x168, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D9__GPIO_3_31            IOMUX_PAD(0x554, 0x16C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D8__GPIO_4_0             IOMUX_PAD(0x558, 0x170, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D7__GPIO_4_1             IOMUX_PAD(0x55C, 0x174, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D6__GPIO_4_2             IOMUX_PAD(0x560, 0x178, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D5__GPIO_4_3             IOMUX_PAD(0x564, 0x17C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D4__GPIO_4_4             IOMUX_PAD(0x568, 0x180, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D3__GPIO_4_5             IOMUX_PAD(0x56C, 0x184, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D2__GPIO_4_6             IOMUX_PAD(0x570, 0x188, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D1__GPIO_4_7             IOMUX_PAD(0x574, 0x18C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D0__GPIO_4_8             IOMUX_PAD(0x578, 0x190, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D8__GPIO_3_12             IOMUX_PAD(0x57C, 0x194, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D9__GPIO_3_13             IOMUX_PAD(0x580, 0x198, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D10__CSI1_D10             IOMUX_PAD(0x584, 0x19C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D11__CSI1_D11             IOMUX_PAD(0x588, 0x1A0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D12__CSI1_D12             IOMUX_PAD(0x58C, 0x1A4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D13__CSI1_D13             IOMUX_PAD(0x590, 0x1A8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D14__CSI1_D14             IOMUX_PAD(0x594, 0x1AC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D15__CSI1_D15             IOMUX_PAD(0x598, 0x1B0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D16__CSI1_D16             IOMUX_PAD(0x59C, 0x1B4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D17__CSI1_D17             IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D18__CSI1_D18             IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D19__CSI1_D19             IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC         IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC         IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK       IOMUX_PAD(0x5B4, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_MCLK__CSI1_MCLK           IOMUX_PAD(0x5B8, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_PKE0__CSI1_PKE0           IOMUX_PAD(0x860, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D12__GPIO_4_9             IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D13__GPIO_4_10            IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D14__GPIO_4_11            IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D15__GPIO_4_12            IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D16__GPIO_4_11            IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D17__GPIO_4_12            IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D18__GPIO_4_11            IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D19__GPIO_4_12            IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_VSYNC__GPIO_4_13          IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_HSYNC__GPIO_4_14          IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_PIXCLK__GPIO_4_15         IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_CLK__GPIO_4_16            IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_CLK__HSI2C_CLK           IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_DAT__GPIO_4_17            IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_DAT__HSI2C_DAT           IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18         IOMUX_PAD(0x5F0, 0x200, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19         IOMUX_PAD(0x5F4, 0x204, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_CK__GPIO_4_20          IOMUX_PAD(0x5F8, 0x208, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_FS__GPIO_4_21          IOMUX_PAD(0x5FC, 0x20C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MOSI__GPIO_4_22          IOMUX_PAD(0x600, 0x210, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MISO__GPIO_4_23          IOMUX_PAD(0x604, 0x214, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS0__GPIO_4_24           IOMUX_PAD(0x608, 0x218, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS1__GPIO_4_25           IOMUX_PAD(0x60C, 0x21C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_RDY__GPIO_4_26           IOMUX_PAD(0x610, 0x220, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SCLK__GPIO_4_27          IOMUX_PAD(0x614, 0x224, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_UART1_RXD__UART1_RXD           IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
+#define MX51_PAD_UART1_TXD__UART1_TXD           IOMUX_PAD(0x61C, 0x22C, 0, 0x0,   0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
+#define MX51_PAD_UART1_RTS__UART1_RTS           IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
+#define MX51_PAD_UART1_CTS__UART1_CTS           IOMUX_PAD(0x624, 0x234, 0, 0x0,   0, MX51_UART1_PAD_CTRL)
+#define MX51_PAD_UART2_RXD__UART2_RXD           IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_UART2_TXD__UART2_TXD           IOMUX_PAD(0x62C, 0x23C, 0, 0x0,   0, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__UART3_RXD          IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__GPIO_1_22           IOMUX_PAD(0x630, 0x240, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__UART3_TXD          IOMUX_PAD(0x634, 0x244, 1, 0x0,   0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__GPIO_1_23           IOMUX_PAD(0x634, 0x244, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_OWIRE_LINE__GPIO_1_24          IOMUX_PAD(0x638, 0x248, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW0__KEY_ROW0             IOMUX_PAD(0x63C, 0x24C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW1__KEY_ROW1             IOMUX_PAD(0x640, 0x250, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW2__KEY_ROW2             IOMUX_PAD(0x644, 0x254, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW3__KEY_ROW3             IOMUX_PAD(0x648, 0x258, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL0__KEY_COL0             IOMUX_PAD(0x64C, 0x25C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL1__KEY_COL1             IOMUX_PAD(0x650, 0x260, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL2__KEY_COL2             IOMUX_PAD(0x654, 0x264, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL3__KEY_COL3             IOMUX_PAD(0x658, 0x268, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__KEY_COL4             IOMUX_PAD(0x65C, 0x26C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__UART3_RTS           IOMUX_PAD(0x65C, 0x26C, 2, 0x9f0, 4, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__I2C2_SCL            IOMUX_PAD(0x65C, 0x26C, (3 | IOMUX_CONFIG_SION), \
+                                                       0x09b8, 1, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__KEY_COL5             IOMUX_PAD(0x660, 0x270, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__UART3_CTS           IOMUX_PAD(0x660, 0x270, 2, 0,     0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__I2C2_SDA            IOMUX_PAD(0x660, 0x270, (3 | IOMUX_CONFIG_SION), \
+                                                       0x09bc, 1, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_USBH1_CLK__USBH1_CLK           IOMUX_PAD(0x678, 0x278, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DIR__USBH1_DIR           IOMUX_PAD(0x67C, 0x27C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__USBH1_STP           IOMUX_PAD(0x680, 0x280, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__GPIO_1_27           IOMUX_PAD(0x680, 0x280, 2, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_NXT__USBH1_NXT           IOMUX_PAD(0x684, 0x284, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA0__USBH1_DATA0       IOMUX_PAD(0x688, 0x288, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA1__USBH1_DATA1       IOMUX_PAD(0x68C, 0x28C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA2__USBH1_DATA2       IOMUX_PAD(0x690, 0x290, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA3__USBH1_DATA3       IOMUX_PAD(0x694, 0x294, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA4__USBH1_DATA4       IOMUX_PAD(0x698, 0x298, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA5__USBH1_DATA5       IOMUX_PAD(0x69C, 0x29C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA6__USBH1_DATA6       IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA7__USBH1_DATA7       IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_DI1_PIN11__GPIO_3_0            IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN12__GPIO_3_1            IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN13__GPIO_3_2            IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D0_CS__GPIO_3_3            IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D1_CS__GPIO_3_4            IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5       IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6       IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7       IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8        IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT0__DISP1_DAT0         IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT1__DISP1_DAT1         IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT2__DISP1_DAT2         IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT3__DISP1_DAT3         IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT4__DISP1_DAT4         IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT5__DISP1_DAT5         IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT6__DISP1_DAT6         IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT7__DISP1_DAT7         IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT8__DISP1_DAT8         IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT9__DISP1_DAT9         IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT10__DISP1_DAT10       IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT11__DISP1_DAT11       IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT12__DISP1_DAT12       IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT13__DISP1_DAT13       IOMUX_PAD(0x700, 0x300, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT14__DISP1_DAT14       IOMUX_PAD(0x704, 0x304, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT15__DISP1_DAT15       IOMUX_PAD(0x708, 0x308, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT16__DISP1_DAT16       IOMUX_PAD(0x70C, 0x30C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT17__DISP1_DAT17       IOMUX_PAD(0x710, 0x310, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT18__DISP1_DAT18       IOMUX_PAD(0x714, 0x314, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT19__DISP1_DAT19       IOMUX_PAD(0x718, 0x318, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT20__DISP1_DAT20       IOMUX_PAD(0x71C, 0x31C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT21__DISP1_DAT21       IOMUX_PAD(0x720, 0x320, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT22__DISP1_DAT22       IOMUX_PAD(0x724, 0x324, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT23__DISP1_DAT23       IOMUX_PAD(0x728, 0x328, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN3__DI1_PIN3             IOMUX_PAD(0x72C, 0x32C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN2__DI1_PIN2             IOMUX_PAD(0x734, 0x330, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP1__DI_GP1                 IOMUX_PAD(0x73C, 0x334, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP2__DI_GP2                 IOMUX_PAD(0x740, 0x338, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP3__DI_GP3                 IOMUX_PAD(0x744, 0x33C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN4__DI2_PIN4             IOMUX_PAD(0x748, 0x340, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN2__DI2_PIN2             IOMUX_PAD(0x74C, 0x344, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN3__DI2_PIN3             IOMUX_PAD(0x750, 0x348, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK     IOMUX_PAD(0x754, 0x34C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP4__DI_GP4                 IOMUX_PAD(0x758, 0x350, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT0__DISP2_DAT0         IOMUX_PAD(0x75C, 0x354, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT1__DISP2_DAT1         IOMUX_PAD(0x760, 0x358, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT2__DISP2_DAT2         IOMUX_PAD(0x764, 0x35C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT3__DISP2_DAT3         IOMUX_PAD(0x768, 0x360, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT4__DISP2_DAT4         IOMUX_PAD(0x76C, 0x364, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT5__DISP2_DAT5         IOMUX_PAD(0x770, 0x368, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT6__GPIO_1_19          IOMUX_PAD(0x774, 0x36C, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT7__GPIO_1_29          IOMUX_PAD(0x778, 0x370, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT8__GPIO_1_30          IOMUX_PAD(0x77C, 0x374, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT9__GPIO_1_31          IOMUX_PAD(0x780, 0x378, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT10__DISP2_DAT10       IOMUX_PAD(0x784, 0x37C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT11__DISP2_DAT11       IOMUX_PAD(0x788, 0x380, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT12__DISP2_DAT12       IOMUX_PAD(0x78C, 0x384, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT13__DISP2_DAT13       IOMUX_PAD(0x790, 0x388, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT14__DISP2_DAT14       IOMUX_PAD(0x794, 0x38C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT15__DISP2_DAT15       IOMUX_PAD(0x798, 0x390, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CMD__SD1_CMD               IOMUX_PAD(0x79C, 0x394, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CLK__SD1_CLK               IOMUX_PAD(0x7A0, 0x398, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA0__SD1_DATA0           IOMUX_PAD(0x7A4, 0x39C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA1__SD1_DATA1           IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA2__SD1_DATA2           IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA3__SD1_DATA3           IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_0__GPIO_1_0            IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_1__GPIO_1_1            IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_CMD__SD2_CMD               IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_CLK__SD2_CLK               IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA0__SD2_DATA0           IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA1__SD2_DATA1           IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA2__SD2_DATA2           IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA3__SD2_DATA3           IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_2__GPIO_1_2            IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_2__I2C2_SCL            IOMUX_PAD(0x7D4, 0x3CC, (2 | IOMUX_CONFIG_SION), \
+                                                       0x9b8,   3, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_GPIO_1_3__GPIO_1_3            IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_3__I2C2_SDA            IOMUX_PAD(0x7D8, 0x3D0, (2 | IOMUX_CONFIG_SION), \
+                                                       0x9bc,   3, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ    IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_4__GPIO_1_4            IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_5__GPIO_1_5            IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_6__GPIO_1_6            IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_7__GPIO_1_7            IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_8__GPIO_1_8            IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_9__GPIO_1_9            IOMUX_PAD(0x818, 0x3EC, 0, 0x0,   0, NO_PAD_CTRL)
 
 #endif /* __MACH_IOMUX_MX51_H__ */

diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
index 3887f3fe29d4401b62584a905fcaa642dd7a80b6..15d59510f597ed8eb5e37df2c44a5c34cdc6dcc9 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #ifndef __MACH_IOMUX_MXC91231_H__

diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index f2f73d31d5ba5cf579d035b52b9f106c4f741d0d..0880a4a1aed1e91c397653515dca3d979cf9b804 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -89,6 +89,21 @@ struct pad_desc {
 #define PAD_CTL_SRE_FAST               (1 << 0)
 #define PAD_CTL_SRE_SLOW               (0 << 0)
 
+
+#define MX51_NUM_GPIO_PORT     4
+
+#define GPIO_PIN_MASK 0x1f
+
+#define GPIO_PORT_SHIFT 5
+#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
+
+#define GPIO_PORTA     (0 << GPIO_PORT_SHIFT)
+#define GPIO_PORTB     (1 << GPIO_PORT_SHIFT)
+#define GPIO_PORTC     (2 << GPIO_PORT_SHIFT)
+#define GPIO_PORTD     (3 << GPIO_PORT_SHIFT)
+#define GPIO_PORTE     (4 << GPIO_PORT_SHIFT)
+#define GPIO_PORTF     (5 << GPIO_PORT_SHIFT)
+
 /*
  * setups a single pad in the iomuxer
  */

diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index c4b40c35a6a1e429f14476a4f76491229c8560cc..564ec9dbc93d324a208cf407de178974435e9eea 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -44,12 +44,12 @@
  */
 #define CONSISTENT_DMA_SIZE SZ_8M
 
-#elif defined(CONFIG_MX1_VIDEO)
+#elif defined(CONFIG_MX1_VIDEO) || defined(CONFIG_VIDEO_MX2_HOSTSUPPORT)
 /*
  * Increase size of DMA-consistent memory region.
  * This is required for i.MX camera driver to capture at least four VGA frames.
  */
 #define CONSISTENT_DMA_SIZE SZ_4M
-#endif /* CONFIG_MX1_VIDEO */
+#endif /* CONFIG_MX1_VIDEO || CONFIG_VIDEO_MX2_HOSTSUPPORT */
 
 #endif /* __ASM_ARCH_MXC_MEMORY_H__ */

diff --git a/arch/arm/plat-mxc/include/mach/mmc.h b/arch/arm/plat-mxc/include/mach/mmc.h
index de2128dada5cf2856118181bec1771fddef95fac..29115f405af91653683465fa9112fd0cff78213f 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/mmc.h
+++ b/arch/arm/plat-mxc/include/mach/mmc.h
@@ -31,6 +31,9 @@ struct imxmmc_platform_data {
 
        /* adjust slot voltage */
        void (*setpower)(struct device *, unsigned int vdd);
+
+       /* enable card detect using DAT3 */
+       int dat3_card_detect;
 };
 
 #endif

diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index 5eba7e6785dec6ddf643366965c5734bdc1fa89a..641b2461823950be06d2573131f7f2b8ba74d3e4 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -91,24 +91,24 @@
 #define MX1_SIM_DATA_INT       16
 #define MX1_RTC_INT            17
 #define MX1_RTC_SAMINT         18
-#define MX1_UART2_MINT_PFERR   19
-#define MX1_UART2_MINT_RTS     20
-#define MX1_UART2_MINT_DTR     21
-#define MX1_UART2_MINT_UARTC   22
-#define MX1_UART2_MINT_TX      23
-#define MX1_UART2_MINT_RX      24
-#define MX1_UART1_MINT_PFERR   25
-#define MX1_UART1_MINT_RTS     26
-#define MX1_UART1_MINT_DTR     27
-#define MX1_UART1_MINT_UARTC   28
-#define MX1_UART1_MINT_TX      29
-#define MX1_UART1_MINT_RX      30
+#define MX1_INT_UART2PFERR     19
+#define MX1_INT_UART2RTS       20
+#define MX1_INT_UART2DTR       21
+#define MX1_INT_UART2UARTC     22
+#define MX1_INT_UART2TX                23
+#define MX1_INT_UART2RX                24
+#define MX1_INT_UART1PFERR     25
+#define MX1_INT_UART1RTS       26
+#define MX1_INT_UART1DTR       27
+#define MX1_INT_UART1UARTC     28
+#define MX1_INT_UART1TX                29
+#define MX1_INT_UART1RX                30
 #define MX1_VOICE_DAC_INT      31
 #define MX1_VOICE_ADC_INT      32
 #define MX1_PEN_DATA_INT       33
 #define MX1_PWM_INT            34
 #define MX1_SDHC_INT           35
-#define MX1_I2C_INT            39
+#define MX1_INT_I2C            39
 #define MX1_CSPI_INT           41
 #define MX1_SSI_TX_INT         42
 #define MX1_SSI_TX_ERR_INT     43
@@ -245,7 +245,7 @@
 #define PEN_DATA_INT MX1_PEN_DATA_INT
 #define PWM_INT MX1_PWM_INT
 #define SDHC_INT MX1_SDHC_INT
-#define I2C_INT MX1_I2C_INT
+#define I2C_INT MX1_INT_I2C
 #define CSPI_INT MX1_CSPI_INT
 #define SSI_TX_INT MX1_SSI_TX_INT
 #define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT

diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 4eb6e334bda589f6d210dc2c3de1a70a60cb6b1b..4a6f800990f83a826e687ae6a8d8776def7a3689 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -11,6 +11,12 @@
 #define MX25_AVIC_BASE_ADDR_VIRT       0xfc400000
 #define MX25_AVIC_SIZE                 SZ_1M
 
+#define MX25_I2C1_BASE_ADDR            (MX25_AIPS1_BASE_ADDR + 0x80000)
+#define MX25_I2C3_BASE_ADDR            (MX25_AIPS1_BASE_ADDR + 0x84000)
+#define MX25_CAN1_BASE_ADDR            (MX25_AIPS1_BASE_ADDR + 0x88000)
+#define MX25_CAN2_BASE_ADDR            (MX25_AIPS1_BASE_ADDR + 0x8c000)
+#define MX25_I2C2_BASE_ADDR            (MX25_AIPS1_BASE_ADDR + 0x98000)
+#define MX25_CSPI1_BASE_ADDR           (MX25_AIPS1_BASE_ADDR + 0xa4000)
 #define MX25_IOMUXC_BASE_ADDR          (MX25_AIPS1_BASE_ADDR + 0xac000)
 
 #define MX25_CRM_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0x80000)
@@ -27,22 +33,48 @@
        IMX_IO_ADDRESS(x, MX25_AIPS2) ?:                        \
        IMX_IO_ADDRESS(x, MX25_AVIC))
 
+#define MX25_AIPS1_IO_ADDRESS(x) \
+       (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT)
+
 #define MX25_UART1_BASE_ADDR           0x43f90000
 #define MX25_UART2_BASE_ADDR           0x43f94000
+#define MX25_AUDMUX_BASE_ADDR          0x43fb0000
+#define MX25_UART3_BASE_ADDR           0x5000c000
+#define MX25_UART4_BASE_ADDR           0x50008000
+#define MX25_UART5_BASE_ADDR           0x5002c000
 
+#define MX25_CSPI3_BASE_ADDR           0x50004000
+#define MX25_CSPI2_BASE_ADDR           0x50010000
 #define MX25_FEC_BASE_ADDR             0x50038000
+#define MX25_SSI2_BASE_ADDR            0x50014000
+#define MX25_SSI1_BASE_ADDR            0x50034000
 #define MX25_NFC_BASE_ADDR             0xbb000000
 #define MX25_DRYICE_BASE_ADDR          0x53ffc000
 #define MX25_LCDC_BASE_ADDR            0x53fbc000
+#define MX25_KPP_BASE_ADDR             0x43fa8000
+#define MX25_OTG_BASE_ADDR             0x53ff4000
+#define MX25_CSI_BASE_ADDR             0x53ff8000
 
-#define MX25_INT_DRYICE        25
-#define MX25_INT_FEC   57
-#define MX25_INT_NANDFC        33
-#define MX25_INT_LCDC  39
-
-#if defined(IMX_NEEDS_DEPRECATED_SYMBOLS)
-#define UART1_BASE_ADDR                        MX25_UART1_BASE_ADDR
-#define UART2_BASE_ADDR                        MX25_UART2_BASE_ADDR
-#endif
+#define MX25_INT_CSPI3         0
+#define MX25_INT_I2C1          3
+#define MX25_INT_I2C2          4
+#define MX25_INT_UART4         5
+#define MX25_INT_I2C3          10
+#define MX25_INT_SSI2          11
+#define MX25_INT_SSI1          12
+#define MX25_INT_CSPI2         13
+#define MX25_INT_CSPI1         14
+#define MX25_INT_CSI           17
+#define MX25_INT_UART3         18
+#define MX25_INT_KPP           24
+#define MX25_INT_DRYICE                25
+#define MX25_INT_UART2         32
+#define MX25_INT_NANDFC                33
+#define MX25_INT_LCDC          39
+#define MX25_INT_UART5         40
+#define MX25_INT_CAN1          43
+#define MX25_INT_CAN2          44
+#define MX25_INT_UART1         45
+#define MX25_INT_FEC           57
 
 #endif /* ifndef __MACH_MX25_H__ */

diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index bae9cd75beee333f097edc45a772add44f5d1d7c..a8ab2e02a8caf36460591865237e6d6c34d534de 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -48,7 +48,7 @@
 #define MX27_CSPI2_BASE_ADDR                   (MX27_AIPI_BASE_ADDR + 0x0f000)
 #define MX27_SSI1_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x10000)
 #define MX27_SSI2_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x11000)
-#define MX27_I2C_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x12000)
+#define MX27_I2C1_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x12000)
 #define MX27_SDHC1_BASE_ADDR                   (MX27_AIPI_BASE_ADDR + 0x13000)
 #define MX27_SDHC2_BASE_ADDR                   (MX27_AIPI_BASE_ADDR + 0x14000)
 #define MX27_GPIO_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x15000)
@@ -150,7 +150,7 @@ static inline void mx27_setup_weimcs(size_t cs,
 #define MX27_INT_SDHC3         9
 #define MX27_INT_SDHC2         10
 #define MX27_INT_SDHC1         11
-#define MX27_INT_I2C           12
+#define MX27_INT_I2C1          12
 #define MX27_INT_SSI2          13
 #define MX27_INT_SSI1          14
 #define MX27_INT_CSPI2         15

diff --git a/arch/arm/plat-mxc/include/mach/mx2_cam.h b/arch/arm/plat-mxc/include/mach/mx2_cam.h
new file mode 100644 (file)
index 0000000..3c080a3
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx2_cam.h
@@ -0,0 +1,46 @@
+/*
+ * mx2-cam.h - i.MX27/i.MX25 camera driver header file
+ *
+ * Copyright (C) 2003, Intel Corporation
+ * Copyright (C) 2008, Sascha Hauer <s.hauer@pengutronix.de>
+ * Copyright (C) 2010, Baruch Siach <baruch@tkos.co.il>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __MACH_MX2_CAM_H_
+#define __MACH_MX2_CAM_H_
+
+#define MX2_CAMERA_SWAP16              (1 << 0)
+#define MX2_CAMERA_EXT_VSYNC           (1 << 1)
+#define MX2_CAMERA_CCIR                        (1 << 2)
+#define MX2_CAMERA_CCIR_INTERLACE      (1 << 3)
+#define MX2_CAMERA_HSYNC_HIGH          (1 << 4)
+#define MX2_CAMERA_GATED_CLOCK         (1 << 5)
+#define MX2_CAMERA_INV_DATA            (1 << 6)
+#define MX2_CAMERA_PCLK_SAMPLE_RISING  (1 << 7)
+#define MX2_CAMERA_PACK_DIR_MSB                (1 << 8)
+
+/**
+ * struct mx2_camera_platform_data - optional platform data for mx2_camera
+ * @flags: any combination of MX2_CAMERA_*
+ * @clk: clock rate of the csi block / 2
+ */
+struct mx2_camera_platform_data {
+       unsigned long flags;
+       unsigned long clk;
+};
+
+#endif /* __MACH_MX2_CAM_H_ */

diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index fb90e119c2b5db473a3d4e01ef48dd6a76921493..afee3ab9d62e2aef32a366f21c82350a562dab22 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -23,7 +23,7 @@
 #define MX31_ETB_SLOT4_BASE_ADDR               (MX31_AIPS1_BASE_ADDR + 0x10000)
 #define MX31_ETB_SLOT5_BASE_ADDR               (MX31_AIPS1_BASE_ADDR + 0x14000)
 #define MX31_ECT_CTIO_BASE_ADDR                        (MX31_AIPS1_BASE_ADDR + 0x18000)
-#define MX31_I2C_BASE_ADDR                     (MX31_AIPS1_BASE_ADDR + 0x80000)
+#define MX31_I2C1_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0x80000)
 #define MX31_I2C3_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0x84000)
 #define MX31_OTG_BASE_ADDR                     (MX31_AIPS1_BASE_ADDR + 0x88000)
 #define MX31_ATA_BASE_ADDR                     (MX31_AIPS1_BASE_ADDR + 0x8c000)
@@ -145,7 +145,7 @@ static inline void mx31_setup_weimcs(size_t cs,
 #define MX31_INT_FIRI          7
 #define MX31_INT_MMC_SDHC2     8
 #define MX31_INT_MMC_SDHC1     9
-#define MX31_INT_I2C           10
+#define MX31_INT_I2C1          10
 #define MX31_INT_SSI2          11
 #define MX31_INT_SSI1          12
 #define MX31_INT_CSPI2         13

diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index 526a55842ae53d6719a1221f4d8b3ccc33a75429..af3038c12e39c03b16d00855e5f5f40b75ba9b97 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -18,7 +18,7 @@
 #define MX35_ETB_SLOT4_BASE_ADDR               (MX35_AIPS1_BASE_ADDR + 0x10000)
 #define MX35_ETB_SLOT5_BASE_ADDR               (MX35_AIPS1_BASE_ADDR + 0x14000)
 #define MX35_ECT_CTIO_BASE_ADDR                        (MX35_AIPS1_BASE_ADDR + 0x18000)
-#define MX35_I2C_BASE_ADDR                     (MX35_AIPS1_BASE_ADDR + 0x80000)
+#define MX35_I2C1_BASE_ADDR                    (MX35_AIPS1_BASE_ADDR + 0x80000)
 #define MX35_I2C3_BASE_ADDR                    (MX35_AIPS1_BASE_ADDR + 0x84000)
 #define MX35_UART1_BASE_ADDR                   (MX35_AIPS1_BASE_ADDR + 0x90000)
 #define MX35_UART2_BASE_ADDR                   (MX35_AIPS1_BASE_ADDR + 0x94000)
@@ -60,6 +60,8 @@
 #define MX35_RTC_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xd8000)
 #define MX35_WDOG_BASE_ADDR                    (MX35_AIPS2_BASE_ADDR + 0xdc000)
 #define MX35_PWM_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xe0000)
+#define MX35_CAN1_BASE_ADDR                    (MX35_AIPS2_BASE_ADDR + 0xe4000)
+#define MX35_CAN2_BASE_ADDR                    (MX35_AIPS2_BASE_ADDR + 0xe8000)
 #define MX35_RTIC_BASE_ADDR                    (MX35_AIPS2_BASE_ADDR + 0xec000)
 #define MX35_OTG_BASE_ADDR             0x53ff4000
 
@@ -123,7 +125,7 @@
 #define MX35_INT_MMC_SDHC1     7
 #define MX35_INT_MMC_SDHC2     8
 #define MX35_INT_MMC_SDHC3     9
-#define MX35_INT_I2C           10
+#define MX35_INT_I2C1          10
 #define MX35_INT_SSI1          11
 #define MX35_INT_SSI2          12
 #define MX35_INT_CSPI2         13

diff --git a/arch/arm/plat-mxc/include/mach/mx3_camera.h b/arch/arm/plat-mxc/include/mach/mx3_camera.h
index 36d7ff27b5e2244861cd7f4750d857e20c7c8fcf..f226ee3777e17368c7901ebfeddaca2d523acf1a 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/mx3_camera.h
+++ b/arch/arm/plat-mxc/include/mach/mx3_camera.h
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
 #ifndef _MX3_CAMERA_H_

diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h
index 5182b986b7851e0d91513b37969312adf15d69de..0ca3101ebf36e92364b33a78fbf4e7db916f2af6 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/mxc91231.h
+++ b/arch/arm/plat-mxc/include/mach/mxc91231.h
@@ -13,10 +13,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 #ifndef __MACH_MXC91231_H__
 #define __MACH_MXC91231_H__

diff --git a/arch/arm/plat-mxc/include/mach/mxc_nand.h b/arch/arm/plat-mxc/include/mach/mxc_nand.h
index 5d2d21d414e0e71716ab8878a14548010faff253..04c0d060d8143ae4c60d526a6198178f2e02bccb 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/mxc_nand.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_nand.h
@@ -20,9 +20,13 @@
 #ifndef __ASM_ARCH_NAND_H
 #define __ASM_ARCH_NAND_H
 
+#include <linux/mtd/partitions.h>
+
 struct mxc_nand_platform_data {
-       int width;      /* data bus width in bytes */
-       int hw_ecc:1;   /* 0 if supress hardware ECC */
-       int flash_bbt:1; /* set to 1 to use a flash based bbt */
+       unsigned int width;     /* data bus width in bytes */
+       unsigned int hw_ecc:1;  /* 0 if supress hardware ECC */
+       unsigned int flash_bbt:1; /* set to 1 to use a flash based bbt */
+       struct mtd_partition *parts;    /* partition table */
+       int nr_parts;                   /* size of parts */
 };
 #endif /* __ASM_ARCH_NAND_H */

diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index ef00199568de15f998571b3cd20a34a29ff56de7..4acd1143a9bdd7444c12ca547ed957b47ef302d6 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #ifndef __ASM_ARCH_MXC_SYSTEM_H__

diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
index 024416ed11cd9673bf5bf478f17412c81f6e98c8..2d9624697cc9c9e7d99c5733e5e750b90c0a592b 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/timex.h
+++ b/arch/arm/plat-mxc/include/mach/timex.h
@@ -11,10 +11,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #ifndef __ASM_ARCH_MXC_TIMEX_H__

diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index b6d3d0fddc48aebb62763c2d364bed0103909063..d9bd37e4667a23f04e3f20ba0fd4fcd8f599b6d6 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -13,10 +13,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 #ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__
 #define __ASM_ARCH_MXC_UNCOMPRESS_H__

diff --git a/arch/arm/plat-mxc/include/mach/vmalloc.h b/arch/arm/plat-mxc/include/mach/vmalloc.h
index 44243a278434b027d604ed590e43d9cdb5749653..ef6379c474be8a66656583cca426bd7b23386f6a 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/vmalloc.h
+++ b/arch/arm/plat-mxc/include/mach/vmalloc.h
@@ -11,10 +11,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #ifndef __ASM_ARCH_MXC_VMALLOC_H__

diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
index 778ddfe57d895c5db1a4969886bd1dac6226f5f0..7331f2ace5fe12b49e1ce431fd01459bc6bae785 100644 (file)
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/irq.c
@@ -142,9 +142,6 @@ void __init mxc_init_irq(void __iomem *irqbase)
        for (i = 0; i < 8; i++)
                __raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
 
-       /* init architectures chained interrupt handler */
-       mxc_register_gpios();
-
 #ifdef CONFIG_FIQ
        /* Initialize FIQ */
        init_FIQ();

diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 97f42799fa589caae5f1c99ebc11670ee16f93a3..925bce4607e78bc91f2fb4605e4c8d5195027ff2 100644 (file)
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -14,10 +14,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/kernel.h>

diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index 9b86d2a60d43789a22d644105981815169123dd7..b3da9aad4295704ef9ea8a4a43c95127d74e6d9e 100644 (file)
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -145,8 +145,6 @@ void __init tzic_init_irq(void __iomem *irqbase)
                set_irq_handler(i, handle_level_irq);
                set_irq_flags(i, IRQF_VALID);
        }
-       mxc_register_gpios();
-
        pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
 }
 

diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index 5a6ef252c38b37732d36e8dc52c97b96d9385604..977c8f9a07a2194322deada32da2afd0481d50ad 100644 (file)
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -23,6 +23,7 @@
 #include <linux/irq.h>
 #include <linux/slab.h>
 
+#include <plat/pincfg.h>
 #include <mach/hardware.h>
 #include <mach/gpio.h>
 
@@ -46,28 +47,217 @@ struct nmk_gpio_chip {
        u32 edge_falling;
 };
 
+static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
+                               unsigned offset, int gpio_mode)
+{
+       u32 bit = 1 << offset;
+       u32 afunc, bfunc;
+
+       afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
+       bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
+       if (gpio_mode & NMK_GPIO_ALT_A)
+               afunc |= bit;
+       if (gpio_mode & NMK_GPIO_ALT_B)
+               bfunc |= bit;
+       writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
+       writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
+}
+
+static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
+                               unsigned offset, enum nmk_gpio_slpm mode)
+{
+       u32 bit = 1 << offset;
+       u32 slpm;
+
+       slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
+       if (mode == NMK_GPIO_SLPM_NOCHANGE)
+               slpm |= bit;
+       else
+               slpm &= ~bit;
+       writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
+}
+
+static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
+                               unsigned offset, enum nmk_gpio_pull pull)
+{
+       u32 bit = 1 << offset;
+       u32 pdis;
+
+       pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
+       if (pull == NMK_GPIO_PULL_NONE)
+               pdis |= bit;
+       else
+               pdis &= ~bit;
+       writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
+
+       if (pull == NMK_GPIO_PULL_UP)
+               writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
+       else if (pull == NMK_GPIO_PULL_DOWN)
+               writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
+}
+
+static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
+                                 unsigned offset)
+{
+       writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
+}
+
+static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
+                            pin_cfg_t cfg)
+{
+       static const char *afnames[] = {
+               [NMK_GPIO_ALT_GPIO]     = "GPIO",
+               [NMK_GPIO_ALT_A]        = "A",
+               [NMK_GPIO_ALT_B]        = "B",
+               [NMK_GPIO_ALT_C]        = "C"
+       };
+       static const char *pullnames[] = {
+               [NMK_GPIO_PULL_NONE]    = "none",
+               [NMK_GPIO_PULL_UP]      = "up",
+               [NMK_GPIO_PULL_DOWN]    = "down",
+               [3] /* illegal */       = "??"
+       };
+       static const char *slpmnames[] = {
+               [NMK_GPIO_SLPM_INPUT]           = "input",
+               [NMK_GPIO_SLPM_NOCHANGE]        = "no-change",
+       };
+
+       int pin = PIN_NUM(cfg);
+       int pull = PIN_PULL(cfg);
+       int af = PIN_ALT(cfg);
+       int slpm = PIN_SLPM(cfg);
+
+       dev_dbg(nmk_chip->chip.dev, "pin %d: af %s, pull %s, slpm %s\n",
+               pin, afnames[af], pullnames[pull], slpmnames[slpm]);
+
+       __nmk_gpio_make_input(nmk_chip, offset);
+       __nmk_gpio_set_pull(nmk_chip, offset, pull);
+       __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
+       __nmk_gpio_set_mode(nmk_chip, offset, af);
+}
+
+/**
+ * nmk_config_pin - configure a pin's mux attributes
+ * @cfg: pin confguration
+ *
+ * Configures a pin's mode (alternate function or GPIO), its pull up status,
+ * and its sleep mode based on the specified configuration.  The @cfg is
+ * usually one of the SoC specific macros defined in mach/<soc>-pins.h.  These
+ * are constructed using, and can be further enhanced with, the macros in
+ * plat/pincfg.h.
+ *
+ * If a pin's mode is set to GPIO, it is configured as an input to avoid
+ * side-effects.  The gpio can be manipulated later using standard GPIO API
+ * calls.
+ */
+int nmk_config_pin(pin_cfg_t cfg)
+{
+       struct nmk_gpio_chip *nmk_chip;
+       int gpio = PIN_NUM(cfg);
+       unsigned long flags;
+
+       nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
+       if (!nmk_chip)
+               return -EINVAL;
+
+       spin_lock_irqsave(&nmk_chip->lock, flags);
+       __nmk_config_pin(nmk_chip, gpio - nmk_chip->chip.base, cfg);
+       spin_unlock_irqrestore(&nmk_chip->lock, flags);
+
+       return 0;
+}
+EXPORT_SYMBOL(nmk_config_pin);
+
+/**
+ * nmk_config_pins - configure several pins at once
+ * @cfgs: array of pin configurations
+ * @num: number of elments in the array
+ *
+ * Configures several pins using nmk_config_pin().  Refer to that function for
+ * further information.
+ */
+int nmk_config_pins(pin_cfg_t *cfgs, int num)
+{
+       int ret = 0;
+       int i;
+
+       for (i = 0; i < num; i++) {
+               int ret = nmk_config_pin(cfgs[i]);
+               if (ret)
+                       break;
+       }
+
+       return ret;
+}
+EXPORT_SYMBOL(nmk_config_pins);
+
+/**
+ * nmk_gpio_set_slpm() - configure the sleep mode of a pin
+ * @gpio: pin number
+ * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
+ *
+ * Sets the sleep mode of a pin.  If @mode is NMK_GPIO_SLPM_INPUT, the pin is
+ * changed to an input (with pullup/down enabled) in sleep and deep sleep.  If
+ * @mode is NMK_GPIO_SLPM_NOCHANGE, the pin remains in the state it was
+ * configured even when in sleep and deep sleep.
+ */
+int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
+{
+       struct nmk_gpio_chip *nmk_chip;
+       unsigned long flags;
+
+       nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
+       if (!nmk_chip)
+               return -EINVAL;
+
+       spin_lock_irqsave(&nmk_chip->lock, flags);
+       __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode);
+       spin_unlock_irqrestore(&nmk_chip->lock, flags);
+
+       return 0;
+}
+
+/**
+ * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
+ * @gpio: pin number
+ * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
+ *
+ * Enables/disables pull up/down on a specified pin.  This only takes effect if
+ * the pin is configured as an input (either explicitly or by the alternate
+ * function).
+ *
+ * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
+ * configured as an input.  Otherwise, due to the way the controller registers
+ * work, this function will change the value output on the pin.
+ */
+int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
+{
+       struct nmk_gpio_chip *nmk_chip;
+       unsigned long flags;
+
+       nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
+       if (!nmk_chip)
+               return -EINVAL;
+
+       spin_lock_irqsave(&nmk_chip->lock, flags);
+       __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull);
+       spin_unlock_irqrestore(&nmk_chip->lock, flags);
+
+       return 0;
+}
+
 /* Mode functions */
 int nmk_gpio_set_mode(int gpio, int gpio_mode)
 {
        struct nmk_gpio_chip *nmk_chip;
        unsigned long flags;
-       u32 afunc, bfunc, bit;
 
        nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
        if (!nmk_chip)
                return -EINVAL;
 
-       bit = 1 << (gpio - nmk_chip->chip.base);
-
        spin_lock_irqsave(&nmk_chip->lock, flags);
-       afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
-       bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
-       if (gpio_mode & NMK_GPIO_ALT_A)
-               afunc |= bit;
-       if (gpio_mode & NMK_GPIO_ALT_B)
-               bfunc |= bit;
-       writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
-       writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
+       __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode);
        spin_unlock_irqrestore(&nmk_chip->lock, flags);
 
        return 0;
@@ -111,32 +301,41 @@ static void nmk_gpio_irq_ack(unsigned int irq)
        writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC);
 }
 
+enum nmk_gpio_irq_type {
+       NORMAL,
+       WAKE,
+};
+
 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
-                                 int gpio, bool enable)
+                                 int gpio, enum nmk_gpio_irq_type which,
+                                 bool enable)
 {
+       u32 rimsc = which == WAKE ? NMK_GPIO_RWIMSC : NMK_GPIO_RIMSC;
+       u32 fimsc = which == WAKE ? NMK_GPIO_FWIMSC : NMK_GPIO_FIMSC;
        u32 bitmask = nmk_gpio_get_bitmask(gpio);
        u32 reg;
 
        /* we must individually set/clear the two edges */
        if (nmk_chip->edge_rising & bitmask) {
-               reg = readl(nmk_chip->addr + NMK_GPIO_RIMSC);
+               reg = readl(nmk_chip->addr + rimsc);
                if (enable)
                        reg |= bitmask;
                else
                        reg &= ~bitmask;
-               writel(reg, nmk_chip->addr + NMK_GPIO_RIMSC);
+               writel(reg, nmk_chip->addr + rimsc);
        }
        if (nmk_chip->edge_falling & bitmask) {
-               reg = readl(nmk_chip->addr + NMK_GPIO_FIMSC);
+               reg = readl(nmk_chip->addr + fimsc);
                if (enable)
                        reg |= bitmask;
                else
                        reg &= ~bitmask;
-               writel(reg, nmk_chip->addr + NMK_GPIO_FIMSC);
+               writel(reg, nmk_chip->addr + fimsc);
        }
 }
 
-static void nmk_gpio_irq_modify(unsigned int irq, bool enable)
+static int nmk_gpio_irq_modify(unsigned int irq, enum nmk_gpio_irq_type which,
+                              bool enable)
 {
        int gpio;
        struct nmk_gpio_chip *nmk_chip;
@@ -147,26 +346,35 @@ static void nmk_gpio_irq_modify(unsigned int irq, bool enable)
        nmk_chip = get_irq_chip_data(irq);
        bitmask = nmk_gpio_get_bitmask(gpio);
        if (!nmk_chip)
-               return;
+               return -EINVAL;
 
        spin_lock_irqsave(&nmk_chip->lock, flags);
-       __nmk_gpio_irq_modify(nmk_chip, gpio, enable);
+       __nmk_gpio_irq_modify(nmk_chip, gpio, which, enable);
        spin_unlock_irqrestore(&nmk_chip->lock, flags);
+
+       return 0;
 }
 
 static void nmk_gpio_irq_mask(unsigned int irq)
 {
-       nmk_gpio_irq_modify(irq, false);
-};
+       nmk_gpio_irq_modify(irq, NORMAL, false);
+}
 
 static void nmk_gpio_irq_unmask(unsigned int irq)
 {
-       nmk_gpio_irq_modify(irq, true);
+       nmk_gpio_irq_modify(irq, NORMAL, true);
+}
+
+static int nmk_gpio_irq_set_wake(unsigned int irq, unsigned int on)
+{
+       return nmk_gpio_irq_modify(irq, WAKE, on);
 }
 
 static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type)
 {
-       bool enabled = !(irq_to_desc(irq)->status & IRQ_DISABLED);
+       struct irq_desc *desc = irq_to_desc(irq);
+       bool enabled = !(desc->status & IRQ_DISABLED);
+       bool wake = desc->wake_depth;
        int gpio;
        struct nmk_gpio_chip *nmk_chip;
        unsigned long flags;
@@ -186,7 +394,10 @@ static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type)
        spin_lock_irqsave(&nmk_chip->lock, flags);
 
        if (enabled)
-               __nmk_gpio_irq_modify(nmk_chip, gpio, false);
+               __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false);
+
+       if (wake)
+               __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false);
 
        nmk_chip->edge_rising &= ~bitmask;
        if (type & IRQ_TYPE_EDGE_RISING)
@@ -197,7 +408,10 @@ static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type)
                nmk_chip->edge_falling |= bitmask;
 
        if (enabled)
-               __nmk_gpio_irq_modify(nmk_chip, gpio, true);
+               __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true);
+
+       if (wake)
+               __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true);
 
        spin_unlock_irqrestore(&nmk_chip->lock, flags);
 
@@ -210,6 +424,7 @@ static struct irq_chip nmk_gpio_irq_chip = {
        .mask           = nmk_gpio_irq_mask,
        .unmask         = nmk_gpio_irq_unmask,
        .set_type       = nmk_gpio_irq_set_type,
+       .set_wake       = nmk_gpio_irq_set_wake,
 };
 
 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
@@ -266,16 +481,6 @@ static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
        return 0;
 }
 
-static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
-                               int val)
-{
-       struct nmk_gpio_chip *nmk_chip =
-               container_of(chip, struct nmk_gpio_chip, chip);
-
-       writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
-       return 0;
-}
-
 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
 {
        struct nmk_gpio_chip *nmk_chip =
@@ -298,12 +503,33 @@ static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
                writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
 }
 
+static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
+                               int val)
+{
+       struct nmk_gpio_chip *nmk_chip =
+               container_of(chip, struct nmk_gpio_chip, chip);
+
+       writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
+       nmk_gpio_set_output(chip, offset, val);
+
+       return 0;
+}
+
+static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+       struct nmk_gpio_chip *nmk_chip =
+               container_of(chip, struct nmk_gpio_chip, chip);
+
+       return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset;
+}
+
 /* This structure is replicated for each GPIO block allocated at probe time */
 static struct gpio_chip nmk_gpio_template = {
        .direction_input        = nmk_gpio_make_input,
        .get                    = nmk_gpio_get_input,
        .direction_output       = nmk_gpio_make_output,
        .set                    = nmk_gpio_set_output,
+       .to_irq                 = nmk_gpio_to_irq,
        .ngpio                  = NMK_GPIO_PER_CHIP,
        .can_sleep              = 0,
 };
@@ -393,30 +619,12 @@ out:
        return ret;
 }
 
-static int __exit nmk_gpio_remove(struct platform_device *dev)
-{
-       struct nmk_gpio_chip *nmk_chip;
-       struct resource *res;
-
-       res = platform_get_resource(dev, IORESOURCE_MEM, 0);
-
-       nmk_chip = platform_get_drvdata(dev);
-       gpiochip_remove(&nmk_chip->chip);
-       clk_disable(nmk_chip->clk);
-       clk_put(nmk_chip->clk);
-       kfree(nmk_chip);
-       release_mem_region(res->start, resource_size(res));
-       return 0;
-}
-
-
 static struct platform_driver nmk_gpio_driver = {
        .driver = {
                .owner = THIS_MODULE,
                .name = "gpio",
                },
        .probe = nmk_gpio_probe,
-       .remove = __exit_p(nmk_gpio_remove),
        .suspend = NULL, /* to be done */
        .resume = NULL,
 };
@@ -426,7 +634,7 @@ static int __init nmk_gpio_init(void)
        return platform_driver_register(&nmk_gpio_driver);
 }
 
-arch_initcall(nmk_gpio_init);
+core_initcall(nmk_gpio_init);
 
 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
 MODULE_DESCRIPTION("Nomadik GPIO Driver");

diff --git a/arch/arm/plat-nomadik/include/plat/gpio.h b/arch/arm/plat-nomadik/include/plat/gpio.h
index 4200811249ca25180e9b2357ed58140f17cb9cd4..aba355101f492687e39e303fff8b26ceb761541e 100644 (file)
--- a/arch/arm/plat-nomadik/include/plat/gpio.h
+++ b/arch/arm/plat-nomadik/include/plat/gpio.h
@@ -55,6 +55,21 @@
 #define NMK_GPIO_ALT_B 2
 #define NMK_GPIO_ALT_C (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B)
 
+/* Pull up/down values */
+enum nmk_gpio_pull {
+       NMK_GPIO_PULL_NONE,
+       NMK_GPIO_PULL_UP,
+       NMK_GPIO_PULL_DOWN,
+};
+
+/* Sleep mode */
+enum nmk_gpio_slpm {
+       NMK_GPIO_SLPM_INPUT,
+       NMK_GPIO_SLPM_NOCHANGE,
+};
+
+extern int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode);
+extern int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull);
 extern int nmk_gpio_set_mode(int gpio, int gpio_mode);
 extern int nmk_gpio_get_mode(int gpio);
 

diff --git a/arch/arm/plat-nomadik/include/plat/mtu.h b/arch/arm/plat-nomadik/include/plat/mtu.h
index 42c907258b14a04e34622d1ca99c638c5827631f..65704a3d42410890b044fd499cfba2ceaf067b9c 100644 (file)
--- a/arch/arm/plat-nomadik/include/plat/mtu.h
+++ b/arch/arm/plat-nomadik/include/plat/mtu.h
@@ -1,6 +1,12 @@
 #ifndef __PLAT_MTU_H
 #define __PLAT_MTU_H
 
+/*
+ * Guaranteed runtime conversion range in seconds for
+ * the clocksource and clockevent.
+ */
+#define MTU_MIN_RANGE 4
+
 /* should be set by the platform code */
 extern void __iomem *mtu_base;
 

diff --git a/arch/arm/plat-nomadik/include/plat/pincfg.h b/arch/arm/plat-nomadik/include/plat/pincfg.h
new file mode 100644 (file)
index 0000000..7eed11c
--- /dev/null
+++ b/arch/arm/plat-nomadik/include/plat/pincfg.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License terms: GNU General Public License, version 2
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
+ *
+ * Based on arch/arm/mach-pxa/include/mach/mfp.h:
+ *   Copyright (C) 2007 Marvell International Ltd.
+ *   eric miao <eric.miao@marvell.com>
+ */
+
+#ifndef __PLAT_PINCFG_H
+#define __PLAT_PINCFG_H
+
+/*
+ * pin configurations are represented by 32-bit integers:
+ *
+ *     bit  0.. 8 - Pin Number (512 Pins Maximum)
+ *     bit  9..10 - Alternate Function Selection
+ *     bit 11..12 - Pull up/down state
+ *     bit     13 - Sleep mode behaviour
+ *
+ * to facilitate the definition, the following macros are provided
+ *
+ * PIN_CFG_DEFAULT - default config (0):
+ *                  pull up/down = disabled
+ *                  sleep mode = input
+ *
+ * PIN_CFG        - default config with alternate function
+ * PIN_CFG_PULL           - default config with alternate function and pull up/down
+ */
+
+typedef unsigned long pin_cfg_t;
+
+#define PIN_NUM_MASK           0x1ff
+#define PIN_NUM(x)             ((x) & PIN_NUM_MASK)
+
+#define PIN_ALT_SHIFT          9
+#define PIN_ALT_MASK           (0x3 << PIN_ALT_SHIFT)
+#define PIN_ALT(x)             (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
+#define PIN_GPIO               (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
+#define PIN_ALT_A              (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
+#define PIN_ALT_B              (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
+#define PIN_ALT_C              (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
+
+#define PIN_PULL_SHIFT         11
+#define PIN_PULL_MASK          (0x3 << PIN_PULL_SHIFT)
+#define PIN_PULL(x)            (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
+#define PIN_PULL_NONE          (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
+#define PIN_PULL_UP            (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
+#define PIN_PULL_DOWN          (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
+
+#define PIN_SLPM_SHIFT         13
+#define PIN_SLPM_MASK          (0x1 << PIN_SLPM_SHIFT)
+#define PIN_SLPM(x)            (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
+#define PIN_SLPM_INPUT         (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
+#define PIN_SLPM_NOCHANGE      (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
+
+#define PIN_CFG_DEFAULT                (PIN_PULL_NONE | PIN_SLPM_INPUT)
+
+#define PIN_CFG(num, alt)              \
+       (PIN_CFG_DEFAULT |\
+        (PIN_NUM(num) | PIN_##alt))
+
+#define PIN_CFG_PULL(num, alt, pull)   \
+       ((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\
+        (PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull))
+
+extern int nmk_config_pin(pin_cfg_t cfg);
+extern int nmk_config_pins(pin_cfg_t *cfgs, int num);
+
+#endif

diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c
index 08aaa4a7f65fe0e868b1a8cbfa8dd80d73209cec..ea3ca86c52836ba1ec9fe780da9c1629db91723f 100644 (file)
--- a/arch/arm/plat-nomadik/timer.c
+++ b/arch/arm/plat-nomadik/timer.c
@@ -42,7 +42,6 @@ static struct clocksource nmdk_clksrc = {
        .rating         = 200,
        .read           = nmdk_read_timer_dummy,
        .mask           = CLOCKSOURCE_MASK(32),
-       .shift          = 20,
        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
@@ -82,6 +81,12 @@ static void nmdk_clkevt_mode(enum clock_event_mode mode,
        case CLOCK_EVT_MODE_UNUSED:
                /* disable irq */
                writel(0, mtu_base + MTU_IMSC);
+               /* disable timer */
+               cr = readl(mtu_base + MTU_CR(1));
+               cr &= ~MTU_CRn_ENA;
+               writel(cr, mtu_base + MTU_CR(1));
+               /* load some high default value */
+               writel(0xffffffff, mtu_base + MTU_LR(1));
                break;
        case CLOCK_EVT_MODE_RESUME:
                break;
@@ -98,7 +103,6 @@ static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
 static struct clock_event_device nmdk_clkevt = {
        .name           = "mtu_1",
        .features       = CLOCK_EVT_FEAT_ONESHOT,
-       .shift          = 32,
        .rating         = 200,
        .set_mode       = nmdk_clkevt_mode,
        .set_next_event = nmdk_clkevt_next,
@@ -151,6 +155,7 @@ void __init nmdk_timer_init(void)
        } else {
                cr |= MTU_CRn_PRESCALE_1;
        }
+       clocksource_calc_mult_shift(&nmdk_clksrc, rate, MTU_MIN_RANGE);
 
        /* Timer 0 is the free running clocksource */
        writel(cr, mtu_base + MTU_CR(0));
@@ -158,7 +163,6 @@ void __init nmdk_timer_init(void)
        writel(0, mtu_base + MTU_BGLR(0));
        writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0));
 
-       nmdk_clksrc.mult = clocksource_hz2mult(rate, nmdk_clksrc.shift);
        /* Now the scheduling clock is ready */
        nmdk_clksrc.read = nmdk_read_timer;
 
@@ -175,8 +179,10 @@ void __init nmdk_timer_init(void)
        } else {
                cr |= MTU_CRn_PRESCALE_1;
        }
+       clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE);
+
        writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */
-       nmdk_clkevt.mult = div_sc(rate, NSEC_PER_SEC, nmdk_clkevt.shift);
+
        nmdk_clkevt.max_delta_ns =
                clockevent_delta2ns(0xffffffff, &nmdk_clkevt);
        nmdk_clkevt.min_delta_ns =

diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 111d39a47ad17be21b8a30209f4b54f8169c43b5..e39a417a368dc92ad6776a68ef6fefc22a046b76 100644 (file)
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -1,6 +1,6 @@
 if ARCH_OMAP
 
-menu "TI OMAP Implementations"
+menu "TI OMAP Common Features"
 
 config ARCH_OMAP_OTG
        bool
@@ -21,24 +21,6 @@ config ARCH_OMAP2PLUS
        help
          "Systems based on omap24xx, omap34xx or omap44xx"
 
-config ARCH_OMAP2
-       bool "TI OMAP2"
-       depends on ARCH_OMAP2PLUS
-       select CPU_V6
-
-config ARCH_OMAP3
-       bool "TI OMAP3"
-       depends on ARCH_OMAP2PLUS
-       select CPU_V7
-       select USB_ARCH_HAS_EHCI
-       select ARM_L1_CACHE_SHIFT_6
-
-config ARCH_OMAP4
-       bool "TI OMAP4"
-       depends on ARCH_OMAP2PLUS
-       select CPU_V7
-       select ARM_GIC
-
 endchoice
 
 comment "OMAP Feature Selections"
@@ -51,7 +33,7 @@ config OMAP_DEBUG_DEVICES
 config OMAP_DEBUG_LEDS
        bool
        depends on OMAP_DEBUG_DEVICES
-       default y if LEDS || LEDS_OMAP_DEBUG
+       default y if LEDS
 
 config OMAP_RESET_CLOCKS
        bool "Reset unused clocks during boot"
@@ -129,7 +111,7 @@ config OMAP_IOMMU_DEBUG
 
 choice
        prompt "System timer"
-       default OMAP_MPU_TIMER
+       default OMAP_32K_TIMER if !ARCH_OMAP15XX
 
 config OMAP_MPU_TIMER
        bool "Use mpu timer"

diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 98f01910c2cfa1568d9858f4180890fdf518d929..9405831b746a5e63dd4dc3a2a6220afce032713c 100644 (file)
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
 # omap_device support (OMAP2+ only at the moment)
 obj-$(CONFIG_ARCH_OMAP2) += omap_device.o
 obj-$(CONFIG_ARCH_OMAP3) += omap_device.o
+obj-$(CONFIG_ARCH_OMAP4) += omap_device.o
 
 obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
 obj-$(CONFIG_OMAP_IOMMU) += iommu.o iovmm.o

diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 219c01e82bc5a3cf70055f5e7593b0c115000e21..3008e71044876bf9007428b8020351b797902094 100644 (file)
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -22,6 +22,7 @@
 #include <linux/serial_reg.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/omapfb.h>
 
 #include <mach/hardware.h>
 #include <asm/system.h>
@@ -35,6 +36,7 @@
 #include <plat/mux.h>
 #include <plat/fpga.h>
 #include <plat/serial.h>
+#include <plat/vram.h>
 
 #include <plat/clock.h>
 
@@ -81,6 +83,12 @@ const void *omap_get_var_config(u16 tag, size_t *len)
 }
 EXPORT_SYMBOL(omap_get_var_config);
 
+void __init omap_reserve(void)
+{
+       omapfb_reserve_sdram_memblock();
+       omap_vram_reserve_sdram_memblock();
+}
+
 /*
  * 32KHz clocksource ... always available, on pretty most chips except
  * OMAP 730 and 1510.  Other timers could be used as clocksources, with
@@ -309,18 +317,18 @@ static struct omap_globals omap3_globals = {
        .uart1_phys     = OMAP3_UART1_BASE,
        .uart2_phys     = OMAP3_UART2_BASE,
        .uart3_phys     = OMAP3_UART3_BASE,
+       .uart4_phys     = OMAP3_UART4_BASE,     /* Only on 3630 */
 };
 
-void __init omap2_set_globals_343x(void)
+void __init omap2_set_globals_3xxx(void)
 {
        __omap2_set_globals(&omap3_globals);
 }
 
-void __init omap2_set_globals_36xx(void)
+void __init omap3_map_io(void)
 {
-       omap3_globals.uart4_phys = OMAP3_UART4_BASE;
-
-       __omap2_set_globals(&omap3_globals);
+       omap2_set_globals_3xxx();
+       omap34xx_map_common_io();
 }
 #endif
 

diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index 53fcef7c5201b10550305cc96db32538c3f31feb..fc05b10226026e6b514adaa10199bf270cbba7f2 100644 (file)
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -39,7 +39,7 @@ static struct h2p2_dbg_fpga __iomem   *fpga;
 static u16                             led_state, hw_led_state;
 
 
-#ifdef CONFIG_LEDS_OMAP_DEBUG
+#ifdef CONFIG_OMAP_DEBUG_LEDS
 #define new_led_api()  1
 #else
 #define new_led_api()  0

diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 95677d17cd1ca02e9626e41e57dae23d16024a7e..d1920be7833bfe8d8336483928b616c6aa73f8d2 100644 (file)
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -24,135 +24,13 @@
 #include <plat/control.h>
 #include <plat/board.h>
 #include <plat/mmc.h>
-#include <plat/mux.h>
 #include <mach/gpio.h>
 #include <plat/menelaus.h>
 #include <plat/mcbsp.h>
-#include <plat/dsp_common.h>
 #include <plat/omap44xx.h>
 
-#if    defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
-
-static struct dsp_platform_data dsp_pdata = {
-       .kdev_list = LIST_HEAD_INIT(dsp_pdata.kdev_list),
-};
-
-static struct resource omap_dsp_resources[] = {
-       {
-               .name   = "dsp_mmu",
-               .start  = -1,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device omap_dsp_device = {
-       .name           = "dsp",
-       .id             = -1,
-       .num_resources  = ARRAY_SIZE(omap_dsp_resources),
-       .resource       = omap_dsp_resources,
-       .dev = {
-               .platform_data = &dsp_pdata,
-       },
-};
-
-static inline void omap_init_dsp(void)
-{
-       struct resource *res;
-       int irq;
-
-       if (cpu_is_omap15xx())
-               irq = INT_1510_DSP_MMU;
-       else if (cpu_is_omap16xx())
-               irq = INT_1610_DSP_MMU;
-       else if (cpu_is_omap24xx())
-               irq = INT_24XX_DSP_MMU;
-
-       res = platform_get_resource_byname(&omap_dsp_device,
-                                          IORESOURCE_IRQ, "dsp_mmu");
-       res->start = irq;
-
-       platform_device_register(&omap_dsp_device);
-}
-
-int dsp_kfunc_device_register(struct dsp_kfunc_device *kdev)
-{
-       static DEFINE_MUTEX(dsp_pdata_lock);
-
-       spin_lock_init(&kdev->lock);
-
-       mutex_lock(&dsp_pdata_lock);
-       list_add_tail(&kdev->entry, &dsp_pdata.kdev_list);
-       mutex_unlock(&dsp_pdata_lock);
-
-       return 0;
-}
-EXPORT_SYMBOL(dsp_kfunc_device_register);
-
-#else
-static inline void omap_init_dsp(void) { }
-#endif /* CONFIG_OMAP_DSP */
-
 /*-------------------------------------------------------------------------*/
-#if    defined(CONFIG_KEYBOARD_OMAP) || defined(CONFIG_KEYBOARD_OMAP_MODULE)
-
-static void omap_init_kp(void)
-{
-       /* 2430 and 34xx keypad is on TWL4030 */
-       if (cpu_is_omap2430() || cpu_is_omap34xx())
-               return;
 
-       if (machine_is_omap_h2() || machine_is_omap_h3()) {
-               omap_cfg_reg(F18_1610_KBC0);
-               omap_cfg_reg(D20_1610_KBC1);
-               omap_cfg_reg(D19_1610_KBC2);
-               omap_cfg_reg(E18_1610_KBC3);
-               omap_cfg_reg(C21_1610_KBC4);
-
-               omap_cfg_reg(G18_1610_KBR0);
-               omap_cfg_reg(F19_1610_KBR1);
-               omap_cfg_reg(H14_1610_KBR2);
-               omap_cfg_reg(E20_1610_KBR3);
-               omap_cfg_reg(E19_1610_KBR4);
-               omap_cfg_reg(N19_1610_KBR5);
-       } else if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
-               omap_cfg_reg(E2_7XX_KBR0);
-               omap_cfg_reg(J7_7XX_KBR1);
-               omap_cfg_reg(E1_7XX_KBR2);
-               omap_cfg_reg(F3_7XX_KBR3);
-               omap_cfg_reg(D2_7XX_KBR4);
-
-               omap_cfg_reg(C2_7XX_KBC0);
-               omap_cfg_reg(D3_7XX_KBC1);
-               omap_cfg_reg(E4_7XX_KBC2);
-               omap_cfg_reg(F4_7XX_KBC3);
-               omap_cfg_reg(E3_7XX_KBC4);
-       } else if (machine_is_omap_h4()) {
-               omap_cfg_reg(T19_24XX_KBR0);
-               omap_cfg_reg(R19_24XX_KBR1);
-               omap_cfg_reg(V18_24XX_KBR2);
-               omap_cfg_reg(M21_24XX_KBR3);
-               omap_cfg_reg(E5__24XX_KBR4);
-               if (omap_has_menelaus()) {
-                       omap_cfg_reg(B3__24XX_KBR5);
-                       omap_cfg_reg(AA4_24XX_KBC2);
-                       omap_cfg_reg(B13_24XX_KBC6);
-               } else {
-                       omap_cfg_reg(M18_24XX_KBR5);
-                       omap_cfg_reg(H19_24XX_KBC2);
-                       omap_cfg_reg(N19_24XX_KBC6);
-               }
-               omap_cfg_reg(R20_24XX_KBC0);
-               omap_cfg_reg(M14_24XX_KBC1);
-               omap_cfg_reg(V17_24XX_KBC3);
-               omap_cfg_reg(P21_24XX_KBC4);
-               omap_cfg_reg(L14_24XX_KBC5);
-       }
-}
-#else
-static inline void omap_init_kp(void) {}
-#endif
-
-/*-------------------------------------------------------------------------*/
 #if defined(CONFIG_OMAP_MCBSP) || defined(CONFIG_OMAP_MCBSP_MODULE)
 
 static struct platform_device **omap_mcbsp_devices;
@@ -419,8 +297,6 @@ static int __init omap_init_devices(void)
        /* please keep these calls, and their implementations above,
         * in alphabetical order so they're easier to sort through.
         */
-       omap_init_dsp();
-       omap_init_kp();
        omap_init_rng();
        omap_init_mcpdm();
        omap_init_uwire();

diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index f7f571e7987e256a61088d3efaefc6b46d5ecd25..ec7eddf9e525e4dc5a9d09a4b23ee3d635d6c14b 100644 (file)
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -290,7 +290,7 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
                val = dma_read(CCR(lch));
 
                /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
-               val &= ~((3 << 19) | 0x1f);
+               val &= ~((1 << 23) | (3 << 19) | 0x1f);
                val |= (dma_trigger & ~0x1f) << 14;
                val |= dma_trigger & 0x1f;
 
@@ -304,11 +304,14 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
                else
                        val &= ~(1 << 18);
 
-               if (src_or_dst_synch)
+               if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
+                       val &= ~(1 << 24);      /* dest synch */
+                       val |= (1 << 23);       /* Prefetch */
+               } else if (src_or_dst_synch) {
                        val |= 1 << 24;         /* source synch */
-               else
+               } else {
                        val &= ~(1 << 24);      /* dest synch */
-
+               }
                dma_write(val, CCR(lch));
        }
 

diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
index d3eea4f47533050618ce2a0e489a79f5f2725088..0054b9501a53976a384cde437b43be7c03cc582a 100644 (file)
--- a/arch/arm/plat-omap/fb.c
+++ b/arch/arm/plat-omap/fb.c
@@ -26,7 +26,7 @@
 #include <linux/mm.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/bootmem.h>
+#include <linux/memblock.h>
 #include <linux/io.h>
 #include <linux/omapfb.h>
 
@@ -171,49 +171,78 @@ static int check_fbmem_region(int region_idx, struct omapfb_mem_region *rg,
        return 0;
 }
 
+static int valid_sdram(unsigned long addr, unsigned long size)
+{
+       struct memblock_property res;
+
+       res.base = addr;
+       res.size = size;
+       return !memblock_find(&res) && res.base == addr && res.size == size;
+}
+
+static int reserve_sdram(unsigned long addr, unsigned long size)
+{
+       if (memblock_is_region_reserved(addr, size))
+               return -EBUSY;
+       if (memblock_reserve(addr, size))
+               return -ENOMEM;
+       return 0;
+}
+
 /*
  * Called from map_io. We need to call to this early enough so that we
  * can reserve the fixed SDRAM regions before VM could get hold of them.
  */
-void __init omapfb_reserve_sdram(void)
+void __init omapfb_reserve_sdram_memblock(void)
 {
-       struct bootmem_data     *bdata;
-       unsigned long           sdram_start, sdram_size;
-       unsigned long           reserved;
-       int                     i;
+       unsigned long reserved = 0;
+       int i;
 
        if (config_invalid)
                return;
 
-       bdata = NODE_DATA(0)->bdata;
-       sdram_start = bdata->node_min_pfn << PAGE_SHIFT;
-       sdram_size = (bdata->node_low_pfn << PAGE_SHIFT) - sdram_start;
-       reserved = 0;
        for (i = 0; ; i++) {
-               struct omapfb_mem_region        rg;
+               struct omapfb_mem_region rg;
 
                if (get_fbmem_region(i, &rg) < 0)
                        break;
+
                if (i == OMAPFB_PLANE_NUM) {
-                       printk(KERN_ERR
-                               "Extraneous FB mem configuration entries\n");
+                       pr_err("Extraneous FB mem configuration entries\n");
                        config_invalid = 1;
                        return;
                }
+
                /* Check if it's our memory type. */
-               if (set_fbmem_region_type(&rg, OMAPFB_MEMTYPE_SDRAM,
-                                         sdram_start, sdram_size) < 0 ||
-                   (rg.type != OMAPFB_MEMTYPE_SDRAM))
+               if (rg.type != OMAPFB_MEMTYPE_SDRAM)
                        continue;
-               BUG_ON(omapfb_config.mem_desc.region[i].size);
-               if (check_fbmem_region(i, &rg, sdram_start, sdram_size) < 0) {
+
+               /* Check if the region falls within SDRAM */
+               if (rg.paddr && !valid_sdram(rg.paddr, rg.size))
+                       continue;
+
+               if (rg.size == 0) {
+                       pr_err("Zero size for FB region %d\n", i);
                        config_invalid = 1;
                        return;
                }
+
                if (rg.paddr) {
-                       reserve_bootmem(rg.paddr, rg.size, BOOTMEM_DEFAULT);
+                       if (reserve_sdram(rg.paddr, rg.size)) {
+                               pr_err("Trying to use reserved memory for FB region %d\n",
+                                       i);
+                               config_invalid = 1;
+                               return;
+                       }
                        reserved += rg.size;
                }
+
+               if (omapfb_config.mem_desc.region[i].size) {
+                       pr_err("FB region %d already set\n", i);
+                       config_invalid = 1;
+                       return;
+               }
+
                omapfb_config.mem_desc.region[i] = rg;
                configured_regions++;
        }
@@ -359,7 +388,10 @@ static inline int omap_init_fb(void)
 
 arch_initcall(omap_init_fb);
 
-void omapfb_reserve_sdram(void) {}
+void omapfb_reserve_sdram_memblock(void)
+{
+}
+
 unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
                                  unsigned long sram_vstart,
                                  unsigned long sram_size,
@@ -375,7 +407,10 @@ void omapfb_set_platform_data(struct omapfb_platform_data *data)
 {
 }
 
-void omapfb_reserve_sdram(void) {}
+void omapfb_reserve_sdram_memblock(void)
+{
+}
+
 unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
                                  unsigned long sram_vstart,
                                  unsigned long sram_size,

diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 9b7e3545f32552e1cdb7d4bfc0b9cc6331de8b0f..7951eefe1a0e90d634c315882427f94fc9c32faa 100644 (file)
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -390,7 +390,9 @@ static inline int gpio_valid(int gpio)
                return 0;
        if (cpu_is_omap7xx() && gpio < 192)
                return 0;
-       if (cpu_is_omap24xx() && gpio < 128)
+       if (cpu_is_omap2420() && gpio < 128)
+               return 0;
+       if (cpu_is_omap2430() && gpio < 160)
                return 0;
        if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
                return 0;

diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index eec2b4993c6951f12fdfbe2bc283b7098eaddae1..a5ce4f0aad35b47864609a3eff307205dae64e21 100644 (file)
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -138,6 +138,16 @@ static inline int omap1_i2c_add_bus(struct platform_device *pdev, int bus_id)
        return platform_device_register(pdev);
 }
 
+/*
+ * XXX This function is a temporary compatibility wrapper - only
+ * needed until the I2C driver can be converted to call
+ * omap_pm_set_max_dev_wakeup_lat() and handle a return code.
+ */
+static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t)
+{
+       omap_pm_set_max_mpu_wakeup_lat(dev, t);
+}
+
 static inline int omap2_i2c_add_bus(struct platform_device *pdev, int bus_id)
 {
        struct resource *res;
@@ -168,7 +178,7 @@ static inline int omap2_i2c_add_bus(struct platform_device *pdev, int bus_id)
                struct omap_i2c_bus_platform_data *pd;
 
                pd = pdev->dev.platform_data;
-               pd->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat;
+               pd->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
        }
 
        return platform_device_register(pdev);

diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index 5cd622039da0db81f4a7b1275449ddd11f830bb1..3cf4fa25ab3d078a49e9488effaebf571fa128da 100644 (file)
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -85,6 +85,14 @@ struct omap_usb_config {
         *  6 == 6 wire unidirectional (or TLL)
         */
        u8              pins[3];
+
+       struct platform_device *udc_device;
+       struct platform_device *ohci_device;
+       struct platform_device *otg_device;
+
+       u32 (*usb0_init)(unsigned nwires, unsigned is_device);
+       u32 (*usb1_init)(unsigned nwires);
+       u32 (*usb2_init)(unsigned nwires, unsigned alt_pingroup);
 };
 
 struct omap_lcd_config {

diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index dfc472ca0cc44acab0877b404c958ff87a21c730..fef4696dcf674c464e3154210a504380429ba76a 100644 (file)
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -19,6 +19,22 @@ struct module;
 struct clk;
 struct clockdomain;
 
+/**
+ * struct clkops - some clock function pointers
+ * @enable: fn ptr that enables the current clock in hardware
+ * @disable: fn ptr that enables the current clock in hardware
+ * @find_idlest: function returning the IDLEST register for the clock's IP blk
+ * @find_companion: function returning the "companion" clk reg for the clock
+ *
+ * A "companion" clk is an accompanying clock to the one being queried
+ * that must be enabled for the IP module connected to the clock to
+ * become accessible by the hardware.  Neither @find_idlest nor
+ * @find_companion should be needed; that information is IP
+ * block-specific; the hwmod code has been created to handle this, but
+ * until hwmod data is ready and drivers have been converted to use PM
+ * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and
+ * @find_companion must, unfortunately, remain.
+ */
 struct clkops {
        int                     (*enable)(struct clk *);
        void                    (*disable)(struct clk *);
@@ -30,12 +46,45 @@ struct clkops {
 
 #ifdef CONFIG_ARCH_OMAP2PLUS
 
+/* struct clksel_rate.flags possibilities */
+#define RATE_IN_242X           (1 << 0)
+#define RATE_IN_243X           (1 << 1)
+#define RATE_IN_3XXX           (1 << 2)        /* rates common to all OMAP3 */
+#define RATE_IN_3430ES2                (1 << 3)        /* 3430ES2 rates only */
+#define RATE_IN_36XX           (1 << 4)
+#define RATE_IN_4430           (1 << 5)
+
+#define RATE_IN_24XX           (RATE_IN_242X | RATE_IN_243X)
+#define RATE_IN_3430ES2PLUS    (RATE_IN_3430ES2 | RATE_IN_36XX)
+
+/**
+ * struct clksel_rate - register bitfield values corresponding to clk divisors
+ * @val: register bitfield value (shifted to bit 0)
+ * @div: clock divisor corresponding to @val
+ * @flags: (see "struct clksel_rate.flags possibilities" above)
+ *
+ * @val should match the value of a read from struct clk.clksel_reg
+ * AND'ed with struct clk.clksel_mask, shifted right to bit 0.
+ *
+ * @div is the divisor that should be applied to the parent clock's rate
+ * to produce the current clock's rate.
+ *
+ * XXX @flags probably should be replaced with an struct omap_chip.
+ */
 struct clksel_rate {
        u32                     val;
        u8                      div;
        u8                      flags;
 };
 
+/**
+ * struct clksel - available parent clocks, and a pointer to their divisors
+ * @parent: struct clk * to a possible parent clock
+ * @rates: available divisors for this parent clock
+ *
+ * A struct clksel is always associated with one or more struct clks
+ * and one or more struct clksel_rates.
+ */
 struct clksel {
        struct clk               *parent;
        const struct clksel_rate *rates;
@@ -116,6 +165,60 @@ struct dpll_data {
 
 #endif
 
+/* struct clk.flags possibilities */
+#define ENABLE_REG_32BIT       (1 << 0)        /* Use 32-bit access */
+#define CLOCK_IDLE_CONTROL     (1 << 1)
+#define CLOCK_NO_IDLE_PARENT   (1 << 2)
+#define ENABLE_ON_INIT         (1 << 3)        /* Enable upon framework init */
+#define INVERT_ENABLE          (1 << 4)        /* 0 enables, 1 disables */
+
+/**
+ * struct clk - OMAP struct clk
+ * @node: list_head connecting this clock into the full clock list
+ * @ops: struct clkops * for this clock
+ * @name: the name of the clock in the hardware (used in hwmod data and debug)
+ * @parent: pointer to this clock's parent struct clk
+ * @children: list_head connecting to the child clks' @sibling list_heads
+ * @sibling: list_head connecting this clk to its parent clk's @children
+ * @rate: current clock rate
+ * @enable_reg: register to write to enable the clock (see @enable_bit)
+ * @recalc: fn ptr that returns the clock's current rate
+ * @set_rate: fn ptr that can change the clock's current rate
+ * @round_rate: fn ptr that can round the clock's current rate
+ * @init: fn ptr to do clock-specific initialization
+ * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
+ * @usecount: number of users that have requested this clock to be enabled
+ * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
+ * @flags: see "struct clk.flags possibilities" above
+ * @clksel_reg: for clksel clks, register va containing src/divisor select
+ * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
+ * @clksel: for clksel clks, pointer to struct clksel for this clock
+ * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
+ * @clkdm_name: clockdomain name that this clock is contained in
+ * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
+ * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
+ * @src_offset: bitshift for source selection bitfield (OMAP1 only)
+ *
+ * XXX @rate_offset, @src_offset should probably be removed and OMAP1
+ * clock code converted to use clksel.
+ *
+ * XXX @usecount is poorly named.  It should be "enable_count" or
+ * something similar.  "users" in the description refers to kernel
+ * code (core code or drivers) that have called clk_enable() and not
+ * yet called clk_disable(); the usecount of parent clocks is also
+ * incremented by the clock code when clk_enable() is called on child
+ * clocks and decremented by the clock code when clk_disable() is
+ * called on child clocks.
+ *
+ * XXX @clkdm, @usecount, @children, @sibling should be marked for
+ * internal use only.
+ *
+ * @children and @sibling are used to optimize parent-to-child clock
+ * tree traversals.  (child-to-parent traversals use @parent.)
+ *
+ * XXX The notion of the clock's current rate probably needs to be
+ * separated from the clock's target rate.
+ */
 struct clk {
        struct list_head        node;
        const struct clkops     *ops;
@@ -129,8 +232,8 @@ struct clk {
        int                     (*set_rate)(struct clk *, unsigned long);
        long                    (*round_rate)(struct clk *, unsigned long);
        void                    (*init)(struct clk *);
-       __u8                    enable_bit;
-       __s8                    usecount;
+       u8                      enable_bit;
+       s8                      usecount;
        u8                      fixed_div;
        u8                      flags;
 #ifdef CONFIG_ARCH_OMAP2PLUS
@@ -141,8 +244,8 @@ struct clk {
        const char              *clkdm_name;
        struct clockdomain      *clkdm;
 #else
-       __u8                    rate_offset;
-       __u8                    src_offset;
+       u8                      rate_offset;
+       u8                      src_offset;
 #endif
 #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
        struct dentry           *dent;  /* For visible tree hierarchy */
@@ -188,23 +291,4 @@ extern const struct clkops clkops_null;
 
 extern struct clk dummy_ck;
 
-/* Clock flags */
-#define ENABLE_REG_32BIT       (1 << 0)        /* Use 32-bit access */
-#define CLOCK_IDLE_CONTROL     (1 << 1)
-#define CLOCK_NO_IDLE_PARENT   (1 << 2)
-#define ENABLE_ON_INIT         (1 << 3)        /* Enable upon framework init */
-#define INVERT_ENABLE          (1 << 4)        /* 0 enables, 1 disables */
-
-/* Clksel_rate flags */
-#define RATE_IN_242X           (1 << 0)
-#define RATE_IN_243X           (1 << 1)
-#define RATE_IN_3XXX           (1 << 2)        /* rates common to all OMAP3 */
-#define RATE_IN_3430ES2                (1 << 3)        /* 3430ES2 rates only */
-#define RATE_IN_36XX           (1 << 4)
-#define RATE_IN_4430           (1 << 5)
-
-#define RATE_IN_24XX           (RATE_IN_242X | RATE_IN_243X)
-
-#define RATE_IN_3430ES2PLUS    (RATE_IN_3430ES2 | RATE_IN_36XX)
-
 #endif

diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index d265018f5e6b729a146a351388f3213dc8c72472..9776b41ad76f57a9f63bd3be3e1044f2f58481af 100644 (file)
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -34,6 +34,8 @@ struct sys_timer;
 extern void omap_map_common_io(void);
 extern struct sys_timer omap_timer;
 
+extern void omap_reserve(void);
+
 /*
  * IO bases for various OMAP processors
  * Except the tap base, rest all the io bases
@@ -56,8 +58,7 @@ struct omap_globals {
 
 void omap2_set_globals_242x(void);
 void omap2_set_globals_243x(void);
-void omap2_set_globals_343x(void);
-void omap2_set_globals_36xx(void);
+void omap2_set_globals_3xxx(void);
 void omap2_set_globals_443x(void);
 
 /* These get called from omap2_set_globals_xxxx(), do not call these */
@@ -67,6 +68,8 @@ void omap2_set_globals_control(struct omap_globals *);
 void omap2_set_globals_prcm(struct omap_globals *);
 void omap2_set_globals_uart(struct omap_globals *);
 
+void omap3_map_io(void);
+
 /**
  * omap_test_timeout - busy-loop, testing a condition
  * @cond: condition to test until it evaluates to true
@@ -87,4 +90,8 @@ void omap2_set_globals_uart(struct omap_globals *);
        }                                                       \
 })
 
+extern struct device *omap2_get_mpuss_device(void);
+extern struct device *omap2_get_dsp_device(void);
+extern struct device *omap2_get_l3_device(void);
+
 #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */

diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 75141742300cfaca52494c0b767160d57ad617de..2e2ae530fced338a7b08fe16bc715582cd27cb44 100644 (file)
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -66,6 +66,8 @@ unsigned int omap_rev(void);
  * family. This difference can be handled separately.
  */
 #define OMAP_REVBITS_00                0x00
+#define OMAP_REVBITS_01                0x01
+#define OMAP_REVBITS_02                0x02
 #define OMAP_REVBITS_10                0x10
 #define OMAP_REVBITS_20                0x20
 #define OMAP_REVBITS_30                0x30
@@ -376,6 +378,8 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define OMAP3430_REV_ES3_1_2   0x34305034
 
 #define OMAP3630_REV_ES1_0     0x36300034
+#define OMAP3630_REV_ES1_1     0x36300134
+#define OMAP3630_REV_ES1_2     0x36300234
 
 #define OMAP35XX_CLASS         0x35000034
 #define OMAP3503_REV(v)                (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8))
@@ -411,6 +415,8 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define CHIP_IS_OMAP3430ES3_1          (1 << 6)
 #define CHIP_IS_OMAP3630ES1            (1 << 7)
 #define CHIP_IS_OMAP4430ES1            (1 << 8)
+#define CHIP_IS_OMAP3630ES1_1           (1 << 9)
+#define CHIP_IS_OMAP3630ES1_2           (1 << 10)
 
 #define CHIP_IS_OMAP24XX               (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
 
@@ -424,11 +430,12 @@ IS_OMAP_TYPE(3517, 0x3517)
  */
 #define CHIP_GE_OMAP3430ES2            (CHIP_IS_OMAP3430ES2 | \
                                         CHIP_IS_OMAP3430ES3_0 | \
-                                        CHIP_IS_OMAP3430ES3_1 | \
-                                        CHIP_IS_OMAP3630ES1)
+                                        CHIP_GE_OMAP3430ES3_1)
 #define CHIP_GE_OMAP3430ES3_1          (CHIP_IS_OMAP3430ES3_1 | \
-                                        CHIP_IS_OMAP3630ES1)
-
+                                        CHIP_IS_OMAP3630ES1 | \
+                                        CHIP_GE_OMAP3630ES1_1)
+#define CHIP_GE_OMAP3630ES1_1          (CHIP_IS_OMAP3630ES1_1 | \
+                                        CHIP_IS_OMAP3630ES1_2)
 
 int omap_chip_is(struct omap_chip_id oci);
 void omap2_check_revision(void);
@@ -444,6 +451,7 @@ extern u32 omap3_features;
 #define OMAP3_HAS_NEON                 BIT(3)
 #define OMAP3_HAS_ISP                  BIT(4)
 #define OMAP3_HAS_192MHZ_CLK           BIT(5)
+#define OMAP3_HAS_IO_WAKEUP            BIT(6)
 
 #define OMAP3_HAS_FEATURE(feat,flag)                   \
 static inline unsigned int omap3_has_ ##feat(void)     \
@@ -457,5 +465,6 @@ OMAP3_HAS_FEATURE(iva, IVA)
 OMAP3_HAS_FEATURE(neon, NEON)
 OMAP3_HAS_FEATURE(isp, ISP)
 OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
+OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP)
 
 #endif

diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index 02232ca2c37f87517acf9d0e3b85a4978de1d056..af3a03941addfd810a24452b2af25c749f3a8632 100644 (file)
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -345,6 +345,7 @@
 #define OMAP_DMA_SYNC_BLOCK            0x02
 #define OMAP_DMA_SYNC_PACKET           0x03
 
+#define OMAP_DMA_DST_SYNC_PREFETCH     0x02
 #define OMAP_DMA_SRC_SYNC              0x01
 #define OMAP_DMA_DST_SYNC              0x00
 

diff --git a/arch/arm/plat-omap/include/plat/dsp_common.h b/arch/arm/plat-omap/include/plat/dsp_common.h
deleted file mode 100644 (file)
index da97736..0000000
--- a/arch/arm/plat-omap/include/plat/dsp_common.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1)
- *
- * Copyright (C) 2004-2006 Nokia Corporation. All rights reserved.
- *
- * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- */
-
-#ifndef ASM_ARCH_DSP_COMMON_H
-#define ASM_ARCH_DSP_COMMON_H
-
-#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_OMAP_MMU_FWK)
-extern void omap_dsp_request_mpui(void);
-extern void omap_dsp_release_mpui(void);
-extern int omap_dsp_request_mem(void);
-extern int omap_dsp_release_mem(void);
-#else
-static inline int omap_dsp_request_mem(void)
-{
-       return 0;
-}
-#define omap_dsp_release_mem() do {} while (0)
-#endif
-
-#endif /* ASM_ARCH_DSP_COMMON_H */

diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index 145838a81ef6a7ea6e255cac816f4252255fd9e4..9fd99b9e40abb4a3e16cac537799c942d0de246f 100644 (file)
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -25,10 +25,26 @@
 #define GPMC_CS_NAND_ADDRESS   0x20
 #define GPMC_CS_NAND_DATA      0x24
 
-#define GPMC_CONFIG            0x50
-#define GPMC_STATUS            0x54
-#define GPMC_CS0_BASE          0x60
-#define GPMC_CS_SIZE           0x30
+/* Control Commands */
+#define GPMC_CONFIG_RDY_BSY    0x00000001
+#define GPMC_CONFIG_DEV_SIZE   0x00000002
+#define GPMC_CONFIG_DEV_TYPE   0x00000003
+#define GPMC_SET_IRQ_STATUS    0x00000004
+#define GPMC_CONFIG_WP         0x00000005
+
+#define GPMC_GET_IRQ_STATUS    0x00000006
+#define GPMC_PREFETCH_FIFO_CNT 0x00000007 /* bytes available in FIFO for r/w */
+#define GPMC_PREFETCH_COUNT    0x00000008 /* remaining bytes to be read/write*/
+#define GPMC_STATUS_BUFFER     0x00000009 /* 1: buffer is available to write */
+
+#define GPMC_NAND_COMMAND      0x0000000a
+#define GPMC_NAND_ADDRESS      0x0000000b
+#define GPMC_NAND_DATA         0x0000000c
+
+/* ECC commands */
+#define GPMC_ECC_READ          0 /* Reset Hardware ECC for read */
+#define GPMC_ECC_WRITE         1 /* Reset Hardware ECC for write */
+#define GPMC_ECC_READSYN       2 /* Reset before syndrom is read back */
 
 #define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)
 #define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 30)
@@ -47,7 +63,6 @@
 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
-#define GPMC_CONFIG1_DEVICETYPE_NAND    GPMC_CONFIG1_DEVICETYPE(2)
 #define GPMC_CONFIG1_MUXADDDATA         (1 << 9)
 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
@@ -56,6 +71,14 @@
 #define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
 #define GPMC_CONFIG7_CSVALID           (1 << 6)
 
+#define GPMC_DEVICETYPE_NOR            0
+#define GPMC_DEVICETYPE_NAND           2
+#define GPMC_CONFIG_WRITEPROTECT       0x00000010
+#define GPMC_STATUS_BUFF_EMPTY         0x00000001
+#define WR_RD_PIN_MONITORING           0x00600000
+#define GPMC_PREFETCH_STATUS_FIFO_CNT(val)     ((val >> 24) & 0x7F)
+#define GPMC_PREFETCH_STATUS_COUNT(val)        (val & 0x00003fff)
+
 /*
  * Note that all values in this struct are in nanoseconds, while
  * the register values are in gpmc_fck cycles.
@@ -108,10 +131,15 @@ extern int gpmc_cs_set_reserved(int cs, int reserved);
 extern int gpmc_cs_reserved(int cs);
 extern int gpmc_prefetch_enable(int cs, int dma_mode,
                                        unsigned int u32_count, int is_write);
-extern void gpmc_prefetch_reset(void);
-extern int gpmc_prefetch_status(void);
+extern int gpmc_prefetch_reset(int cs);
 extern void omap3_gpmc_save_context(void);
 extern void omap3_gpmc_restore_context(void);
 extern void gpmc_init(void);
+extern int gpmc_read_status(int cmd);
+extern int gpmc_cs_configure(int cs, int cmd, int wval);
+extern int gpmc_nand_read(int cs, int cmd);
+extern int gpmc_nand_write(int cs, int cmd, int wval);
 
+int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size);
+int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code);
 #endif

diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index 0752af9d099e017e216887c7f4d67a01d283330d..33c7d41cb6a55b1f166f563f76f79ffd0acf8481 100644 (file)
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -80,6 +80,7 @@ struct iommu_functions {
 
        int (*enable)(struct iommu *obj);
        void (*disable)(struct iommu *obj);
+       void (*set_twl)(struct iommu *obj, bool on);
        u32 (*fault_isr)(struct iommu *obj, u32 *ra);
 
        void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr);
@@ -143,6 +144,7 @@ extern void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
 extern u32 iotlb_cr_to_virt(struct cr_regs *cr);
 
 extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e);
+extern void iommu_set_twl(struct iommu *obj, bool on);
 extern void flush_iotlb_page(struct iommu *obj, u32 da);
 extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end);
 extern void flush_iotlb_all(struct iommu *obj);

diff --git a/arch/arm/plat-omap/include/plat/mux.h b/arch/arm/plat-omap/include/plat/mux.h
index c7472a28ce24d9d48a1c3a637ba7de71e35fd18a..aeba71796ad943b0f412104682cab2a40cabda92 100644 (file)
--- a/arch/arm/plat-omap/include/plat/mux.h
+++ b/arch/arm/plat-omap/include/plat/mux.h
@@ -114,28 +114,11 @@
        PU_PD_REG(NA, 0)                \
 },
 
-#define MUX_CFG_24XX(desc, reg_offset, mode,                   \
-                               pull_en, pull_mode, dbg)        \
-{                                                              \
-       .name           = desc,                                 \
-       .debug          = dbg,                                  \
-       .mux_reg        = reg_offset,                           \
-       .mask           = mode,                                 \
-       .pull_val       = pull_en,                              \
-       .pu_pd_val      = pull_mode,                            \
-},
-
-/* 24xx/34xx mux bit defines */
-#define OMAP2_PULL_ENA         (1 << 3)
-#define OMAP2_PULL_UP          (1 << 4)
-#define OMAP2_ALTELECTRICALSEL (1 << 5)
-
 struct pin_config {
        char                    *name;
        const unsigned int      mux_reg;
        unsigned char           debug;
 
-#if    defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2)
        const unsigned char mask_offset;
        const unsigned char mask;
 
@@ -147,7 +130,6 @@ struct pin_config {
        const char *pu_pd_name;
        const unsigned int pu_pd_reg;
        const unsigned char pu_pd_val;
-#endif
 
 #if    defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
        const char *mux_reg_name;
@@ -191,6 +173,10 @@ enum omap7xx_index {
        SPI_7XX_4,
        SPI_7XX_5,
        SPI_7XX_6,
+
+       /* UART */
+       UART_7XX_1,
+       UART_7XX_2,
 };
 
 enum omap1xxx_index {
@@ -446,208 +432,6 @@ enum omap1xxx_index {
 
 };
 
-enum omap24xx_index {
-       /* 24xx I2C */
-       M19_24XX_I2C1_SCL,
-       L15_24XX_I2C1_SDA,
-       J15_24XX_I2C2_SCL,
-       H19_24XX_I2C2_SDA,
-
-       /* 24xx Menelaus interrupt */
-       W19_24XX_SYS_NIRQ,
-
-       /* 24xx clock */
-       W14_24XX_SYS_CLKOUT,
-
-       /* 24xx GPMC chipselects, wait pin monitoring */
-       E2_GPMC_NCS2,
-       L2_GPMC_NCS7,
-       L3_GPMC_WAIT0,
-       N7_GPMC_WAIT1,
-       M1_GPMC_WAIT2,
-       P1_GPMC_WAIT3,
-
-       /* 242X McBSP */
-       Y15_24XX_MCBSP2_CLKX,
-       R14_24XX_MCBSP2_FSX,
-       W15_24XX_MCBSP2_DR,
-       V15_24XX_MCBSP2_DX,
-
-       /* 24xx GPIO */
-       M21_242X_GPIO11,
-       P21_242X_GPIO12,
-       AA10_242X_GPIO13,
-       AA6_242X_GPIO14,
-       AA4_242X_GPIO15,
-       Y11_242X_GPIO16,
-       AA12_242X_GPIO17,
-       AA8_242X_GPIO58,
-       Y20_24XX_GPIO60,
-       W4__24XX_GPIO74,
-       N15_24XX_GPIO85,
-       M15_24XX_GPIO92,
-       P20_24XX_GPIO93,
-       P18_24XX_GPIO95,
-       M18_24XX_GPIO96,
-       L14_24XX_GPIO97,
-       J15_24XX_GPIO99,
-       V14_24XX_GPIO117,
-       P14_24XX_GPIO125,
-
-       /* 242x DBG GPIO */
-       V4_242X_GPIO49,
-       W2_242X_GPIO50,
-       U4_242X_GPIO51,
-       V3_242X_GPIO52,
-       V2_242X_GPIO53,
-       V6_242X_GPIO53,
-       T4_242X_GPIO54,
-       Y4_242X_GPIO54,
-       T3_242X_GPIO55,
-       U2_242X_GPIO56,
-
-       /* 24xx external DMA requests */
-       AA10_242X_DMAREQ0,
-       AA6_242X_DMAREQ1,
-       E4_242X_DMAREQ2,
-       G4_242X_DMAREQ3,
-       D3_242X_DMAREQ4,
-       E3_242X_DMAREQ5,
-
-       /* UART3 */
-       K15_24XX_UART3_TX,
-       K14_24XX_UART3_RX,
-
-       /* MMC/SDIO */
-       G19_24XX_MMC_CLKO,
-       H18_24XX_MMC_CMD,
-       F20_24XX_MMC_DAT0,
-       H14_24XX_MMC_DAT1,
-       E19_24XX_MMC_DAT2,
-       D19_24XX_MMC_DAT3,
-       F19_24XX_MMC_DAT_DIR0,
-       E20_24XX_MMC_DAT_DIR1,
-       F18_24XX_MMC_DAT_DIR2,
-       E18_24XX_MMC_DAT_DIR3,
-       G18_24XX_MMC_CMD_DIR,
-       H15_24XX_MMC_CLKI,
-
-       /* Full speed USB */
-       J20_24XX_USB0_PUEN,
-       J19_24XX_USB0_VP,
-       K20_24XX_USB0_VM,
-       J18_24XX_USB0_RCV,
-       K19_24XX_USB0_TXEN,
-       J14_24XX_USB0_SE0,
-       K18_24XX_USB0_DAT,
-
-       N14_24XX_USB1_SE0,
-       W12_24XX_USB1_SE0,
-       P15_24XX_USB1_DAT,
-       R13_24XX_USB1_DAT,
-       W20_24XX_USB1_TXEN,
-       P13_24XX_USB1_TXEN,
-       V19_24XX_USB1_RCV,
-       V12_24XX_USB1_RCV,
-
-       AA10_24XX_USB2_SE0,
-       Y11_24XX_USB2_DAT,
-       AA12_24XX_USB2_TXEN,
-       AA6_24XX_USB2_RCV,
-       AA4_24XX_USB2_TLLSE0,
-
-       /* Keypad GPIO*/
-       T19_24XX_KBR0,
-       R19_24XX_KBR1,
-       V18_24XX_KBR2,
-       M21_24XX_KBR3,
-       E5__24XX_KBR4,
-       M18_24XX_KBR5,
-       R20_24XX_KBC0,
-       M14_24XX_KBC1,
-       H19_24XX_KBC2,
-       V17_24XX_KBC3,
-       P21_24XX_KBC4,
-       L14_24XX_KBC5,
-       N19_24XX_KBC6,
-
-       /* 24xx Menelaus Keypad GPIO */
-       B3__24XX_KBR5,
-       AA4_24XX_KBC2,
-       B13_24XX_KBC6,
-
-       /* 2430 USB */
-       AD9_2430_USB0_PUEN,
-       Y11_2430_USB0_VP,
-       AD7_2430_USB0_VM,
-       AE7_2430_USB0_RCV,
-       AD4_2430_USB0_TXEN,
-       AF9_2430_USB0_SE0,
-       AE6_2430_USB0_DAT,
-       AD24_2430_USB1_SE0,
-       AB24_2430_USB1_RCV,
-       Y25_2430_USB1_TXEN,
-       AA26_2430_USB1_DAT,
-
-       /* 2430 HS-USB */
-       AD9_2430_USB0HS_DATA3,
-       Y11_2430_USB0HS_DATA4,
-       AD7_2430_USB0HS_DATA5,
-       AE7_2430_USB0HS_DATA6,
-       AD4_2430_USB0HS_DATA2,
-       AF9_2430_USB0HS_DATA0,
-       AE6_2430_USB0HS_DATA1,
-       AE8_2430_USB0HS_CLK,
-       AD8_2430_USB0HS_DIR,
-       AE5_2430_USB0HS_STP,
-       AE9_2430_USB0HS_NXT,
-       AC7_2430_USB0HS_DATA7,
-
-       /* 2430 McBSP */
-       AD6_2430_MCBSP_CLKS,
-
-       AB2_2430_MCBSP1_CLKR,
-       AD5_2430_MCBSP1_FSR,
-       AA1_2430_MCBSP1_DX,
-       AF3_2430_MCBSP1_DR,
-       AB3_2430_MCBSP1_FSX,
-       Y9_2430_MCBSP1_CLKX,
-
-       AC10_2430_MCBSP2_FSX,
-       AD16_2430_MCBSP2_CLX,
-       AE13_2430_MCBSP2_DX,
-       AD13_2430_MCBSP2_DR,
-       AC10_2430_MCBSP2_FSX_OFF,
-       AD16_2430_MCBSP2_CLX_OFF,
-       AE13_2430_MCBSP2_DX_OFF,
-       AD13_2430_MCBSP2_DR_OFF,
-
-       AC9_2430_MCBSP3_CLKX,
-       AE4_2430_MCBSP3_FSX,
-       AE2_2430_MCBSP3_DR,
-       AF4_2430_MCBSP3_DX,
-
-       N3_2430_MCBSP4_CLKX,
-       AD23_2430_MCBSP4_DR,
-       AB25_2430_MCBSP4_DX,
-       AC25_2430_MCBSP4_FSX,
-
-       AE16_2430_MCBSP5_CLKX,
-       AF12_2430_MCBSP5_FSX,
-       K7_2430_MCBSP5_DX,
-       M1_2430_MCBSP5_DR,
-
-       /* 2430 McSPI*/
-       Y18_2430_MCSPI1_CLK,
-       AD15_2430_MCSPI1_SIMO,
-       AE17_2430_MCSPI1_SOMI,
-       U1_2430_MCSPI1_CS0,
-
-       /* Touchscreen GPIO */
-       AF19_2430_GPIO_85,
-
-};
-
 struct omap_mux_cfg {
        struct pin_config       *pins;
        unsigned long           size;

diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
index f8efd5466b1d07f61e08c7539e0e1e19db2f8ed4..6562cd082bb1b461eff3abbcfc770c9fcb93d845 100644 (file)
--- a/arch/arm/plat-omap/include/plat/nand.h
+++ b/arch/arm/plat-omap/include/plat/nand.h
@@ -21,13 +21,11 @@ struct omap_nand_platform_data {
        int                     (*dev_ready)(struct omap_nand_platform_data *);
        int                     dma_channel;
        unsigned long           phys_base;
-       void __iomem            *gpmc_cs_baseaddr;
-       void __iomem            *gpmc_baseaddr;
        int                     devsize;
 };
 
-/* size (4 KiB) for IO mapping */
-#define        NAND_IO_SIZE    SZ_4K
+/* minimum size for IO mapping */
+#define        NAND_IO_SIZE    4
 
 #if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
 extern int gpmc_nand_init(struct omap_nand_platform_data *d);

diff --git a/arch/arm/plat-omap/include/plat/omap-pm.h b/arch/arm/plat-omap/include/plat/omap-pm.h
index 3ee41d7114929d771cadbb9f02191fd16c5b5abe..728fbb9dd549ac4bf987b2dfc2144371da184718 100644 (file)
--- a/arch/arm/plat-omap/include/plat/omap-pm.h
+++ b/arch/arm/plat-omap/include/plat/omap-pm.h
@@ -1,8 +1,8 @@
 /*
  * omap-pm.h - OMAP power management interface
  *
- * Copyright (C) 2008-2009 Texas Instruments, Inc.
- * Copyright (C) 2008-2009 Nokia Corporation
+ * Copyright (C) 2008-2010 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
  * Paul Walmsley
  *
  * Interface developed by (in alphabetical order): Karthik Dasu, Jouni
@@ -16,6 +16,7 @@
 
 #include <linux/device.h>
 #include <linux/cpufreq.h>
+#include <linux/clk.h>
 
 #include "powerdomain.h"
 
@@ -89,7 +90,7 @@ void omap_pm_if_exit(void);
  * @t: maximum MPU wakeup latency in microseconds
  *
  * Request that the maximum interrupt latency for the MPU to be no
- * greater than 't' microseconds. "Interrupt latency" in this case is
+ * greater than @t microseconds. "Interrupt latency" in this case is
  * defined as the elapsed time from the occurrence of a hardware or
  * timer interrupt to the time when the device driver's interrupt
  * service routine has been entered by the MPU.
@@ -105,15 +106,19 @@ void omap_pm_if_exit(void);
  * elapsed from when a device driver enables a hardware device with
  * clk_enable(), to when the device is ready for register access or
  * other use.  To control this device wakeup latency, use
- * set_max_dev_wakeup_lat()
+ * omap_pm_set_max_dev_wakeup_lat()
  *
- * Multiple calls to set_max_mpu_wakeup_lat() will replace the
+ * Multiple calls to omap_pm_set_max_mpu_wakeup_lat() will replace the
  * previous t value.  To remove the latency target for the MPU, call
  * with t = -1.
  *
- * No return value.
+ * XXX This constraint will be deprecated soon in favor of the more
+ * general omap_pm_set_max_dev_wakeup_lat()
+ *
+ * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
+ * is not satisfiable, or 0 upon success.
  */
-void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t);
+int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t);
 
 
 /**
@@ -123,8 +128,8 @@ void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t);
  * @r: minimum throughput (in KiB/s)
  *
  * Request that the minimum data throughput on the OCP interconnect
- * attached to device 'dev' interconnect agent 'tbus_id' be no less
- * than 'r' KiB/s.
+ * attached to device @dev interconnect agent @tbus_id be no less
+ * than @r KiB/s.
  *
  * It is expected that the OMAP PM or bus code will use this
  * information to set the interconnect clock to run at the lowest
@@ -138,40 +143,44 @@ void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t);
  * code will also need to add an minimum L3 interconnect speed
  * constraint,
  *
- * Multiple calls to set_min_bus_tput() will replace the previous rate
- * value for this device.  To remove the interconnect throughput
- * restriction for this device, call with r = 0.
+ * Multiple calls to omap_pm_set_min_bus_tput() will replace the
+ * previous rate value for this device.  To remove the interconnect
+ * throughput restriction for this device, call with r = 0.
  *
- * No return value.
+ * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
+ * is not satisfiable, or 0 upon success.
  */
-void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r);
+int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r);
 
 
 /**
  * omap_pm_set_max_dev_wakeup_lat - set the maximum device enable latency
- * @dev: struct device *
+ * @req_dev: struct device * requesting the constraint, or NULL if none
+ * @dev: struct device * to set the constraint one
  * @t: maximum device wakeup latency in microseconds
  *
- * Request that the maximum amount of time necessary for a device to
- * become accessible after its clocks are enabled should be no greater
- * than 't' microseconds.  Specifically, this represents the time from
- * when a device driver enables device clocks with clk_enable(), to
- * when the register reads and writes on the device will succeed.
- * This function should be called before clk_disable() is called,
- * since the power state transition decision may be made during
- * clk_disable().
+ * Request that the maximum amount of time necessary for a device @dev
+ * to become accessible after its clocks are enabled should be no
+ * greater than @t microseconds.  Specifically, this represents the
+ * time from when a device driver enables device clocks with
+ * clk_enable(), to when the register reads and writes on the device
+ * will succeed.  This function should be called before clk_disable()
+ * is called, since the power state transition decision may be made
+ * during clk_disable().
  *
  * It is intended that underlying PM code will use this information to
  * determine what power state to put the powerdomain enclosing this
  * device into.
  *
- * Multiple calls to set_max_dev_wakeup_lat() will replace the
- * previous wakeup latency values for this device.  To remove the wakeup
- * latency restriction for this device, call with t = -1.
+ * Multiple calls to omap_pm_set_max_dev_wakeup_lat() will replace the
+ * previous wakeup latency values for this device.  To remove the
+ * wakeup latency restriction for this device, call with t = -1.
  *
- * No return value.
+ * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
+ * is not satisfiable, or 0 upon success.
  */
-void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t);
+int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev,
+                                  long t);
 
 
 /**
@@ -198,10 +207,71 @@ void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t);
  * value for this device.  To remove the maximum DMA latency for this
  * device, call with t = -1.
  *
- * No return value.
+ * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
+ * is not satisfiable, or 0 upon success.
  */
-void omap_pm_set_max_sdma_lat(struct device *dev, long t);
+int omap_pm_set_max_sdma_lat(struct device *dev, long t);
+
 
+/**
+ * omap_pm_set_min_clk_rate - set minimum clock rate requested by @dev
+ * @dev: struct device * requesting the constraint
+ * @clk: struct clk * to set the minimum rate constraint on
+ * @r: minimum rate in Hz
+ *
+ * Request that the minimum clock rate on the device @dev's clk @clk
+ * be no less than @r Hz.
+ *
+ * It is expected that the OMAP PM code will use this information to
+ * find an OPP or clock setting that will satisfy this clock rate
+ * constraint, along with any other applicable system constraints on
+ * the clock rate or corresponding voltage, etc.
+ *
+ * omap_pm_set_min_clk_rate() differs from the clock code's
+ * clk_set_rate() in that it considers other constraints before taking
+ * any hardware action, and may change a system OPP rather than just a
+ * clock rate.  clk_set_rate() is intended to be a low-level
+ * interface.
+ *
+ * omap_pm_set_min_clk_rate() is easily open to abuse.  A better API
+ * would be something like "omap_pm_set_min_dev_performance()";
+ * however, there is no easily-generalizable concept of performance
+ * that applies to all devices.  Only a device (and possibly the
+ * device subsystem) has both the subsystem-specific knowledge, and
+ * the hardware IP block-specific knowledge, to translate a constraint
+ * on "touchscreen sampling accuracy" or "number of pixels or polygons
+ * rendered per second" to a clock rate.  This translation can be
+ * dependent on the hardware IP block's revision, or firmware version,
+ * and the driver is the only code on the system that has this
+ * information and can know how to translate that into a clock rate.
+ *
+ * The intended use-case for this function is for userspace or other
+ * kernel code to communicate a particular performance requirement to
+ * a subsystem; then for the subsystem to communicate that requirement
+ * to something that is meaningful to the device driver; then for the
+ * device driver to convert that requirement to a clock rate, and to
+ * then call omap_pm_set_min_clk_rate().
+ *
+ * Users of this function (such as device drivers) should not simply
+ * call this function with some high clock rate to ensure "high
+ * performance."  Rather, the device driver should take a performance
+ * constraint from its subsystem, such as "render at least X polygons
+ * per second," and use some formula or table to convert that into a
+ * clock rate constraint given the hardware type and hardware
+ * revision.  Device drivers or subsystems should not assume that they
+ * know how to make a power/performance tradeoff - some device use
+ * cases may tolerate a lower-fidelity device function for lower power
+ * consumption; others may demand a higher-fidelity device function,
+ * no matter what the power consumption.
+ *
+ * Multiple calls to omap_pm_set_min_clk_rate() will replace the
+ * previous rate value for the device @dev.  To remove the minimum clock
+ * rate constraint for the device, call with r = 0.
+ *
+ * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
+ * is not satisfiable, or 0 upon success.
+ */
+int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r);
 
 /*
  * DSP Bridge-specific constraints

diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index 3694b622c4acd4cf6b01bb8f19298fb6e968e1a8..25cd9ac3b0958eb1a61d166b485731be2a480dab 100644 (file)
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -101,6 +101,8 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
 int omap_device_register(struct omap_device *od);
 int omap_early_device_register(struct omap_device *od);
 
+void __iomem *omap_device_get_rt_va(struct omap_device *od);
+
 /* OMAP PM interface */
 int omap_device_align_pm_lat(struct platform_device *pdev,
                             u32 new_wakeup_lat_limit);

diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 0eccc09ac4a9f634ebc782b88b979548d6da3c38..a4e508dfaba2716a46a9d20d1ac59337dce1fae2 100644 (file)
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -1,7 +1,7 @@
 /*
  * omap_hwmod macros, structures
  *
- * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2009-2010 Nokia Corporation
  * Paul Walmsley
  *
  * Created in collaboration with (alphabetical order): Benoît Cousson,
@@ -419,7 +419,7 @@ struct omap_hwmod_class {
  * @slaves: ptr to array of OCP ifs that this hwmod can respond on
  * @dev_attr: arbitrary device attributes that can be passed to the driver
  * @_sysc_cache: internal-use hwmod flags
- * @_rt_va: cached register target start address (internal use)
+ * @_mpu_rt_va: cached register target start address (internal use)
  * @_mpu_port_index: cached MPU register target slave ID (internal use)
  * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6)
  * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift
@@ -460,7 +460,7 @@ struct omap_hwmod {
        struct omap_hwmod_ocp_if        **slaves;  /* connect to *_TA */
        void                            *dev_attr;
        u32                             _sysc_cache;
-       void __iomem                    *_rt_va;
+       void __iomem                    *_mpu_rt_va;
        struct list_head                node;
        u16                             flags;
        u8                              _mpu_port_index;
@@ -482,11 +482,14 @@ int omap_hwmod_init(struct omap_hwmod **ohs);
 int omap_hwmod_register(struct omap_hwmod *oh);
 int omap_hwmod_unregister(struct omap_hwmod *oh);
 struct omap_hwmod *omap_hwmod_lookup(const char *name);
-int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh));
-int omap_hwmod_late_init(void);
+int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
+                       void *data);
+int omap_hwmod_late_init(u8 skip_setup_idle);
 
 int omap_hwmod_enable(struct omap_hwmod *oh);
+int _omap_hwmod_enable(struct omap_hwmod *oh);
 int omap_hwmod_idle(struct omap_hwmod *oh);
+int _omap_hwmod_idle(struct omap_hwmod *oh);
 int omap_hwmod_shutdown(struct omap_hwmod *oh);
 
 int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
@@ -504,6 +507,7 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh);
 int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
 
 struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
+void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh);
 
 int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
                                 struct omap_hwmod *init_oh);

diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
index 8983d54c4fd2e95a8a30c2a5920376cb07893eb6..6a3ff65c030350e121649f5bed7cb9d9f8d76724 100644 (file)
--- a/arch/arm/plat-omap/include/plat/smp.h
+++ b/arch/arm/plat-omap/include/plat/smp.h
@@ -30,6 +30,7 @@
 extern void omap_secondary_startup(void);
 extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
 extern void omap_auxcoreboot_addr(u32 cpu_addr);
+extern u32 omap_read_auxcoreboot0(void);
 
 /*
  * We use Soft IRQ1 as the IPI

diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index bbedd71943f61caf9d20ca8e4461f721da4410ab..ddf723be48dc997c867226ec5838dd27fe55db05 100644 (file)
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -25,6 +25,8 @@
 
 #include <plat/serial.h>
 
+#define MDR1_MODE_MASK                 0x07
+
 static volatile u8 *uart_base;
 static int uart_shift;
 
@@ -42,6 +44,10 @@ static void putc(int c)
        if (!uart_base)
                return;
 
+       /* Check for UART 16x mode */
+       if ((uart_base[UART_OMAP_MDR1 << uart_shift] & MDR1_MODE_MASK) != 0)
+               return;
+
        while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE))
                barrier();
        uart_base[UART_TX << uart_shift] = c;

diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 98eef5360e6d7cbfebfdcb199ab4565e80fb81b5..2a9427c8cc485430a28b4184afc4b20fd654dc7c 100644 (file)
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -81,7 +81,34 @@ extern void usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata);
 
 #endif
 
-void omap_usb_init(struct omap_usb_config *pdata);
+
+/*
+ * FIXME correct answer depends on hmc_mode,
+ * as does (on omap1) any nonzero value for config->otg port number
+ */
+#ifdef CONFIG_USB_GADGET_OMAP
+#define        is_usb0_device(config)  1
+#else
+#define        is_usb0_device(config)  0
+#endif
+
+void omap_otg_init(struct omap_usb_config *config);
+
+#if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE)
+void omap1_usb_init(struct omap_usb_config *pdata);
+#else
+static inline void omap1_usb_init(struct omap_usb_config *pdata)
+{
+}
+#endif
+
+#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE)
+void omap2_usbfs_init(struct omap_usb_config *pdata);
+#else
+static inline omap2_usbfs_init(struct omap_usb_config *pdata)
+{
+}
+#endif
 
 /*-------------------------------------------------------------------------*/
 
@@ -192,4 +219,24 @@ void omap_usb_init(struct omap_usb_config *pdata);
 #      define  USB0PUENACTLOI          (1 << 16)
 #      define  USBSTANDBYCTRL          (1 << 15)
 
+#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB)
+u32 omap1_usb0_init(unsigned nwires, unsigned is_device);
+u32 omap1_usb1_init(unsigned nwires);
+u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup);
+#else
+static inline u32 omap1_usb0_init(unsigned nwires, unsigned is_device)
+{
+       return 0;
+}
+static inline u32 omap1_usb1_init(unsigned nwires)
+{
+       return 0;
+
+}
+static inline u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
+{
+       return 0;
+}
+#endif
+
 #endif /* __ASM_ARCH_OMAP_USB_H */

diff --git a/arch/arm/plat-omap/include/plat/vram.h b/arch/arm/plat-omap/include/plat/vram.h
index edd4987758a64db91d606a26806593ae2a48d698..0aa4ecd12c7d5768f74efa2d4e7977f729e2338d 100644 (file)
--- a/arch/arm/plat-omap/include/plat/vram.h
+++ b/arch/arm/plat-omap/include/plat/vram.h
@@ -38,7 +38,7 @@ extern void omap_vram_get_info(unsigned long *vram, unsigned long *free_vram,
 extern void omap_vram_set_sdram_vram(u32 size, u32 start);
 extern void omap_vram_set_sram_vram(u32 size, u32 start);
 
-extern void omap_vram_reserve_sdram(void);
+extern void omap_vram_reserve_sdram_memblock(void);
 extern unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
                                            unsigned long sram_vstart,
                                            unsigned long sram_size,
@@ -48,7 +48,7 @@ extern unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
 static inline void omap_vram_set_sdram_vram(u32 size, u32 start) { }
 static inline void omap_vram_set_sram_vram(u32 size, u32 start) { }
 
-static inline void omap_vram_reserve_sdram(void) { }
+static inline void omap_vram_reserve_sdram_memblock(void) { }
 static inline unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
                                            unsigned long sram_vstart,
                                            unsigned long sram_size,

diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index bc094dbacee6e2ed04c20ae7367c65179ed59b52..a202a2ce6e3d0018ee3022ead0ba835527e3a4b0 100644 (file)
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -370,6 +370,23 @@ void flush_iotlb_all(struct iommu *obj)
 }
 EXPORT_SYMBOL_GPL(flush_iotlb_all);
 
+/**
+ * iommu_set_twl - enable/disable table walking logic
+ * @obj:       target iommu
+ * @on:                enable/disable
+ *
+ * Function used to enable/disable TWL. If one wants to work
+ * exclusively with locked TLB entries and receive notifications
+ * for TLB miss then call this function to disable TWL.
+ */
+void iommu_set_twl(struct iommu *obj, bool on)
+{
+       clk_enable(obj->clk);
+       arch_iommu->set_twl(obj, on);
+       clk_disable(obj->clk);
+}
+EXPORT_SYMBOL_GPL(iommu_set_twl);
+
 #if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE)
 
 ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t bytes)
@@ -653,7 +670,7 @@ void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd, u32 **ppte)
        if (!*iopgd)
                goto out;
 
-       if (*iopgd & IOPGD_TABLE)
+       if (iopgd_is_table(*iopgd))
                iopte = iopte_offset(iopgd, da);
 out:
        *ppgd = iopgd;
@@ -670,7 +687,7 @@ static size_t iopgtable_clear_entry_core(struct iommu *obj, u32 da)
        if (!*iopgd)
                return 0;
 
-       if (*iopgd & IOPGD_TABLE) {
+       if (iopgd_is_table(*iopgd)) {
                int i;
                u32 *iopte = iopte_offset(iopgd, da);
 
@@ -745,7 +762,7 @@ static void iopgtable_clear_entry_all(struct iommu *obj)
                if (!*iopgd)
                        continue;
 
-               if (*iopgd & IOPGD_TABLE)
+               if (iopgd_is_table(*iopgd))
                        iopte_free(iopte_offset(iopgd, 0));
 
                *iopgd = 0;
@@ -783,9 +800,11 @@ static irqreturn_t iommu_fault_handler(int irq, void *data)
        if (!stat)
                return IRQ_HANDLED;
 
+       iommu_disable(obj);
+
        iopgd = iopgd_offset(obj, da);
 
-       if (!(*iopgd & IOPGD_TABLE)) {
+       if (!iopgd_is_table(*iopgd)) {
                dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x\n", __func__,
                        da, iopgd, *iopgd);
                return IRQ_NONE;

diff --git a/arch/arm/plat-omap/iopgtable.h b/arch/arm/plat-omap/iopgtable.h
index ab23b6a140fd17502f9be35c21ee6bbc721fcc63..c3e93bb0911f1f405abc33d3eb85be7736b9e1a2 100644 (file)
--- a/arch/arm/plat-omap/iopgtable.h
+++ b/arch/arm/plat-omap/iopgtable.h
@@ -63,6 +63,8 @@
 #define IOPGD_SECTION          (2 << 0)
 #define IOPGD_SUPER            (1 << 18 | 2 << 0)
 
+#define iopgd_is_table(x)      (((x) & 3) == IOPGD_TABLE)
+
 #define IOPTE_SMALL            (2 << 0)
 #define IOPTE_LARGE            (1 << 0)
 
@@ -70,12 +72,12 @@
 #define iopgd_index(da)                (((da) >> IOPGD_SHIFT) & (PTRS_PER_IOPGD - 1))
 #define iopgd_offset(obj, da)  ((obj)->iopgd + iopgd_index(da))
 
-#define iopte_paddr(iopgd)     (*iopgd & ~((1 << 10) - 1))
-#define iopte_vaddr(iopgd)     ((u32 *)phys_to_virt(iopte_paddr(iopgd)))
+#define iopgd_page_paddr(iopgd)        (*iopgd & ~((1 << 10) - 1))
+#define iopgd_page_vaddr(iopgd)        ((u32 *)phys_to_virt(iopgd_page_paddr(iopgd)))
 
 /* to find an entry in the second-level page table. */
 #define iopte_index(da)                (((da) >> IOPTE_SHIFT) & (PTRS_PER_IOPTE - 1))
-#define iopte_offset(iopgd, da)        (iopte_vaddr(iopgd) + iopte_index(da))
+#define iopte_offset(iopgd, da)        (iopgd_page_vaddr(iopgd) + iopte_index(da))
 
 static inline u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa,
                                   u32 flags)

diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
index 06703635ace15672b7d82f3fad9e4a032dc2afaa..0d4aa0d5876c0360d51b76ed7f827c2339a8fd4f 100644 (file)
--- a/arch/arm/plat-omap/mux.c
+++ b/arch/arm/plat-omap/mux.c
@@ -54,7 +54,7 @@ int __init_or_module omap_cfg_reg(const unsigned long index)
 {
        struct pin_config *reg;
 
-       if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+       if (!cpu_class_is_omap1()) {
                printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n",
                                index);
                WARN_ON(1);

diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c
index 186bca82cfab76dbe64cb8ebb883efedbee18ba2..e129ce80c53b515b934d940bfc5fe09163ddbbdd 100644 (file)
--- a/arch/arm/plat-omap/omap-pm-noop.c
+++ b/arch/arm/plat-omap/omap-pm-noop.c
@@ -34,11 +34,11 @@ struct omap_opp *l3_opps;
  * Device-driver-originated constraints (via board-*.c files)
  */
 
-void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t)
+int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t)
 {
        if (!dev || t < -1) {
-               WARN_ON(1);
-               return;
+               WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
+               return -EINVAL;
        };
 
        if (t == -1)
@@ -58,14 +58,16 @@ void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t)
         *
         * TI CDP code can call constraint_set here.
         */
+
+       return 0;
 }
 
-void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r)
+int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r)
 {
        if (!dev || (agent_id != OCP_INITIATOR_AGENT &&
            agent_id != OCP_TARGET_AGENT)) {
-               WARN_ON(1);
-               return;
+               WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
+               return -EINVAL;
        };
 
        if (r == 0)
@@ -83,13 +85,16 @@ void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r)
         *
         * TI CDP code can call constraint_set here on the VDD2 OPP.
         */
+
+       return 0;
 }
 
-void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t)
+int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev,
+                                  long t)
 {
-       if (!dev || t < -1) {
-               WARN_ON(1);
-               return;
+       if (!req_dev || !dev || t < -1) {
+               WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
+               return -EINVAL;
        };
 
        if (t == -1)
@@ -111,13 +116,15 @@ void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t)
         *
         * TI CDP code can call constraint_set here.
         */
+
+       return 0;
 }
 
-void omap_pm_set_max_sdma_lat(struct device *dev, long t)
+int omap_pm_set_max_sdma_lat(struct device *dev, long t)
 {
        if (!dev || t < -1) {
-               WARN_ON(1);
-               return;
+               WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
+               return -EINVAL;
        };
 
        if (t == -1)
@@ -139,8 +146,36 @@ void omap_pm_set_max_sdma_lat(struct device *dev, long t)
         * TI CDP code can call constraint_set here.
         */
 
+       return 0;
 }
 
+int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r)
+{
+       if (!dev || !c || r < 0) {
+               WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
+               return -EINVAL;
+       }
+
+       if (r == 0)
+               pr_debug("OMAP PM: remove min clk rate constraint: "
+                        "dev %s\n", dev_name(dev));
+       else
+               pr_debug("OMAP PM: add min clk rate constraint: "
+                        "dev %s, rate = %ld Hz\n", dev_name(dev), r);
+
+       /*
+        * Code in a real implementation should keep track of these
+        * constraints on the clock, and determine the highest minimum
+        * clock rate.  It should iterate over each OPP and determine
+        * whether the OPP will result in a clock rate that would
+        * satisfy this constraint (and any other PM constraint in effect
+        * at that time).  Once it finds the lowest-voltage OPP that
+        * meets those conditions, it should switch to it, or return
+        * an error if the code is not capable of doing so.
+        */
+
+       return 0;
+}
 
 /*
  * DSP Bridge-specific constraints

diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index f899603051ac628b83cebd32badac5cf4c55ddad..d2b160942ccc5ec0a2e0fb2efe3e7e288da9cb12 100644 (file)
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -1,7 +1,7 @@
 /*
  * omap_device implementation
  *
- * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2009-2010 Nokia Corporation
  * Paul Walmsley, Kevin Hilman
  *
  * Developed in collaboration with (alphabetical order): Benoit
@@ -90,8 +90,11 @@
 #define USE_WAKEUP_LAT                 0
 #define IGNORE_WAKEUP_LAT              1
 
-
-#define OMAP_DEVICE_MAGIC 0xf00dcafe
+/*
+ * OMAP_DEVICE_MAGIC: used to determine whether a struct omap_device
+ * obtained via container_of() is in fact a struct omap_device
+ */
+#define OMAP_DEVICE_MAGIC               0xf00dcafe
 
 /* Private functions */
 
@@ -359,7 +362,7 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
        struct omap_device *od;
        char *pdev_name2;
        struct resource *res = NULL;
-       int res_count;
+       int i, res_count;
        struct omap_hwmod **hwmods;
 
        if (!ohs || oh_cnt == 0 || !pdev_name)
@@ -404,7 +407,9 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
        od->pdev.num_resources = res_count;
        od->pdev.resource = res;
 
-       platform_device_add_data(&od->pdev, pdata, pdata_len);
+       ret = platform_device_add_data(&od->pdev, pdata, pdata_len);
+       if (ret)
+               goto odbs_exit4;
 
        od->pm_lats = pm_lats;
        od->pm_lats_cnt = pm_lats_cnt;
@@ -416,6 +421,9 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
        else
                ret = omap_device_register(od);
 
+       for (i = 0; i < oh_cnt; i++)
+               hwmods[i]->od = od;
+
        if (ret)
                goto odbs_exit4;
 
@@ -652,6 +660,25 @@ struct powerdomain *omap_device_get_pwrdm(struct omap_device *od)
        return omap_hwmod_get_pwrdm(od->hwmods[0]);
 }
 
+/**
+ * omap_device_get_mpu_rt_va - return the MPU's virtual addr for the hwmod base
+ * @od: struct omap_device *
+ *
+ * Return the MPU's virtual address for the base of the hwmod, from
+ * the ioremap() that the hwmod code does.  Only valid if there is one
+ * hwmod associated with this device.  Returns NULL if there are zero
+ * or more than one hwmods associated with this omap_device;
+ * otherwise, passes along the return value from
+ * omap_hwmod_get_mpu_rt_va().
+ */
+void __iomem *omap_device_get_rt_va(struct omap_device *od)
+{
+       if (od->hwmods_cnt != 1)
+               return NULL;
+
+       return omap_hwmod_get_mpu_rt_va(od->hwmods[0]);
+}
+
 /*
  * Public functions intended for use in omap_device_pm_latency
  * .activate_func and .deactivate_func function pointers

diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index d3bf17cd36f37f997c1c3dbe879905f70bdf5289..f3570884883e574df243384475c2fd66b68906ee 100644 (file)
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -22,524 +22,13 @@
 
 #include <linux/module.h>
 #include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/errno.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/usb/otg.h>
 #include <linux/io.h>
 
-#include <asm/irq.h>
-#include <asm/system.h>
-#include <mach/hardware.h>
-
-#include <plat/control.h>
-#include <plat/mux.h>
 #include <plat/usb.h>
 #include <plat/board.h>
 
-#ifdef CONFIG_ARCH_OMAP1
-
-#define INT_USB_IRQ_GEN                IH2_BASE + 20
-#define INT_USB_IRQ_NISO       IH2_BASE + 30
-#define INT_USB_IRQ_ISO                IH2_BASE + 29
-#define INT_USB_IRQ_HGEN       INT_USB_HHC_1
-#define INT_USB_IRQ_OTG                IH2_BASE + 8
-
-#else
-
-#define INT_USB_IRQ_GEN                INT_24XX_USB_IRQ_GEN
-#define INT_USB_IRQ_NISO       INT_24XX_USB_IRQ_NISO
-#define INT_USB_IRQ_ISO                INT_24XX_USB_IRQ_ISO
-#define INT_USB_IRQ_HGEN       INT_24XX_USB_IRQ_HGEN
-#define INT_USB_IRQ_OTG                INT_24XX_USB_IRQ_OTG
-
-#endif
-
-
-/* These routines should handle the standard chip-specific modes
- * for usb0/1/2 ports, covering basic mux and transceiver setup.
- *
- * Some board-*.c files will need to set up additional mux options,
- * like for suspend handling, vbus sensing, GPIOs, and the D+ pullup.
- */
-
-/* TESTED ON:
- *  - 1611B H2 (with usb1 mini-AB) using standard Mini-B or OTG cables
- *  - 5912 OSK OHCI (with usb0 standard-A), standard A-to-B cables
- *  - 5912 OSK UDC, with *nonstandard* A-to-A cable
- *  - 1510 Innovator UDC with bundled usb0 cable
- *  - 1510 Innovator OHCI with bundled usb1/usb2 cable
- *  - 1510 Innovator OHCI with custom usb0 cable, feeding 5V VBUS
- *  - 1710 custom development board using alternate pin group
- *  - 1710 H3 (with usb1 mini-AB) using standard Mini-B or OTG cables
- */
-
-/*-------------------------------------------------------------------------*/
-
-#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP15XX)
-
-static void omap2_usb_devconf_clear(u8 port, u32 mask)
-{
-       u32 r;
-
-       r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-       r &= ~USBTXWRMODEI(port, mask);
-       omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
-}
-
-static void omap2_usb_devconf_set(u8 port, u32 mask)
-{
-       u32 r;
-
-       r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-       r |= USBTXWRMODEI(port, mask);
-       omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
-}
-
-static void omap2_usb2_disable_5pinbitll(void)
-{
-       u32 r;
-
-       r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-       r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI);
-       omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
-}
-
-static void omap2_usb2_enable_5pinunitll(void)
-{
-       u32 r;
-
-       r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-       r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI;
-       omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
-}
-
-static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
-{
-       u32     syscon1 = 0;
-
-       if (cpu_is_omap24xx())
-               omap2_usb_devconf_clear(0, USB_BIDIR_TLL);
-
-       if (nwires == 0) {
-               if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
-                       u32 l;
-
-                       /* pulldown D+/D- */
-                       l = omap_readl(USB_TRANSCEIVER_CTRL);
-                       l &= ~(3 << 1);
-                       omap_writel(l, USB_TRANSCEIVER_CTRL);
-               }
-               return 0;
-       }
-
-       if (is_device) {
-               if (cpu_is_omap24xx())
-                       omap_cfg_reg(J20_24XX_USB0_PUEN);
-               else if (cpu_is_omap7xx()) {
-                       omap_cfg_reg(AA17_7XX_USB_DM);
-                       omap_cfg_reg(W16_7XX_USB_PU_EN);
-                       omap_cfg_reg(W17_7XX_USB_VBUSI);
-                       omap_cfg_reg(W18_7XX_USB_DMCK_OUT);
-                       omap_cfg_reg(W19_7XX_USB_DCRST);
-               } else
-                       omap_cfg_reg(W4_USB_PUEN);
-       }
-
-       /* internal transceiver (unavailable on 17xx, 24xx) */
-       if (!cpu_class_is_omap2() && nwires == 2) {
-               u32 l;
-
-               // omap_cfg_reg(P9_USB_DP);
-               // omap_cfg_reg(R8_USB_DM);
-
-               if (cpu_is_omap15xx()) {
-                       /* This works on 1510-Innovator */
-                       return 0;
-               }
-
-               /* NOTES:
-                *  - peripheral should configure VBUS detection!
-                *  - only peripherals may use the internal D+/D- pulldowns
-                *  - OTG support on this port not yet written
-                */
-
-               /* Don't do this for omap7xx -- it causes USB to not work correctly */
-               if (!cpu_is_omap7xx()) {
-                       l = omap_readl(USB_TRANSCEIVER_CTRL);
-                       l &= ~(7 << 4);
-                       if (!is_device)
-                               l |= (3 << 1);
-                       omap_writel(l, USB_TRANSCEIVER_CTRL);
-               }
-
-               return 3 << 16;
-       }
-
-       /* alternate pin config, external transceiver */
-       if (cpu_is_omap15xx()) {
-               printk(KERN_ERR "no usb0 alt pin config on 15xx\n");
-               return 0;
-       }
-
-       if (cpu_is_omap24xx()) {
-               omap_cfg_reg(K18_24XX_USB0_DAT);
-               omap_cfg_reg(K19_24XX_USB0_TXEN);
-               omap_cfg_reg(J14_24XX_USB0_SE0);
-               if (nwires != 3)
-                       omap_cfg_reg(J18_24XX_USB0_RCV);
-       } else {
-               omap_cfg_reg(V6_USB0_TXD);
-               omap_cfg_reg(W9_USB0_TXEN);
-               omap_cfg_reg(W5_USB0_SE0);
-               if (nwires != 3)
-                       omap_cfg_reg(Y5_USB0_RCV);
-       }
-
-       /* NOTE:  SPEED and SUSP aren't configured here.  OTG hosts
-        * may be able to use I2C requests to set those bits along
-        * with VBUS switching and overcurrent detection.
-        */
-
-       if (cpu_class_is_omap1() && nwires != 6) {
-               u32 l;
-
-               l = omap_readl(USB_TRANSCEIVER_CTRL);
-               l &= ~CONF_USB2_UNI_R;
-               omap_writel(l, USB_TRANSCEIVER_CTRL);
-       }
-
-       switch (nwires) {
-       case 3:
-               syscon1 = 2;
-               if (cpu_is_omap24xx())
-                       omap2_usb_devconf_set(0, USB_BIDIR);
-               break;
-       case 4:
-               syscon1 = 1;
-               if (cpu_is_omap24xx())
-                       omap2_usb_devconf_set(0, USB_BIDIR);
-               break;
-       case 6:
-               syscon1 = 3;
-               if (cpu_is_omap24xx()) {
-                       omap_cfg_reg(J19_24XX_USB0_VP);
-                       omap_cfg_reg(K20_24XX_USB0_VM);
-                       omap2_usb_devconf_set(0, USB_UNIDIR);
-               } else {
-                       u32 l;
-
-                       omap_cfg_reg(AA9_USB0_VP);
-                       omap_cfg_reg(R9_USB0_VM);
-                       l = omap_readl(USB_TRANSCEIVER_CTRL);
-                       l |= CONF_USB2_UNI_R;
-                       omap_writel(l, USB_TRANSCEIVER_CTRL);
-               }
-               break;
-       default:
-               printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
-                       0, nwires);
-       }
-       return syscon1 << 16;
-}
-
-static u32 __init omap_usb1_init(unsigned nwires)
-{
-       u32     syscon1 = 0;
-
-       if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) {
-               u32 l;
-
-               l = omap_readl(USB_TRANSCEIVER_CTRL);
-               l &= ~CONF_USB1_UNI_R;
-               omap_writel(l, USB_TRANSCEIVER_CTRL);
-       }
-       if (cpu_is_omap24xx())
-               omap2_usb_devconf_clear(1, USB_BIDIR_TLL);
-
-       if (nwires == 0)
-               return 0;
-
-       /* external transceiver */
-       if (cpu_class_is_omap1()) {
-               omap_cfg_reg(USB1_TXD);
-               omap_cfg_reg(USB1_TXEN);
-               if (nwires != 3)
-                       omap_cfg_reg(USB1_RCV);
-       }
-
-       if (cpu_is_omap15xx()) {
-               omap_cfg_reg(USB1_SEO);
-               omap_cfg_reg(USB1_SPEED);
-               // SUSP
-       } else if (cpu_is_omap1610() || cpu_is_omap5912()) {
-               omap_cfg_reg(W13_1610_USB1_SE0);
-               omap_cfg_reg(R13_1610_USB1_SPEED);
-               // SUSP
-       } else if (cpu_is_omap1710()) {
-               omap_cfg_reg(R13_1710_USB1_SE0);
-               // SUSP
-       } else if (cpu_is_omap24xx()) {
-               /* NOTE:  board-specific code must set up pin muxing for usb1,
-                * since each signal could come out on either of two balls.
-                */
-       } else {
-               pr_debug("usb%d cpu unrecognized\n", 1);
-               return 0;
-       }
-
-       switch (nwires) {
-       case 2:
-               if (!cpu_is_omap24xx())
-                       goto bad;
-               /* NOTE: board-specific code must override this setting if
-                * this TLL link is not using DP/DM
-                */
-               syscon1 = 1;
-               omap2_usb_devconf_set(1, USB_BIDIR_TLL);
-               break;
-       case 3:
-               syscon1 = 2;
-               if (cpu_is_omap24xx())
-                       omap2_usb_devconf_set(1, USB_BIDIR);
-               break;
-       case 4:
-               syscon1 = 1;
-               if (cpu_is_omap24xx())
-                       omap2_usb_devconf_set(1, USB_BIDIR);
-               break;
-       case 6:
-               if (cpu_is_omap24xx())
-                       goto bad;
-               syscon1 = 3;
-               omap_cfg_reg(USB1_VP);
-               omap_cfg_reg(USB1_VM);
-               if (!cpu_is_omap15xx()) {
-                       u32 l;
-
-                       l = omap_readl(USB_TRANSCEIVER_CTRL);
-                       l |= CONF_USB1_UNI_R;
-                       omap_writel(l, USB_TRANSCEIVER_CTRL);
-               }
-               break;
-       default:
-bad:
-               printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
-                       1, nwires);
-       }
-       return syscon1 << 20;
-}
-
-static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
-{
-       u32     syscon1 = 0;
-
-       if (cpu_is_omap24xx()) {
-               omap2_usb2_disable_5pinbitll();
-               alt_pingroup = 0;
-       }
-
-       /* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */
-       if (alt_pingroup || nwires == 0)
-               return 0;
-
-       if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) {
-               u32 l;
-
-               l = omap_readl(USB_TRANSCEIVER_CTRL);
-               l &= ~CONF_USB2_UNI_R;
-               omap_writel(l, USB_TRANSCEIVER_CTRL);
-       }
-
-       /* external transceiver */
-       if (cpu_is_omap15xx()) {
-               omap_cfg_reg(USB2_TXD);
-               omap_cfg_reg(USB2_TXEN);
-               omap_cfg_reg(USB2_SEO);
-               if (nwires != 3)
-                       omap_cfg_reg(USB2_RCV);
-               /* there is no USB2_SPEED */
-       } else if (cpu_is_omap16xx()) {
-               omap_cfg_reg(V6_USB2_TXD);
-               omap_cfg_reg(W9_USB2_TXEN);
-               omap_cfg_reg(W5_USB2_SE0);
-               if (nwires != 3)
-                       omap_cfg_reg(Y5_USB2_RCV);
-               // FIXME omap_cfg_reg(USB2_SPEED);
-       } else if (cpu_is_omap24xx()) {
-               omap_cfg_reg(Y11_24XX_USB2_DAT);
-               omap_cfg_reg(AA10_24XX_USB2_SE0);
-               if (nwires > 2)
-                       omap_cfg_reg(AA12_24XX_USB2_TXEN);
-               if (nwires > 3)
-                       omap_cfg_reg(AA6_24XX_USB2_RCV);
-       } else {
-               pr_debug("usb%d cpu unrecognized\n", 1);
-               return 0;
-       }
-       // if (cpu_class_is_omap1()) omap_cfg_reg(USB2_SUSP);
-
-       switch (nwires) {
-       case 2:
-               if (!cpu_is_omap24xx())
-                       goto bad;
-               /* NOTE: board-specific code must override this setting if
-                * this TLL link is not using DP/DM
-                */
-               syscon1 = 1;
-               omap2_usb_devconf_set(2, USB_BIDIR_TLL);
-               break;
-       case 3:
-               syscon1 = 2;
-               if (cpu_is_omap24xx())
-                       omap2_usb_devconf_set(2, USB_BIDIR);
-               break;
-       case 4:
-               syscon1 = 1;
-               if (cpu_is_omap24xx())
-                       omap2_usb_devconf_set(2, USB_BIDIR);
-               break;
-       case 5:
-               if (!cpu_is_omap24xx())
-                       goto bad;
-               omap_cfg_reg(AA4_24XX_USB2_TLLSE0);
-               /* NOTE: board-specific code must override this setting if
-                * this TLL link is not using DP/DM.  Something must also
-                * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED}
-                */
-               syscon1 = 3;
-               omap2_usb2_enable_5pinunitll();
-               break;
-       case 6:
-               if (cpu_is_omap24xx())
-                       goto bad;
-               syscon1 = 3;
-               if (cpu_is_omap15xx()) {
-                       omap_cfg_reg(USB2_VP);
-                       omap_cfg_reg(USB2_VM);
-               } else {
-                       u32 l;
-
-                       omap_cfg_reg(AA9_USB2_VP);
-                       omap_cfg_reg(R9_USB2_VM);
-                       l = omap_readl(USB_TRANSCEIVER_CTRL);
-                       l |= CONF_USB2_UNI_R;
-                       omap_writel(l, USB_TRANSCEIVER_CTRL);
-               }
-               break;
-       default:
-bad:
-               printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
-                       2, nwires);
-       }
-       return syscon1 << 24;
-}
-
-#endif
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef CONFIG_USB_GADGET_OMAP
-
-static struct resource udc_resources[] = {
-       /* order is significant! */
-       {               /* registers */
-               .start          = UDC_BASE,
-               .end            = UDC_BASE + 0xff,
-               .flags          = IORESOURCE_MEM,
-       }, {            /* general IRQ */
-               .start          = INT_USB_IRQ_GEN,
-               .flags          = IORESOURCE_IRQ,
-       }, {            /* PIO IRQ */
-               .start          = INT_USB_IRQ_NISO,
-               .flags          = IORESOURCE_IRQ,
-       }, {            /* SOF IRQ */
-               .start          = INT_USB_IRQ_ISO,
-               .flags          = IORESOURCE_IRQ,
-       },
-};
-
-static u64 udc_dmamask = ~(u32)0;
-
-static struct platform_device udc_device = {
-       .name           = "omap_udc",
-       .id             = -1,
-       .dev = {
-               .dma_mask               = &udc_dmamask,
-               .coherent_dma_mask      = 0xffffffff,
-       },
-       .num_resources  = ARRAY_SIZE(udc_resources),
-       .resource       = udc_resources,
-};
-
-#endif
-
-#if    defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-
-/* The dmamask must be set for OHCI to work */
-static u64 ohci_dmamask = ~(u32)0;
-
-static struct resource ohci_resources[] = {
-       {
-               .start  = OMAP_OHCI_BASE,
-               .end    = OMAP_OHCI_BASE + 0xff,
-               .flags  = IORESOURCE_MEM,
-       },
-       {
-               .start  = INT_USB_IRQ_HGEN,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device ohci_device = {
-       .name                   = "ohci",
-       .id                     = -1,
-       .dev = {
-               .dma_mask               = &ohci_dmamask,
-               .coherent_dma_mask      = 0xffffffff,
-       },
-       .num_resources  = ARRAY_SIZE(ohci_resources),
-       .resource               = ohci_resources,
-};
-
-#endif
-
-#if    defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG)
-
-static struct resource otg_resources[] = {
-       /* order is significant! */
-       {
-               .start          = OTG_BASE,
-               .end            = OTG_BASE + 0xff,
-               .flags          = IORESOURCE_MEM,
-       }, {
-               .start          = INT_USB_IRQ_OTG,
-               .flags          = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device otg_device = {
-       .name           = "omap_otg",
-       .id             = -1,
-       .num_resources  = ARRAY_SIZE(otg_resources),
-       .resource       = otg_resources,
-};
-
-#endif
-
-/*-------------------------------------------------------------------------*/
-
-// FIXME correct answer depends on hmc_mode,
-// as does (on omap1) any nonzero value for config->otg port number
-#ifdef CONFIG_USB_GADGET_OMAP
-#define        is_usb0_device(config)  1
-#else
-#define        is_usb0_device(config)  0
-#endif
-
-/*-------------------------------------------------------------------------*/
-
 #ifdef CONFIG_ARCH_OMAP_OTG
 
 void __init
@@ -560,9 +49,9 @@ omap_otg_init(struct omap_usb_config *config)
        /* pin muxing and transceiver pinouts */
        if (config->pins[0] > 2)        /* alt pingroup 2 */
                alt_pingroup = 1;
-       syscon |= omap_usb0_init(config->pins[0], is_usb0_device(config));
-       syscon |= omap_usb1_init(config->pins[1]);
-       syscon |= omap_usb2_init(config->pins[2], alt_pingroup);
+       syscon |= config->usb0_init(config->pins[0], is_usb0_device(config));
+       syscon |= config->usb1_init(config->pins[1]);
+       syscon |= config->usb2_init(config->pins[2], alt_pingroup);
        pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
        omap_writel(syscon, OTG_SYSCON_1);
 
@@ -610,15 +99,11 @@ omap_otg_init(struct omap_usb_config *config)
 
 #ifdef CONFIG_USB_GADGET_OMAP
        if (config->otg || config->register_dev) {
+               struct platform_device *udc_device = config->udc_device;
+
                syscon &= ~DEV_IDLE_EN;
-               udc_device.dev.platform_data = config;
-               /* IRQ numbers for omap7xx */
-               if(cpu_is_omap7xx()) {
-                       udc_resources[1].start = INT_7XX_USB_GENI;
-                       udc_resources[2].start = INT_7XX_USB_NON_ISO;
-                       udc_resources[3].start = INT_7XX_USB_ISO;
-               }
-               status = platform_device_register(&udc_device);
+               udc_device->dev.platform_data = config;
+               status = platform_device_register(udc_device);
                if (status)
                        pr_debug("can't register UDC device, %d\n", status);
        }
@@ -626,11 +111,11 @@ omap_otg_init(struct omap_usb_config *config)
 
 #if    defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
        if (config->otg || config->register_host) {
+               struct platform_device *ohci_device = config->ohci_device;
+
                syscon &= ~HST_IDLE_EN;
-               ohci_device.dev.platform_data = config;
-               if (cpu_is_omap7xx())
-                       ohci_resources[1].start = INT_7XX_USB_HHC_1;
-               status = platform_device_register(&ohci_device);
+               ohci_device->dev.platform_data = config;
+               status = platform_device_register(ohci_device);
                if (status)
                        pr_debug("can't register OHCI device, %d\n", status);
        }
@@ -638,11 +123,11 @@ omap_otg_init(struct omap_usb_config *config)
 
 #ifdef CONFIG_USB_OTG
        if (config->otg) {
+               struct platform_device *otg_device = config->otg_device;
+
                syscon &= ~OTG_IDLE_EN;
-               otg_device.dev.platform_data = config;
-               if (cpu_is_omap7xx())
-                       otg_resources[1].start = INT_7XX_USB_OTG;
-               status = platform_device_register(&otg_device);
+               otg_device->dev.platform_data = config;
+               status = platform_device_register(otg_device);
                if (status)
                        pr_debug("can't register OTG device, %d\n", status);
        }
@@ -654,102 +139,5 @@ omap_otg_init(struct omap_usb_config *config)
 }
 
 #else
-static inline void omap_otg_init(struct omap_usb_config *config) {}
-#endif
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef CONFIG_ARCH_OMAP15XX
-
-/* ULPD_DPLL_CTRL */
-#define DPLL_IOB               (1 << 13)
-#define DPLL_PLL_ENABLE                (1 << 4)
-#define DPLL_LOCK              (1 << 0)
-
-/* ULPD_APLL_CTRL */
-#define APLL_NDPLL_SWITCH      (1 << 0)
-
-
-static void __init omap_1510_usb_init(struct omap_usb_config *config)
-{
-       unsigned int val;
-       u16 w;
-
-       omap_usb0_init(config->pins[0], is_usb0_device(config));
-       omap_usb1_init(config->pins[1]);
-       omap_usb2_init(config->pins[2], 0);
-
-       val = omap_readl(MOD_CONF_CTRL_0) & ~(0x3f << 1);
-       val |= (config->hmc_mode << 1);
-       omap_writel(val, MOD_CONF_CTRL_0);
-
-       printk("USB: hmc %d", config->hmc_mode);
-       if (config->pins[0])
-               printk(", usb0 %d wires%s", config->pins[0],
-                       is_usb0_device(config) ? " (dev)" : "");
-       if (config->pins[1])
-               printk(", usb1 %d wires", config->pins[1]);
-       if (config->pins[2])
-               printk(", usb2 %d wires", config->pins[2]);
-       printk("\n");
-
-       /* use DPLL for 48 MHz function clock */
-       pr_debug("APLL %04x DPLL %04x REQ %04x\n", omap_readw(ULPD_APLL_CTRL),
-                       omap_readw(ULPD_DPLL_CTRL), omap_readw(ULPD_SOFT_REQ));
-
-       w = omap_readw(ULPD_APLL_CTRL);
-       w &= ~APLL_NDPLL_SWITCH;
-       omap_writew(w, ULPD_APLL_CTRL);
-
-       w = omap_readw(ULPD_DPLL_CTRL);
-       w |= DPLL_IOB | DPLL_PLL_ENABLE;
-       omap_writew(w, ULPD_DPLL_CTRL);
-
-       w = omap_readw(ULPD_SOFT_REQ);
-       w |= SOFT_UDC_REQ | SOFT_DPLL_REQ;
-       omap_writew(w, ULPD_SOFT_REQ);
-
-       while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK))
-               cpu_relax();
-
-#ifdef CONFIG_USB_GADGET_OMAP
-       if (config->register_dev) {
-               int status;
-
-               udc_device.dev.platform_data = config;
-               status = platform_device_register(&udc_device);
-               if (status)
-                       pr_debug("can't register UDC device, %d\n", status);
-               /* udc driver gates 48MHz by D+ pullup */
-       }
-#endif
-
-#if    defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-       if (config->register_host) {
-               int status;
-
-               ohci_device.dev.platform_data = config;
-               status = platform_device_register(&ohci_device);
-               if (status)
-                       pr_debug("can't register OHCI device, %d\n", status);
-               /* hcd explicitly gates 48MHz */
-       }
-#endif
-}
-
-#else
-static inline void omap_1510_usb_init(struct omap_usb_config *config) {}
+void omap_otg_init(struct omap_usb_config *config) {}
 #endif
-
-/*-------------------------------------------------------------------------*/
-
-void __init omap_usb_init(struct omap_usb_config *pdata)
-{
-       if (cpu_is_omap7xx() || cpu_is_omap16xx() || cpu_is_omap24xx())
-               omap_otg_init(pdata);
-       else if (cpu_is_omap15xx())
-               omap_1510_usb_init(pdata);
-       else
-               printk(KERN_ERR "USB: No init for your chip yet\n");
-}
-

diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
index 54c84a492a0f0ab95de7ffa1590e0c5cf5259dc1..779553a1595e938ead6a4764e84ee8d87087acb9 100644 (file)
--- a/arch/arm/plat-orion/pcie.c
+++ b/arch/arm/plat-orion/pcie.c
@@ -13,6 +13,7 @@
 #include <linux/mbus.h>
 #include <asm/mach/pci.h>
 #include <plat/pcie.h>
+#include <linux/delay.h>
 
 /*
  * PCIe unit register offsets.
@@ -46,6 +47,8 @@
 #define  PCIE_STAT_BUS_OFFS            8
 #define  PCIE_STAT_BUS_MASK            0xff
 #define  PCIE_STAT_LINK_DOWN           1
+#define PCIE_DEBUG_CTRL         0x1a60
+#define  PCIE_DEBUG_SOFT_RESET         (1<<20)
 
 
 u32 __init orion_pcie_dev_id(void __iomem *base)
@@ -85,6 +88,32 @@ void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr)
        writel(stat, base + PCIE_STAT_OFF);
 }
 
+void __init orion_pcie_reset(void __iomem *base)
+{
+       u32 reg;
+       int i;
+
+       /*
+        * MV-S104860-U0, Rev. C:
+        * PCI Express Unit Soft Reset
+        * When set, generates an internal reset in the PCI Express unit.
+        * This bit should be cleared after the link is re-established.
+        */
+       reg = readl(base + PCIE_DEBUG_CTRL);
+       reg |= PCIE_DEBUG_SOFT_RESET;
+       writel(reg, base + PCIE_DEBUG_CTRL);
+
+       for (i = 0; i < 20; i++) {
+               mdelay(10);
+
+               if (orion_pcie_link_up(base))
+                       break;
+       }
+
+       reg &= ~(PCIE_DEBUG_SOFT_RESET);
+       writel(reg, base + PCIE_DEBUG_CTRL);
+}
+
 /*
  * Setup PCIE BARs and Address Decode Wins:
  * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
@@ -152,6 +181,11 @@ void __init orion_pcie_setup(void __iomem *base,
        u16 cmd;
        u32 mask;
 
+       /*
+        * soft reset PCIe unit
+        */
+       orion_pcie_reset(base);
+
        /*
         * Point PCIe unit MBUS decode windows to DRAM space.
         */

diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c
index a1025d38f38370ddcb769898cf3854bdab2bbe29..ab211652e4ca79d3e814bc9967cdace8d10edf7c 100644 (file)
--- a/arch/arm/plat-spear/time.c
+++ b/arch/arm/plat-spear/time.c
@@ -58,6 +58,11 @@
 
 #define INT_STATUS             0x1
 
+/*
+ * Minimum clocksource/clockevent timer range in seconds
+ */
+#define SPEAR_MIN_RANGE 4
+
 static __iomem void *gpt_base;
 static struct clk *gpt_clk;
 
@@ -66,44 +71,6 @@ static void clockevent_set_mode(enum clock_event_mode mode,
 static int clockevent_next_event(unsigned long evt,
                                 struct clock_event_device *clk_event_dev);
 
-/*
- * Following clocksource_set_clock and clockevent_set_clock picked
- * from arch/mips/kernel/time.c
- */
-
-void __init clocksource_set_clock(struct clocksource *cs, unsigned int clock)
-{
-       u64 temp;
-       u32 shift;
-
-       /* Find a shift value */
-       for (shift = 32; shift > 0; shift--) {
-               temp = (u64) NSEC_PER_SEC << shift;
-               do_div(temp, clock);
-               if ((temp >> 32) == 0)
-                       break;
-       }
-       cs->shift = shift;
-       cs->mult = (u32) temp;
-}
-
-void __init clockevent_set_clock(struct clock_event_device *cd,
-       unsigned int clock)
-{
-       u64 temp;
-       u32 shift;
-
-       /* Find a shift value */
-       for (shift = 32; shift > 0; shift--) {
-               temp = (u64) clock << shift;
-               do_div(temp, NSEC_PER_SEC);
-               if ((temp >> 32) == 0)
-                       break;
-       }
-       cd->shift = shift;
-       cd->mult = (u32) temp;
-}
-
 static cycle_t clocksource_read_cycles(struct clocksource *cs)
 {
        return (cycle_t) readw(gpt_base + COUNT(CLKSRC));
@@ -138,7 +105,7 @@ static void spear_clocksource_init(void)
        val |= CTRL_ENABLE ;
        writew(val, gpt_base + CR(CLKSRC));
 
-       clocksource_set_clock(&clksrc, tick_rate);
+       clocksource_calc_mult_shift(&clksrc, tick_rate, SPEAR_MIN_RANGE);
 
        /* register the clocksource */
        clocksource_register(&clksrc);
@@ -233,7 +200,7 @@ static void __init spear_clockevent_init(void)
        tick_rate = clk_get_rate(gpt_clk);
        tick_rate >>= CTRL_PRESCALER16;
 
-       clockevent_set_clock(&clkevt, tick_rate);
+       clockevents_calc_mult_shift(&clkevt, tick_rate, SPEAR_MIN_RANGE);
 
        clkevt.max_delta_ns = clockevent_delta2ns(0xfff0,
                        &clkevt);

diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
index 9b1a66816aa652d97460bca5feafe5ec97069d61..5cf88e8427b15e66aafa287f1960e937a26fb89a 100644 (file)
--- a/arch/arm/plat-versatile/Makefile
+++ b/arch/arm/plat-versatile/Makefile
@@ -2,3 +2,7 @@ obj-y   := clock.o
 obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o
 obj-$(CONFIG_ARCH_REALVIEW) += sched-clock.o
 obj-$(CONFIG_ARCH_VERSATILE) += sched-clock.o
+ifeq ($(CONFIG_LEDS_CLASS),y)
+obj-$(CONFIG_ARCH_REALVIEW) += leds.o
+obj-$(CONFIG_ARCH_VERSATILE) += leds.o
+endif

diff --git a/arch/arm/plat-versatile/leds.c b/arch/arm/plat-versatile/leds.c
new file mode 100644 (file)
index 0000000..3169fa5
--- /dev/null
+++ b/arch/arm/plat-versatile/leds.c
@@ -0,0 +1,103 @@
+/*
+ * Driver for the 8 user LEDs found on the RealViews and Versatiles
+ * Based on DaVinci's DM365 board code
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ * Author: Linus Walleij <triad@df.lth.se>
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+
+#ifdef VERSATILE_SYS_BASE
+#define LEDREG (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
+#endif
+
+#ifdef REALVIEW_SYS_BASE
+#define LEDREG (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
+#endif
+
+struct versatile_led {
+       struct led_classdev     cdev;
+       u8                      mask;
+};
+
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+       const char *name;
+       const char *trigger;
+} versatile_leds[] = {
+       { "versatile:0", "heartbeat", },
+       { "versatile:1", "mmc0", },
+       { "versatile:2", },
+       { "versatile:3", },
+       { "versatile:4", },
+       { "versatile:5", },
+       { "versatile:6", },
+       { "versatile:7", },
+};
+
+static void versatile_led_set(struct led_classdev *cdev,
+                             enum led_brightness b)
+{
+       struct versatile_led *led = container_of(cdev,
+                                                struct versatile_led, cdev);
+       u32 reg = readl(LEDREG);
+
+       if (b != LED_OFF)
+               reg |= led->mask;
+       else
+               reg &= ~led->mask;
+       writel(reg, LEDREG);
+}
+
+static enum led_brightness versatile_led_get(struct led_classdev *cdev)
+{
+       struct versatile_led *led = container_of(cdev,
+                                                struct versatile_led, cdev);
+       u32 reg = readl(LEDREG);
+
+       return (reg & led->mask) ? LED_FULL : LED_OFF;
+}
+
+static int __init versatile_leds_init(void)
+{
+       int i;
+
+       /* All ON */
+       writel(0xff, LEDREG);
+       for (i = 0; i < ARRAY_SIZE(versatile_leds); i++) {
+               struct versatile_led *led;
+
+               led = kzalloc(sizeof(*led), GFP_KERNEL);
+               if (!led)
+                       break;
+
+               led->cdev.name = versatile_leds[i].name;
+               led->cdev.brightness_set = versatile_led_set;
+               led->cdev.brightness_get = versatile_led_get;
+               led->cdev.default_trigger = versatile_leds[i].trigger;
+               led->mask = BIT(i);
+
+               if (led_classdev_register(NULL, &led->cdev) < 0) {
+                       kfree(led);
+                       break;
+               }
+       }
+
+       return 0;
+}
+
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(versatile_leds_init);

diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 315a540c7ce50370757320350ed07322d0f3bd86..8063a322c790dd80b3c6b0719541d9e937c2a2bc 100644 (file)
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -15,6 +15,7 @@
 #include <linux/sched.h>
 #include <linux/init.h>
 
+#include <asm/cputype.h>
 #include <asm/thread_notify.h>
 #include <asm/vfp.h>
 
@@ -549,10 +550,13 @@ static int __init vfp_init(void)
                /*
                 * Check for the presence of the Advanced SIMD
                 * load/store instructions, integer and single
-                * precision floating point operations.
+                * precision floating point operations. Only check
+                * for NEON if the hardware has the MVFR registers.
                 */
-               if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100)
-                       elf_hwcap |= HWCAP_NEON;
+               if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
+                       if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100)
+                               elf_hwcap |= HWCAP_NEON;
+               }
 #endif
        }
        return 0;

diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c
index f60b2b6a0931d7d7279bfbfe7d29b3ac7ce6efea..d31590e7011bf895092535d15af5df6cc2e62df5 100644 (file)
--- a/drivers/amba/bus.c
+++ b/drivers/amba/bus.c
@@ -122,6 +122,31 @@ static int __init amba_init(void)
 
 postcore_initcall(amba_init);
 
+static int amba_get_enable_pclk(struct amba_device *pcdev)
+{
+       struct clk *pclk = clk_get(&pcdev->dev, "apb_pclk");
+       int ret;
+
+       pcdev->pclk = pclk;
+
+       if (IS_ERR(pclk))
+               return PTR_ERR(pclk);
+
+       ret = clk_enable(pclk);
+       if (ret)
+               clk_put(pclk);
+
+       return ret;
+}
+
+static void amba_put_disable_pclk(struct amba_device *pcdev)
+{
+       struct clk *pclk = pcdev->pclk;
+
+       clk_disable(pclk);
+       clk_put(pclk);
+}
+
 /*
  * These are the device model conversion veneers; they convert the
  * device model structures to our more specific structures.
@@ -130,17 +155,33 @@ static int amba_probe(struct device *dev)
 {
        struct amba_device *pcdev = to_amba_device(dev);
        struct amba_driver *pcdrv = to_amba_driver(dev->driver);
-       struct amba_id *id;
+       struct amba_id *id = amba_lookup(pcdrv->id_table, pcdev);
+       int ret;
 
-       id = amba_lookup(pcdrv->id_table, pcdev);
+       do {
+               ret = amba_get_enable_pclk(pcdev);
+               if (ret)
+                       break;
+
+               ret = pcdrv->probe(pcdev, id);
+               if (ret == 0)
+                       break;
 
-       return pcdrv->probe(pcdev, id);
+               amba_put_disable_pclk(pcdev);
+       } while (0);
+
+       return ret;
 }
 
 static int amba_remove(struct device *dev)
 {
+       struct amba_device *pcdev = to_amba_device(dev);
        struct amba_driver *drv = to_amba_driver(dev->driver);
-       return drv->remove(to_amba_device(dev));
+       int ret = drv->remove(pcdev);
+
+       amba_put_disable_pclk(pcdev);
+
+       return ret;
 }
 
 static void amba_shutdown(struct device *dev)
@@ -203,7 +244,6 @@ static void amba_device_release(struct device *dev)
  */
 int amba_device_register(struct amba_device *dev, struct resource *parent)
 {
-       u32 pid, cid;
        u32 size;
        void __iomem *tmp;
        int i, ret;
@@ -241,25 +281,35 @@ int amba_device_register(struct amba_device *dev, struct resource *parent)
                goto err_release;
        }
 
-       /*
-        * Read pid and cid based on size of resource
-        * they are located at end of region
-        */
-       for (pid = 0, i = 0; i < 4; i++)
-               pid |= (readl(tmp + size - 0x20 + 4 * i) & 255) << (i * 8);
-       for (cid = 0, i = 0; i < 4; i++)
-               cid |= (readl(tmp + size - 0x10 + 4 * i) & 255) << (i * 8);
+       ret = amba_get_enable_pclk(dev);
+       if (ret == 0) {
+               u32 pid, cid;
 
-       iounmap(tmp);
+               /*
+                * Read pid and cid based on size of resource
+                * they are located at end of region
+                */
+               for (pid = 0, i = 0; i < 4; i++)
+                       pid |= (readl(tmp + size - 0x20 + 4 * i) & 255) <<
+                               (i * 8);
+               for (cid = 0, i = 0; i < 4; i++)
+                       cid |= (readl(tmp + size - 0x10 + 4 * i) & 255) <<
+                               (i * 8);
 
-       if (cid == 0xb105f00d)
-               dev->periphid = pid;
+               amba_put_disable_pclk(dev);
 
-       if (!dev->periphid) {
-               ret = -ENODEV;
-               goto err_release;
+               if (cid == 0xb105f00d)
+                       dev->periphid = pid;
+
+               if (!dev->periphid)
+                       ret = -ENODEV;
        }
 
+       iounmap(tmp);
+
+       if (ret)
+               goto err_release;
+
        ret = device_add(&dev->dev);
        if (ret)
                goto err_release;

diff --git a/drivers/gpio/pl061.c b/drivers/gpio/pl061.c
index ee568c8fcbd01db804dc071be08a1da4b5ee6e87..5005990f751f44e142bbe7ec11869bc45efd9772 100644 (file)
--- a/drivers/gpio/pl061.c
+++ b/drivers/gpio/pl061.c
@@ -232,7 +232,7 @@ static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
        desc->chip->unmask(irq);
 }
 
-static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
+static int pl061_probe(struct amba_device *dev, struct amba_id *id)
 {
        struct pl061_platform_data *pdata;
        struct pl061_gpio *chip;
@@ -333,7 +333,7 @@ free_mem:
        return ret;
 }
 
-static struct amba_id pl061_ids[] __initdata = {
+static struct amba_id pl061_ids[] = {
        {
                .id     = 0x00041061,
                .mask   = 0x000fffff,

diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
index 81bf25e67ce1668b88a6af271c994dde5e25cbe5..e4112622e5a25e7eb90b615bcc93475bcfd054a7 100644 (file)
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -302,6 +302,15 @@ config LEDS_MC13783
          This option enable support for on-chip LED drivers found
          on Freescale Semiconductor MC13783 PMIC.
 
+config LEDS_NS2
+       tristate "LED support for Network Space v2 GPIO LEDs"
+       depends on MACH_NETSPACE_V2 || MACH_INETSPACE_V2 || MACH_NETSPACE_MAX_V2
+       default y
+       help
+         This option enable support for the dual-GPIO LED found on the
+         Network Space v2 board (and parents). This include Internet Space v2,
+         Network Space (Max) v2 and d2 Network v2 boards.
+
 config LEDS_TRIGGERS
        bool "LED Trigger support"
        help

diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
index 2493de4993741d8f59b006292e75c97d245baf9a..7d6b95831f8eb5da86fad02ab6eedf680c437e3c 100644 (file)
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_LEDS_LT3593)             += leds-lt3593.o
 obj-$(CONFIG_LEDS_ADP5520)             += leds-adp5520.o
 obj-$(CONFIG_LEDS_DELL_NETBOOKS)       += dell-led.o
 obj-$(CONFIG_LEDS_MC13783)             += leds-mc13783.o
+obj-$(CONFIG_LEDS_NS2)                 += leds-ns2.o
 
 # LED SPI Drivers
 obj-$(CONFIG_LEDS_DAC124S085)          += leds-dac124s085.o

diff --git a/drivers/leds/leds-ns2.c b/drivers/leds/leds-ns2.c
new file mode 100644 (file)
index 0000000..74dce4b
--- /dev/null
+++ b/drivers/leds/leds-ns2.c
@@ -0,0 +1,338 @@
+/*
+ * leds-ns2.c - Driver for the Network Space v2 (and parents) dual-GPIO LED
+ *
+ * Copyright (C) 2010 LaCie
+ *
+ * Author: Simon Guinot <sguinot@lacie.com>
+ *
+ * Based on leds-gpio.c by Raphael Assenat <raph@8d.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <mach/leds-ns2.h>
+
+/*
+ * The Network Space v2 dual-GPIO LED is wired to a CPLD and can blink in
+ * relation with the SATA activity. This capability is exposed through the
+ * "sata" sysfs attribute.
+ *
+ * The following array detail the different LED registers and the combination
+ * of their possible values:
+ *
+ *  cmd_led   |  slow_led  | /SATA active | LED state
+ *            |            |              |
+ *     1      |     0      |      x       |  off
+ *     -      |     1      |      x       |  on
+ *     0      |     0      |      1       |  on
+ *     0      |     0      |      0       |  blink (rate 300ms)
+ */
+
+enum ns2_led_modes {
+       NS_V2_LED_OFF,
+       NS_V2_LED_ON,
+       NS_V2_LED_SATA,
+};
+
+struct ns2_led_mode_value {
+       enum ns2_led_modes      mode;
+       int                     cmd_level;
+       int                     slow_level;
+};
+
+static struct ns2_led_mode_value ns2_led_modval[] = {
+       { NS_V2_LED_OFF , 1, 0 },
+       { NS_V2_LED_ON  , 0, 1 },
+       { NS_V2_LED_ON  , 1, 1 },
+       { NS_V2_LED_SATA, 0, 0 },
+};
+
+struct ns2_led_data {
+       struct led_classdev     cdev;
+       unsigned                cmd;
+       unsigned                slow;
+       unsigned char           sata; /* True when SATA mode active. */
+       rwlock_t                rw_lock; /* Lock GPIOs. */
+};
+
+static int ns2_led_get_mode(struct ns2_led_data *led_dat,
+                           enum ns2_led_modes *mode)
+{
+       int i;
+       int ret = -EINVAL;
+       int cmd_level;
+       int slow_level;
+
+       read_lock(&led_dat->rw_lock);
+
+       cmd_level = gpio_get_value(led_dat->cmd);
+       slow_level = gpio_get_value(led_dat->slow);
+
+       for (i = 0; i < ARRAY_SIZE(ns2_led_modval); i++) {
+               if (cmd_level == ns2_led_modval[i].cmd_level &&
+                   slow_level == ns2_led_modval[i].slow_level) {
+                       *mode = ns2_led_modval[i].mode;
+                       ret = 0;
+                       break;
+               }
+       }
+
+       read_unlock(&led_dat->rw_lock);
+
+       return ret;
+}
+
+static void ns2_led_set_mode(struct ns2_led_data *led_dat,
+                            enum ns2_led_modes mode)
+{
+       int i;
+
+       write_lock(&led_dat->rw_lock);
+
+       for (i = 0; i < ARRAY_SIZE(ns2_led_modval); i++) {
+               if (mode == ns2_led_modval[i].mode) {
+                       gpio_set_value(led_dat->cmd,
+                                      ns2_led_modval[i].cmd_level);
+                       gpio_set_value(led_dat->slow,
+                                      ns2_led_modval[i].slow_level);
+               }
+       }
+
+       write_unlock(&led_dat->rw_lock);
+}
+
+static void ns2_led_set(struct led_classdev *led_cdev,
+                       enum led_brightness value)
+{
+       struct ns2_led_data *led_dat =
+               container_of(led_cdev, struct ns2_led_data, cdev);
+       enum ns2_led_modes mode;
+
+       if (value == LED_OFF)
+               mode = NS_V2_LED_OFF;
+       else if (led_dat->sata)
+               mode = NS_V2_LED_SATA;
+       else
+               mode = NS_V2_LED_ON;
+
+       ns2_led_set_mode(led_dat, mode);
+}
+
+static ssize_t ns2_led_sata_store(struct device *dev,
+                                 struct device_attribute *attr,
+                                 const char *buff, size_t count)
+{
+       int ret;
+       unsigned long enable;
+       enum ns2_led_modes mode;
+       struct ns2_led_data *led_dat = dev_get_drvdata(dev);
+
+       ret = strict_strtoul(buff, 10, &enable);
+       if (ret < 0)
+               return ret;
+
+       enable = !!enable;
+
+       if (led_dat->sata == enable)
+               return count;
+
+       ret = ns2_led_get_mode(led_dat, &mode);
+       if (ret < 0)
+               return ret;
+
+       if (enable && mode == NS_V2_LED_ON)
+               ns2_led_set_mode(led_dat, NS_V2_LED_SATA);
+       if (!enable && mode == NS_V2_LED_SATA)
+               ns2_led_set_mode(led_dat, NS_V2_LED_ON);
+
+       led_dat->sata = enable;
+
+       return count;
+}
+
+static ssize_t ns2_led_sata_show(struct device *dev,
+                                struct device_attribute *attr, char *buf)
+{
+       struct ns2_led_data *led_dat = dev_get_drvdata(dev);
+
+       return sprintf(buf, "%d\n", led_dat->sata);
+}
+
+static DEVICE_ATTR(sata, 0644, ns2_led_sata_show, ns2_led_sata_store);
+
+static int __devinit
+create_ns2_led(struct platform_device *pdev, struct ns2_led_data *led_dat,
+              const struct ns2_led *template)
+{
+       int ret;
+       enum ns2_led_modes mode;
+
+       ret = gpio_request(template->cmd, template->name);
+       if (ret == 0) {
+               ret = gpio_direction_output(template->cmd,
+                                           gpio_get_value(template->cmd));
+               if (ret)
+                       gpio_free(template->cmd);
+       }
+       if (ret) {
+               dev_err(&pdev->dev, "%s: failed to setup command GPIO\n",
+                       template->name);
+       }
+
+       ret = gpio_request(template->slow, template->name);
+       if (ret == 0) {
+               ret = gpio_direction_output(template->slow,
+                                           gpio_get_value(template->slow));
+               if (ret)
+                       gpio_free(template->slow);
+       }
+       if (ret) {
+               dev_err(&pdev->dev, "%s: failed to setup slow GPIO\n",
+                       template->name);
+               goto err_free_cmd;
+       }
+
+       rwlock_init(&led_dat->rw_lock);
+
+       led_dat->cdev.name = template->name;
+       led_dat->cdev.default_trigger = template->default_trigger;
+       led_dat->cdev.blink_set = NULL;
+       led_dat->cdev.brightness_set = ns2_led_set;
+       led_dat->cdev.flags |= LED_CORE_SUSPENDRESUME;
+       led_dat->cmd = template->cmd;
+       led_dat->slow = template->slow;
+
+       ret = ns2_led_get_mode(led_dat, &mode);
+       if (ret < 0)
+               goto err_free_slow;
+
+       /* Set LED initial state. */
+       led_dat->sata = (mode == NS_V2_LED_SATA) ? 1 : 0;
+       led_dat->cdev.brightness =
+               (mode == NS_V2_LED_OFF) ? LED_OFF : LED_FULL;
+
+       ret = led_classdev_register(&pdev->dev, &led_dat->cdev);
+       if (ret < 0)
+               goto err_free_slow;
+
+       dev_set_drvdata(led_dat->cdev.dev, led_dat);
+       ret = device_create_file(led_dat->cdev.dev, &dev_attr_sata);
+       if (ret < 0)
+               goto err_free_cdev;
+
+       return 0;
+
+err_free_cdev:
+       led_classdev_unregister(&led_dat->cdev);
+err_free_slow:
+       gpio_free(led_dat->slow);
+err_free_cmd:
+       gpio_free(led_dat->cmd);
+
+       return ret;
+}
+
+static void __devexit delete_ns2_led(struct ns2_led_data *led_dat)
+{
+       device_remove_file(led_dat->cdev.dev, &dev_attr_sata);
+       led_classdev_unregister(&led_dat->cdev);
+       gpio_free(led_dat->cmd);
+       gpio_free(led_dat->slow);
+}
+
+static int __devinit ns2_led_probe(struct platform_device *pdev)
+{
+       struct ns2_led_platform_data *pdata = pdev->dev.platform_data;
+       struct ns2_led_data *leds_data;
+       int i;
+       int ret;
+
+       if (!pdata)
+               return -EINVAL;
+
+       leds_data = kzalloc(sizeof(struct ns2_led_data) *
+                           pdata->num_leds, GFP_KERNEL);
+       if (!leds_data)
+               return -ENOMEM;
+
+       for (i = 0; i < pdata->num_leds; i++) {
+               ret = create_ns2_led(pdev, &leds_data[i], &pdata->leds[i]);
+               if (ret < 0)
+                       goto err;
+
+       }
+
+       platform_set_drvdata(pdev, leds_data);
+
+       return 0;
+
+err:
+       for (i = i - 1; i >= 0; i--)
+               delete_ns2_led(&leds_data[i]);
+
+       kfree(leds_data);
+
+       return ret;
+}
+
+static int __devexit ns2_led_remove(struct platform_device *pdev)
+{
+       int i;
+       struct ns2_led_platform_data *pdata = pdev->dev.platform_data;
+       struct ns2_led_data *leds_data;
+
+       leds_data = platform_get_drvdata(pdev);
+
+       for (i = 0; i < pdata->num_leds; i++)
+               delete_ns2_led(&leds_data[i]);
+
+       kfree(leds_data);
+       platform_set_drvdata(pdev, NULL);
+
+       return 0;
+}
+
+static struct platform_driver ns2_led_driver = {
+       .probe          = ns2_led_probe,
+       .remove         = __devexit_p(ns2_led_remove),
+       .driver         = {
+               .name   = "leds-ns2",
+               .owner  = THIS_MODULE,
+       },
+};
+MODULE_ALIAS("platform:leds-ns2");
+
+static int __init ns2_led_init(void)
+{
+       return platform_driver_register(&ns2_led_driver);
+}
+
+static void __exit ns2_led_exit(void)
+{
+       platform_driver_unregister(&ns2_led_driver);
+}
+
+module_init(ns2_led_init);
+module_exit(ns2_led_exit);
+
+MODULE_AUTHOR("Simon Guinot <sguinot@lacie.com>");
+MODULE_DESCRIPTION("Network Space v2 LED driver");
+MODULE_LICENSE("GPL");

diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
index bdbc9d305419d8778d7bfceded703e1fb55d4c9b..27e2acce3c3a846648b913597b40fe10928a4a7d 100644 (file)
--- a/drivers/media/video/Kconfig
+++ b/drivers/media/video/Kconfig
@@ -969,6 +969,19 @@ config VIDEO_OMAP2
        ---help---
          This is a v4l2 driver for the TI OMAP2 camera capture interface
 
+config VIDEO_MX2_HOSTSUPPORT
+        bool
+
+config VIDEO_MX2
+       tristate "i.MX27/i.MX25 Camera Sensor Interface driver"
+       depends on VIDEO_DEV && SOC_CAMERA && (MACH_MX27 || ARCH_MX25)
+       select VIDEOBUF_DMA_CONTIG
+       select VIDEO_MX2_HOSTSUPPORT
+       ---help---
+         This is a v4l2 driver for the i.MX27 and the i.MX25 Camera Sensor
+         Interface
+
+
 #
 # USB Multimedia device configuration
 #

diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile
index cc93859d3164771fce15e54236984340b4b5f373..b08bd2b65cd0a3db5928dbbb4fb25829c904d27f 100644 (file)
--- a/drivers/media/video/Makefile
+++ b/drivers/media/video/Makefile
@@ -162,6 +162,7 @@ obj-$(CONFIG_SOC_CAMERA)            += soc_camera.o soc_mediabus.o
 obj-$(CONFIG_SOC_CAMERA_PLATFORM)      += soc_camera_platform.o
 # soc-camera host drivers have to be linked after camera drivers
 obj-$(CONFIG_VIDEO_MX1)                        += mx1_camera.o
+obj-$(CONFIG_VIDEO_MX2)                        += mx2_camera.o
 obj-$(CONFIG_VIDEO_MX3)                        += mx3_camera.o
 obj-$(CONFIG_VIDEO_PXA27x)             += pxa_camera.o
 obj-$(CONFIG_VIDEO_SH_MOBILE_CEU)      += sh_mobile_ceu_camera.o

diff --git a/drivers/media/video/mx2_camera.c b/drivers/media/video/mx2_camera.c
new file mode 100644 (file)
index 0000000..026bef0
--- /dev/null
+++ b/drivers/media/video/mx2_camera.c
@@ -0,0 +1,1513 @@
+/*
+ * V4L2 Driver for i.MX27/i.MX25 camera host
+ *
+ * Copyright (C) 2008, Sascha Hauer, Pengutronix
+ * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+#include <linux/errno.h>
+#include <linux/fs.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/moduleparam.h>
+#include <linux/time.h>
+#include <linux/version.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+#include <linux/clk.h>
+
+#include <media/v4l2-common.h>
+#include <media/v4l2-dev.h>
+#include <media/videobuf-dma-contig.h>
+#include <media/soc_camera.h>
+#include <media/soc_mediabus.h>
+
+#include <linux/videodev2.h>
+
+#include <mach/mx2_cam.h>
+#ifdef CONFIG_MACH_MX27
+#include <mach/dma-mx1-mx2.h>
+#endif
+#include <mach/hardware.h>
+
+#include <asm/dma.h>
+
+#define MX2_CAM_DRV_NAME "mx2-camera"
+#define MX2_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
+#define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera"
+
+/* reset values */
+#define CSICR1_RESET_VAL       0x40000800
+#define CSICR2_RESET_VAL       0x0
+#define CSICR3_RESET_VAL       0x0
+
+/* csi control reg 1 */
+#define CSICR1_SWAP16_EN       (1 << 31)
+#define CSICR1_EXT_VSYNC       (1 << 30)
+#define CSICR1_EOF_INTEN       (1 << 29)
+#define CSICR1_PRP_IF_EN       (1 << 28)
+#define CSICR1_CCIR_MODE       (1 << 27)
+#define CSICR1_COF_INTEN       (1 << 26)
+#define CSICR1_SF_OR_INTEN     (1 << 25)
+#define CSICR1_RF_OR_INTEN     (1 << 24)
+#define CSICR1_STATFF_LEVEL    (3 << 22)
+#define CSICR1_STATFF_INTEN    (1 << 21)
+#define CSICR1_RXFF_LEVEL(l)   (((l) & 3) << 19)       /* MX27 */
+#define CSICR1_FB2_DMA_INTEN   (1 << 20)               /* MX25 */
+#define CSICR1_FB1_DMA_INTEN   (1 << 19)               /* MX25 */
+#define CSICR1_RXFF_INTEN      (1 << 18)
+#define CSICR1_SOF_POL         (1 << 17)
+#define CSICR1_SOF_INTEN       (1 << 16)
+#define CSICR1_MCLKDIV(d)      (((d) & 0xF) << 12)
+#define CSICR1_HSYNC_POL       (1 << 11)
+#define CSICR1_CCIR_EN         (1 << 10)
+#define CSICR1_MCLKEN          (1 << 9)
+#define CSICR1_FCC             (1 << 8)
+#define CSICR1_PACK_DIR                (1 << 7)
+#define CSICR1_CLR_STATFIFO    (1 << 6)
+#define CSICR1_CLR_RXFIFO      (1 << 5)
+#define CSICR1_GCLK_MODE       (1 << 4)
+#define CSICR1_INV_DATA                (1 << 3)
+#define CSICR1_INV_PCLK                (1 << 2)
+#define CSICR1_REDGE           (1 << 1)
+
+#define SHIFT_STATFF_LEVEL     22
+#define SHIFT_RXFF_LEVEL       19
+#define SHIFT_MCLKDIV          12
+
+/* control reg 3 */
+#define CSICR3_FRMCNT          (0xFFFF << 16)
+#define CSICR3_FRMCNT_RST      (1 << 15)
+#define CSICR3_DMA_REFLASH_RFF (1 << 14)
+#define CSICR3_DMA_REFLASH_SFF (1 << 13)
+#define CSICR3_DMA_REQ_EN_RFF  (1 << 12)
+#define CSICR3_DMA_REQ_EN_SFF  (1 << 11)
+#define CSICR3_RXFF_LEVEL(l)   (((l) & 7) << 4)        /* MX25 */
+#define CSICR3_CSI_SUP         (1 << 3)
+#define CSICR3_ZERO_PACK_EN    (1 << 2)
+#define CSICR3_ECC_INT_EN      (1 << 1)
+#define CSICR3_ECC_AUTO_EN     (1 << 0)
+
+#define SHIFT_FRMCNT           16
+
+/* csi status reg */
+#define CSISR_SFF_OR_INT       (1 << 25)
+#define CSISR_RFF_OR_INT       (1 << 24)
+#define CSISR_STATFF_INT       (1 << 21)
+#define CSISR_DMA_TSF_FB2_INT  (1 << 20)       /* MX25 */
+#define CSISR_DMA_TSF_FB1_INT  (1 << 19)       /* MX25 */
+#define CSISR_RXFF_INT         (1 << 18)
+#define CSISR_EOF_INT          (1 << 17)
+#define CSISR_SOF_INT          (1 << 16)
+#define CSISR_F2_INT           (1 << 15)
+#define CSISR_F1_INT           (1 << 14)
+#define CSISR_COF_INT          (1 << 13)
+#define CSISR_ECC_INT          (1 << 1)
+#define CSISR_DRDY             (1 << 0)
+
+#define CSICR1                 0x00
+#define CSICR2                 0x04
+#define CSISR                  (cpu_is_mx27() ? 0x08 : 0x18)
+#define CSISTATFIFO            0x0c
+#define CSIRFIFO               0x10
+#define CSIRXCNT               0x14
+#define CSICR3                 (cpu_is_mx27() ? 0x1C : 0x08)
+#define CSIDMASA_STATFIFO      0x20
+#define CSIDMATA_STATFIFO      0x24
+#define CSIDMASA_FB1           0x28
+#define CSIDMASA_FB2           0x2c
+#define CSIFBUF_PARA           0x30
+#define CSIIMAG_PARA           0x34
+
+/* EMMA PrP */
+#define PRP_CNTL                       0x00
+#define PRP_INTR_CNTL                  0x04
+#define PRP_INTRSTATUS                 0x08
+#define PRP_SOURCE_Y_PTR               0x0c
+#define PRP_SOURCE_CB_PTR              0x10
+#define PRP_SOURCE_CR_PTR              0x14
+#define PRP_DEST_RGB1_PTR              0x18
+#define PRP_DEST_RGB2_PTR              0x1c
+#define PRP_DEST_Y_PTR                 0x20
+#define PRP_DEST_CB_PTR                        0x24
+#define PRP_DEST_CR_PTR                        0x28
+#define PRP_SRC_FRAME_SIZE             0x2c
+#define PRP_DEST_CH1_LINE_STRIDE       0x30
+#define PRP_SRC_PIXEL_FORMAT_CNTL      0x34
+#define PRP_CH1_PIXEL_FORMAT_CNTL      0x38
+#define PRP_CH1_OUT_IMAGE_SIZE         0x3c
+#define PRP_CH2_OUT_IMAGE_SIZE         0x40
+#define PRP_SRC_LINE_STRIDE            0x44
+#define PRP_CSC_COEF_012               0x48
+#define PRP_CSC_COEF_345               0x4c
+#define PRP_CSC_COEF_678               0x50
+#define PRP_CH1_RZ_HORI_COEF1          0x54
+#define PRP_CH1_RZ_HORI_COEF2          0x58
+#define PRP_CH1_RZ_HORI_VALID          0x5c
+#define PRP_CH1_RZ_VERT_COEF1          0x60
+#define PRP_CH1_RZ_VERT_COEF2          0x64
+#define PRP_CH1_RZ_VERT_VALID          0x68
+#define PRP_CH2_RZ_HORI_COEF1          0x6c
+#define PRP_CH2_RZ_HORI_COEF2          0x70
+#define PRP_CH2_RZ_HORI_VALID          0x74
+#define PRP_CH2_RZ_VERT_COEF1          0x78
+#define PRP_CH2_RZ_VERT_COEF2          0x7c
+#define PRP_CH2_RZ_VERT_VALID          0x80
+
+#define PRP_CNTL_CH1EN         (1 << 0)
+#define PRP_CNTL_CH2EN         (1 << 1)
+#define PRP_CNTL_CSIEN         (1 << 2)
+#define PRP_CNTL_DATA_IN_YUV420        (0 << 3)
+#define PRP_CNTL_DATA_IN_YUV422        (1 << 3)
+#define PRP_CNTL_DATA_IN_RGB16 (2 << 3)
+#define PRP_CNTL_DATA_IN_RGB32 (3 << 3)
+#define PRP_CNTL_CH1_OUT_RGB8  (0 << 5)
+#define PRP_CNTL_CH1_OUT_RGB16 (1 << 5)
+#define PRP_CNTL_CH1_OUT_RGB32 (2 << 5)
+#define PRP_CNTL_CH1_OUT_YUV422        (3 << 5)
+#define PRP_CNTL_CH2_OUT_YUV420        (0 << 7)
+#define PRP_CNTL_CH2_OUT_YUV422 (1 << 7)
+#define PRP_CNTL_CH2_OUT_YUV444        (2 << 7)
+#define PRP_CNTL_CH1_LEN       (1 << 9)
+#define PRP_CNTL_CH2_LEN       (1 << 10)
+#define PRP_CNTL_SKIP_FRAME    (1 << 11)
+#define PRP_CNTL_SWRST         (1 << 12)
+#define PRP_CNTL_CLKEN         (1 << 13)
+#define PRP_CNTL_WEN           (1 << 14)
+#define PRP_CNTL_CH1BYP                (1 << 15)
+#define PRP_CNTL_IN_TSKIP(x)   ((x) << 16)
+#define PRP_CNTL_CH1_TSKIP(x)  ((x) << 19)
+#define PRP_CNTL_CH2_TSKIP(x)  ((x) << 22)
+#define PRP_CNTL_INPUT_FIFO_LEVEL(x)   ((x) << 25)
+#define PRP_CNTL_RZ_FIFO_LEVEL(x)      ((x) << 27)
+#define PRP_CNTL_CH2B1EN       (1 << 29)
+#define PRP_CNTL_CH2B2EN       (1 << 30)
+#define PRP_CNTL_CH2FEN                (1 << 31)
+
+/* IRQ Enable and status register */
+#define PRP_INTR_RDERR         (1 << 0)
+#define PRP_INTR_CH1WERR       (1 << 1)
+#define PRP_INTR_CH2WERR       (1 << 2)
+#define PRP_INTR_CH1FC         (1 << 3)
+#define PRP_INTR_CH2FC         (1 << 5)
+#define PRP_INTR_LBOVF         (1 << 7)
+#define PRP_INTR_CH2OVF                (1 << 8)
+
+#define mx27_camera_emma(pcdev)        (cpu_is_mx27() && pcdev->use_emma)
+
+#define MAX_VIDEO_MEM  16
+
+struct mx2_camera_dev {
+       struct device           *dev;
+       struct soc_camera_host  soc_host;
+       struct soc_camera_device *icd;
+       struct clk              *clk_csi, *clk_emma;
+
+       unsigned int            irq_csi, irq_emma;
+       void __iomem            *base_csi, *base_emma;
+       unsigned long           base_dma;
+
+       struct mx2_camera_platform_data *pdata;
+       struct resource         *res_csi, *res_emma;
+       unsigned long           platform_flags;
+
+       struct list_head        capture;
+       struct list_head        active_bufs;
+
+       spinlock_t              lock;
+
+       int                     dma;
+       struct mx2_buffer       *active;
+       struct mx2_buffer       *fb1_active;
+       struct mx2_buffer       *fb2_active;
+
+       int                     use_emma;
+
+       u32                     csicr1;
+
+       void                    *discard_buffer;
+       dma_addr_t              discard_buffer_dma;
+       size_t                  discard_size;
+};
+
+/* buffer for one video frame */
+struct mx2_buffer {
+       /* common v4l buffer stuff -- must be first */
+       struct videobuf_buffer          vb;
+
+       enum v4l2_mbus_pixelcode        code;
+
+       int bufnum;
+};
+
+static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev)
+{
+       unsigned long flags;
+
+       clk_disable(pcdev->clk_csi);
+       writel(0, pcdev->base_csi + CSICR1);
+       if (mx27_camera_emma(pcdev)) {
+               writel(0, pcdev->base_emma + PRP_CNTL);
+       } else if (cpu_is_mx25()) {
+               spin_lock_irqsave(&pcdev->lock, flags);
+               pcdev->fb1_active = NULL;
+               pcdev->fb2_active = NULL;
+               writel(0, pcdev->base_csi + CSIDMASA_FB1);
+               writel(0, pcdev->base_csi + CSIDMASA_FB2);
+               spin_unlock_irqrestore(&pcdev->lock, flags);
+       }
+}
+
+/*
+ * The following two functions absolutely depend on the fact, that
+ * there can be only one camera on mx2 camera sensor interface
+ */
+static int mx2_camera_add_device(struct soc_camera_device *icd)
+{
+       struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
+       struct mx2_camera_dev *pcdev = ici->priv;
+       int ret;
+       u32 csicr1;
+
+       if (pcdev->icd)
+               return -EBUSY;
+
+       ret = clk_enable(pcdev->clk_csi);
+       if (ret < 0)
+               return ret;
+
+       csicr1 = CSICR1_MCLKEN;
+
+       if (mx27_camera_emma(pcdev)) {
+               csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC |
+                       CSICR1_RXFF_LEVEL(0);
+       } else if (cpu_is_mx27())
+               csicr1 |= CSICR1_SOF_INTEN | CSICR1_RXFF_LEVEL(2);
+
+       pcdev->csicr1 = csicr1;
+       writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
+
+       pcdev->icd = icd;
+
+       dev_info(icd->dev.parent, "Camera driver attached to camera %d\n",
+                icd->devnum);
+
+       return 0;
+}
+
+static void mx2_camera_remove_device(struct soc_camera_device *icd)
+{
+       struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
+       struct mx2_camera_dev *pcdev = ici->priv;
+
+       BUG_ON(icd != pcdev->icd);
+
+       dev_info(icd->dev.parent, "Camera driver detached from camera %d\n",
+                icd->devnum);
+
+       mx2_camera_deactivate(pcdev);
+
+       if (pcdev->discard_buffer) {
+               dma_free_coherent(ici->v4l2_dev.dev, pcdev->discard_size,
+                               pcdev->discard_buffer,
+                               pcdev->discard_buffer_dma);
+               pcdev->discard_buffer = NULL;
+       }
+
+       pcdev->icd = NULL;
+}
+
+#ifdef CONFIG_MACH_MX27
+static void mx27_camera_dma_enable(struct mx2_camera_dev *pcdev)
+{
+       u32 tmp;
+
+       imx_dma_enable(pcdev->dma);
+
+       tmp = readl(pcdev->base_csi + CSICR1);
+       tmp |= CSICR1_RF_OR_INTEN;
+       writel(tmp, pcdev->base_csi + CSICR1);
+}
+
+static irqreturn_t mx27_camera_irq(int irq_csi, void *data)
+{
+       struct mx2_camera_dev *pcdev = data;
+       u32 status = readl(pcdev->base_csi + CSISR);
+
+       if (status & CSISR_SOF_INT && pcdev->active) {
+               u32 tmp;
+
+               tmp = readl(pcdev->base_csi + CSICR1);
+               writel(tmp | CSICR1_CLR_RXFIFO, pcdev->base_csi + CSICR1);
+               mx27_camera_dma_enable(pcdev);
+       }
+
+       writel(CSISR_SOF_INT | CSISR_RFF_OR_INT, pcdev->base_csi + CSISR);
+
+       return IRQ_HANDLED;
+}
+#else
+static irqreturn_t mx27_camera_irq(int irq_csi, void *data)
+{
+       return IRQ_NONE;
+}
+#endif /* CONFIG_MACH_MX27 */
+
+static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb,
+               int state)
+{
+       struct videobuf_buffer *vb;
+       struct mx2_buffer *buf;
+       struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active :
+               &pcdev->fb2_active;
+       u32 fb_reg = fb == 1 ? CSIDMASA_FB1 : CSIDMASA_FB2;
+       unsigned long flags;
+
+       spin_lock_irqsave(&pcdev->lock, flags);
+
+       vb = &(*fb_active)->vb;
+       dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
+               vb, vb->baddr, vb->bsize);
+
+       vb->state = state;
+       do_gettimeofday(&vb->ts);
+       vb->field_count++;
+
+       wake_up(&vb->done);
+
+       if (list_empty(&pcdev->capture)) {
+               buf = NULL;
+               writel(0, pcdev->base_csi + fb_reg);
+       } else {
+               buf = list_entry(pcdev->capture.next, struct mx2_buffer,
+                               vb.queue);
+               vb = &buf->vb;
+               list_del(&vb->queue);
+               vb->state = VIDEOBUF_ACTIVE;
+               writel(videobuf_to_dma_contig(vb), pcdev->base_csi + fb_reg);
+       }
+
+       *fb_active = buf;
+
+       spin_unlock_irqrestore(&pcdev->lock, flags);
+}
+
+static irqreturn_t mx25_camera_irq(int irq_csi, void *data)
+{
+       struct mx2_camera_dev *pcdev = data;
+       u32 status = readl(pcdev->base_csi + CSISR);
+
+       if (status & CSISR_DMA_TSF_FB1_INT)
+               mx25_camera_frame_done(pcdev, 1, VIDEOBUF_DONE);
+       else if (status & CSISR_DMA_TSF_FB2_INT)
+               mx25_camera_frame_done(pcdev, 2, VIDEOBUF_DONE);
+
+       /* FIXME: handle CSISR_RFF_OR_INT */
+
+       writel(status, pcdev->base_csi + CSISR);
+
+       return IRQ_HANDLED;
+}
+
+/*
+ *  Videobuf operations
+ */
+static int mx2_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
+                             unsigned int *size)
+{
+       struct soc_camera_device *icd = vq->priv_data;
+       int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
+                       icd->current_fmt->host_fmt);
+
+       dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size);
+
+       if (bytes_per_line < 0)
+               return bytes_per_line;
+
+       *size = bytes_per_line * icd->user_height;
+
+       if (0 == *count)
+               *count = 32;
+       if (*size * *count > MAX_VIDEO_MEM * 1024 * 1024)
+               *count = (MAX_VIDEO_MEM * 1024 * 1024) / *size;
+
+       return 0;
+}
+
+static void free_buffer(struct videobuf_queue *vq, struct mx2_buffer *buf)
+{
+       struct soc_camera_device *icd = vq->priv_data;
+       struct videobuf_buffer *vb = &buf->vb;
+
+       dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
+               vb, vb->baddr, vb->bsize);
+
+       /*
+        * This waits until this buffer is out of danger, i.e., until it is no
+        * longer in STATE_QUEUED or STATE_ACTIVE
+        */
+       videobuf_waiton(vb, 0, 0);
+
+       videobuf_dma_contig_free(vq, vb);
+       dev_dbg(&icd->dev, "%s freed\n", __func__);
+
+       vb->state = VIDEOBUF_NEEDS_INIT;
+}
+
+static int mx2_videobuf_prepare(struct videobuf_queue *vq,
+               struct videobuf_buffer *vb, enum v4l2_field field)
+{
+       struct soc_camera_device *icd = vq->priv_data;
+       struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
+       int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
+                       icd->current_fmt->host_fmt);
+       int ret = 0;
+
+       dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
+               vb, vb->baddr, vb->bsize);
+
+       if (bytes_per_line < 0)
+               return bytes_per_line;
+
+#ifdef DEBUG
+       /*
+        * This can be useful if you want to see if we actually fill
+        * the buffer with something
+        */
+       memset((void *)vb->baddr, 0xaa, vb->bsize);
+#endif
+
+       if (buf->code   != icd->current_fmt->code ||
+           vb->width   != icd->user_width ||
+           vb->height  != icd->user_height ||
+           vb->field   != field) {
+               buf->code       = icd->current_fmt->code;
+               vb->width       = icd->user_width;
+               vb->height      = icd->user_height;
+               vb->field       = field;
+               vb->state       = VIDEOBUF_NEEDS_INIT;
+       }
+
+       vb->size = bytes_per_line * vb->height;
+       if (vb->baddr && vb->bsize < vb->size) {
+               ret = -EINVAL;
+               goto out;
+       }
+
+       if (vb->state == VIDEOBUF_NEEDS_INIT) {
+               ret = videobuf_iolock(vq, vb, NULL);
+               if (ret)
+                       goto fail;
+
+               vb->state = VIDEOBUF_PREPARED;
+       }
+
+       return 0;
+
+fail:
+       free_buffer(vq, buf);
+out:
+       return ret;
+}
+
+static void mx2_videobuf_queue(struct videobuf_queue *vq,
+                              struct videobuf_buffer *vb)
+{
+       struct soc_camera_device *icd = vq->priv_data;
+       struct soc_camera_host *ici =
+               to_soc_camera_host(icd->dev.parent);
+       struct mx2_camera_dev *pcdev = ici->priv;
+       struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
+       unsigned long flags;
+
+       dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
+               vb, vb->baddr, vb->bsize);
+
+       spin_lock_irqsave(&pcdev->lock, flags);
+
+       vb->state = VIDEOBUF_QUEUED;
+       list_add_tail(&vb->queue, &pcdev->capture);
+
+       if (mx27_camera_emma(pcdev)) {
+               goto out;
+#ifdef CONFIG_MACH_MX27
+       } else if (cpu_is_mx27()) {
+               int ret;
+
+               if (pcdev->active == NULL) {
+                       ret = imx_dma_setup_single(pcdev->dma,
+                                       videobuf_to_dma_contig(vb), vb->size,
+                                       (u32)pcdev->base_dma + 0x10,
+                                       DMA_MODE_READ);
+                       if (ret) {
+                               vb->state = VIDEOBUF_ERROR;
+                               wake_up(&vb->done);
+                               goto out;
+                       }
+
+                       vb->state = VIDEOBUF_ACTIVE;
+                       pcdev->active = buf;
+               }
+#endif
+       } else { /* cpu_is_mx25() */
+               u32 csicr3, dma_inten = 0;
+
+               if (pcdev->fb1_active == NULL) {
+                       writel(videobuf_to_dma_contig(vb),
+                                       pcdev->base_csi + CSIDMASA_FB1);
+                       pcdev->fb1_active = buf;
+                       dma_inten = CSICR1_FB1_DMA_INTEN;
+               } else if (pcdev->fb2_active == NULL) {
+                       writel(videobuf_to_dma_contig(vb),
+                                       pcdev->base_csi + CSIDMASA_FB2);
+                       pcdev->fb2_active = buf;
+                       dma_inten = CSICR1_FB2_DMA_INTEN;
+               }
+
+               if (dma_inten) {
+                       list_del(&vb->queue);
+                       vb->state = VIDEOBUF_ACTIVE;
+
+                       csicr3 = readl(pcdev->base_csi + CSICR3);
+
+                       /* Reflash DMA */
+                       writel(csicr3 | CSICR3_DMA_REFLASH_RFF,
+                                       pcdev->base_csi + CSICR3);
+
+                       /* clear & enable interrupts */
+                       writel(dma_inten, pcdev->base_csi + CSISR);
+                       pcdev->csicr1 |= dma_inten;
+                       writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
+
+                       /* enable DMA */
+                       csicr3 |= CSICR3_DMA_REQ_EN_RFF | CSICR3_RXFF_LEVEL(1);
+                       writel(csicr3, pcdev->base_csi + CSICR3);
+               }
+       }
+
+out:
+       spin_unlock_irqrestore(&pcdev->lock, flags);
+}
+
+static void mx2_videobuf_release(struct videobuf_queue *vq,
+                                struct videobuf_buffer *vb)
+{
+       struct soc_camera_device *icd = vq->priv_data;
+       struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
+       struct mx2_camera_dev *pcdev = ici->priv;
+       struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
+       unsigned long flags;
+
+#ifdef DEBUG
+       dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
+               vb, vb->baddr, vb->bsize);
+
+       switch (vb->state) {
+       case VIDEOBUF_ACTIVE:
+               dev_info(&icd->dev, "%s (active)\n", __func__);
+               break;
+       case VIDEOBUF_QUEUED:
+               dev_info(&icd->dev, "%s (queued)\n", __func__);
+               break;
+       case VIDEOBUF_PREPARED:
+               dev_info(&icd->dev, "%s (prepared)\n", __func__);
+               break;
+       default:
+               dev_info(&icd->dev, "%s (unknown) %d\n", __func__,
+                               vb->state);
+               break;
+       }
+#endif
+
+       /*
+        * Terminate only queued but inactive buffers. Active buffers are
+        * released when they become inactive after videobuf_waiton().
+        *
+        * FIXME: implement forced termination of active buffers, so that the
+        * user won't get stuck in an uninterruptible state. This requires a
+        * specific handling for each of the three DMA types that this driver
+        * supports.
+        */
+       spin_lock_irqsave(&pcdev->lock, flags);
+       if (vb->state == VIDEOBUF_QUEUED) {
+               list_del(&vb->queue);
+               vb->state = VIDEOBUF_ERROR;
+       }
+       spin_unlock_irqrestore(&pcdev->lock, flags);
+
+       free_buffer(vq, buf);
+}
+
+static struct videobuf_queue_ops mx2_videobuf_ops = {
+       .buf_setup      = mx2_videobuf_setup,
+       .buf_prepare    = mx2_videobuf_prepare,
+       .buf_queue      = mx2_videobuf_queue,
+       .buf_release    = mx2_videobuf_release,
+};
+
+static void mx2_camera_init_videobuf(struct videobuf_queue *q,
+                             struct soc_camera_device *icd)
+{
+       struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
+       struct mx2_camera_dev *pcdev = ici->priv;
+
+       videobuf_queue_dma_contig_init(q, &mx2_videobuf_ops, pcdev->dev,
+                       &pcdev->lock, V4L2_BUF_TYPE_VIDEO_CAPTURE,
+                       V4L2_FIELD_NONE, sizeof(struct mx2_buffer), icd);
+}
+
+#define MX2_BUS_FLAGS  (SOCAM_DATAWIDTH_8 | \
+                       SOCAM_MASTER | \
+                       SOCAM_VSYNC_ACTIVE_HIGH | \
+                       SOCAM_VSYNC_ACTIVE_LOW | \
+                       SOCAM_HSYNC_ACTIVE_HIGH | \
+                       SOCAM_HSYNC_ACTIVE_LOW | \
+                       SOCAM_PCLK_SAMPLE_RISING | \
+                       SOCAM_PCLK_SAMPLE_FALLING | \
+                       SOCAM_DATA_ACTIVE_HIGH | \
+                       SOCAM_DATA_ACTIVE_LOW)
+
+static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev)
+{
+       u32 cntl;
+       int count = 0;
+
+       cntl = readl(pcdev->base_emma + PRP_CNTL);
+       writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL);
+       while (count++ < 100) {
+               if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST))
+                       return 0;
+               barrier();
+               udelay(1);
+       }
+
+       return -ETIMEDOUT;
+}
+
+static void mx27_camera_emma_buf_init(struct soc_camera_device *icd,
+               int bytesperline)
+{
+       struct soc_camera_host *ici =
+               to_soc_camera_host(icd->dev.parent);
+       struct mx2_camera_dev *pcdev = ici->priv;
+
+       writel(pcdev->discard_buffer_dma,
+                       pcdev->base_emma + PRP_DEST_RGB1_PTR);
+       writel(pcdev->discard_buffer_dma,
+                       pcdev->base_emma + PRP_DEST_RGB2_PTR);
+
+       /*
+        * We only use the EMMA engine to get rid of the broken
+        * DMA Engine. No color space consversion at the moment.
+        * We adjust incoming and outgoing pixelformat to rgb16
+        * and adjust the bytesperline accordingly.
+        */
+       writel(PRP_CNTL_CH1EN |
+                       PRP_CNTL_CSIEN |
+                       PRP_CNTL_DATA_IN_RGB16 |
+                       PRP_CNTL_CH1_OUT_RGB16 |
+                       PRP_CNTL_CH1_LEN |
+                       PRP_CNTL_CH1BYP |
+                       PRP_CNTL_CH1_TSKIP(0) |
+                       PRP_CNTL_IN_TSKIP(0),
+                       pcdev->base_emma + PRP_CNTL);
+
+       writel(((bytesperline >> 1) << 16) | icd->user_height,
+                       pcdev->base_emma + PRP_SRC_FRAME_SIZE);
+       writel(((bytesperline >> 1) << 16) | icd->user_height,
+                       pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE);
+       writel(bytesperline,
+                       pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE);
+       writel(0x2ca00565, /* RGB565 */
+                       pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL);
+       writel(0x2ca00565, /* RGB565 */
+                       pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL);
+
+       /* Enable interrupts */
+       writel(PRP_INTR_RDERR |
+                       PRP_INTR_CH1WERR |
+                       PRP_INTR_CH2WERR |
+                       PRP_INTR_CH1FC |
+                       PRP_INTR_CH2FC |
+                       PRP_INTR_LBOVF |
+                       PRP_INTR_CH2OVF,
+                       pcdev->base_emma + PRP_INTR_CNTL);
+}
+
+static int mx2_camera_set_bus_param(struct soc_camera_device *icd,
+               __u32 pixfmt)
+{
+       struct soc_camera_host *ici =
+               to_soc_camera_host(icd->dev.parent);
+       struct mx2_camera_dev *pcdev = ici->priv;
+       unsigned long camera_flags, common_flags;
+       int ret = 0;
+       int bytesperline;
+       u32 csicr1 = pcdev->csicr1;
+
+       camera_flags = icd->ops->query_bus_param(icd);
+
+       common_flags = soc_camera_bus_param_compatible(camera_flags,
+                               MX2_BUS_FLAGS);
+       if (!common_flags)
+               return -EINVAL;
+
+       if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
+           (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
+               if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH)
+                       common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
+               else
+                       common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
+       }
+
+       if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
+           (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
+               if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING)
+                       common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
+               else
+                       common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
+       }
+
+       ret = icd->ops->set_bus_param(icd, common_flags);
+       if (ret < 0)
+               return ret;
+
+       if (common_flags & SOCAM_PCLK_SAMPLE_FALLING)
+               csicr1 |= CSICR1_INV_PCLK;
+       if (common_flags & SOCAM_VSYNC_ACTIVE_HIGH)
+               csicr1 |= CSICR1_SOF_POL;
+       if (common_flags & SOCAM_HSYNC_ACTIVE_HIGH)
+               csicr1 |= CSICR1_HSYNC_POL;
+       if (pcdev->platform_flags & MX2_CAMERA_SWAP16)
+               csicr1 |= CSICR1_SWAP16_EN;
+       if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC)
+               csicr1 |= CSICR1_EXT_VSYNC;
+       if (pcdev->platform_flags & MX2_CAMERA_CCIR)
+               csicr1 |= CSICR1_CCIR_EN;
+       if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE)
+               csicr1 |= CSICR1_CCIR_MODE;
+       if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK)
+               csicr1 |= CSICR1_GCLK_MODE;
+       if (pcdev->platform_flags & MX2_CAMERA_INV_DATA)
+               csicr1 |= CSICR1_INV_DATA;
+       if (pcdev->platform_flags & MX2_CAMERA_PACK_DIR_MSB)
+               csicr1 |= CSICR1_PACK_DIR;
+
+       pcdev->csicr1 = csicr1;
+
+       bytesperline = soc_mbus_bytes_per_line(icd->user_width,
+                       icd->current_fmt->host_fmt);
+       if (bytesperline < 0)
+               return bytesperline;
+
+       if (mx27_camera_emma(pcdev)) {
+               ret = mx27_camera_emma_prp_reset(pcdev);
+               if (ret)
+                       return ret;
+
+               if (pcdev->discard_buffer)
+                       dma_free_coherent(ici->v4l2_dev.dev,
+                               pcdev->discard_size, pcdev->discard_buffer,
+                               pcdev->discard_buffer_dma);
+
+               /*
+                * I didn't manage to properly enable/disable the prp
+                * on a per frame basis during running transfers,
+                * thus we allocate a buffer here and use it to
+                * discard frames when no buffer is available.
+                * Feel free to work on this ;)
+                */
+               pcdev->discard_size = icd->user_height * bytesperline;
+               pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev,
+                               pcdev->discard_size, &pcdev->discard_buffer_dma,
+                               GFP_KERNEL);
+               if (!pcdev->discard_buffer)
+                       return -ENOMEM;
+
+               mx27_camera_emma_buf_init(icd, bytesperline);
+       } else if (cpu_is_mx25()) {
+               writel((bytesperline * icd->user_height) >> 2,
+                               pcdev->base_csi + CSIRXCNT);
+               writel((bytesperline << 16) | icd->user_height,
+                               pcdev->base_csi + CSIIMAG_PARA);
+       }
+
+       writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
+
+       return 0;
+}
+
+static int mx2_camera_set_crop(struct soc_camera_device *icd,
+                               struct v4l2_crop *a)
+{
+       struct v4l2_rect *rect = &a->c;
+       struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
+       struct v4l2_mbus_framefmt mf;
+       int ret;
+
+       soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
+       soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
+
+       ret = v4l2_subdev_call(sd, video, s_crop, a);
+       if (ret < 0)
+               return ret;
+
+       /* The capture device might have changed its output  */
+       ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
+       if (ret < 0)
+               return ret;
+
+       dev_dbg(icd->dev.parent, "Sensor cropped %dx%d\n",
+               mf.width, mf.height);
+
+       icd->user_width         = mf.width;
+       icd->user_height        = mf.height;
+
+       return ret;
+}
+
+static int mx2_camera_set_fmt(struct soc_camera_device *icd,
+                              struct v4l2_format *f)
+{
+       struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
+       struct mx2_camera_dev *pcdev = ici->priv;
+       struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
+       const struct soc_camera_format_xlate *xlate;
+       struct v4l2_pix_format *pix = &f->fmt.pix;
+       struct v4l2_mbus_framefmt mf;
+       int ret;
+
+       xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
+       if (!xlate) {
+               dev_warn(icd->dev.parent, "Format %x not found\n",
+                               pix->pixelformat);
+               return -EINVAL;
+       }
+
+       /* eMMA can only do RGB565 */
+       if (mx27_camera_emma(pcdev) && pix->pixelformat != V4L2_PIX_FMT_RGB565)
+               return -EINVAL;
+
+       mf.width        = pix->width;
+       mf.height       = pix->height;
+       mf.field        = pix->field;
+       mf.colorspace   = pix->colorspace;
+       mf.code         = xlate->code;
+
+       ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
+       if (ret < 0 && ret != -ENOIOCTLCMD)
+               return ret;
+
+       if (mf.code != xlate->code)
+               return -EINVAL;
+
+       pix->width              = mf.width;
+       pix->height             = mf.height;
+       pix->field              = mf.field;
+       pix->colorspace         = mf.colorspace;
+       icd->current_fmt        = xlate;
+
+       return 0;
+}
+
+static int mx2_camera_try_fmt(struct soc_camera_device *icd,
+                                 struct v4l2_format *f)
+{
+       struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
+       struct mx2_camera_dev *pcdev = ici->priv;
+       struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
+       const struct soc_camera_format_xlate *xlate;
+       struct v4l2_pix_format *pix = &f->fmt.pix;
+       struct v4l2_mbus_framefmt mf;
+       __u32 pixfmt = pix->pixelformat;
+       unsigned int width_limit;
+       int ret;
+
+       xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
+       if (pixfmt && !xlate) {
+               dev_warn(icd->dev.parent, "Format %x not found\n", pixfmt);
+               return -EINVAL;
+       }
+
+       /* FIXME: implement MX27 limits */
+
+       /* eMMA can only do RGB565 */
+       if (mx27_camera_emma(pcdev) && pixfmt != V4L2_PIX_FMT_RGB565)
+               return -EINVAL;
+
+       /* limit to MX25 hardware capabilities */
+       if (cpu_is_mx25()) {
+               if (xlate->host_fmt->bits_per_sample <= 8)
+                       width_limit = 0xffff * 4;
+               else
+                       width_limit = 0xffff * 2;
+               /* CSIIMAG_PARA limit */
+               if (pix->width > width_limit)
+                       pix->width = width_limit;
+               if (pix->height > 0xffff)
+                       pix->height = 0xffff;
+
+               pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
+                               xlate->host_fmt);
+               if (pix->bytesperline < 0)
+                       return pix->bytesperline;
+               pix->sizeimage = pix->height * pix->bytesperline;
+               if (pix->sizeimage > (4 * 0x3ffff)) { /* CSIRXCNT limit */
+                       dev_warn(icd->dev.parent,
+                                       "Image size (%u) above limit\n",
+                                       pix->sizeimage);
+                       return -EINVAL;
+               }
+       }
+
+       /* limit to sensor capabilities */
+       mf.width        = pix->width;
+       mf.height       = pix->height;
+       mf.field        = pix->field;
+       mf.colorspace   = pix->colorspace;
+       mf.code         = xlate->code;
+
+       ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
+       if (ret < 0)
+               return ret;
+
+       if (mf.field == V4L2_FIELD_ANY)
+               mf.field = V4L2_FIELD_NONE;
+       if (mf.field != V4L2_FIELD_NONE) {
+               dev_err(icd->dev.parent, "Field type %d unsupported.\n",
+                               mf.field);
+               return -EINVAL;
+       }
+
+       pix->width      = mf.width;
+       pix->height     = mf.height;
+       pix->field      = mf.field;
+       pix->colorspace = mf.colorspace;
+
+       return 0;
+}
+
+static int mx2_camera_querycap(struct soc_camera_host *ici,
+                              struct v4l2_capability *cap)
+{
+       /* cap->name is set by the friendly caller:-> */
+       strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card));
+       cap->version = MX2_CAM_VERSION_CODE;
+       cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
+
+       return 0;
+}
+
+static int mx2_camera_reqbufs(struct soc_camera_file *icf,
+                             struct v4l2_requestbuffers *p)
+{
+       int i;
+
+       for (i = 0; i < p->count; i++) {
+               struct mx2_buffer *buf = container_of(icf->vb_vidq.bufs[i],
+                                                     struct mx2_buffer, vb);
+               INIT_LIST_HEAD(&buf->vb.queue);
+       }
+
+       return 0;
+}
+
+#ifdef CONFIG_MACH_MX27
+static void mx27_camera_frame_done(struct mx2_camera_dev *pcdev, int state)
+{
+       struct videobuf_buffer *vb;
+       struct mx2_buffer *buf;
+       unsigned long flags;
+       int ret;
+
+       spin_lock_irqsave(&pcdev->lock, flags);
+
+       if (!pcdev->active) {
+               dev_err(pcdev->dev, "%s called with no active buffer!\n",
+                               __func__);
+               goto out;
+       }
+
+       vb = &pcdev->active->vb;
+       buf = container_of(vb, struct mx2_buffer, vb);
+       WARN_ON(list_empty(&vb->queue));
+       dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
+               vb, vb->baddr, vb->bsize);
+
+       /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
+       list_del_init(&vb->queue);
+       vb->state = state;
+       do_gettimeofday(&vb->ts);
+       vb->field_count++;
+
+       wake_up(&vb->done);
+
+       if (list_empty(&pcdev->capture)) {
+               pcdev->active = NULL;
+               goto out;
+       }
+
+       pcdev->active = list_entry(pcdev->capture.next,
+                       struct mx2_buffer, vb.queue);
+
+       vb = &pcdev->active->vb;
+       vb->state = VIDEOBUF_ACTIVE;
+
+       ret = imx_dma_setup_single(pcdev->dma, videobuf_to_dma_contig(vb),
+                       vb->size, (u32)pcdev->base_dma + 0x10, DMA_MODE_READ);
+
+       if (ret) {
+               vb->state = VIDEOBUF_ERROR;
+               pcdev->active = NULL;
+               wake_up(&vb->done);
+       }
+
+out:
+       spin_unlock_irqrestore(&pcdev->lock, flags);
+}
+
+static void mx27_camera_dma_err_callback(int channel, void *data, int err)
+{
+       struct mx2_camera_dev *pcdev = data;
+
+       mx27_camera_frame_done(pcdev, VIDEOBUF_ERROR);
+}
+
+static void mx27_camera_dma_callback(int channel, void *data)
+{
+       struct mx2_camera_dev *pcdev = data;
+
+       mx27_camera_frame_done(pcdev, VIDEOBUF_DONE);
+}
+
+#define DMA_REQ_CSI_RX          31 /* FIXME: Add this to a resource */
+
+static int __devinit mx27_camera_dma_init(struct platform_device *pdev,
+               struct mx2_camera_dev *pcdev)
+{
+       int err;
+
+       pcdev->dma = imx_dma_request_by_prio("CSI RX DMA", DMA_PRIO_HIGH);
+       if (pcdev->dma < 0) {
+               dev_err(&pdev->dev, "%s failed to request DMA channel\n",
+                               __func__);
+               return pcdev->dma;
+       }
+
+       err = imx_dma_setup_handlers(pcdev->dma, mx27_camera_dma_callback,
+                                       mx27_camera_dma_err_callback, pcdev);
+       if (err) {
+               dev_err(&pdev->dev, "%s failed to set DMA callback\n",
+                               __func__);
+               goto err_out;
+       }
+
+       err = imx_dma_config_channel(pcdev->dma,
+                       IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_FIFO,
+                       IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
+                       DMA_REQ_CSI_RX, 1);
+       if (err) {
+               dev_err(&pdev->dev, "%s failed to config DMA channel\n",
+                               __func__);
+               goto err_out;
+       }
+
+       imx_dma_config_burstlen(pcdev->dma, 64);
+
+       return 0;
+
+err_out:
+       imx_dma_free(pcdev->dma);
+
+       return err;
+}
+#endif /* CONFIG_MACH_MX27 */
+
+static unsigned int mx2_camera_poll(struct file *file, poll_table *pt)
+{
+       struct soc_camera_file *icf = file->private_data;
+
+       return videobuf_poll_stream(file, &icf->vb_vidq, pt);
+}
+
+static struct soc_camera_host_ops mx2_soc_camera_host_ops = {
+       .owner          = THIS_MODULE,
+       .add            = mx2_camera_add_device,
+       .remove         = mx2_camera_remove_device,
+       .set_fmt        = mx2_camera_set_fmt,
+       .set_crop       = mx2_camera_set_crop,
+       .try_fmt        = mx2_camera_try_fmt,
+       .init_videobuf  = mx2_camera_init_videobuf,
+       .reqbufs        = mx2_camera_reqbufs,
+       .poll           = mx2_camera_poll,
+       .querycap       = mx2_camera_querycap,
+       .set_bus_param  = mx2_camera_set_bus_param,
+};
+
+static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev,
+               int bufnum, int state)
+{
+       struct mx2_buffer *buf;
+       struct videobuf_buffer *vb;
+       unsigned long phys;
+
+       if (!list_empty(&pcdev->active_bufs)) {
+               buf = list_entry(pcdev->active_bufs.next,
+                       struct mx2_buffer, vb.queue);
+
+               BUG_ON(buf->bufnum != bufnum);
+
+               vb = &buf->vb;
+#ifdef DEBUG
+               phys = videobuf_to_dma_contig(vb);
+               if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum)
+                               != phys) {
+                       dev_err(pcdev->dev, "%p != %p\n", phys,
+                                       readl(pcdev->base_emma +
+                                               PRP_DEST_RGB1_PTR +
+                                               4 * bufnum));
+               }
+#endif
+               dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, vb,
+                               vb->baddr, vb->bsize);
+
+               list_del(&vb->queue);
+               vb->state = state;
+               do_gettimeofday(&vb->ts);
+               vb->field_count++;
+
+               wake_up(&vb->done);
+       }
+
+       if (list_empty(&pcdev->capture)) {
+               writel(pcdev->discard_buffer_dma, pcdev->base_emma +
+                               PRP_DEST_RGB1_PTR + 4 * bufnum);
+               return;
+       }
+
+       buf = list_entry(pcdev->capture.next,
+                       struct mx2_buffer, vb.queue);
+
+       buf->bufnum = bufnum;
+
+       list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
+
+       vb = &buf->vb;
+       vb->state = VIDEOBUF_ACTIVE;
+
+       phys = videobuf_to_dma_contig(vb);
+       writel(phys, pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum);
+}
+
+static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data)
+{
+       struct mx2_camera_dev *pcdev = data;
+       unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS);
+       struct mx2_buffer *buf;
+
+       if (status & (1 << 7)) { /* overflow */
+               u32 cntl;
+               /*
+                * We only disable channel 1 here since this is the only
+                * enabled channel
+                *
+                * FIXME: the correct DMA overflow handling should be resetting
+                * the buffer, returning an error frame, and continuing with
+                * the next one.
+                */
+               cntl = readl(pcdev->base_emma + PRP_CNTL);
+               writel(cntl & ~PRP_CNTL_CH1EN, pcdev->base_emma + PRP_CNTL);
+               writel(cntl, pcdev->base_emma + PRP_CNTL);
+       }
+       if ((status & (3 << 5)) == (3 << 5)
+                       && !list_empty(&pcdev->active_bufs)) {
+               /*
+                * Both buffers have triggered, process the one we're expecting
+                * to first
+                */
+               buf = list_entry(pcdev->active_bufs.next,
+                       struct mx2_buffer, vb.queue);
+               mx27_camera_frame_done_emma(pcdev, buf->bufnum, VIDEOBUF_DONE);
+               status &= ~(1 << (6 - buf->bufnum)); /* mark processed */
+       }
+       if (status & (1 << 6))
+               mx27_camera_frame_done_emma(pcdev, 0, VIDEOBUF_DONE);
+       if (status & (1 << 5))
+               mx27_camera_frame_done_emma(pcdev, 1, VIDEOBUF_DONE);
+
+       writel(status, pcdev->base_emma + PRP_INTRSTATUS);
+
+       return IRQ_HANDLED;
+}
+
+static int __devinit mx27_camera_emma_init(struct mx2_camera_dev *pcdev)
+{
+       struct resource *res_emma = pcdev->res_emma;
+       int err = 0;
+
+       if (!request_mem_region(res_emma->start, resource_size(res_emma),
+                               MX2_CAM_DRV_NAME)) {
+               err = -EBUSY;
+               goto out;
+       }
+
+       pcdev->base_emma = ioremap(res_emma->start, resource_size(res_emma));
+       if (!pcdev->base_emma) {
+               err = -ENOMEM;
+               goto exit_release;
+       }
+
+       err = request_irq(pcdev->irq_emma, mx27_camera_emma_irq, 0,
+                       MX2_CAM_DRV_NAME, pcdev);
+       if (err) {
+               dev_err(pcdev->dev, "Camera EMMA interrupt register failed \n");
+               goto exit_iounmap;
+       }
+
+       pcdev->clk_emma = clk_get(NULL, "emma");
+       if (IS_ERR(pcdev->clk_emma)) {
+               err = PTR_ERR(pcdev->clk_emma);
+               goto exit_free_irq;
+       }
+
+       clk_enable(pcdev->clk_emma);
+
+       err = mx27_camera_emma_prp_reset(pcdev);
+       if (err)
+               goto exit_clk_emma_put;
+
+       return err;
+
+exit_clk_emma_put:
+       clk_disable(pcdev->clk_emma);
+       clk_put(pcdev->clk_emma);
+exit_free_irq:
+       free_irq(pcdev->irq_emma, pcdev);
+exit_iounmap:
+       iounmap(pcdev->base_emma);
+exit_release:
+       release_mem_region(res_emma->start, resource_size(res_emma));
+out:
+       return err;
+}
+
+static int __devinit mx2_camera_probe(struct platform_device *pdev)
+{
+       struct mx2_camera_dev *pcdev;
+       struct resource *res_csi, *res_emma;
+       void __iomem *base_csi;
+       int irq_csi, irq_emma;
+       irq_handler_t mx2_cam_irq_handler = cpu_is_mx25() ? mx25_camera_irq
+               : mx27_camera_irq;
+       int err = 0;
+
+       dev_dbg(&pdev->dev, "initialising\n");
+
+       res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       irq_csi = platform_get_irq(pdev, 0);
+       if (res_csi == NULL || irq_csi < 0) {
+               dev_err(&pdev->dev, "Missing platform resources data\n");
+               err = -ENODEV;
+               goto exit;
+       }
+
+       pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
+       if (!pcdev) {
+               dev_err(&pdev->dev, "Could not allocate pcdev\n");
+               err = -ENOMEM;
+               goto exit;
+       }
+
+       pcdev->clk_csi = clk_get(&pdev->dev, NULL);
+       if (IS_ERR(pcdev->clk_csi)) {
+               err = PTR_ERR(pcdev->clk_csi);
+               goto exit_kfree;
+       }
+
+       dev_dbg(&pdev->dev, "Camera clock frequency: %ld\n",
+                       clk_get_rate(pcdev->clk_csi));
+
+       /* Initialize DMA */
+#ifdef CONFIG_MACH_MX27
+       if (cpu_is_mx27()) {
+               err = mx27_camera_dma_init(pdev, pcdev);
+               if (err)
+                       goto exit_clk_put;
+       }
+#endif /* CONFIG_MACH_MX27 */
+
+       pcdev->res_csi = res_csi;
+       pcdev->pdata = pdev->dev.platform_data;
+       if (pcdev->pdata) {
+               long rate;
+
+               pcdev->platform_flags = pcdev->pdata->flags;
+
+               rate = clk_round_rate(pcdev->clk_csi, pcdev->pdata->clk * 2);
+               if (rate <= 0) {
+                       err = -ENODEV;
+                       goto exit_dma_free;
+               }
+               err = clk_set_rate(pcdev->clk_csi, rate);
+               if (err < 0)
+                       goto exit_dma_free;
+       }
+
+       INIT_LIST_HEAD(&pcdev->capture);
+       INIT_LIST_HEAD(&pcdev->active_bufs);
+       spin_lock_init(&pcdev->lock);
+
+       /*
+        * Request the regions.
+        */
+       if (!request_mem_region(res_csi->start, resource_size(res_csi),
+                               MX2_CAM_DRV_NAME)) {
+               err = -EBUSY;
+               goto exit_dma_free;
+       }
+
+       base_csi = ioremap(res_csi->start, resource_size(res_csi));
+       if (!base_csi) {
+               err = -ENOMEM;
+               goto exit_release;
+       }
+       pcdev->irq_csi = irq_csi;
+       pcdev->base_csi = base_csi;
+       pcdev->base_dma = res_csi->start;
+       pcdev->dev = &pdev->dev;
+
+       err = request_irq(pcdev->irq_csi, mx2_cam_irq_handler, 0,
+                       MX2_CAM_DRV_NAME, pcdev);
+       if (err) {
+               dev_err(pcdev->dev, "Camera interrupt register failed \n");
+               goto exit_iounmap;
+       }
+
+       if (cpu_is_mx27()) {
+               /* EMMA support */
+               res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+               irq_emma = platform_get_irq(pdev, 1);
+
+               if (res_emma && irq_emma >= 0) {
+                       dev_info(&pdev->dev, "Using EMMA\n");
+                       pcdev->use_emma = 1;
+                       pcdev->res_emma = res_emma;
+                       pcdev->irq_emma = irq_emma;
+                       if (mx27_camera_emma_init(pcdev))
+                               goto exit_free_irq;
+               }
+       }
+
+       pcdev->soc_host.drv_name        = MX2_CAM_DRV_NAME,
+       pcdev->soc_host.ops             = &mx2_soc_camera_host_ops,
+       pcdev->soc_host.priv            = pcdev;
+       pcdev->soc_host.v4l2_dev.dev    = &pdev->dev;
+       pcdev->soc_host.nr              = pdev->id;
+       err = soc_camera_host_register(&pcdev->soc_host);
+       if (err)
+               goto exit_free_emma;
+
+       return 0;
+
+exit_free_emma:
+       if (mx27_camera_emma(pcdev)) {
+               free_irq(pcdev->irq_emma, pcdev);
+               clk_disable(pcdev->clk_emma);
+               clk_put(pcdev->clk_emma);
+               iounmap(pcdev->base_emma);
+               release_mem_region(res_emma->start, resource_size(res_emma));
+       }
+exit_free_irq:
+       free_irq(pcdev->irq_csi, pcdev);
+exit_iounmap:
+       iounmap(base_csi);
+exit_release:
+       release_mem_region(res_csi->start, resource_size(res_csi));
+exit_dma_free:
+#ifdef CONFIG_MACH_MX27
+       if (cpu_is_mx27())
+               imx_dma_free(pcdev->dma);
+exit_clk_put:
+       clk_put(pcdev->clk_csi);
+#endif /* CONFIG_MACH_MX27 */
+exit_kfree:
+       kfree(pcdev);
+exit:
+       return err;
+}
+
+static int __devexit mx2_camera_remove(struct platform_device *pdev)
+{
+       struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
+       struct mx2_camera_dev *pcdev = container_of(soc_host,
+                       struct mx2_camera_dev, soc_host);
+       struct resource *res;
+
+       clk_put(pcdev->clk_csi);
+#ifdef CONFIG_MACH_MX27
+       if (cpu_is_mx27())
+               imx_dma_free(pcdev->dma);
+#endif /* CONFIG_MACH_MX27 */
+       free_irq(pcdev->irq_csi, pcdev);
+       if (mx27_camera_emma(pcdev))
+               free_irq(pcdev->irq_emma, pcdev);
+
+       soc_camera_host_unregister(&pcdev->soc_host);
+
+       iounmap(pcdev->base_csi);
+
+       if (mx27_camera_emma(pcdev)) {
+               clk_disable(pcdev->clk_emma);
+               clk_put(pcdev->clk_emma);
+               iounmap(pcdev->base_emma);
+               res = pcdev->res_emma;
+               release_mem_region(res->start, resource_size(res));
+       }
+
+       res = pcdev->res_csi;
+       release_mem_region(res->start, resource_size(res));
+
+       kfree(pcdev);
+
+       dev_info(&pdev->dev, "MX2 Camera driver unloaded\n");
+
+       return 0;
+}
+
+static struct platform_driver mx2_camera_driver = {
+       .driver         = {
+               .name   = MX2_CAM_DRV_NAME,
+       },
+       .remove         = __devexit_p(mx2_camera_remove),
+};
+
+
+static int __init mx2_camera_init(void)
+{
+       return platform_driver_probe(&mx2_camera_driver, &mx2_camera_probe);
+}
+
+static void __exit mx2_camera_exit(void)
+{
+       return platform_driver_unregister(&mx2_camera_driver);
+}
+
+module_init(mx2_camera_init);
+module_exit(mx2_camera_exit);
+
+MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver");
+MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>");
+MODULE_LICENSE("GPL");

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 26386a92f5aafbb614c3308d7c03c05f638cfc15..9b089dfb173ef987f5220d38bce0336c66b92a0f 100644 (file)
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -353,6 +353,16 @@ config VMWARE_BALLOON
          To compile this driver as a module, choose M here: the
          module will be called vmware_balloon.
 
+config ARM_CHARLCD
+       bool "ARM Ltd. Character LCD Driver"
+       depends on PLAT_VERSATILE
+       help
+         This is a driver for the character LCD found on the ARM Ltd.
+         Versatile and RealView Platform Baseboards. It doesn't do
+         very much more than display the text "ARM Linux" on the first
+         line and the Linux version on the second line, but that's
+         still useful.
+
 source "drivers/misc/c2port/Kconfig"
 source "drivers/misc/eeprom/Kconfig"
 source "drivers/misc/cb710/Kconfig"

diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 6ed06a19474acc23de3b93b732ecce25b9a55c40..67552d6e932784b2e8c19e8f0c840483a52faa65 100644 (file)
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -31,3 +31,4 @@ obj-$(CONFIG_IWMC3200TOP)      += iwmc3200top/
 obj-y                          += eeprom/
 obj-y                          += cb710/
 obj-$(CONFIG_VMWARE_BALLOON)   += vmware_balloon.o
+obj-$(CONFIG_ARM_CHARLCD)      += arm-charlcd.o

diff --git a/drivers/misc/arm-charlcd.c b/drivers/misc/arm-charlcd.c
new file mode 100644 (file)
index 0000000..9e3879e
--- /dev/null
+++ b/drivers/misc/arm-charlcd.c
@@ -0,0 +1,396 @@
+/*
+ * Driver for the on-board character LCD found on some ARM reference boards
+ * This is basically an Hitachi HD44780 LCD with a custom IP block to drive it
+ * http://en.wikipedia.org/wiki/HD44780_Character_LCD
+ * Currently it will just display the text "ARM Linux" and the linux version
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ * Author: Linus Walleij <triad@df.lth.se>
+ */
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/workqueue.h>
+#include <generated/utsrelease.h>
+
+#define DRIVERNAME "arm-charlcd"
+#define CHARLCD_TIMEOUT (msecs_to_jiffies(1000))
+
+/* Offsets to registers */
+#define CHAR_COM       0x00U
+#define CHAR_DAT       0x04U
+#define CHAR_RD                0x08U
+#define CHAR_RAW       0x0CU
+#define CHAR_MASK      0x10U
+#define CHAR_STAT      0x14U
+
+#define CHAR_RAW_CLEAR 0x00000000U
+#define CHAR_RAW_VALID 0x00000100U
+
+/* Hitachi HD44780 display commands */
+#define HD_CLEAR                       0x01U
+#define HD_HOME                                0x02U
+#define HD_ENTRYMODE                   0x04U
+#define HD_ENTRYMODE_INCREMENT         0x02U
+#define HD_ENTRYMODE_SHIFT             0x01U
+#define HD_DISPCTRL                    0x08U
+#define HD_DISPCTRL_ON                 0x04U
+#define HD_DISPCTRL_CURSOR_ON          0x02U
+#define HD_DISPCTRL_CURSOR_BLINK       0x01U
+#define HD_CRSR_SHIFT                  0x10U
+#define HD_CRSR_SHIFT_DISPLAY          0x08U
+#define HD_CRSR_SHIFT_DISPLAY_RIGHT    0x04U
+#define HD_FUNCSET                     0x20U
+#define HD_FUNCSET_8BIT                        0x10U
+#define HD_FUNCSET_2_LINES             0x08U
+#define HD_FUNCSET_FONT_5X10           0x04U
+#define HD_SET_CGRAM                   0x40U
+#define HD_SET_DDRAM                   0x80U
+#define HD_BUSY_FLAG                   0x80U
+
+/**
+ * @dev: a pointer back to containing device
+ * @phybase: the offset to the controller in physical memory
+ * @physize: the size of the physical page
+ * @virtbase: the offset to the controller in virtual memory
+ * @irq: reserved interrupt number
+ * @complete: completion structure for the last LCD command
+ */
+struct charlcd {
+       struct device *dev;
+       u32 phybase;
+       u32 physize;
+       void __iomem *virtbase;
+       int irq;
+       struct completion complete;
+       struct delayed_work init_work;
+};
+
+static irqreturn_t charlcd_interrupt(int irq, void *data)
+{
+       struct charlcd *lcd = data;
+       u8 status;
+
+       status = readl(lcd->virtbase + CHAR_STAT) & 0x01;
+       /* Clear IRQ */
+       writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW);
+       if (status)
+               complete(&lcd->complete);
+       else
+               dev_info(lcd->dev, "Spurious IRQ (%02x)\n", status);
+       return IRQ_HANDLED;
+}
+
+
+static void charlcd_wait_complete_irq(struct charlcd *lcd)
+{
+       int ret;
+
+       ret = wait_for_completion_interruptible_timeout(&lcd->complete,
+                                                       CHARLCD_TIMEOUT);
+       /* Disable IRQ after completion */
+       writel(0x00, lcd->virtbase + CHAR_MASK);
+
+       if (ret < 0) {
+               dev_err(lcd->dev,
+                       "wait_for_completion_interruptible_timeout() "
+                       "returned %d waiting for ready\n", ret);
+               return;
+       }
+
+       if (ret == 0) {
+               dev_err(lcd->dev, "charlcd controller timed out "
+                       "waiting for ready\n");
+               return;
+       }
+}
+
+static u8 charlcd_4bit_read_char(struct charlcd *lcd)
+{
+       u8 data;
+       u32 val;
+       int i;
+
+       /* If we can, use an IRQ to wait for the data, else poll */
+       if (lcd->irq >= 0)
+               charlcd_wait_complete_irq(lcd);
+       else {
+               i = 0;
+               val = 0;
+               while (!(val & CHAR_RAW_VALID) && i < 10) {
+                       udelay(100);
+                       val = readl(lcd->virtbase + CHAR_RAW);
+                       i++;
+               }
+
+               writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW);
+       }
+       msleep(1);
+
+       /* Read the 4 high bits of the data */
+       data = readl(lcd->virtbase + CHAR_RD) & 0xf0;
+
+       /*
+        * The second read for the low bits does not trigger an IRQ
+        * so in this case we have to poll for the 4 lower bits
+        */
+       i = 0;
+       val = 0;
+       while (!(val & CHAR_RAW_VALID) && i < 10) {
+               udelay(100);
+               val = readl(lcd->virtbase + CHAR_RAW);
+               i++;
+       }
+       writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW);
+       msleep(1);
+
+       /* Read the 4 low bits of the data */
+       data |= (readl(lcd->virtbase + CHAR_RD) >> 4) & 0x0f;
+
+       return data;
+}
+
+static bool charlcd_4bit_read_bf(struct charlcd *lcd)
+{
+       if (lcd->irq >= 0) {
+               /*
+                * If we'll use IRQs to wait for the busyflag, clear any
+                * pending flag and enable IRQ
+                */
+               writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW);
+               init_completion(&lcd->complete);
+               writel(0x01, lcd->virtbase + CHAR_MASK);
+       }
+       readl(lcd->virtbase + CHAR_COM);
+       return charlcd_4bit_read_char(lcd) & HD_BUSY_FLAG ? true : false;
+}
+
+static void charlcd_4bit_wait_busy(struct charlcd *lcd)
+{
+       int retries = 50;
+
+       udelay(100);
+       while (charlcd_4bit_read_bf(lcd) && retries)
+               retries--;
+       if (!retries)
+               dev_err(lcd->dev, "timeout waiting for busyflag\n");
+}
+
+static void charlcd_4bit_command(struct charlcd *lcd, u8 cmd)
+{
+       u32 cmdlo = (cmd << 4) & 0xf0;
+       u32 cmdhi = (cmd & 0xf0);
+
+       writel(cmdhi, lcd->virtbase + CHAR_COM);
+       udelay(10);
+       writel(cmdlo, lcd->virtbase + CHAR_COM);
+       charlcd_4bit_wait_busy(lcd);
+}
+
+static void charlcd_4bit_char(struct charlcd *lcd, u8 ch)
+{
+       u32 chlo = (ch << 4) & 0xf0;
+       u32 chhi = (ch & 0xf0);
+
+       writel(chhi, lcd->virtbase + CHAR_DAT);
+       udelay(10);
+       writel(chlo, lcd->virtbase + CHAR_DAT);
+       charlcd_4bit_wait_busy(lcd);
+}
+
+static void charlcd_4bit_print(struct charlcd *lcd, int line, const char *str)
+{
+       u8 offset;
+       int i;
+
+       /*
+        * We support line 0, 1
+        * Line 1 runs from 0x00..0x27
+        * Line 2 runs from 0x28..0x4f
+        */
+       if (line == 0)
+               offset = 0;
+       else if (line == 1)
+               offset = 0x28;
+       else
+               return;
+
+       /* Set offset */
+       charlcd_4bit_command(lcd, HD_SET_DDRAM | offset);
+
+       /* Send string */
+       for (i = 0; i < strlen(str) && i < 0x28; i++)
+               charlcd_4bit_char(lcd, str[i]);
+}
+
+static void charlcd_4bit_init(struct charlcd *lcd)
+{
+       /* These commands cannot be checked with the busy flag */
+       writel(HD_FUNCSET | HD_FUNCSET_8BIT, lcd->virtbase + CHAR_COM);
+       msleep(5);
+       writel(HD_FUNCSET | HD_FUNCSET_8BIT, lcd->virtbase + CHAR_COM);
+       udelay(100);
+       writel(HD_FUNCSET | HD_FUNCSET_8BIT, lcd->virtbase + CHAR_COM);
+       udelay(100);
+       /* Go to 4bit mode */
+       writel(HD_FUNCSET, lcd->virtbase + CHAR_COM);
+       udelay(100);
+       /*
+        * 4bit mode, 2 lines, 5x8 font, after this the number of lines
+        * and the font cannot be changed until the next initialization sequence
+        */
+       charlcd_4bit_command(lcd, HD_FUNCSET | HD_FUNCSET_2_LINES);
+       charlcd_4bit_command(lcd, HD_DISPCTRL | HD_DISPCTRL_ON);
+       charlcd_4bit_command(lcd, HD_ENTRYMODE | HD_ENTRYMODE_INCREMENT);
+       charlcd_4bit_command(lcd, HD_CLEAR);
+       charlcd_4bit_command(lcd, HD_HOME);
+       /* Put something useful in the display */
+       charlcd_4bit_print(lcd, 0, "ARM Linux");
+       charlcd_4bit_print(lcd, 1, UTS_RELEASE);
+}
+
+static void charlcd_init_work(struct work_struct *work)
+{
+       struct charlcd *lcd =
+               container_of(work, struct charlcd, init_work.work);
+
+       charlcd_4bit_init(lcd);
+}
+
+static int __init charlcd_probe(struct platform_device *pdev)
+{
+       int ret;
+       struct charlcd *lcd;
+       struct resource *res;
+
+       lcd = kzalloc(sizeof(struct charlcd), GFP_KERNEL);
+       if (!lcd)
+               return -ENOMEM;
+
+       lcd->dev = &pdev->dev;
+
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       if (!res) {
+               ret = -ENOENT;
+               goto out_no_resource;
+       }
+       lcd->phybase = res->start;
+       lcd->physize = resource_size(res);
+
+       if (request_mem_region(lcd->phybase, lcd->physize,
+                              DRIVERNAME) == NULL) {
+               ret = -EBUSY;
+               goto out_no_memregion;
+       }
+
+       lcd->virtbase = ioremap(lcd->phybase, lcd->physize);
+       if (!lcd->virtbase) {
+               ret = -ENOMEM;
+               goto out_no_remap;
+       }
+
+       lcd->irq = platform_get_irq(pdev, 0);
+       /* If no IRQ is supplied, we'll survive without it */
+       if (lcd->irq >= 0) {
+               if (request_irq(lcd->irq, charlcd_interrupt, IRQF_DISABLED,
+                               DRIVERNAME, lcd)) {
+                       ret = -EIO;
+                       goto out_no_irq;
+               }
+       }
+
+       platform_set_drvdata(pdev, lcd);
+
+       /*
+        * Initialize the display in a delayed work, because
+        * it is VERY slow and would slow down the boot of the system.
+        */
+       INIT_DELAYED_WORK(&lcd->init_work, charlcd_init_work);
+       schedule_delayed_work(&lcd->init_work, 0);
+
+       dev_info(&pdev->dev, "initalized ARM character LCD at %08x\n",
+               lcd->phybase);
+
+       return 0;
+
+out_no_irq:
+       iounmap(lcd->virtbase);
+out_no_remap:
+       platform_set_drvdata(pdev, NULL);
+out_no_memregion:
+       release_mem_region(lcd->phybase, SZ_4K);
+out_no_resource:
+       kfree(lcd);
+       return ret;
+}
+
+static int __exit charlcd_remove(struct platform_device *pdev)
+{
+       struct charlcd *lcd = platform_get_drvdata(pdev);
+
+       if (lcd) {
+               free_irq(lcd->irq, lcd);
+               iounmap(lcd->virtbase);
+               release_mem_region(lcd->phybase, lcd->physize);
+               platform_set_drvdata(pdev, NULL);
+               kfree(lcd);
+       }
+
+       return 0;
+}
+
+static int charlcd_suspend(struct device *dev)
+{
+       struct platform_device *pdev = to_platform_device(dev);
+       struct charlcd *lcd = platform_get_drvdata(pdev);
+
+       /* Power the display off */
+       charlcd_4bit_command(lcd, HD_DISPCTRL);
+       return 0;
+}
+
+static int charlcd_resume(struct device *dev)
+{
+       struct platform_device *pdev = to_platform_device(dev);
+       struct charlcd *lcd = platform_get_drvdata(pdev);
+
+       /* Turn the display back on */
+       charlcd_4bit_command(lcd, HD_DISPCTRL | HD_DISPCTRL_ON);
+       return 0;
+}
+
+static const struct dev_pm_ops charlcd_pm_ops = {
+       .suspend = charlcd_suspend,
+       .resume = charlcd_resume,
+};
+
+static struct platform_driver charlcd_driver = {
+       .driver = {
+               .name = DRIVERNAME,
+               .owner = THIS_MODULE,
+               .pm = &charlcd_pm_ops,
+       },
+       .remove = __exit_p(charlcd_remove),
+};
+
+static int __init charlcd_init(void)
+{
+       return platform_driver_probe(&charlcd_driver, charlcd_probe);
+}
+
+static void __exit charlcd_exit(void)
+{
+       platform_driver_unregister(&charlcd_driver);
+}
+
+module_init(charlcd_init);
+module_exit(charlcd_exit);
+
+MODULE_AUTHOR("Linus Walleij <triad@df.lth.se>");
+MODULE_DESCRIPTION("ARM Character LCD Driver");
+MODULE_LICENSE("GPL v2");

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 2ed435bd4b6c18c426640140cf39908b1d065574..840b301b567142b4e264924a14feb91c5cb54003 100644 (file)
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -26,7 +26,6 @@
 #include <linux/amba/mmci.h>
 #include <linux/regulator/consumer.h>
 
-#include <asm/cacheflush.h>
 #include <asm/div64.h>
 #include <asm/io.h>
 #include <asm/sizes.h>
@@ -37,12 +36,39 @@
 
 static unsigned int fmax = 515633;
 
+/**
+ * struct variant_data - MMCI variant-specific quirks
+ * @clkreg: default value for MCICLOCK register
+ * @clkreg_enable: enable value for MMCICLOCK register
+ * @datalength_bits: number of bits in the MMCIDATALENGTH register
+ */
+struct variant_data {
+       unsigned int            clkreg;
+       unsigned int            clkreg_enable;
+       unsigned int            datalength_bits;
+};
+
+static struct variant_data variant_arm = {
+       .datalength_bits        = 16,
+};
+
+static struct variant_data variant_u300 = {
+       .clkreg_enable          = 1 << 13, /* HWFCEN */
+       .datalength_bits        = 16,
+};
+
+static struct variant_data variant_ux500 = {
+       .clkreg                 = MCI_CLK_ENABLE,
+       .clkreg_enable          = 1 << 14, /* HWFCEN */
+       .datalength_bits        = 24,
+};
 /*
  * This must be called with host->lock held
  */
 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
 {
-       u32 clk = 0;
+       struct variant_data *variant = host->variant;
+       u32 clk = variant->clkreg;
 
        if (desired) {
                if (desired >= host->mclk) {
@@ -54,8 +80,8 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
                                clk = 255;
                        host->cclk = host->mclk / (2 * (clk + 1));
                }
-               if (host->hw_designer == AMBA_VENDOR_ST)
-                       clk |= MCI_ST_FCEN; /* Bug fix in ST IP block */
+
+               clk |= variant->clkreg_enable;
                clk |= MCI_CLK_ENABLE;
                /* This hasn't proven to be worthwhile */
                /* clk |= MCI_CLK_PWRSAVE; */
@@ -98,6 +124,18 @@ static void mmci_stop_data(struct mmci_host *host)
        host->data = NULL;
 }
 
+static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
+{
+       unsigned int flags = SG_MITER_ATOMIC;
+
+       if (data->flags & MMC_DATA_READ)
+               flags |= SG_MITER_TO_SG;
+       else
+               flags |= SG_MITER_FROM_SG;
+
+       sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
+}
+
 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
 {
        unsigned int datactrl, timeout, irqmask;
@@ -109,7 +147,7 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
                data->blksz, data->blocks, data->flags);
 
        host->data = data;
-       host->size = data->blksz;
+       host->size = data->blksz * data->blocks;
        host->data_xfered = 0;
 
        mmci_init_sg(host, data);
@@ -210,8 +248,17 @@ mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
                 * We hit an error condition.  Ensure that any data
                 * partially written to a page is properly coherent.
                 */
-               if (host->sg_len && data->flags & MMC_DATA_READ)
-                       flush_dcache_page(sg_page(host->sg_ptr));
+               if (data->flags & MMC_DATA_READ) {
+                       struct sg_mapping_iter *sg_miter = &host->sg_miter;
+                       unsigned long flags;
+
+                       local_irq_save(flags);
+                       if (sg_miter_next(sg_miter)) {
+                               flush_dcache_page(sg_miter->page);
+                               sg_miter_stop(sg_miter);
+                       }
+                       local_irq_restore(flags);
+               }
        }
        if (status & MCI_DATAEND) {
                mmci_stop_data(host);
@@ -314,15 +361,18 @@ static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int rem
 static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
 {
        struct mmci_host *host = dev_id;
+       struct sg_mapping_iter *sg_miter = &host->sg_miter;
        void __iomem *base = host->base;
+       unsigned long flags;
        u32 status;
 
        status = readl(base + MMCISTATUS);
 
        dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
 
+       local_irq_save(flags);
+
        do {
-               unsigned long flags;
                unsigned int remain, len;
                char *buffer;
 
@@ -336,11 +386,11 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
                if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
                        break;
 
-               /*
-                * Map the current scatter buffer.
-                */
-               buffer = mmci_kmap_atomic(host, &flags) + host->sg_off;
-               remain = host->sg_ptr->length - host->sg_off;
+               if (!sg_miter_next(sg_miter))
+                       break;
+
+               buffer = sg_miter->addr;
+               remain = sg_miter->length;
 
                len = 0;
                if (status & MCI_RXACTIVE)
@@ -348,31 +398,24 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
                if (status & MCI_TXACTIVE)
                        len = mmci_pio_write(host, buffer, remain, status);
 
-               /*
-                * Unmap the buffer.
-                */
-               mmci_kunmap_atomic(host, buffer, &flags);
+               sg_miter->consumed = len;
 
-               host->sg_off += len;
                host->size -= len;
                remain -= len;
 
                if (remain)
                        break;
 
-               /*
-                * If we were reading, and we have completed this
-                * page, ensure that the data cache is coherent.
-                */
                if (status & MCI_RXACTIVE)
-                       flush_dcache_page(sg_page(host->sg_ptr));
-
-               if (!mmci_next_sg(host))
-                       break;
+                       flush_dcache_page(sg_miter->page);
 
                status = readl(base + MMCISTATUS);
        } while (1);
 
+       sg_miter_stop(sg_miter);
+
+       local_irq_restore(flags);
+
        /*
         * If we're nearing the end of the read, switch to
         * "any data available" mode.
@@ -477,16 +520,9 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
                        /* This implicitly enables the regulator */
                        mmc_regulator_set_ocr(host->vcc, ios->vdd);
 #endif
-               /*
-                * The translate_vdd function is not used if you have
-                * an external regulator, or your design is really weird.
-                * Using it would mean sending in power control BOTH using
-                * a regulator AND the 4 MMCIPWR bits. If we don't have
-                * a regulator, we might have some other platform specific
-                * power control behind this translate function.
-                */
-               if (!host->vcc && host->plat->translate_vdd)
-                       pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
+               if (host->plat->vdd_handler)
+                       pwr |= host->plat->vdd_handler(mmc_dev(mmc), ios->vdd,
+                                                      ios->power_mode);
                /* The ST version does not have this, fall through to POWER_ON */
                if (host->hw_designer != AMBA_VENDOR_ST) {
                        pwr |= MCI_PWR_UP;
@@ -555,21 +591,10 @@ static const struct mmc_host_ops mmci_ops = {
        .get_cd         = mmci_get_cd,
 };
 
-static void mmci_check_status(unsigned long data)
-{
-       struct mmci_host *host = (struct mmci_host *)data;
-       unsigned int status = mmci_get_cd(host->mmc);
-
-       if (status ^ host->oldstat)
-               mmc_detect_change(host->mmc, 0);
-
-       host->oldstat = status;
-       mod_timer(&host->timer, jiffies + HZ);
-}
-
 static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
 {
        struct mmci_platform_data *plat = dev->dev.platform_data;
+       struct variant_data *variant = id->data;
        struct mmci_host *host;
        struct mmc_host *mmc;
        int ret;
@@ -613,6 +638,7 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
                goto clk_free;
 
        host->plat = plat;
+       host->variant = variant;
        host->mclk = clk_get_rate(host->clk);
        /*
         * According to the spec, mclk is max 100 MHz,
@@ -673,6 +699,7 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
        if (host->vcc == NULL)
                mmc->ocr_avail = plat->ocr_mask;
        mmc->caps = plat->capabilities;
+       mmc->caps |= MMC_CAP_NEEDS_POLL;
 
        /*
         * We can do SGIO
@@ -681,10 +708,11 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
        mmc->max_phys_segs = NR_SG;
 
        /*
-        * Since we only have a 16-bit data length register, we must
-        * ensure that we don't exceed 2^16-1 bytes in a single request.
+        * Since only a certain number of bits are valid in the data length
+        * register, we must ensure that we don't exceed 2^num-1 bytes in a
+        * single request.
         */
-       mmc->max_req_size = 65535;
+       mmc->max_req_size = (1 << variant->datalength_bits) - 1;
 
        /*
         * Set the maximum segment size.  Since we aren't doing DMA
@@ -738,7 +766,6 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
        writel(MCI_IRQENABLE, host->base + MMCIMASK0);
 
        amba_set_drvdata(dev, mmc);
-       host->oldstat = mmci_get_cd(host->mmc);
 
        mmc_add_host(mmc);
 
@@ -746,12 +773,6 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
                mmc_hostname(mmc), amba_rev(dev), amba_config(dev),
                (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]);
 
-       init_timer(&host->timer);
-       host->timer.data = (unsigned long)host;
-       host->timer.function = mmci_check_status;
-       host->timer.expires = jiffies + HZ;
-       add_timer(&host->timer);
-
        return 0;
 
  irq0_free:
@@ -785,8 +806,6 @@ static int __devexit mmci_remove(struct amba_device *dev)
        if (mmc) {
                struct mmci_host *host = mmc_priv(mmc);
 
-               del_timer_sync(&host->timer);
-
                mmc_remove_host(mmc);
 
                writel(0, host->base + MMCIMASK0);
@@ -860,19 +879,28 @@ static struct amba_id mmci_ids[] = {
        {
                .id     = 0x00041180,
                .mask   = 0x000fffff,
+               .data   = &variant_arm,
        },
        {
                .id     = 0x00041181,
                .mask   = 0x000fffff,
+               .data   = &variant_arm,
        },
        /* ST Micro variants */
        {
                .id     = 0x00180180,
                .mask   = 0x00ffffff,
+               .data   = &variant_u300,
        },
        {
                .id     = 0x00280180,
                .mask   = 0x00ffffff,
+               .data   = &variant_u300,
+       },
+       {
+               .id     = 0x00480180,
+               .mask   = 0x00ffffff,
+               .data   = &variant_ux500,
        },
        { 0, 0 },
 };

diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index d77062e5e3af5425b15d31c6609aafa784ddeff3..68970cfb81e1396ca9f5a3f817e4c7ede777d6ea 100644 (file)
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -28,8 +28,6 @@
 #define MCI_4BIT_BUS           (1 << 11)
 /* 8bit wide buses supported in ST Micro versions */
 #define MCI_ST_8BIT_BUS                (1 << 12)
-/* HW flow control on the ST Micro version */
-#define MCI_ST_FCEN            (1 << 13)
 
 #define MMCIARGUMENT           0x008
 #define MMCICOMMAND            0x00c
@@ -145,6 +143,7 @@
 #define NR_SG          16
 
 struct clk;
+struct variant_data;
 
 struct mmci_host {
        void __iomem            *base;
@@ -164,6 +163,7 @@ struct mmci_host {
        unsigned int            cclk;
        u32                     pwr;
        struct mmci_platform_data *plat;
+       struct variant_data     *variant;
 
        u8                      hw_designer;
        u8                      hw_revision:4;
@@ -171,42 +171,9 @@ struct mmci_host {
        struct timer_list       timer;
        unsigned int            oldstat;
 
-       unsigned int            sg_len;
-
        /* pio stuff */
-       struct scatterlist      *sg_ptr;
-       unsigned int            sg_off;
+       struct sg_mapping_iter  sg_miter;
        unsigned int            size;
        struct regulator        *vcc;
 };
 
-static inline void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
-{
-       /*
-        * Ideally, we want the higher levels to pass us a scatter list.
-        */
-       host->sg_len = data->sg_len;
-       host->sg_ptr = data->sg;
-       host->sg_off = 0;
-}
-
-static inline int mmci_next_sg(struct mmci_host *host)
-{
-       host->sg_ptr++;
-       host->sg_off = 0;
-       return --host->sg_len;
-}
-
-static inline char *mmci_kmap_atomic(struct mmci_host *host, unsigned long *flags)
-{
-       struct scatterlist *sg = host->sg_ptr;
-
-       local_irq_save(*flags);
-       return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
-}
-
-static inline void mmci_kunmap_atomic(struct mmci_host *host, void *buffer, unsigned long *flags)
-{
-       kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
-       local_irq_restore(*flags);
-}

diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c
index d9d4a72e0ec792d42386d21afcf327fa5b59f69c..350f78e8624511cfd1378c4b8365a2d6d956a4ae 100644 (file)
--- a/drivers/mmc/host/mxcmmc.c
+++ b/drivers/mmc/host/mxcmmc.c
@@ -119,6 +119,7 @@ struct mxcmci_host {
        int                     detect_irq;
        int                     dma;
        int                     do_dma;
+       int                     default_irq_mask;
        int                     use_sdio;
        unsigned int            power_mode;
        struct imxmmc_platform_data *pdata;
@@ -228,7 +229,7 @@ static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
 static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
                unsigned int cmdat)
 {
-       u32 int_cntr;
+       u32 int_cntr = host->default_irq_mask;
        unsigned long flags;
 
        WARN_ON(host->cmd != NULL);
@@ -275,7 +276,7 @@ static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
 static void mxcmci_finish_request(struct mxcmci_host *host,
                struct mmc_request *req)
 {
-       u32 int_cntr = 0;
+       u32 int_cntr = host->default_irq_mask;
        unsigned long flags;
 
        spin_lock_irqsave(&host->lock, flags);
@@ -585,6 +586,9 @@ static irqreturn_t mxcmci_irq(int irq, void *devid)
                  (stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE)))
                mxcmci_data_done(host, stat);
 #endif
+       if (host->default_irq_mask &&
+                 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL)))
+               mmc_detect_change(host->mmc, msecs_to_jiffies(200));
        return IRQ_HANDLED;
 }
 
@@ -809,6 +813,12 @@ static int mxcmci_probe(struct platform_device *pdev)
        else
                mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
 
+       if (host->pdata && host->pdata->dat3_card_detect)
+               host->default_irq_mask =
+                       INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN;
+       else
+               host->default_irq_mask = 0;
+
        host->res = r;
        host->irq = irq;
 
@@ -835,7 +845,7 @@ static int mxcmci_probe(struct platform_device *pdev)
        /* recommended in data sheet */
        writew(0x2db4, host->base + MMC_REG_READ_TO);
 
-       writel(0, host->base + MMC_REG_INT_CNTR);
+       writel(host->default_irq_mask, host->base + MMC_REG_INT_CNTR);
 
 #ifdef HAS_DMA
        host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW);
@@ -926,43 +936,47 @@ static int mxcmci_remove(struct platform_device *pdev)
 }
 
 #ifdef CONFIG_PM
-static int mxcmci_suspend(struct platform_device *dev, pm_message_t state)
+static int mxcmci_suspend(struct device *dev)
 {
-       struct mmc_host *mmc = platform_get_drvdata(dev);
+       struct mmc_host *mmc = dev_get_drvdata(dev);
+       struct mxcmci_host *host = mmc_priv(mmc);
        int ret = 0;
 
        if (mmc)
                ret = mmc_suspend_host(mmc);
+       clk_disable(host->clk);
 
        return ret;
 }
 
-static int mxcmci_resume(struct platform_device *dev)
+static int mxcmci_resume(struct device *dev)
 {
-       struct mmc_host *mmc = platform_get_drvdata(dev);
-       struct mxcmci_host *host;
+       struct mmc_host *mmc = dev_get_drvdata(dev);
+       struct mxcmci_host *host = mmc_priv(mmc);
        int ret = 0;
 
-       if (mmc) {
-               host = mmc_priv(mmc);
+       clk_enable(host->clk);
+       if (mmc)
                ret = mmc_resume_host(mmc);
-       }
 
        return ret;
 }
-#else
-#define mxcmci_suspend  NULL
-#define mxcmci_resume   NULL
-#endif /* CONFIG_PM */
+
+static const struct dev_pm_ops mxcmci_pm_ops = {
+       .suspend        = mxcmci_suspend,
+       .resume         = mxcmci_resume,
+};
+#endif
 
 static struct platform_driver mxcmci_driver = {
        .probe          = mxcmci_probe,
        .remove         = mxcmci_remove,
-       .suspend        = mxcmci_suspend,
-       .resume         = mxcmci_resume,
        .driver         = {
                .name           = DRIVER_NAME,
                .owner          = THIS_MODULE,
+#ifdef CONFIG_PM
+               .pm     = &mxcmci_pm_ops,
+#endif
        }
 };
 

diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index 82e94389824e74e2c8ca6b8007da09475dc5b1da..0d76b169482f47afff1bbb4f09696c771e3f829e 100644 (file)
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -623,8 +623,7 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
                else
                        host->buf_start = column + mtd->writesize;
 
-               if (mtd->writesize > 512)
-                       command = NAND_CMD_READ0; /* only READ0 is valid */
+               command = NAND_CMD_READ0; /* only READ0 is valid */
 
                send_cmd(host, command, false);
                mxc_do_addr_cycle(mtd, column, page_addr);
@@ -639,31 +638,11 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
                break;
 
        case NAND_CMD_SEQIN:
-               if (column >= mtd->writesize) {
-                       /*
-                        * FIXME: before send SEQIN command for write OOB,
-                        * We must read one page out.
-                        * For K9F1GXX has no READ1 command to set current HW
-                        * pointer to spare area, we must write the whole page
-                        * including OOB together.
-                        */
-                       if (mtd->writesize > 512)
-                               /* call ourself to read a page */
-                               mxc_nand_command(mtd, NAND_CMD_READ0, 0,
-                                               page_addr);
-
-                       host->buf_start = column;
-
-                       /* Set program pointer to spare region */
-                       if (mtd->writesize == 512)
-                               send_cmd(host, NAND_CMD_READOOB, false);
-               } else {
-                       host->buf_start = column;
+               if (column >= mtd->writesize)
+                       /* call ourself to read a page */
+                       mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
 
-                       /* Set program pointer to page start */
-                       if (mtd->writesize == 512)
-                               send_cmd(host, NAND_CMD_READ0, false);
-               }
+               host->buf_start = column;
 
                send_cmd(host, command, false);
                mxc_do_addr_cycle(mtd, column, page_addr);
@@ -853,6 +832,8 @@ static int __init mxcnd_probe(struct platform_device *pdev)
            parse_mtd_partitions(mtd, part_probes, &host->parts, 0);
        if (nr_parts > 0)
                add_mtd_partitions(mtd, host->parts, nr_parts);
+       else if (pdata->parts)
+               add_mtd_partitions(mtd, pdata->parts, pdata->nr_parts);
        else
 #endif
        {

diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index ee87325c7712a8eeee4bbc683f93014c9901f337..133d51528f8dc0fb79eae4d12230e1a65bd7595e 100644 (file)
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -7,6 +7,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#define CONFIG_MTD_NAND_OMAP_HWECC
 
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
@@ -23,20 +24,8 @@
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 
-#define GPMC_IRQ_STATUS                0x18
-#define GPMC_ECC_CONFIG                0x1F4
-#define GPMC_ECC_CONTROL       0x1F8
-#define GPMC_ECC_SIZE_CONFIG   0x1FC
-#define GPMC_ECC1_RESULT       0x200
-
 #define        DRIVER_NAME     "omap2-nand"
 
-#define        NAND_WP_OFF     0
-#define NAND_WP_BIT    0x00000010
-
-#define        GPMC_BUF_FULL   0x00000001
-#define        GPMC_BUF_EMPTY  0x00000000
-
 #define NAND_Ecc_P1e           (1 << 0)
 #define NAND_Ecc_P2e           (1 << 1)
 #define NAND_Ecc_P4e           (1 << 2)
@@ -139,33 +128,10 @@ struct omap_nand_info {
 
        int                             gpmc_cs;
        unsigned long                   phys_base;
-       void __iomem                    *gpmc_cs_baseaddr;
-       void __iomem                    *gpmc_baseaddr;
-       void __iomem                    *nand_pref_fifo_add;
        struct completion               comp;
        int                             dma_ch;
 };
 
-/**
- * omap_nand_wp - This function enable or disable the Write Protect feature
- * @mtd: MTD device structure
- * @mode: WP ON/OFF
- */
-static void omap_nand_wp(struct mtd_info *mtd, int mode)
-{
-       struct omap_nand_info *info = container_of(mtd,
-                                               struct omap_nand_info, mtd);
-
-       unsigned long config = __raw_readl(info->gpmc_baseaddr + GPMC_CONFIG);
-
-       if (mode)
-               config &= ~(NAND_WP_BIT);       /* WP is ON */
-       else
-               config |= (NAND_WP_BIT);        /* WP is OFF */
-
-       __raw_writel(config, (info->gpmc_baseaddr + GPMC_CONFIG));
-}
-
 /**
  * omap_hwcontrol - hardware specific access to control-lines
  * @mtd: MTD device structure
@@ -181,31 +147,17 @@ static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
        struct omap_nand_info *info = container_of(mtd,
                                        struct omap_nand_info, mtd);
-       switch (ctrl) {
-       case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
-               info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr +
-                                               GPMC_CS_NAND_COMMAND;
-               info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr +
-                                               GPMC_CS_NAND_DATA;
-               break;
-
-       case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
-               info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr +
-                                               GPMC_CS_NAND_ADDRESS;
-               info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr +
-                                               GPMC_CS_NAND_DATA;
-               break;
-
-       case NAND_CTRL_CHANGE | NAND_NCE:
-               info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr +
-                                               GPMC_CS_NAND_DATA;
-               info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr +
-                                               GPMC_CS_NAND_DATA;
-               break;
-       }
 
-       if (cmd != NAND_CMD_NONE)
-               __raw_writeb(cmd, info->nand.IO_ADDR_W);
+       if (cmd != NAND_CMD_NONE) {
+               if (ctrl & NAND_CLE)
+                       gpmc_nand_write(info->gpmc_cs, GPMC_NAND_COMMAND, cmd);
+
+               else if (ctrl & NAND_ALE)
+                       gpmc_nand_write(info->gpmc_cs, GPMC_NAND_ADDRESS, cmd);
+
+               else /* NAND_NCE */
+                       gpmc_nand_write(info->gpmc_cs, GPMC_NAND_DATA, cmd);
+       }
 }
 
 /**
@@ -232,11 +184,14 @@ static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
        struct omap_nand_info *info = container_of(mtd,
                                                struct omap_nand_info, mtd);
        u_char *p = (u_char *)buf;
+       u32     status = 0;
 
        while (len--) {
                iowrite8(*p++, info->nand.IO_ADDR_W);
-               while (GPMC_BUF_EMPTY == (readl(info->gpmc_baseaddr +
-                                               GPMC_STATUS) & GPMC_BUF_FULL));
+               /* wait until buffer is available for write */
+               do {
+                       status = gpmc_read_status(GPMC_STATUS_BUFFER);
+               } while (!status);
        }
 }
 
@@ -264,16 +219,16 @@ static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
        struct omap_nand_info *info = container_of(mtd,
                                                struct omap_nand_info, mtd);
        u16 *p = (u16 *) buf;
-
+       u32     status = 0;
        /* FIXME try bursts of writesw() or DMA ... */
        len >>= 1;
 
        while (len--) {
                iowrite16(*p++, info->nand.IO_ADDR_W);
-
-               while (GPMC_BUF_EMPTY == (readl(info->gpmc_baseaddr +
-                                               GPMC_STATUS) & GPMC_BUF_FULL))
-                       ;
+               /* wait until buffer is available for write */
+               do {
+                       status = gpmc_read_status(GPMC_STATUS_BUFFER);
+               } while (!status);
        }
 }
 
@@ -287,7 +242,7 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
 {
        struct omap_nand_info *info = container_of(mtd,
                                                struct omap_nand_info, mtd);
-       uint32_t pfpw_status = 0, r_count = 0;
+       uint32_t r_count = 0;
        int ret = 0;
        u32 *p = (u32 *)buf;
 
@@ -310,16 +265,16 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
                else
                        omap_read_buf8(mtd, buf, len);
        } else {
+               p = (u32 *) buf;
                do {
-                       pfpw_status = gpmc_prefetch_status();
-                       r_count = ((pfpw_status >> 24) & 0x7F) >> 2;
-                       ioread32_rep(info->nand_pref_fifo_add, p, r_count);
+                       r_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
+                       r_count = r_count >> 2;
+                       ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
                        p += r_count;
                        len -= r_count << 2;
                } while (len);
-
                /* disable and stop the PFPW engine */
-               gpmc_prefetch_reset();
+               gpmc_prefetch_reset(info->gpmc_cs);
        }
 }
 
@@ -334,13 +289,13 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
 {
        struct omap_nand_info *info = container_of(mtd,
                                                struct omap_nand_info, mtd);
-       uint32_t pfpw_status = 0, w_count = 0;
+       uint32_t pref_count = 0, w_count = 0;
        int i = 0, ret = 0;
-       u16 *p = (u16 *) buf;
+       u16 *p;
 
        /* take care of subpage writes */
        if (len % 2 != 0) {
-               writeb(*buf, info->nand.IO_ADDR_R);
+               writeb(*buf, info->nand.IO_ADDR_W);
                p = (u16 *)(buf + 1);
                len--;
        }
@@ -354,16 +309,19 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
                else
                        omap_write_buf8(mtd, buf, len);
        } else {
-               pfpw_status = gpmc_prefetch_status();
-               while (pfpw_status & 0x3FFF) {
-                       w_count = ((pfpw_status >> 24) & 0x7F) >> 1;
+               p = (u16 *) buf;
+               while (len) {
+                       w_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
+                       w_count = w_count >> 1;
                        for (i = 0; (i < w_count) && len; i++, len -= 2)
-                               iowrite16(*p++, info->nand_pref_fifo_add);
-                       pfpw_status = gpmc_prefetch_status();
+                               iowrite16(*p++, info->nand.IO_ADDR_W);
                }
-
+               /* wait for data to flushed-out before reset the prefetch */
+               do {
+                       pref_count = gpmc_read_status(GPMC_PREFETCH_COUNT);
+               } while (pref_count);
                /* disable and stop the PFPW engine */
-               gpmc_prefetch_reset();
+               gpmc_prefetch_reset(info->gpmc_cs);
        }
 }
 
@@ -451,8 +409,9 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
        /* setup and start DMA using dma_addr */
        wait_for_completion(&info->comp);
 
-       while (0x3fff & (prefetch_status = gpmc_prefetch_status()))
-               ;
+       do {
+               prefetch_status = gpmc_read_status(GPMC_PREFETCH_COUNT);
+       } while (prefetch_status);
        /* disable and stop the PFPW engine */
        gpmc_prefetch_reset();
 
@@ -530,29 +489,6 @@ static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
 }
 
 #ifdef CONFIG_MTD_NAND_OMAP_HWECC
-/**
- * omap_hwecc_init - Initialize the HW ECC for NAND flash in GPMC controller
- * @mtd: MTD device structure
- */
-static void omap_hwecc_init(struct mtd_info *mtd)
-{
-       struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
-                                                       mtd);
-       struct nand_chip *chip = mtd->priv;
-       unsigned long val = 0x0;
-
-       /* Read from ECC Control Register */
-       val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_CONTROL);
-       /* Clear all ECC | Enable Reg1 */
-       val = ((0x00000001<<8) | 0x00000001);
-       __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
-
-       /* Read from ECC Size Config Register */
-       val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG);
-       /* ECCSIZE1=512 | Select eccResultsize[0-3] */
-       val = ((((chip->ecc.size >> 1) - 1) << 22) | (0x0000000F));
-       __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG);
-}
 
 /**
  * gen_true_ecc - This function will generate true ECC value
@@ -755,19 +691,7 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 {
        struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
                                                        mtd);
-       unsigned long val = 0x0;
-       unsigned long reg;
-
-       /* Start Reading from HW ECC1_Result = 0x200 */
-       reg = (unsigned long)(info->gpmc_baseaddr + GPMC_ECC1_RESULT);
-       val = __raw_readl(reg);
-       *ecc_code++ = val;          /* P128e, ..., P1e */
-       *ecc_code++ = val >> 16;    /* P128o, ..., P1o */
-       /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
-       *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
-       reg += 4;
-
-       return 0;
+       return gpmc_calculate_ecc(info->gpmc_cs, dat, ecc_code);
 }
 
 /**
@@ -781,32 +705,10 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
                                                        mtd);
        struct nand_chip *chip = mtd->priv;
        unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
-       unsigned long val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_CONFIG);
-
-       switch (mode) {
-       case NAND_ECC_READ:
-               __raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
-               /* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
-               val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
-               break;
-       case NAND_ECC_READSYN:
-                __raw_writel(0x100, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
-               /* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
-               val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
-               break;
-       case NAND_ECC_WRITE:
-               __raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
-               /* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
-               val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
-               break;
-       default:
-               DEBUG(MTD_DEBUG_LEVEL0, "Error: Unrecognized Mode[%d]!\n",
-                                       mode);
-               break;
-       }
 
-       __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_CONFIG);
+       gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size);
 }
+
 #endif
 
 /**
@@ -834,14 +736,10 @@ static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
        else
                timeo += (HZ * 20) / 1000;
 
-       this->IO_ADDR_W = (void *) info->gpmc_cs_baseaddr +
-                                               GPMC_CS_NAND_COMMAND;
-       this->IO_ADDR_R = (void *) info->gpmc_cs_baseaddr + GPMC_CS_NAND_DATA;
-
-       __raw_writeb(NAND_CMD_STATUS & 0xFF, this->IO_ADDR_W);
-
+       gpmc_nand_write(info->gpmc_cs,
+                       GPMC_NAND_COMMAND, (NAND_CMD_STATUS & 0xFF));
        while (time_before(jiffies, timeo)) {
-               status = __raw_readb(this->IO_ADDR_R);
+               status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA);
                if (status & NAND_STATUS_READY)
                        break;
                cond_resched();
@@ -855,22 +753,22 @@ static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
  */
 static int omap_dev_ready(struct mtd_info *mtd)
 {
+       unsigned int val = 0;
        struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
                                                        mtd);
-       unsigned int val = __raw_readl(info->gpmc_baseaddr + GPMC_IRQ_STATUS);
 
+       val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
        if ((val & 0x100) == 0x100) {
                /* Clear IRQ Interrupt */
                val |= 0x100;
                val &= ~(0x0);
-               __raw_writel(val, info->gpmc_baseaddr + GPMC_IRQ_STATUS);
+               gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, val);
        } else {
                unsigned int cnt = 0;
                while (cnt++ < 0x1FF) {
                        if  ((val & 0x100) == 0x100)
                                return 0;
-                       val = __raw_readl(info->gpmc_baseaddr +
-                                                       GPMC_IRQ_STATUS);
+                       val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
                }
        }
 
@@ -901,8 +799,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
        info->pdev = pdev;
 
        info->gpmc_cs           = pdata->cs;
-       info->gpmc_baseaddr     = pdata->gpmc_baseaddr;
-       info->gpmc_cs_baseaddr  = pdata->gpmc_cs_baseaddr;
        info->phys_base         = pdata->phys_base;
 
        info->mtd.priv          = &info->nand;
@@ -913,7 +809,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
        info->nand.options      |= NAND_SKIP_BBTSCAN;
 
        /* NAND write protect off */
-       omap_nand_wp(&info->mtd, NAND_WP_OFF);
+       gpmc_cs_configure(info->gpmc_cs, GPMC_CONFIG_WP, 0);
 
        if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
                                pdev->dev.driver->name)) {
@@ -948,8 +844,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
        }
 
        if (use_prefetch) {
-               /* copy the virtual address of nand base for fifo access */
-               info->nand_pref_fifo_add = info->nand.IO_ADDR_R;
 
                info->nand.read_buf   = omap_read_buf_pref;
                info->nand.write_buf  = omap_write_buf_pref;
@@ -989,8 +883,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
        info->nand.ecc.correct          = omap_correct_data;
        info->nand.ecc.mode             = NAND_ECC_HW;
 
-       /* init HW ECC */
-       omap_hwecc_init(&info->mtd);
 #else
        info->nand.ecc.mode = NAND_ECC_SOFT;
 #endif
@@ -1040,7 +932,7 @@ static int omap_nand_remove(struct platform_device *pdev)
 
        /* Release NAND device, its internal structures and partitions */
        nand_release(&info->mtd);
-       iounmap(info->nand_pref_fifo_add);
+       iounmap(info->nand.IO_ADDR_R);
        kfree(&info->mtd);
        return 0;
 }

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 78b74e83ce5df7f242fe579676f7623c8d84e6f3..5a1bd5db2a93b3bfc3540e5cd81b76d05b553e0e 100644 (file)
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -29,6 +29,7 @@
 #include <linux/mii.h>
 #include <linux/ethtool.h>
 #include <linux/phy.h>
+#include <linux/marvell_phy.h>
 
 #include <asm/io.h>
 #include <asm/irq.h>
@@ -48,8 +49,6 @@
 #define MII_M1145_RGMII_RX_DELAY       0x0080
 #define MII_M1145_RGMII_TX_DELAY       0x0002
 
-#define M1145_DEV_FLAGS_RESISTANCE     0x00000001
-
 #define MII_M1111_PHY_LED_CONTROL      0x18
 #define MII_M1111_PHY_LED_DIRECT       0x4100
 #define MII_M1111_PHY_LED_COMBINE      0x411c
@@ -350,7 +349,10 @@ static int m88e1118_config_init(struct phy_device *phydev)
                return err;
 
        /* Adjust LED Control */
-       err = phy_write(phydev, 0x10, 0x021e);
+       if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
+               err = phy_write(phydev, 0x10, 0x1100);
+       else
+               err = phy_write(phydev, 0x10, 0x021e);
        if (err < 0)
                return err;
 
@@ -398,7 +400,7 @@ static int m88e1145_config_init(struct phy_device *phydev)
                if (err < 0)
                        return err;
 
-               if (phydev->dev_flags & M1145_DEV_FLAGS_RESISTANCE) {
+               if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
                        err = phy_write(phydev, 0x1d, 0x0012);
                        if (err < 0)
                                return err;
@@ -529,8 +531,8 @@ static int m88e1121_did_interrupt(struct phy_device *phydev)
 
 static struct phy_driver marvell_drivers[] = {
        {
-               .phy_id = 0x01410c60,
-               .phy_id_mask = 0xfffffff0,
+               .phy_id = MARVELL_PHY_ID_88E1101,
+               .phy_id_mask = MARVELL_PHY_ID_MASK,
                .name = "Marvell 88E1101",
                .features = PHY_GBIT_FEATURES,
                .flags = PHY_HAS_INTERRUPT,
@@ -541,8 +543,8 @@ static struct phy_driver marvell_drivers[] = {
                .driver = { .owner = THIS_MODULE },
        },
        {
-               .phy_id = 0x01410c90,
-               .phy_id_mask = 0xfffffff0,
+               .phy_id = MARVELL_PHY_ID_88E1112,
+               .phy_id_mask = MARVELL_PHY_ID_MASK,
                .name = "Marvell 88E1112",
                .features = PHY_GBIT_FEATURES,
                .flags = PHY_HAS_INTERRUPT,
@@ -554,8 +556,8 @@ static struct phy_driver marvell_drivers[] = {
                .driver = { .owner = THIS_MODULE },
        },
        {
-               .phy_id = 0x01410cc0,
-               .phy_id_mask = 0xfffffff0,
+               .phy_id = MARVELL_PHY_ID_88E1111,
+               .phy_id_mask = MARVELL_PHY_ID_MASK,
                .name = "Marvell 88E1111",
                .features = PHY_GBIT_FEATURES,
                .flags = PHY_HAS_INTERRUPT,
@@ -567,8 +569,8 @@ static struct phy_driver marvell_drivers[] = {
                .driver = { .owner = THIS_MODULE },
        },
        {
-               .phy_id = 0x01410e10,
-               .phy_id_mask = 0xfffffff0,
+               .phy_id = MARVELL_PHY_ID_88E1118,
+               .phy_id_mask = MARVELL_PHY_ID_MASK,
                .name = "Marvell 88E1118",
                .features = PHY_GBIT_FEATURES,
                .flags = PHY_HAS_INTERRUPT,
@@ -580,8 +582,8 @@ static struct phy_driver marvell_drivers[] = {
                .driver = {.owner = THIS_MODULE,},
        },
        {
-               .phy_id = 0x01410cb0,
-               .phy_id_mask = 0xfffffff0,
+               .phy_id = MARVELL_PHY_ID_88E1121R,
+               .phy_id_mask = MARVELL_PHY_ID_MASK,
                .name = "Marvell 88E1121R",
                .features = PHY_GBIT_FEATURES,
                .flags = PHY_HAS_INTERRUPT,
@@ -593,8 +595,8 @@ static struct phy_driver marvell_drivers[] = {
                .driver = { .owner = THIS_MODULE },
        },
        {
-               .phy_id = 0x01410cd0,
-               .phy_id_mask = 0xfffffff0,
+               .phy_id = MARVELL_PHY_ID_88E1145,
+               .phy_id_mask = MARVELL_PHY_ID_MASK,
                .name = "Marvell 88E1145",
                .features = PHY_GBIT_FEATURES,
                .flags = PHY_HAS_INTERRUPT,
@@ -606,8 +608,8 @@ static struct phy_driver marvell_drivers[] = {
                .driver = { .owner = THIS_MODULE },
        },
        {
-               .phy_id = 0x01410e30,
-               .phy_id_mask = 0xfffffff0,
+               .phy_id = MARVELL_PHY_ID_88E1240,
+               .phy_id_mask = MARVELL_PHY_ID_MASK,
                .name = "Marvell 88E1240",
                .features = PHY_GBIT_FEATURES,
                .flags = PHY_HAS_INTERRUPT,

diff --git a/drivers/parisc/led.c b/drivers/parisc/led.c
index 188bc8496a264feb05758e36cd7c2e23dea37b63..d02be78a41386b2ecb94c249cff8da11776ecb4a 100644 (file)
--- a/drivers/parisc/led.c
+++ b/drivers/parisc/led.c
@@ -176,16 +176,18 @@ static ssize_t led_proc_write(struct file *file, const char *buf,
        size_t count, loff_t *pos)
 {
        void *data = PDE(file->f_path.dentry->d_inode)->data;
-       char *cur, lbuf[count + 1];
+       char *cur, lbuf[32];
        int d;
 
        if (!capable(CAP_SYS_ADMIN))
                return -EACCES;
 
-       memset(lbuf, 0, count + 1);
+       if (count >= sizeof(lbuf))
+               count = sizeof(lbuf)-1;
 
        if (copy_from_user(lbuf, buf, count))
                return -EFAULT;
+       lbuf[count] = 0;
 
        cur = lbuf;
 

diff --git a/drivers/rtc/rtc-pl031.c b/drivers/rtc/rtc-pl031.c
index 3587d9922f2895832059f1ea1163e715750dd19a..71bbefc3544ee7782539083ace3ca2ea11931a1e 100644 (file)
--- a/drivers/rtc/rtc-pl031.c
+++ b/drivers/rtc/rtc-pl031.c
@@ -456,7 +456,7 @@ static struct rtc_class_ops stv2_pl031_ops = {
        .irq_set_freq = pl031_irq_set_freq,
 };
 
-static struct amba_id pl031_ids[] __initdata = {
+static struct amba_id pl031_ids[] = {
        {
                .id = 0x00041031,
                .mask = 0x000fffff,

diff --git a/drivers/serial/amba-pl010.c b/drivers/serial/amba-pl010.c
index b09a638d051fde98c37e52a58eb2cb9a25756663..50441ffe8e3856592dbfdae368e9891b64078d50 100644 (file)
--- a/drivers/serial/amba-pl010.c
+++ b/drivers/serial/amba-pl010.c
@@ -782,7 +782,7 @@ static int pl010_resume(struct amba_device *dev)
        return 0;
 }
 
-static struct amba_id pl010_ids[] __initdata = {
+static struct amba_id pl010_ids[] = {
        {
                .id     = 0x00041010,
                .mask   = 0x000fffff,

diff --git a/drivers/serial/amba-pl011.c b/drivers/serial/amba-pl011.c
index eb4cb480b93e9be344f9f84bbd574c68fe3ec8e6..6ca7a44f29c205ef37c95318253e2592efaa459b 100644 (file)
--- a/drivers/serial/amba-pl011.c
+++ b/drivers/serial/amba-pl011.c
@@ -69,9 +69,12 @@
 struct uart_amba_port {
        struct uart_port        port;
        struct clk              *clk;
-       unsigned int            im;     /* interrupt mask */
+       unsigned int            im;             /* interrupt mask */
        unsigned int            old_status;
-       unsigned int            ifls;   /* vendor-specific */
+       unsigned int            ifls;           /* vendor-specific */
+       unsigned int            lcrh_tx;        /* vendor-specific */
+       unsigned int            lcrh_rx;        /* vendor-specific */
+       bool                    oversampling;   /* vendor-specific */
        bool                    autorts;
 };
 
@@ -79,16 +82,25 @@ struct uart_amba_port {
 struct vendor_data {
        unsigned int            ifls;
        unsigned int            fifosize;
+       unsigned int            lcrh_tx;
+       unsigned int            lcrh_rx;
+       bool                    oversampling;
 };
 
 static struct vendor_data vendor_arm = {
        .ifls                   = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
        .fifosize               = 16,
+       .lcrh_tx                = UART011_LCRH,
+       .lcrh_rx                = UART011_LCRH,
+       .oversampling           = false,
 };
 
 static struct vendor_data vendor_st = {
        .ifls                   = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
        .fifosize               = 64,
+       .lcrh_tx                = ST_UART011_LCRH_TX,
+       .lcrh_rx                = ST_UART011_LCRH_RX,
+       .oversampling           = true,
 };
 
 static void pl011_stop_tx(struct uart_port *port)
@@ -327,12 +339,12 @@ static void pl011_break_ctl(struct uart_port *port, int break_state)
        unsigned int lcr_h;
 
        spin_lock_irqsave(&uap->port.lock, flags);
-       lcr_h = readw(uap->port.membase + UART011_LCRH);
+       lcr_h = readw(uap->port.membase + uap->lcrh_tx);
        if (break_state == -1)
                lcr_h |= UART01x_LCRH_BRK;
        else
                lcr_h &= ~UART01x_LCRH_BRK;
-       writew(lcr_h, uap->port.membase + UART011_LCRH);
+       writew(lcr_h, uap->port.membase + uap->lcrh_tx);
        spin_unlock_irqrestore(&uap->port.lock, flags);
 }
 
@@ -393,7 +405,17 @@ static int pl011_startup(struct uart_port *port)
        writew(cr, uap->port.membase + UART011_CR);
        writew(0, uap->port.membase + UART011_FBRD);
        writew(1, uap->port.membase + UART011_IBRD);
-       writew(0, uap->port.membase + UART011_LCRH);
+       writew(0, uap->port.membase + uap->lcrh_rx);
+       if (uap->lcrh_tx != uap->lcrh_rx) {
+               int i;
+               /*
+                * Wait 10 PCLKs before writing LCRH_TX register,
+                * to get this delay write read only register 10 times
+                */
+               for (i = 0; i < 10; ++i)
+                       writew(0xff, uap->port.membase + UART011_MIS);
+               writew(0, uap->port.membase + uap->lcrh_tx);
+       }
        writew(0, uap->port.membase + UART01x_DR);
        while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
                barrier();
@@ -422,10 +444,19 @@ static int pl011_startup(struct uart_port *port)
        return retval;
 }
 
+static void pl011_shutdown_channel(struct uart_amba_port *uap,
+                                       unsigned int lcrh)
+{
+      unsigned long val;
+
+      val = readw(uap->port.membase + lcrh);
+      val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
+      writew(val, uap->port.membase + lcrh);
+}
+
 static void pl011_shutdown(struct uart_port *port)
 {
        struct uart_amba_port *uap = (struct uart_amba_port *)port;
-       unsigned long val;
 
        /*
         * disable all interrupts
@@ -450,9 +481,9 @@ static void pl011_shutdown(struct uart_port *port)
        /*
         * disable break condition and fifos
         */
-       val = readw(uap->port.membase + UART011_LCRH);
-       val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
-       writew(val, uap->port.membase + UART011_LCRH);
+       pl011_shutdown_channel(uap, uap->lcrh_rx);
+       if (uap->lcrh_rx != uap->lcrh_tx)
+               pl011_shutdown_channel(uap, uap->lcrh_tx);
 
        /*
         * Shut down the clock producer
@@ -472,8 +503,13 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
        /*
         * Ask the core to calculate the divisor for us.
         */
-       baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
-       quot = port->uartclk * 4 / baud;
+       baud = uart_get_baud_rate(port, termios, old, 0,
+                                 port->uartclk/(uap->oversampling ? 8 : 16));
+
+       if (baud > port->uartclk/16)
+               quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
+       else
+               quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
 
        switch (termios->c_cflag & CSIZE) {
        case CS5:
@@ -552,6 +588,13 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
                uap->autorts = false;
        }
 
+       if (uap->oversampling) {
+               if (baud > port->uartclk/16)
+                       old_cr |= ST_UART011_CR_OVSFACT;
+               else
+                       old_cr &= ~ST_UART011_CR_OVSFACT;
+       }
+
        /* Set baud rate */
        writew(quot & 0x3f, port->membase + UART011_FBRD);
        writew(quot >> 6, port->membase + UART011_IBRD);
@@ -561,7 +604,17 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
         * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
         * ----------^----------^----------^----------^-----
         */
-       writew(lcr_h, port->membase + UART011_LCRH);
+       writew(lcr_h, port->membase + uap->lcrh_rx);
+       if (uap->lcrh_rx != uap->lcrh_tx) {
+               int i;
+               /*
+                * Wait 10 PCLKs before writing LCRH_TX register,
+                * to get this delay write read only register 10 times
+                */
+               for (i = 0; i < 10; ++i)
+                       writew(0xff, uap->port.membase + UART011_MIS);
+               writew(lcr_h, port->membase + uap->lcrh_tx);
+       }
        writew(old_cr, port->membase + UART011_CR);
 
        spin_unlock_irqrestore(&port->lock, flags);
@@ -688,7 +741,7 @@ pl011_console_get_options(struct uart_amba_port *uap, int *baud,
        if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
                unsigned int lcr_h, ibrd, fbrd;
 
-               lcr_h = readw(uap->port.membase + UART011_LCRH);
+               lcr_h = readw(uap->port.membase + uap->lcrh_tx);
 
                *parity = 'n';
                if (lcr_h & UART01x_LCRH_PEN) {
@@ -707,6 +760,12 @@ pl011_console_get_options(struct uart_amba_port *uap, int *baud,
                fbrd = readw(uap->port.membase + UART011_FBRD);
 
                *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
+
+               if (uap->oversampling) {
+                       if (readw(uap->port.membase + UART011_CR)
+                                 & ST_UART011_CR_OVSFACT)
+                               *baud *= 2;
+               }
        }
 }
 
@@ -800,6 +859,9 @@ static int pl011_probe(struct amba_device *dev, struct amba_id *id)
        }
 
        uap->ifls = vendor->ifls;
+       uap->lcrh_rx = vendor->lcrh_rx;
+       uap->lcrh_tx = vendor->lcrh_tx;
+       uap->oversampling = vendor->oversampling;
        uap->port.dev = &dev->dev;
        uap->port.mapbase = dev->res.start;
        uap->port.membase = base;
@@ -868,7 +930,7 @@ static int pl011_resume(struct amba_device *dev)
 }
 #endif
 
-static struct amba_id pl011_ids[] __initdata = {
+static struct amba_id pl011_ids[] = {
        {
                .id     = 0x00041011,
                .mask   = 0x000fffff,

diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
index eaa79c8a9b8c2bee44fdce43f2963d19087213a3..93ead19507b632c20095980fd5b0350d6407d23d 100644 (file)
--- a/drivers/usb/gadget/at91_udc.c
+++ b/drivers/usb/gadget/at91_udc.c
@@ -76,11 +76,12 @@
 static const char driver_name [] = "at91_udc";
 static const char ep0name[] = "ep0";
 
+#define VBUS_POLL_TIMEOUT      msecs_to_jiffies(1000)
 
-#define at91_udp_read(dev, reg) \
-       __raw_readl((dev)->udp_baseaddr + (reg))
-#define at91_udp_write(dev, reg, val) \
-       __raw_writel((val), (dev)->udp_baseaddr + (reg))
+#define at91_udp_read(udc, reg) \
+       __raw_readl((udc)->udp_baseaddr + (reg))
+#define at91_udp_write(udc, reg, val) \
+       __raw_writel((val), (udc)->udp_baseaddr + (reg))
 
 /*-------------------------------------------------------------------------*/
 
@@ -102,8 +103,9 @@ static void proc_ep_show(struct seq_file *s, struct at91_ep *ep)
        u32                     csr;
        struct at91_request     *req;
        unsigned long   flags;
+       struct at91_udc *udc = ep->udc;
 
-       local_irq_save(flags);
+       spin_lock_irqsave(&udc->lock, flags);
 
        csr = __raw_readl(ep->creg);
 
@@ -147,7 +149,7 @@ static void proc_ep_show(struct seq_file *s, struct at91_ep *ep)
                                &req->req, length,
                                req->req.length, req->req.buf);
        }
-       local_irq_restore(flags);
+       spin_unlock_irqrestore(&udc->lock, flags);
 }
 
 static void proc_irq_show(struct seq_file *s, const char *label, u32 mask)
@@ -272,7 +274,9 @@ static void done(struct at91_ep *ep, struct at91_request *req, int status)
                VDBG("%s done %p, status %d\n", ep->ep.name, req, status);
 
        ep->stopped = 1;
+       spin_unlock(&udc->lock);
        req->req.complete(&ep->ep, &req->req);
+       spin_lock(&udc->lock);
        ep->stopped = stopped;
 
        /* ep0 is always ready; other endpoints need a non-empty queue */
@@ -472,7 +476,7 @@ static int at91_ep_enable(struct usb_ep *_ep,
                                const struct usb_endpoint_descriptor *desc)
 {
        struct at91_ep  *ep = container_of(_ep, struct at91_ep, ep);
-       struct at91_udc *dev = ep->udc;
+       struct at91_udc *udc = ep->udc;
        u16             maxpacket;
        u32             tmp;
        unsigned long   flags;
@@ -487,7 +491,7 @@ static int at91_ep_enable(struct usb_ep *_ep,
                return -EINVAL;
        }
 
-       if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
+       if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
                DBG("bogus device state\n");
                return -ESHUTDOWN;
        }
@@ -521,7 +525,7 @@ bogus_max:
        }
 
 ok:
-       local_irq_save(flags);
+       spin_lock_irqsave(&udc->lock, flags);
 
        /* initialize endpoint to match this descriptor */
        ep->is_in = usb_endpoint_dir_in(desc);
@@ -540,10 +544,10 @@ ok:
         * reset/init endpoint fifo.  NOTE:  leaves fifo_bank alone,
         * since endpoint resets don't reset hw pingpong state.
         */
-       at91_udp_write(dev, AT91_UDP_RST_EP, ep->int_mask);
-       at91_udp_write(dev, AT91_UDP_RST_EP, 0);
+       at91_udp_write(udc, AT91_UDP_RST_EP, ep->int_mask);
+       at91_udp_write(udc, AT91_UDP_RST_EP, 0);
 
-       local_irq_restore(flags);
+       spin_unlock_irqrestore(&udc->lock, flags);
        return 0;
 }
 
@@ -556,7 +560,7 @@ static int at91_ep_disable (struct usb_ep * _ep)
        if (ep == &ep->udc->ep[0])
                return -EINVAL;
 
-       local_irq_save(flags);
+       spin_lock_irqsave(&udc->lock, flags);
 
        nuke(ep, -ESHUTDOWN);
 
@@ -571,7 +575,7 @@ static int at91_ep_disable (struct usb_ep * _ep)
                __raw_writel(0, ep->creg);
        }
 
-       local_irq_restore(flags);
+       spin_unlock_irqrestore(&udc->lock, flags);
        return 0;
 }
 
@@ -607,7 +611,7 @@ static int at91_ep_queue(struct usb_ep *_ep,
 {
        struct at91_request     *req;
        struct at91_ep          *ep;
-       struct at91_udc         *dev;
+       struct at91_udc         *udc;
        int                     status;
        unsigned long           flags;
 
@@ -625,9 +629,9 @@ static int at91_ep_queue(struct usb_ep *_ep,
                return -EINVAL;
        }
 
-       dev = ep->udc;
+       udc = ep->udc;
 
-       if (!dev || !dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
+       if (!udc || !udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
                DBG("invalid device\n");
                return -EINVAL;
        }
@@ -635,7 +639,7 @@ static int at91_ep_queue(struct usb_ep *_ep,
        _req->status = -EINPROGRESS;
        _req->actual = 0;
 
-       local_irq_save(flags);
+       spin_lock_irqsave(&udc->lock, flags);
 
        /* try to kickstart any empty and idle queue */
        if (list_empty(&ep->queue) && !ep->stopped) {
@@ -653,7 +657,7 @@ static int at91_ep_queue(struct usb_ep *_ep,
                if (is_ep0) {
                        u32     tmp;
 
-                       if (!dev->req_pending) {
+                       if (!udc->req_pending) {
                                status = -EINVAL;
                                goto done;
                        }
@@ -662,11 +666,11 @@ static int at91_ep_queue(struct usb_ep *_ep,
                         * defer changing CONFG until after the gadget driver
                         * reconfigures the endpoints.
                         */
-                       if (dev->wait_for_config_ack) {
-                               tmp = at91_udp_read(dev, AT91_UDP_GLB_STAT);
+                       if (udc->wait_for_config_ack) {
+                               tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT);
                                tmp ^= AT91_UDP_CONFG;
                                VDBG("toggle config\n");
-                               at91_udp_write(dev, AT91_UDP_GLB_STAT, tmp);
+                               at91_udp_write(udc, AT91_UDP_GLB_STAT, tmp);
                        }
                        if (req->req.length == 0) {
 ep0_in_status:
@@ -676,7 +680,7 @@ ep0_in_status:
                                tmp &= ~SET_FX;
                                tmp |= CLR_FX | AT91_UDP_TXPKTRDY;
                                __raw_writel(tmp, ep->creg);
-                               dev->req_pending = 0;
+                               udc->req_pending = 0;
                                goto done;
                        }
                }
@@ -695,31 +699,40 @@ ep0_in_status:
 
        if (req && !status) {
                list_add_tail (&req->queue, &ep->queue);
-               at91_udp_write(dev, AT91_UDP_IER, ep->int_mask);
+               at91_udp_write(udc, AT91_UDP_IER, ep->int_mask);
        }
 done:
-       local_irq_restore(flags);
+       spin_unlock_irqrestore(&udc->lock, flags);
        return (status < 0) ? status : 0;
 }
 
 static int at91_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 {
-       struct at91_ep  *ep;
+       struct at91_ep          *ep;
        struct at91_request     *req;
+       unsigned long           flags;
+       struct at91_udc         *udc;
 
        ep = container_of(_ep, struct at91_ep, ep);
        if (!_ep || ep->ep.name == ep0name)
                return -EINVAL;
 
+       udc = ep->udc;
+
+       spin_lock_irqsave(&udc->lock, flags);
+
        /* make sure it's actually queued on this endpoint */
        list_for_each_entry (req, &ep->queue, queue) {
                if (&req->req == _req)
                        break;
        }
-       if (&req->req != _req)
+       if (&req->req != _req) {
+               spin_unlock_irqrestore(&udc->lock, flags);
                return -EINVAL;
+       }
 
        done(ep, req, -ECONNRESET);
+       spin_unlock_irqrestore(&udc->lock, flags);
        return 0;
 }
 
@@ -736,7 +749,7 @@ static int at91_ep_set_halt(struct usb_ep *_ep, int value)
                return -EINVAL;
 
        creg = ep->creg;
-       local_irq_save(flags);
+       spin_lock_irqsave(&udc->lock, flags);
 
        csr = __raw_readl(creg);
 
@@ -761,7 +774,7 @@ static int at91_ep_set_halt(struct usb_ep *_ep, int value)
                __raw_writel(csr, creg);
        }
 
-       local_irq_restore(flags);
+       spin_unlock_irqrestore(&udc->lock, flags);
        return status;
 }
 
@@ -795,7 +808,7 @@ static int at91_wakeup(struct usb_gadget *gadget)
        unsigned long   flags;
 
        DBG("%s\n", __func__ );
-       local_irq_save(flags);
+       spin_lock_irqsave(&udc->lock, flags);
 
        if (!udc->clocked || !udc->suspended)
                goto done;
@@ -809,7 +822,7 @@ static int at91_wakeup(struct usb_gadget *gadget)
        at91_udp_write(udc, AT91_UDP_GLB_STAT, glbstate);
 
 done:
-       local_irq_restore(flags);
+       spin_unlock_irqrestore(&udc->lock, flags);
        return status;
 }
 
@@ -851,8 +864,11 @@ static void stop_activity(struct at91_udc *udc)
                ep->stopped = 1;
                nuke(ep, -ESHUTDOWN);
        }
-       if (driver)
+       if (driver) {
+               spin_unlock(&udc->lock);
                driver->disconnect(&udc->gadget);
+               spin_lock(&udc->lock);
+       }
 
        udc_reinit(udc);
 }
@@ -935,13 +951,13 @@ static int at91_vbus_session(struct usb_gadget *gadget, int is_active)
        unsigned long   flags;
 
        // VDBG("vbus %s\n", is_active ? "on" : "off");
-       local_irq_save(flags);
+       spin_lock_irqsave(&udc->lock, flags);
        udc->vbus = (is_active != 0);
        if (udc->driver)
                pullup(udc, is_active);
        else
                pullup(udc, 0);
-       local_irq_restore(flags);
+       spin_unlock_irqrestore(&udc->lock, flags);
        return 0;
 }
 
@@ -950,10 +966,10 @@ static int at91_pullup(struct usb_gadget *gadget, int is_on)
        struct at91_udc *udc = to_udc(gadget);
        unsigned long   flags;
 
-       local_irq_save(flags);
+       spin_lock_irqsave(&udc->lock, flags);
        udc->enabled = is_on = !!is_on;
        pullup(udc, is_on);
-       local_irq_restore(flags);
+       spin_unlock_irqrestore(&udc->lock, flags);
        return 0;
 }
 
@@ -962,9 +978,9 @@ static int at91_set_selfpowered(struct usb_gadget *gadget, int is_on)
        struct at91_udc *udc = to_udc(gadget);
        unsigned long   flags;
 
-       local_irq_save(flags);
+       spin_lock_irqsave(&udc->lock, flags);
        udc->selfpowered = (is_on != 0);
-       local_irq_restore(flags);
+       spin_unlock_irqrestore(&udc->lock, flags);
        return 0;
 }
 
@@ -1226,8 +1242,11 @@ static void handle_setup(struct at91_udc *udc, struct at91_ep *ep, u32 csr)
 #undef w_length
 
        /* pass request up to the gadget driver */
-       if (udc->driver)
+       if (udc->driver) {
+               spin_unlock(&udc->lock);
                status = udc->driver->setup(&udc->gadget, &pkt.r);
+               spin_lock(&udc->lock);
+       }
        else
                status = -ENODEV;
        if (status < 0) {
@@ -1378,6 +1397,9 @@ static irqreturn_t at91_udc_irq (int irq, void *_udc)
        struct at91_udc         *udc = _udc;
        u32                     rescans = 5;
        int                     disable_clock = 0;
+       unsigned long           flags;
+
+       spin_lock_irqsave(&udc->lock, flags);
 
        if (!udc->clocked) {
                clk_on(udc);
@@ -1433,8 +1455,11 @@ static irqreturn_t at91_udc_irq (int irq, void *_udc)
                         * and then into standby to avoid drawing more than
                         * 500uA power (2500uA for some high-power configs).
                         */
-                       if (udc->driver && udc->driver->suspend)
+                       if (udc->driver && udc->driver->suspend) {
+                               spin_unlock(&udc->lock);
                                udc->driver->suspend(&udc->gadget);
+                               spin_lock(&udc->lock);
+                       }
 
                /* host initiated resume */
                } else if (status & AT91_UDP_RXRSM) {
@@ -1451,8 +1476,11 @@ static irqreturn_t at91_udc_irq (int irq, void *_udc)
                         * would normally want to switch out of slow clock
                         * mode into normal mode.
                         */
-                       if (udc->driver && udc->driver->resume)
+                       if (udc->driver && udc->driver->resume) {
+                               spin_unlock(&udc->lock);
                                udc->driver->resume(&udc->gadget);
+                               spin_lock(&udc->lock);
+                       }
 
                /* endpoint IRQs are cleared by handling them */
                } else {
@@ -1474,6 +1502,8 @@ static irqreturn_t at91_udc_irq (int irq, void *_udc)
        if (disable_clock)
                clk_off(udc);
 
+       spin_unlock_irqrestore(&udc->lock, flags);
+
        return IRQ_HANDLED;
 }
 
@@ -1556,24 +1586,53 @@ static struct at91_udc controller = {
        /* ep6 and ep7 are also reserved (custom silicon might use them) */
 };
 
+static void at91_vbus_update(struct at91_udc *udc, unsigned value)
+{
+       value ^= udc->board.vbus_active_low;
+       if (value != udc->vbus)
+               at91_vbus_session(&udc->gadget, value);
+}
+
 static irqreturn_t at91_vbus_irq(int irq, void *_udc)
 {
        struct at91_udc *udc = _udc;
-       unsigned        value;
 
        /* vbus needs at least brief debouncing */
        udelay(10);
-       value = gpio_get_value(udc->board.vbus_pin);
-       if (value != udc->vbus)
-               at91_vbus_session(&udc->gadget, value);
+       at91_vbus_update(udc, gpio_get_value(udc->board.vbus_pin));
 
        return IRQ_HANDLED;
 }
 
+static void at91_vbus_timer_work(struct work_struct *work)
+{
+       struct at91_udc *udc = container_of(work, struct at91_udc,
+                                           vbus_timer_work);
+
+       at91_vbus_update(udc, gpio_get_value_cansleep(udc->board.vbus_pin));
+
+       if (!timer_pending(&udc->vbus_timer))
+               mod_timer(&udc->vbus_timer, jiffies + VBUS_POLL_TIMEOUT);
+}
+
+static void at91_vbus_timer(unsigned long data)
+{
+       struct at91_udc *udc = (struct at91_udc *)data;
+
+       /*
+        * If we are polling vbus it is likely that the gpio is on an
+        * bus such as i2c or spi which may sleep, so schedule some work
+        * to read the vbus gpio
+        */
+       if (!work_pending(&udc->vbus_timer_work))
+               schedule_work(&udc->vbus_timer_work);
+}
+
 int usb_gadget_register_driver (struct usb_gadget_driver *driver)
 {
        struct at91_udc *udc = &controller;
        int             retval;
+       unsigned long   flags;
 
        if (!driver
                        || driver->speed < USB_SPEED_FULL
@@ -1605,9 +1664,9 @@ int usb_gadget_register_driver (struct usb_gadget_driver *driver)
                return retval;
        }
 
-       local_irq_disable();
+       spin_lock_irqsave(&udc->lock, flags);
        pullup(udc, 1);
-       local_irq_enable();
+       spin_unlock_irqrestore(&udc->lock, flags);
 
        DBG("bound to %s\n", driver->driver.name);
        return 0;
@@ -1617,15 +1676,16 @@ EXPORT_SYMBOL (usb_gadget_register_driver);
 int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
 {
        struct at91_udc *udc = &controller;
+       unsigned long   flags;
 
        if (!driver || driver != udc->driver || !driver->unbind)
                return -EINVAL;
 
-       local_irq_disable();
+       spin_lock_irqsave(&udc->lock, flags);
        udc->enabled = 0;
        at91_udp_write(udc, AT91_UDP_IDR, ~0);
        pullup(udc, 0);
-       local_irq_enable();
+       spin_unlock_irqrestore(&udc->lock, flags);
 
        driver->unbind(&udc->gadget);
        udc->gadget.dev.driver = NULL;
@@ -1641,8 +1701,13 @@ EXPORT_SYMBOL (usb_gadget_unregister_driver);
 
 static void at91udc_shutdown(struct platform_device *dev)
 {
+       struct at91_udc *udc = platform_get_drvdata(dev);
+       unsigned long   flags;
+
        /* force disconnect on reboot */
+       spin_lock_irqsave(&udc->lock, flags);
        pullup(platform_get_drvdata(dev), 0);
+       spin_unlock_irqrestore(&udc->lock, flags);
 }
 
 static int __init at91udc_probe(struct platform_device *pdev)
@@ -1683,6 +1748,7 @@ static int __init at91udc_probe(struct platform_device *pdev)
        udc->board = *(struct at91_udc_data *) dev->platform_data;
        udc->pdev = pdev;
        udc->enabled = 0;
+       spin_lock_init(&udc->lock);
 
        /* rm9200 needs manual D+ pullup; off by default */
        if (cpu_is_at91rm9200()) {
@@ -1763,13 +1829,23 @@ static int __init at91udc_probe(struct platform_device *pdev)
                 * Get the initial state of VBUS - we cannot expect
                 * a pending interrupt.
                 */
-               udc->vbus = gpio_get_value(udc->board.vbus_pin);
-               if (request_irq(udc->board.vbus_pin, at91_vbus_irq,
-                               IRQF_DISABLED, driver_name, udc)) {
-                       DBG("request vbus irq %d failed\n",
-                                       udc->board.vbus_pin);
-                       retval = -EBUSY;
-                       goto fail3;
+               udc->vbus = gpio_get_value_cansleep(udc->board.vbus_pin) ^
+                       udc->board.vbus_active_low;
+
+               if (udc->board.vbus_polled) {
+                       INIT_WORK(&udc->vbus_timer_work, at91_vbus_timer_work);
+                       setup_timer(&udc->vbus_timer, at91_vbus_timer,
+                                   (unsigned long)udc);
+                       mod_timer(&udc->vbus_timer,
+                                 jiffies + VBUS_POLL_TIMEOUT);
+               } else {
+                       if (request_irq(udc->board.vbus_pin, at91_vbus_irq,
+                                       IRQF_DISABLED, driver_name, udc)) {
+                               DBG("request vbus irq %d failed\n",
+                                   udc->board.vbus_pin);
+                               retval = -EBUSY;
+                               goto fail3;
+                       }
                }
        } else {
                DBG("no VBUS detection, assuming always-on\n");
@@ -1804,13 +1880,16 @@ static int __exit at91udc_remove(struct platform_device *pdev)
 {
        struct at91_udc *udc = platform_get_drvdata(pdev);
        struct resource *res;
+       unsigned long   flags;
 
        DBG("remove\n");
 
        if (udc->driver)
                return -EBUSY;
 
+       spin_lock_irqsave(&udc->lock, flags);
        pullup(udc, 0);
+       spin_unlock_irqrestore(&udc->lock, flags);
 
        device_init_wakeup(&pdev->dev, 0);
        remove_debug_file(udc);
@@ -1840,6 +1919,7 @@ static int at91udc_suspend(struct platform_device *pdev, pm_message_t mesg)
 {
        struct at91_udc *udc = platform_get_drvdata(pdev);
        int             wake = udc->driver && device_may_wakeup(&pdev->dev);
+       unsigned long   flags;
 
        /* Unless we can act normally to the host (letting it wake us up
         * whenever it has work for us) force disconnect.  Wakeup requires
@@ -1849,13 +1929,15 @@ static int at91udc_suspend(struct platform_device *pdev, pm_message_t mesg)
        if ((!udc->suspended && udc->addr)
                        || !wake
                        || at91_suspend_entering_slow_clock()) {
+               spin_lock_irqsave(&udc->lock, flags);
                pullup(udc, 0);
                wake = 0;
+               spin_unlock_irqrestore(&udc->lock, flags);
        } else
                enable_irq_wake(udc->udp_irq);
 
        udc->active_suspend = wake;
-       if (udc->board.vbus_pin > 0 && wake)
+       if (udc->board.vbus_pin > 0 && !udc->board.vbus_polled && wake)
                enable_irq_wake(udc->board.vbus_pin);
        return 0;
 }
@@ -1863,15 +1945,20 @@ static int at91udc_suspend(struct platform_device *pdev, pm_message_t mesg)
 static int at91udc_resume(struct platform_device *pdev)
 {
        struct at91_udc *udc = platform_get_drvdata(pdev);
+       unsigned long   flags;
 
-       if (udc->board.vbus_pin > 0 && udc->active_suspend)
+       if (udc->board.vbus_pin > 0 && !udc->board.vbus_polled &&
+           udc->active_suspend)
                disable_irq_wake(udc->board.vbus_pin);
 
        /* maybe reconnect to host; if so, clocks on */
        if (udc->active_suspend)
                disable_irq_wake(udc->udp_irq);
-       else
+       else {
+               spin_lock_irqsave(&udc->lock, flags);
                pullup(udc, 1);
+               spin_unlock_irqrestore(&udc->lock, flags);
+       }
        return 0;
 }
 #else

diff --git a/drivers/usb/gadget/at91_udc.h b/drivers/usb/gadget/at91_udc.h
index c65d62295890e94584045ab9f0cc4b872ab29711..108ca54f9092ff4d01679292cd5acf0d221e81a1 100644 (file)
--- a/drivers/usb/gadget/at91_udc.h
+++ b/drivers/usb/gadget/at91_udc.h
@@ -144,6 +144,9 @@ struct at91_udc {
        struct proc_dir_entry           *pde;
        void __iomem                    *udp_baseaddr;
        int                             udp_irq;
+       spinlock_t                      lock;
+       struct timer_list               vbus_timer;
+       struct work_struct              vbus_timer_work;
 };
 
 static inline struct at91_udc *to_udc(struct usb_gadget *g)

diff --git a/drivers/usb/gadget/fsl_mxc_udc.c b/drivers/usb/gadget/fsl_mxc_udc.c
index d0b8bde59e59effdff3df5e5d84b5a79a817903d..eafa6d2c5ed734b278eaf1d34c69ab8f3290e383 100644 (file)
--- a/drivers/usb/gadget/fsl_mxc_udc.c
+++ b/drivers/usb/gadget/fsl_mxc_udc.c
@@ -30,7 +30,7 @@ int fsl_udc_clk_init(struct platform_device *pdev)
 
        pdata = pdev->dev.platform_data;
 
-       if (!cpu_is_mx35()) {
+       if (!cpu_is_mx35() && !cpu_is_mx25()) {
                mxc_ahb_clk = clk_get(&pdev->dev, "usb_ahb");
                if (IS_ERR(mxc_ahb_clk))
                        return PTR_ERR(mxc_ahb_clk);

diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index bd4027745aa7039e5cfcdd6b1bf4057ad8569d85..a8ad8ac120a2bfe733eaa2d151ad528afc15685d 100644 (file)
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -182,7 +182,7 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev)
        }
        clk_enable(priv->usbclk);
 
-       if (!cpu_is_mx35()) {
+       if (!cpu_is_mx35() && !cpu_is_mx25()) {
                priv->ahbclk = clk_get(dev, "usb_ahb");
                if (IS_ERR(priv->ahbclk)) {
                        ret = PTR_ERR(priv->ahbclk);

diff --git a/drivers/video/console/Kconfig b/drivers/video/console/Kconfig
index 8e8f18d29d7ae5258705244710d160a3107dbe23..5a35f22372b9959e52f1a8ab267a17baaf492b92 100644 (file)
--- a/drivers/video/console/Kconfig
+++ b/drivers/video/console/Kconfig
@@ -6,7 +6,7 @@ menu "Console display driver support"
 
 config VGA_CONSOLE
        bool "VGA text console" if EMBEDDED || !X86
-       depends on !ARCH_ACORN && !ARCH_EBSA110 && !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !ARCH_VERSATILE && !SUPERH && !BLACKFIN && !AVR32 && !MN10300
+       depends on !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !SUPERH && !BLACKFIN && !AVR32 && !MN10300 && (!ARM || ARCH_FOOTBRIDGE || ARCH_INTEGRATOR || ARCH_NETWINDER)
        default y
        help
          Saying Y here will allow you to use Linux in text mode through a

diff --git a/drivers/video/imxfb.c b/drivers/video/imxfb.c
index b4b6deceed153ae1b11bab3384249113359ec2c0..43f0639b1c10b7a7ede287df51b0ab28277031c1 100644 (file)
--- a/drivers/video/imxfb.c
+++ b/drivers/video/imxfb.c
@@ -175,6 +175,7 @@ struct imxfb_info {
 
        struct imx_fb_videomode *mode;
        int                     num_modes;
+       struct backlight_device *bl;
 
        void (*lcd_power)(int);
        void (*backlight_power)(int);
@@ -449,6 +450,73 @@ static int imxfb_set_par(struct fb_info *info)
        return 0;
 }
 
+
+
+static int imxfb_bl_get_brightness(struct backlight_device *bl)
+{
+       struct imxfb_info *fbi = bl_get_data(bl);
+
+       return readl(fbi->regs + LCDC_PWMR) & 0xFF;
+}
+
+static int imxfb_bl_update_status(struct backlight_device *bl)
+{
+       struct imxfb_info *fbi = bl_get_data(bl);
+       int brightness = bl->props.brightness;
+
+       if (bl->props.power != FB_BLANK_UNBLANK)
+               brightness = 0;
+       if (bl->props.fb_blank != FB_BLANK_UNBLANK)
+               brightness = 0;
+
+       fbi->pwmr = (fbi->pwmr & ~0xFF) | brightness;
+
+       if (bl->props.fb_blank != FB_BLANK_UNBLANK)
+               clk_enable(fbi->clk);
+       writel(fbi->pwmr, fbi->regs + LCDC_PWMR);
+       if (bl->props.fb_blank != FB_BLANK_UNBLANK)
+               clk_disable(fbi->clk);
+
+       return 0;
+}
+
+static const struct backlight_ops imxfb_lcdc_bl_ops = {
+       .update_status = imxfb_bl_update_status,
+       .get_brightness = imxfb_bl_get_brightness,
+};
+
+static void imxfb_init_backlight(struct imxfb_info *fbi)
+{
+       struct backlight_properties props;
+       struct backlight_device *bl;
+
+       if (fbi->bl)
+               return;
+
+       memset(&props, 0, sizeof(struct backlight_properties));
+       props.max_brightness = 0xff;
+       writel(fbi->pwmr, fbi->regs + LCDC_PWMR);
+
+       bl = backlight_device_register("imxfb-bl", &fbi->pdev->dev, fbi,
+                                      &imxfb_lcdc_bl_ops, &props);
+       if (IS_ERR(bl)) {
+               dev_err(&fbi->pdev->dev, "error %ld on backlight register\n",
+                               PTR_ERR(bl));
+               return;
+       }
+
+       fbi->bl = bl;
+       bl->props.power = FB_BLANK_UNBLANK;
+       bl->props.fb_blank = FB_BLANK_UNBLANK;
+       bl->props.brightness = imxfb_bl_get_brightness(bl);
+}
+
+static void imxfb_exit_backlight(struct imxfb_info *fbi)
+{
+       if (fbi->bl)
+               backlight_device_unregister(fbi->bl);
+}
+
 static void imxfb_enable_controller(struct imxfb_info *fbi)
 {
        pr_debug("Enabling LCD controller\n");
@@ -579,7 +647,6 @@ static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *inf
                        fbi->regs + LCDC_SIZE);
 
        writel(fbi->pcr, fbi->regs + LCDC_PCR);
-       writel(fbi->pwmr, fbi->regs + LCDC_PWMR);
        writel(fbi->lscr1, fbi->regs + LCDC_LSCR1);
        writel(fbi->dmacr, fbi->regs + LCDC_DMACR);
 
@@ -779,6 +846,8 @@ static int __init imxfb_probe(struct platform_device *pdev)
        }
 
        imxfb_enable_controller(fbi);
+       fbi->pdev = pdev;
+       imxfb_init_backlight(fbi);
 
        return 0;
 
@@ -816,6 +885,7 @@ static int __devexit imxfb_remove(struct platform_device *pdev)
 
        imxfb_disable_controller(fbi);
 
+       imxfb_exit_backlight(fbi);
        unregister_framebuffer(info);
 
        pdata = pdev->dev.platform_data;

diff --git a/drivers/video/omap/lcd_apollon.c b/drivers/video/omap/lcd_apollon.c
index 2be94eb3bbf518319bbd952e220af96c7d6c49e4..10459d8bd9a01268f99321aee171d8be0abf4294 100644 (file)
--- a/drivers/video/omap/lcd_apollon.c
+++ b/drivers/video/omap/lcd_apollon.c
@@ -25,7 +25,6 @@
 #include <linux/platform_device.h>
 
 #include <mach/gpio.h>
-#include <plat/mux.h>
 
 #include "omapfb.h"
 
@@ -34,8 +33,6 @@
 static int apollon_panel_init(struct lcd_panel *panel,
                                struct omapfb_device *fbdev)
 {
-       /* configure LCD PWR_EN */
-       omap_cfg_reg(M21_242X_GPIO11);
        return 0;
 }
 

diff --git a/drivers/video/omap2/vram.c b/drivers/video/omap2/vram.c
index 3b1237ad85ed384a3adba6dfe07451d2a732ed11..f6fdc2085f3e20147a4e9b0ae8ab4080c4fa4728 100644 (file)
--- a/drivers/video/omap2/vram.c
+++ b/drivers/video/omap2/vram.c
@@ -25,7 +25,7 @@
 #include <linux/list.h>
 #include <linux/slab.h>
 #include <linux/seq_file.h>
-#include <linux/bootmem.h>
+#include <linux/memblock.h>
 #include <linux/completion.h>
 #include <linux/debugfs.h>
 #include <linux/jiffies.h>
@@ -525,10 +525,8 @@ early_param("vram", omap_vram_early_vram);
  * Called from map_io. We need to call to this early enough so that we
  * can reserve the fixed SDRAM regions before VM could get hold of them.
  */
-void __init omap_vram_reserve_sdram(void)
+void __init omap_vram_reserve_sdram_memblock(void)
 {
-       struct bootmem_data     *bdata;
-       unsigned long           sdram_start, sdram_size;
        u32 paddr;
        u32 size = 0;
 
@@ -555,29 +553,28 @@ void __init omap_vram_reserve_sdram(void)
 
        size = PAGE_ALIGN(size);
 
-       bdata = NODE_DATA(0)->bdata;
-       sdram_start = bdata->node_min_pfn << PAGE_SHIFT;
-       sdram_size = (bdata->node_low_pfn << PAGE_SHIFT) - sdram_start;
-
        if (paddr) {
-               if ((paddr & ~PAGE_MASK) || paddr < sdram_start ||
-                               paddr + size > sdram_start + sdram_size) {
+               struct memblock_property res;
+
+               res.base = paddr;
+               res.size = size;
+               if ((paddr & ~PAGE_MASK) || memblock_find(&res) ||
+                   res.base != paddr || res.size != size) {
                        pr_err("Illegal SDRAM region for VRAM\n");
                        return;
                }
 
-               if (reserve_bootmem(paddr, size, BOOTMEM_EXCLUSIVE) < 0) {
-                       pr_err("FB: failed to reserve VRAM\n");
+               if (memblock_is_region_reserved(paddr, size)) {
+                       pr_err("FB: failed to reserve VRAM - busy\n");
                        return;
                }
-       } else {
-               if (size > sdram_size) {
-                       pr_err("Illegal SDRAM size for VRAM\n");
+
+               if (memblock_reserve(paddr, size) < 0) {
+                       pr_err("FB: failed to reserve VRAM - no memory\n");
                        return;
                }
-
-               paddr = virt_to_phys(alloc_bootmem_pages(size));
-               BUG_ON(paddr & ~PAGE_MASK);
+       } else {
+               paddr = memblock_alloc_base(size, PAGE_SIZE, MEMBLOCK_REAL_LIMIT);
        }
 
        omap_vram_add_region(paddr, size);

diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h
index 8b1038607831360ed621ddb5542c9f686338758e..b0c1740124365979f9e6e50a0671bf217206bdda 100644 (file)
--- a/include/linux/amba/bus.h
+++ b/include/linux/amba/bus.h
@@ -14,14 +14,19 @@
 #ifndef ASMARM_AMBA_H
 #define ASMARM_AMBA_H
 
+#include <linux/clk.h>
 #include <linux/device.h>
+#include <linux/err.h>
 #include <linux/resource.h>
 
 #define AMBA_NR_IRQS   2
 
+struct clk;
+
 struct amba_device {
        struct device           dev;
        struct resource         res;
+       struct clk              *pclk;
        u64                     dma_mask;
        unsigned int            periphid;
        unsigned int            irq[AMBA_NR_IRQS];
@@ -59,6 +64,12 @@ struct amba_device *amba_find_device(const char *, struct device *, unsigned int
 int amba_request_regions(struct amba_device *, const char *);
 void amba_release_regions(struct amba_device *);
 
+#define amba_pclk_enable(d)    \
+       (IS_ERR((d)->pclk) ? 0 : clk_enable((d)->pclk))
+
+#define amba_pclk_disable(d)   \
+       do { if (!IS_ERR((d)->pclk)) clk_disable((d)->pclk); } while (0)
+
 #define amba_config(d) (((d)->periphid >> 24) & 0xff)
 #define amba_rev(d)    (((d)->periphid >> 20) & 0x0f)
 #define amba_manf(d)   (((d)->periphid >> 12) & 0xff)

diff --git a/include/linux/amba/mmci.h b/include/linux/amba/mmci.h
index 7e466fe72025e26fb9fde46fe91202f5768d9a3d..ca84ce70d5d5fca84b7de66533ba06cab54e5298 100644 (file)
--- a/include/linux/amba/mmci.h
+++ b/include/linux/amba/mmci.h
@@ -15,9 +15,10 @@
  * @ocr_mask: available voltages on the 4 pins from the block, this
  * is ignored if a regulator is used, see the MMC_VDD_* masks in
  * mmc/host.h
- * @translate_vdd: a callback function to translate a MMC_VDD_*
- * mask into a value to be binary or:ed and written into the
- * MMCIPWR register of the block
+ * @vdd_handler: a callback function to translate a MMC_VDD_*
+ * mask into a value to be binary (or set some other custom bits
+ * in MMCIPWR) or:ed and written into the MMCIPWR register of the
+ * block.  May also control external power based on the power_mode.
  * @status: if no GPIO read function was given to the block in
  * gpio_wp (below) this function will be called to determine
  * whether a card is present in the MMC slot or not
@@ -29,7 +30,8 @@
 struct mmci_platform_data {
        unsigned int f_max;
        unsigned int ocr_mask;
-       u32 (*translate_vdd)(struct device *, unsigned int);
+       u32 (*vdd_handler)(struct device *, unsigned int vdd,
+                          unsigned char power_mode);
        unsigned int (*status)(struct device *);
        int     gpio_wp;
        int     gpio_cd;

diff --git a/include/linux/amba/serial.h b/include/linux/amba/serial.h
index 5a5a7fd62490ca34fe27baa952f48de8831d8197..e1b634b635f2a3df5e8a0787c76ea371ae9d8f1a 100644 (file)
--- a/include/linux/amba/serial.h
+++ b/include/linux/amba/serial.h
@@ -38,10 +38,12 @@
 #define UART01x_FR             0x18    /* Flag register (Read only). */
 #define UART010_IIR            0x1C    /* Interrupt indentification register (Read). */
 #define UART010_ICR            0x1C    /* Interrupt clear register (Write). */
+#define ST_UART011_LCRH_RX     0x1C    /* Rx line control register. */
 #define UART01x_ILPR           0x20    /* IrDA low power counter register. */
 #define UART011_IBRD           0x24    /* Integer baud rate divisor register. */
 #define UART011_FBRD           0x28    /* Fractional baud rate divisor register. */
 #define UART011_LCRH           0x2c    /* Line control register. */
+#define ST_UART011_LCRH_TX     0x2c    /* Tx Line control register. */
 #define UART011_CR             0x30    /* Control register. */
 #define UART011_IFLS           0x34    /* Interrupt fifo level select. */
 #define UART011_IMSC           0x38    /* Interrupt mask. */
@@ -84,6 +86,7 @@
 #define UART010_CR_TIE                 0x0020
 #define UART010_CR_RIE                 0x0010
 #define UART010_CR_MSIE                0x0008
+#define ST_UART011_CR_OVSFACT  0x0008  /* Oversampling factor */
 #define UART01x_CR_IIRLP       0x0004  /* SIR low power mode */
 #define UART01x_CR_SIREN       0x0002  /* SIR enable */
 #define UART01x_CR_UARTEN      0x0001  /* UART enable */

diff --git a/include/linux/marvell_phy.h b/include/linux/marvell_phy.h
new file mode 100644 (file)
index 0000000..2ed4fb8
--- /dev/null
+++ b/include/linux/marvell_phy.h
@@ -0,0 +1,20 @@
+#ifndef _MARVELL_PHY_H
+#define _MARVELL_PHY_H
+
+/* Mask used for ID comparisons */
+#define MARVELL_PHY_ID_MASK            0xfffffff0
+
+/* Known PHY IDs */
+#define MARVELL_PHY_ID_88E1101         0x01410c60
+#define MARVELL_PHY_ID_88E1112         0x01410c90
+#define MARVELL_PHY_ID_88E1111         0x01410cc0
+#define MARVELL_PHY_ID_88E1118         0x01410e10
+#define MARVELL_PHY_ID_88E1121R                0x01410cb0
+#define MARVELL_PHY_ID_88E1145         0x01410cd0
+#define MARVELL_PHY_ID_88E1240         0x01410e30
+
+/* struct phy_device dev_flags definitions */
+#define MARVELL_PHY_M1145_FLAGS_RESISTANCE     0x00000001
+#define MARVELL_PHY_M1118_DNS323_LEDS          0x00000002
+
+#endif /* _MARVELL_PHY_H */

diff --git a/include/linux/omapfb.h b/include/linux/omapfb.h
index 9bdd91486b49d94c42e9ac00efd29e1b282a53b5..7e4cd616bcb57c0e51358073873502c9c417c3ef 100644 (file)
--- a/include/linux/omapfb.h
+++ b/include/linux/omapfb.h
@@ -253,7 +253,7 @@ struct omapfb_platform_data {
 /* in arch/arm/plat-omap/fb.c */
 extern void omapfb_set_platform_data(struct omapfb_platform_data *data);
 extern void omapfb_set_ctrl_platform_data(void *pdata);
-extern void omapfb_reserve_sdram(void);
+extern void omapfb_reserve_sdram_memblock(void);
 
 #endif
 

diff --git a/lib/atomic64_test.c b/lib/atomic64_test.c
index 250ed11d3ed2b83b8e2a87845fe97a7db096b33c..44524cc8c32a6ca179d67b8df91394c516ee6046 100644 (file)
--- a/lib/atomic64_test.c
+++ b/lib/atomic64_test.c
@@ -114,7 +114,7 @@ static __init int test_atomic64(void)
        BUG_ON(v.counter != r);
 
 #if defined(CONFIG_X86) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
-    defined(CONFIG_S390) || defined(_ASM_GENERIC_ATOMIC64_H)
+    defined(CONFIG_S390) || defined(_ASM_GENERIC_ATOMIC64_H) || defined(CONFIG_ARM)
        INIT(onestwos);
        BUG_ON(atomic64_dec_if_positive(&v) != (onestwos - 1));
        r -= one;

diff --git a/tools/perf/arch/arm/Makefile b/tools/perf/arch/arm/Makefile
new file mode 100644 (file)
index 0000000..15130b5
--- /dev/null
+++ b/tools/perf/arch/arm/Makefile
@@ -0,0 +1,4 @@
+ifndef NO_DWARF
+PERF_HAVE_DWARF_REGS := 1
+LIB_OBJS += $(OUTPUT)arch/$(ARCH)/util/dwarf-regs.o
+endif

diff --git a/tools/perf/arch/arm/util/dwarf-regs.c b/tools/perf/arch/arm/util/dwarf-regs.c
new file mode 100644 (file)
index 0000000..fff6450
--- /dev/null
+++ b/tools/perf/arch/arm/util/dwarf-regs.c
@@ -0,0 +1,64 @@
+/*
+ * Mapping of DWARF debug register numbers into register names.
+ *
+ * Copyright (C) 2010 Will Deacon, ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <libio.h>
+#include <dwarf-regs.h>
+
+struct pt_regs_dwarfnum {
+       const char *name;
+       unsigned int dwarfnum;
+};
+
+#define STR(s) #s
+#define REG_DWARFNUM_NAME(r, num) {.name = r, .dwarfnum = num}
+#define GPR_DWARFNUM_NAME(num) \
+       {.name = STR(%r##num), .dwarfnum = num}
+#define REG_DWARFNUM_END {.name = NULL, .dwarfnum = 0}
+
+/*
+ * Reference:
+ * http://infocenter.arm.com/help/topic/com.arm.doc.ihi0040a/IHI0040A_aadwarf.pdf
+ */
+static const struct pt_regs_dwarfnum regdwarfnum_table[] = {
+       GPR_DWARFNUM_NAME(0),
+       GPR_DWARFNUM_NAME(1),
+       GPR_DWARFNUM_NAME(2),
+       GPR_DWARFNUM_NAME(3),
+       GPR_DWARFNUM_NAME(4),
+       GPR_DWARFNUM_NAME(5),
+       GPR_DWARFNUM_NAME(6),
+       GPR_DWARFNUM_NAME(7),
+       GPR_DWARFNUM_NAME(8),
+       GPR_DWARFNUM_NAME(9),
+       GPR_DWARFNUM_NAME(10),
+       REG_DWARFNUM_NAME("%fp", 11),
+       REG_DWARFNUM_NAME("%ip", 12),
+       REG_DWARFNUM_NAME("%sp", 13),
+       REG_DWARFNUM_NAME("%lr", 14),
+       REG_DWARFNUM_NAME("%pc", 15),
+       REG_DWARFNUM_END,
+};
+
+/**
+ * get_arch_regstr() - lookup register name from it's DWARF register number
+ * @n: the DWARF register number
+ *
+ * get_arch_regstr() returns the name of the register in struct
+ * regdwarfnum_table from it's DWARF register number. If the register is not
+ * found in the table, this returns NULL;
+ */
+const char *get_arch_regstr(unsigned int n)
+{
+       const struct pt_regs_dwarfnum *roff;
+       for (roff = regdwarfnum_table; roff->name != NULL; roff++)
+               if (roff->dwarfnum == n)
+                       return roff->name;
+       return NULL;
+}