struct sh_mtu2_channel {
struct sh_mtu2_device *mtu;
+ unsigned int index;
void __iomem *base;
int irq;
static void sh_mtu2_start_stop_ch(struct sh_mtu2_channel *ch, int start)
{
- struct sh_timer_config *cfg = ch->mtu->pdev->dev.platform_data;
unsigned long flags, value;
/* start stop register shared by multiple timer channels */
value = sh_mtu2_read(ch, TSTR);
if (start)
- value |= 1 << cfg->timer_bit;
+ value |= 1 << ch->index;
else
- value &= ~(1 << cfg->timer_bit);
+ value &= ~(1 << ch->index);
sh_mtu2_write(ch, TSTR, value);
raw_spin_unlock_irqrestore(&sh_mtu2_lock, flags);
/* enable clock */
ret = clk_enable(ch->mtu->clk);
if (ret) {
- dev_err(&ch->mtu->pdev->dev, "cannot enable clock\n");
+ dev_err(&ch->mtu->pdev->dev, "ch%u: cannot enable clock\n",
+ ch->index);
return ret;
}
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
dev_info(&ch->mtu->pdev->dev,
- "used for periodic clock events\n");
+ "ch%u: used for periodic clock events\n", ch->index);
sh_mtu2_enable(ch);
break;
case CLOCK_EVT_MODE_UNUSED:
ced->suspend = sh_mtu2_clock_event_suspend;
ced->resume = sh_mtu2_clock_event_resume;
- dev_info(&ch->mtu->pdev->dev, "used for clock events\n");
+ dev_info(&ch->mtu->pdev->dev, "ch%u: used for clock events\n",
+ ch->index);
clockevents_register_device(ced);
ret = request_irq(ch->irq, sh_mtu2_interrupt,
IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
dev_name(&ch->mtu->pdev->dev), ch);
if (ret) {
- dev_err(&ch->mtu->pdev->dev, "failed to request irq %d\n",
- ch->irq);
+ dev_err(&ch->mtu->pdev->dev, "ch%u: failed to request irq %d\n",
+ ch->index, ch->irq);
return;
}
}
memset(ch, 0, sizeof(*ch));
ch->mtu = mtu;
+ ch->index = cfg->timer_bit;
ch->irq = platform_get_irq(mtu->pdev, 0);
if (ch->irq < 0) {
- dev_err(&mtu->pdev->dev, "failed to get irq\n");
+ dev_err(&mtu->pdev->dev, "ch%u: failed to get irq\n",
+ ch->index);
return ch->irq;
}