ARM: ux500: fix clock for GPIO blocks 6 and 7

The clock assignment in the device tree for GPIO blocks 6
and 7 was incorrect, indicating this was managed by bit 1 on
PRCC 2 while it was in fact bit 11 on PRCC 2.

Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi
index 55abf1292ddd6fa1f0e0aee6cf469bb15f5b175d..5112f4cd8bce7934fe808f1affd2dd2feb6bc13b 100644 (file)
--- a/arch/arm/boot/dts/ste-dbx5x0.dtsi
+++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi
@@ -197,7 +197,7 @@
                        #gpio-cells = <2>;
                        gpio-bank = <6>;
 
-                       clocks = <&prcc_pclk 2 1>;
+                       clocks = <&prcc_pclk 2 11>;
                };
 
                gpio7: gpio@8011e080 {
@@ -212,7 +212,7 @@
                        #gpio-cells = <2>;
                        gpio-bank = <7>;
 
-                       clocks = <&prcc_pclk 2 1>;
+                       clocks = <&prcc_pclk 2 11>;
                };
 
                gpio8: gpio@a03fe000 {