drm/nouveau: make fifo.create_context() responsible for mapping control regs

The regs belong to PFIFO, they're different for pretty much the same
generations we need different PFIFO control for, and NVC0 is going
to be even more different than the rest.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/nouveau_channel.c b/drivers/gpu/drm/nouveau/nouveau_channel.c
index 3e49babd62ace02da6205caeedeb97f2646a9e3d..a3d33a582a984260689ab4e81d3e5e3f8f3c01b3 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_channel.c
+++ b/drivers/gpu/drm/nouveau/nouveau_channel.c
@@ -113,7 +113,7 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
        struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
        struct nouveau_channel *chan;
        unsigned long flags;
-       int user, ret;
+       int ret;
 
        /* allocate and lock channel structure */
        chan = kzalloc(sizeof(*chan), GFP_KERNEL);
@@ -160,23 +160,6 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
        }
 
        nouveau_dma_pre_init(chan);
-
-       /* Locate channel's user control regs */
-       if (dev_priv->card_type < NV_40)
-               user = NV03_USER(chan->id);
-       else
-       if (dev_priv->card_type < NV_50)
-               user = NV40_USER(chan->id);
-       else
-               user = NV50_USER(chan->id);
-
-       chan->user = ioremap(pci_resource_start(dev->pdev, 0) + user,
-                                                               PAGE_SIZE);
-       if (!chan->user) {
-               NV_ERROR(dev, "ioremap of regs failed.\n");
-               nouveau_channel_put(&chan);
-               return -ENOMEM;
-       }
        chan->user_put = 0x40;
        chan->user_get = 0x44;
 
@@ -356,9 +339,6 @@ nouveau_channel_del(struct kref *ref)
        struct nouveau_channel *chan =
                container_of(ref, struct nouveau_channel, ref);
 
-       if (chan->user)
-               iounmap(chan->user);
-
        kfree(chan);
 }
 

diff --git a/drivers/gpu/drm/nouveau/nv04_fifo.c b/drivers/gpu/drm/nouveau/nv04_fifo.c
index a32ba8ccaae6bdb4669d6abddbd65ad78b6f8042..f89d104698df55578bf91d699ab25cb99c10f21a 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv04_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv04_fifo.c
@@ -129,6 +129,11 @@ nv04_fifo_create_context(struct nouveau_channel *chan)
        if (ret)
                return ret;
 
+       chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
+                            NV03_USER(chan->id), PAGE_SIZE);
+       if (!chan->user)
+               return -ENOMEM;
+
        spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 
        /* Setup initial state */
@@ -173,6 +178,10 @@ nv04_fifo_destroy_context(struct nouveau_channel *chan)
        spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 
        /* Free the channel resources */
+       if (chan->user) {
+               iounmap(chan->user);
+               chan->user = NULL;
+       }
        nouveau_gpuobj_ref(NULL, &chan->ramfc);
 }
 

diff --git a/drivers/gpu/drm/nouveau/nv10_fifo.c b/drivers/gpu/drm/nouveau/nv10_fifo.c
index acb9216e6d0a2cfdc35dd0f217d0074526bb4494..d2ecbff4bee1bc35fd8559a851b2ccf052114814 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv10_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv10_fifo.c
@@ -53,6 +53,11 @@ nv10_fifo_create_context(struct nouveau_channel *chan)
        if (ret)
                return ret;
 
+       chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
+                            NV03_USER(chan->id), PAGE_SIZE);
+       if (!chan->user)
+               return -ENOMEM;
+
        /* Fill entries that are seen filled in dumps of nvidia driver just
         * after channel's is put into DMA mode
         */

diff --git a/drivers/gpu/drm/nouveau/nv40_fifo.c b/drivers/gpu/drm/nouveau/nv40_fifo.c
index f6b3580c685aa8b7039d823da7af3449df994b33..c86e4d4e9b967a864b208009200e394ce79e9f03 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv40_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv40_fifo.c
@@ -47,6 +47,11 @@ nv40_fifo_create_context(struct nouveau_channel *chan)
        if (ret)
                return ret;
 
+       chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
+                            NV40_USER(chan->id), PAGE_SIZE);
+       if (!chan->user)
+               return -ENOMEM;
+
        spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 
        nv_wi32(dev, fc +  0, chan->pushbuf_base);

diff --git a/drivers/gpu/drm/nouveau/nv50_fifo.c b/drivers/gpu/drm/nouveau/nv50_fifo.c
index ed18952ae7f492f697c13120b39bfdc6919ac9f3..7add3dfde3dff7f2c22f7713095f192a60c1924e 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv50_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv50_fifo.c
@@ -261,6 +261,11 @@ nv50_fifo_create_context(struct nouveau_channel *chan)
        }
        ramfc = chan->ramfc;
 
+       chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
+                            NV50_USER(chan->id), PAGE_SIZE);
+       if (!chan->user)
+               return -ENOMEM;
+
        spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 
        nv_wo32(ramfc, 0x48, chan->pushbuf->cinst >> 4);
@@ -327,6 +332,10 @@ nv50_fifo_destroy_context(struct nouveau_channel *chan)
        spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 
        /* Free the channel resources */
+       if (chan->user) {
+               iounmap(chan->user);
+               chan->user = NULL;
+       }
        nouveau_gpuobj_ref(NULL, &ramfc);
        nouveau_gpuobj_ref(NULL, &chan->cache);
 }