drm/i915/kbl: Add Kabylake PCI ID

v2: separate out device info into different GT (Damien)
v3: Add is_kabylake to the KBL gt3 structuer (Damien)
    Sort the platforms in older -> newer order (Damien)

v4: Split platform definition since is_skylake=1 on
    kabylake structure was Nacked. (Rodrigo)

v5: (Rodrigo) Rebase after commit 3cb27f38f
("drm/i915: remove an extra level of indirection in PCI ID list")

Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Deepak S <deepak.s@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446059991-17033-1-git-send-email-rodrigo.vivi@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7b29aeeae29ec70361cb537157941a17430faa9f..f020daadc16ddec156cb770e487dc192004b8faa 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -466,6 +466,9 @@ static const struct pci_device_id pciidlist[] = {
        INTEL_SKL_GT2_IDS(&intel_skylake_info),
        INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
        INTEL_BXT_IDS(&intel_broxton_info),
+       INTEL_KBL_GT1_IDS(&intel_kabylake_info),
+       INTEL_KBL_GT2_IDS(&intel_kabylake_info),
+       INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
        {0, 0, 0}
 };
 

diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 17c445612e0107646f54d407d70169465ff12776..2e7a159ccf9317dd93f615ca8e330916966b8ef3 100644 (file)
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -291,4 +291,33 @@
        INTEL_VGA_DEVICE(0x1A84, info), \
        INTEL_VGA_DEVICE(0x5A84, info)
 
+#define INTEL_KBL_GT1_IDS(info)        \
+       INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
+       INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
+       INTEL_VGA_DEVICE(0x5917, info), /* DT  GT1.5 */ \
+       INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
+       INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
+       INTEL_VGA_DEVICE(0x5902, info), /* DT  GT1 */ \
+       INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
+       INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
+
+#define INTEL_KBL_GT2_IDS(info)        \
+       INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
+       INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \
+       INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \
+       INTEL_VGA_DEVICE(0x5912, info), /* DT  GT2 */ \
+       INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
+       INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
+       INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
+
+#define INTEL_KBL_GT3_IDS(info) \
+       INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \
+       INTEL_VGA_DEVICE(0x592B, info), /* Halo GT3 */ \
+       INTEL_VGA_DEVICE(0x592A, info) /* SRV GT3 */
+
+#define INTEL_KBL_IDS(info) \
+       INTEL_KBL_GT1_IDS(info), \
+       INTEL_KBL_GT2_IDS(info), \
+       INTEL_KBL_GT3_IDS(info)
+
 #endif /* _I915_PCIIDS_H */