ARM: dts: imx6q-sabrelite: add i2c1 pinctrl support

Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 2f631f25fffe069b8e2f9bc72187b044a5f215a3..85b7c6c1ecf24d29d916a0a25f7cdf2b7a548b9e 100644 (file)
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -76,6 +76,8 @@
                        i2c@021a0000 { /* I2C1 */
                                status = "okay";
                                clock-frequency = <100000>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_i2c1_1>;
 
                                codec: sgtl5000@0a {
                                        compatible = "fsl,sgtl5000";

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index b5a15c4c2fdcc089fbf328ebf6d32b6ba64e10a7..32ea8998c72e6a5b37f25815d937ab697d12211e 100644 (file)
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -486,6 +486,13 @@
                                reg = <0x020e0000 0x4000>;
 
                                /* shared pinctrl settings */
+                               i2c1 {
+                                       pinctrl_i2c1_1: i2c1grp-1 {
+                                               fsl,pins = <137 0x4001b8b1      /* MX6Q_PAD_EIM_D21__I2C1_SCL */
+                                                           196 0x4001b8b1>;    /* MX6Q_PAD_EIM_D28__I2C1_SDA */
+                                       };
+                               };
+
                                usdhc3 {
                                        pinctrl_usdhc3_1: usdhc3grp-1 {
                                                fsl,pins = <1273 0x17059        /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */