#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA186_CLK_I2C1>;
- clock-names = "i2c";
+ clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C1>;
reset-names = "i2c";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA186_CLK_I2C3>;
- clock-names = "i2c";
+ clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C3>;
reset-names = "i2c";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA186_CLK_I2C4>;
- clock-names = "i2c";
+ clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C4>;
reset-names = "i2c";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA186_CLK_I2C6>;
- clock-names = "i2c";
+ clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C6>;
reset-names = "i2c";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA186_CLK_I2C7>;
- clock-names = "i2c";
+ clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C7>;
reset-names = "i2c";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA186_CLK_I2C9>;
- clock-names = "i2c";
+ clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C9>;
reset-names = "i2c";
status = "disabled";
compatible = "nvidia,tegra186-sdhci";
reg = <0x0 0x03400000 0x0 0x200>;
resets = <&bpmp TEGRA186_RESET_SDMMC1>;
- reset-names = "sdmmc";
+ reset-names = "sdhci";
clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
- clock-names = "sdmmc";
interrupts = <GIC_SPI 62 0x04>;
status = "disabled";
};
compatible = "nvidia,tegra186-sdhci";
reg = <0x0 0x03460000 0x0 0x200>;
resets = <&bpmp TEGRA186_RESET_SDMMC4>;
- reset-names = "sdmmc";
+ reset-names = "sdhci";
clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
- clock-names = "sdmmc";
interrupts = <GIC_SPI 31 0x04>;
status = "disabled";
};
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA186_CLK_I2C2>;
- clock-names = "i2c";
+ clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C2>;
reset-names = "i2c";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA186_CLK_I2C8>;
- clock-names = "i2c";
+ clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C8>;
reset-names = "i2c";
status = "disabled";
bpmp_i2c: i2c {
compatible = "nvidia,tegra186-bpmp-i2c";
- nvidia,bpmp = <&bpmp>;
nvidia,bpmp-bus-id = <5>;
#address-cells = <1>;
#size-cells = <0>;
u32 mvebu_get_nand_clock(void)
{
+ u32 reg;
+
+ if (mvebu_soc_family() == MVEBU_SOC_A38X)
+ reg = MVEBU_DFX_DIV_CLK_CTRL(1);
+ else
+ reg = MVEBU_CORE_DIV_CLK_CTRL(1);
+
return CONFIG_SYS_MVEBU_PLL_CLOCK /
- ((readl(MVEBU_CORE_DIV_CLK_CTRL(1)) &
+ ((readl(reg) &
NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
}
#define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000))
#define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000))
#define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe0000))
+#define MVEBU_DFX_BASE (MVEBU_REGISTER(0xe4000))
#define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200))
#define MBUS_ERR_PROP_EN (1 << 8)
#define SPI_PUP_EN BIT(5)
#define MVEBU_CORE_DIV_CLK_CTRL(i) (MVEBU_CLOCK_BASE + ((i) * 0x8))
+#define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0x250 + ((i) * 0x4))
#define NAND_ECC_DIVCKL_RATIO_OFFS 8
#define NAND_ECC_DIVCKL_RATIO_MASK (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)
DEBUG_INIT_S("PCIe, Idx ");
DEBUG_INIT_D(pex_idx, 1);
DEBUG_INIT_S
- (": Link upgraded to Gen2 based on client cpabilities\n");
+ (": Link upgraded to Gen2 based on client capabilities\n");
}
/* Update pex DEVICE ID */
}
} else {
test_result = SERDES_ALREADY_IN_USE;
- if (test_result == SERDES_ALREADY_IN_USE) {
- printf("%s: Error: serdes lane %d is configured to type %s: type already in use\n",
- __func__, serdes_id,
- serdes_type_to_string[serdes_type]);
- return MV_FAIL;
- } else if (test_result == WRONG_NUMBER_OF_UNITS) {
- printf("%s: Warning: serdes lane %d is set to type %s.\n",
- __func__, serdes_id,
- serdes_type_to_string[serdes_type]);
- printf("%s: Maximum supported lanes are already set to this type (limit = %d)\n",
- __func__, serd_max_num);
- return MV_FAIL;
- } else if (test_result == UNIT_NUMBER_VIOLATION) {
- printf("%s: Warning: serdes lane %d type is %s: current device support only %d units of this type.\n",
- __func__, serdes_id,
- serdes_type_to_string[serdes_type],
- serd_max_num);
- return MV_FAIL;
- }
+ }
+
+ if (test_result == SERDES_ALREADY_IN_USE) {
+ printf("%s: Error: serdes lane %d is configured to type %s: type already in use\n",
+ __func__, serdes_id,
+ serdes_type_to_string[serdes_type]);
+ return MV_FAIL;
+ } else if (test_result == WRONG_NUMBER_OF_UNITS) {
+ printf("%s: Warning: serdes lane %d is set to type %s.\n",
+ __func__, serdes_id,
+ serdes_type_to_string[serdes_type]);
+ printf("%s: Maximum supported lanes are already set to this type (limit = %d)\n",
+ __func__, serd_max_num);
+ return MV_FAIL;
+ } else if (test_result == UNIT_NUMBER_VIOLATION) {
+ printf("%s: Warning: serdes lane %d type is %s: current device support only %d units of this type.\n",
+ __func__, serdes_id,
+ serdes_type_to_string[serdes_type],
+ serd_max_num);
+ return MV_FAIL;
}
return MV_OK;
static int tegra186_bpmp_i2c_probe(struct udevice *dev)
{
struct tegra186_bpmp_i2c *priv = dev_get_priv(dev);
- int ret;
- struct fdtdec_phandle_args args;
-
- ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
- "nvidia,bpmp", NULL, 0, 0, &args);
- if (ret < 0) {
- debug("%s: fdtdec_parse_phandle_with_args() failed: %d\n",
- __func__, ret);
- return ret;
- }
priv->bpmp_bus_id = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
"nvidia,bpmp-bus-id", U32_MAX);
error("reset_get_by_name() failed: %d\n", ret);
return ret;
}
- ret = clk_get_by_name(dev, "i2c", &i2c_bus->clk);
+ ret = clk_get_by_name(dev, "div-clk", &i2c_bus->clk);
if (ret) {
error("clk_get_by_name() failed: %d\n", ret);
return ret;
struct udevice dev;
int ret;
dev.of_offset = node;
- ret = reset_get_by_name(&dev, "sdmmc", &host->reset_ctl);
+ ret = reset_get_by_name(&dev, "sdhci", &host->reset_ctl);
if (ret) {
- debug("reset_get_by_index() failed: %d\n", ret);
+ debug("reset_get_by_name() failed: %d\n", ret);
return ret;
}
- ret = clk_get_by_name(&dev, "sdmmc", &host->clk);
+ ret = clk_get_by_index(&dev, 0, &host->clk);
if (ret) {
debug("clk_get_by_index() failed: %d\n", ret);
return ret;
priv->freq = plat->frequency;
priv->periph_id = plat->periph_id;
+ /* Change SPI clock to correct frequency, PLLP_OUT0 source */
+ clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
+ priv->freq);
+
return 0;
}
priv->freq = plat->frequency;
priv->periph_id = plat->periph_id;
+ /* Change SPI clock to correct frequency, PLLP_OUT0 source */
+ clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
+ priv->freq);
+
return 0;
}
priv->freq = plat->frequency;
priv->periph_id = plat->periph_id;
+ /* Change SPI clock to correct frequency, PLLP_OUT0 source */
+ clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
+
return 0;
}
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS 0
-#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS 0
-#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS 0
-#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS 0
-#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS 0
-#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
/* DS414 bus width is 32bits */
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS 0
-#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS 0
-#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
hdr->blockid = IBR_HDR_UART_ID;
- /*
- * Subtract mkimage header size from destination address
- * as this header is not expected by the Marvell BootROM.
- * This way, the execution address is identical to the
- * one the image is compiled for (TEXT_BASE).
- */
- hdr->destaddr = hdr->destaddr - sizeof(struct image_header);
-
if (image_ver == 0) {
struct main_hdr_v0 *hdr_v0 = img;
hdr_v0->srcaddr = hdr_v0->ext
? sizeof(struct kwb_header)
: sizeof(*hdr_v0);
+ } else {
+ /*
+ * Subtract mkimage header size from destination address
+ * as this header is not expected by the Marvell BootROM.
+ * This way, the execution address is identical to the
+ * one the image is compiled for (TEXT_BASE).
+ */
+ hdr->destaddr = hdr->destaddr - sizeof(struct image_header);
}
hdr->checksum = kwboot_img_csum8(hdr, hdrsz) - csum;