doc: dt: add documentation for lpc1850-ccu clk driver

Add DT binding documentation for lpc1850-ccu clk driver.

Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>

diff --git a/Documentation/devicetree/bindings/clock/lpc1850-ccu.txt b/Documentation/devicetree/bindings/clock/lpc1850-ccu.txt
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+* NXP LPC1850 Clock Control Unit (CCU)
+
+Each CGU base clock has several clock branches which can be turned on
+or off independently by the Clock Control Units CCU1 or CCU2. The
+branch clocks are distributed between CCU1 and CCU2.
+
+ - Above text taken from NXP LPC1850 User Manual.
+
+This binding uses the common clock binding:
+    Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible:
+       Should be "nxp,lpc1850-ccu"
+- reg:
+       Shall define the base and range of the address space
+       containing clock control registers
+- #clock-cells:
+       Shall have value <1>.  The permitted clock-specifier values
+       are the branch clock names defined in table below.
+- clocks:
+       Shall contain a list of phandles for the base clocks routed
+       from the CGU to the specific CCU. See mapping of base clocks
+       and CCU in table below.
+- clock-names:
+       Shall contain a list of names for the base clock routed
+       from the CGU to the specific CCU. Valid CCU clock names:
+       "base_usb0_clk",  "base_periph_clk", "base_usb1_clk",
+       "base_cpu_clk",   "base_spifi_clk",  "base_spi_clk",
+       "base_apb1_clk",  "base_apb3_clk",   "base_adchs_clk",
+       "base_sdio_clk",  "base_ssp0_clk",   "base_ssp1_clk",
+       "base_uart0_clk", "base_uart1_clk",  "base_uart2_clk",
+       "base_uart3_clk", "base_audio_clk"
+
+Which branch clocks that are available on the CCU depends on the
+specific LPC part. Check the user manual for your specific part.
+
+A list of CCU clocks can be found in dt-bindings/clock/lpc18xx-ccu.h.
+
+Example board file:
+
+soc {
+       ccu1: clock-controller@40051000 {
+               compatible = "nxp,lpc1850-ccu";
+               reg = <0x40051000 0x1000>;
+               #clock-cells = <1>;
+               clocks = <&cgu BASE_APB3_CLK>,   <&cgu BASE_APB1_CLK>,
+                        <&cgu BASE_SPIFI_CLK>,  <&cgu BASE_CPU_CLK>,
+                        <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
+                        <&cgu BASE_USB1_CLK>,   <&cgu BASE_SPI_CLK>;
+               clock-names = "base_apb3_clk",   "base_apb1_clk",
+                             "base_spifi_clk",  "base_cpu_clk",
+                             "base_periph_clk", "base_usb0_clk",
+                             "base_usb1_clk",   "base_spi_clk";
+       };
+
+       ccu2: clock-controller@40052000 {
+               compatible = "nxp,lpc1850-ccu";
+               reg = <0x40052000 0x1000>;
+               #clock-cells = <1>;
+               clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
+                        <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
+                        <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
+                        <&cgu BASE_SSP0_CLK>,  <&cgu BASE_SDIO_CLK>;
+               clock-names = "base_audio_clk", "base_uart3_clk",
+                             "base_uart2_clk", "base_uart1_clk",
+                             "base_uart0_clk", "base_ssp1_clk",
+                             "base_ssp0_clk",  "base_sdio_clk";
+       };
+
+       /* A user of CCU brach clocks */
+       uart1: serial@40082000 {
+               ...
+               clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
+               ...
+       };
+};