sh: clock-cpg div4 set_rate() shift fix

Make sure the div4 bitfield is shifted according
to the enable_bit value in sh_clk_div4_set_rate().

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

diff --git a/arch/sh/kernel/cpu/clock-cpg.c b/arch/sh/kernel/cpu/clock-cpg.c
index 2827abb5d2abc21df11cf1aa202b1de805974985..72a5e621a9bbcdbe54b1adeed575e77e69315a8a 100644 (file)
--- a/arch/sh/kernel/cpu/clock-cpg.c
+++ b/arch/sh/kernel/cpu/clock-cpg.c
@@ -192,8 +192,8 @@ static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id
                return idx;
 
        value = __raw_readl(clk->enable_reg);
-       value &= ~0xf;
-       value |= idx;
+       value &= ~(0xf << clk->enable_bit);
+       value |= (idx << clk->enable_bit);
        __raw_writel(value, clk->enable_reg);
 
        return 0;