Although 400M bus setpoint can save some SOC domain power,
but it will also bring some additional power consumption
to DDR3, and the DDR performace's drop could also lead to
more heat generated by COREs which will spent more time
waiting for DDR data ready, also, there is not many usecases
that need this setpoint, all in all, we should remove 400M
setpoint.
Signed-off-by: Anson Huang <b20788@freescale.com>
*/
high_cpu_freq = 1;
if (low_bus_freq_mode || audio_bus_freq_mode)
- set_high_bus_freq(0);
+ set_high_bus_freq(1);
} else {
/* Update count */
if (clk->flags & AHB_HIGH_SET_POINT)
/* Set to either high or
* medium setpoint.
*/
- set_high_bus_freq(0);
+ set_high_bus_freq(1);
}
}
}
#else
bus_freq_scaling_is_active = 1;
#endif
- set_high_bus_freq(0);
+ set_high_bus_freq(1);
/* Make sure system can enter low bus mode if it should be in
low bus mode */
if (low_freq_bus_used() && !low_bus_freq_mode)
.enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
.disable = _clk_disable,
.secondary = &usboh3_clk[1],
- .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+ .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
},
{
.parent = &mmdc_ch0_axi_clk[0],